Exposure mask, semiconductor device, and method of manufacturing semiconductor device

Abstract

The invention relates to an exposure mask, a semiconductor device and a method of manufacturing the semiconductor device. An exposure mask for forming a pattern having a first width includes a first line, a second line, and at least one bridging line. The first line may extend in a first direction. The first line has a second width narrower than the first width. The second line may extend parallel to and spaced apart from the first line. The second line is formed to have a second width. A bridging line may be connected between the first line and the second line.

Description

Technical Field

[0001] Various embodiments relate generally to semiconductor devices, and more particularly, to an exposure mask, a semiconductor device formed using the exposure mask, and a method of manufacturing the semiconductor device. Background Art

[0002] In order to provide a semiconductor device having high integration and small size, an optical device having high resolution may be used to form a fine pattern on a substrate.

[0003] Optical equipment with high resolution can form fine patterns with target width.

[0004] The semiconductor device may include a region where a pattern having a first pitch may be formed, and a region where a pattern having a second pitch wider than the first pitch may be formed. Therefore, when patterns having various pitches are formed using an optical device optimized for a specific region, the profile of the pattern may be degraded due to a focus error in an exposure process. Summary of the invention

[0005] According to example embodiments, an exposure mask for forming a pattern having a first width may be provided. The exposure mask may include a first line, a second line, and at least one bridge line. The first line may extend along a first direction. The first line may have a second width narrower than the first width. The second line may extend parallel to the first line and be spaced apart from the first line. The second line may have a second width. The bridge line may be connected between the first line and the second line.

[0006] According to example embodiments, a semiconductor device may be provided. The semiconductor device may include a semiconductor substrate, a first target pattern, and a second target pattern. The semiconductor substrate may include a first region and a second region. The first target pattern may be formed in the first region. The first target pattern may extend in a first direction and have a second width. The second target pattern may be formed in the second region. The second target pattern may have a first width wider than the second width. The second target pattern may include a first line, a second line, and at least one bridge line. The first line may extend in a first direction. The first line may have a second width. The second line may extend in the first direction. The second line may be spaced apart from the first line in a second direction different from the first direction. The second line may have a second width. The bridge line may be connected between the first line and the second line.

[0007] According to an example embodiment, a semiconductor device is provided. The semiconductor device may include a lower structure, a first line, a second line, and a plurality of bridge lines. The lower structure may include a plurality of contacts arranged along a first direction. The first line may extend along a first side of the contact above the lower structure in the first direction. The first line may have a second width. The second line may extend along a second side of the contact above the lower structure in the first direction. The first side of the contact may be positioned opposite to the second side of the contact. The second line may extend along the first direction. The second line may have a second width. Bridge lines may be connected between the first line and the second line. These bridge lines may contact the first surface of the contact, thereby connecting the first line and the second line.

[0008] According to example embodiments, a method for manufacturing a semiconductor device is provided. In the method for manufacturing the semiconductor device, a semiconductor substrate may be provided, the semiconductor substrate including a first region and a second region. The semiconductor substrate may include a lower structure. A first target pattern may be formed on the lower structure in the first region. The first target pattern may have a second width narrower than the first width. A photoresist pattern may be formed on the lower structure in the second region using an exposure mask. The exposure mask may include a first line, a second line, and at least one bridge line. The first line may extend in a first direction. The first line may have a second width. The second line may extend parallel to the first line and be spaced apart from the first line. The second line may have a second width. The bridge line may be connected between the first line and the second line. A photoresist pattern may be used to pattern a layer of the lower structure below the photoresist pattern to form a second target pattern having a first width.

[0009] According to example embodiments, a semiconductor device is provided. The semiconductor device may include a semiconductor substrate including a first region and a second region. A first target pattern having a first width may be formed in the first region. A plurality of spaced-apart second target patterns may be formed in the second region, wherein each of the second target patterns may be formed to have a second width. Each of the second target patterns may include a first line extending in a first direction; a second line spaced apart from the first line in a second direction different from the first direction; and at least one bridge line connected between the first line and the second line. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features, and advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figures 1A to 1C is a view illustrating a pattern according to a target width in an optical device having a high resolution;

[0012] Figure 2 is a view illustrating an exposure mask according to an example embodiment;

[0013] Figure 3 is a plan view illustrating a semiconductor device according to an example embodiment;

[0014] 4A to 4D illustrates a cross-sectional view of a semiconductor device formed using a method of manufacturing a semiconductor device according to example embodiments; and

[0015] FIG. 5A to FIG. 5D A plan view of a semiconductor device formed using a method of manufacturing a semiconductor device according to example embodiments is illustrated. DETAILED DESCRIPTION

[0016] Various embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The accompanying drawings are schematic illustrations of various embodiments (and intermediate structures). As such, variations in the configuration and shape of the illustrations, for example due to manufacturing techniques and / or tolerances, are contemplated. Therefore, the described embodiments should not be interpreted as being limited to the specific configurations and shapes illustrated herein, but may include deviations in configurations and shapes that do not depart from the spirit and scope of the invention as set forth in the appended claims.

[0017] This specification refers to cross-sections and / or plan illustrations of idealized embodiments. However, such embodiments should not be construed as limiting the concepts of the present invention. Although multiple embodiments will be shown and described, it will be appreciated by those of ordinary skill in the art that these embodiments may be modified without departing from the principles and spirit of the present invention.

[0018] Generally speaking, term can be understood at least in part according to the use in context.For example, term " one or more " used in this article can be used to describe any feature, structure or characteristic with singular meaning at least in part depending on context, or can be used to describe the combination of feature, structure or characteristic with plural meaning.Similarly, terms such as " one ", " one " or " the " can also be understood to express singular usage or express plural usage at least in part depending on context.In addition, term " based on " can be understood to be not necessarily intended to express exclusive one group of factors, and on the contrary can at least in part depend on context and allow to exist additional factors that are not necessarily clearly described.

[0019] It should be easily understood that the meaning of “on,” “over,” and “on” in the present disclosure should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “on” means not only the meaning of “above something” or “on something,” but also includes the meaning of “over something” or “on something” without intervening features or layers therebetween (i.e., directly on something).

[0020] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0021] Figures 1A to 1C is a view illustrating a pattern according to a target width in an optical device with high resolution.

[0022] For example, a process for manufacturing a semiconductor integrated circuit may include a photolithography process, in which a circuit pattern of an exposure mask may be transferred to a photoresist film on a wafer using an illumination device.

[0023] A photoresist pattern formed by a photolithography process may be used as a mask for etching a layer below the photoresist pattern. The width of the photoresist pattern may correspond to the width of a target pattern formed by the layer. Therefore, the width of the photoresist pattern may be an important factor for determining the integration of a semiconductor device.

[0024] The target pattern is formed with a target width. In order to provide a target pattern that can be repeatedly arranged in the same direction (e.g., the X direction), an optical device including a variable illuminator such as a dipole illuminator can be used. A variable illuminator can be used to form a target pattern with a width of less than about 80 nm.

[0025] Figure 1A The Normalized Image Log Slope (NILS) according to the target width (line width) is shown. Figure 1B shows an image of a target pattern having a width of about 76 nm, and Figure 1C An image of a target pattern having a width of approximately 160 nm is shown.

[0026] NILS may be a value obtained by normalizing an image using the slope and width of the image. The image may be accurately made proportional to an increase in the normalized value.

[0027] Figure 1B An image of a target pattern with a width of about 76 nm formed using a variable illuminator is shown. NILS of the target pattern can be as follows Figure 1A The ones indicated by B are of good quality.

[0028] However, a target pattern having a width of about 160 nm can be formed as Figure 1A As indicated by E in Figure 1C Shown are abnormal or low quality profiles.

[0029] Such abnormal or low quality profiles may be caused by a disabled pitch section problem resulting from low exposure in a modified illuminator optimized for fine patterns. th In a manufacturing environment that is optimal for the formation of fine patterns, it may be advantageous to form a pattern with a target pitch in a disabled pitch section according to the density difference of the pattern on the substrate.

[0030] The semiconductor device may be divided into a unit region and a peripheral region. The width of the target pattern in the peripheral region may be wider than the width of the target pattern in the unit region. In order to form the target pattern using a single illuminator, the target pattern may include different widths in the unit region and the peripheral region, and an exposure mask may be used, wherein the exposure mask is capable of forming a pattern having a width wider than the width of the pattern in the unit region in the peripheral region.

[0031] Figure 2 is a view illustrating an exposure mask according to example embodiments.

[0032] Reference Figure 2 , a target pattern having a first width L used as a line pattern may be formed using the exposure mask 100 .

[0033] The exposure mask 100 includes a first line 110, a second line 120, and at least one bridge line 130. The first line 110 may extend in a first direction (Y direction). The first line 110 has a second width A narrower than the first width L. The second line 120 may extend parallel to the first line 110 and be spaced apart from the first line 110. The second line 120 may have a second width A. The bridge line 130 is connected between the first line 110 and the second line 120. The line group including the first line 110, the second line 120, and the bridge line 130 may be arranged repeatedly at set intervals along the second direction (X direction) in the exposure mask. Each line group in the repeated line group is separated from the next closest line group by a gap, which gap may be the same gap between consecutive line groups. The line group or line pattern is formed with a first width L. The gap S between the first line 110 and the second line 120 may be wider than the second width A.

[0034] The semiconductor device may have a first region and a second region. The first region corresponds to a cell region. The second region corresponds to a peripheral region. A first target pattern having a second width A is formed in the first region. A second target pattern having a first width is formed in the second region.

[0035] Can be used Figure 2 The exposure mask 100 is used to form a second target pattern having a first width in the second region.

[0036] In example embodiments, the second width A may be less than half of the first width. For example, when the first width L is about 130 nm to about 170 nm, the second width A may be about 65 nm to about 85 nm, but is not limited thereto. The gap S between the first line 110 and the second line 120 may be about 10 nm wider than the second width A, but is not limited thereto.

[0037] The modified illuminator can be used to transcribe an image including first and second lines 110 and 120 having a second width A and bridge line 130 onto a photoresist film to form a photoresist pattern. The photoresist pattern can be used as an etching mask to pattern a layer to form a pattern with a good quality profile.

[0038] Figure 3 is a plan view illustrating a semiconductor device according to example embodiments.

[0039] Reference Figure 3 , the semiconductor device 200 of the example embodiment includes a semiconductor substrate 210, a first target pattern 240, and a second target pattern 250. Figure 3In the example of FIG. 1 , a first region 220 and a second region 230 are included on a semiconductor substrate 210 . A first target pattern 240 is formed in the first region 220 . A second target pattern 250 is formed in the second region 230 .

[0040] The first target pattern 240 may extend in the first direction (Y direction). Each first target pattern 240 is formed with a second width A. The plurality of first target patterns 240 are spaced apart from each other by a distance M along the second direction (X direction). Figure 3 In the example of FIG. 2 , first target patterns 240 are shown to be parallel to each other and spaced apart from each other.

[0041] The second target pattern 250 is formed with a first width L that is wider than the second width A. The second target pattern 250 includes a first line 251 , a second line 253 , and at least one bridge line 255 .

[0042] The first line 251 may extend in the first direction. The first line 251 is formed with a second width A. The second line 253 is spaced apart from the first line 251 along the second direction by a distance S. The second line 253 may extend in the first direction. The second line 253 is formed with a second width A. One or more bridge lines 255 are connected between the first line 251 and the second line 253.

[0043] In an example embodiment, one of the plurality of contacts 320 is formed below each of the bridge lines 255. Thus, each of the bridge lines is formed at a position corresponding to the position of one of the plurality of contacts. The contacts 320 may be arranged along a first direction. In this example, the bridge line 255 contacts the upper surface or first surface of the contact 320. The second target pattern 250 is electrically connected through the contact.

[0044] According to example embodiments, the first and second lines 251 and 253 in the second region 230 are formed with a second width A. The bridge line 255 is connected between the first and second lines 251 and 253. Therefore, the second target pattern 250 is a target pattern having a first width L. The first width L may be, for example, at least 2A.

[0045] 4A to 4D A cross-sectional view of a semiconductor device formed using a method of manufacturing the semiconductor device according to example embodiments is illustrated. FIG. 5A to FIG. 5D A plan view of a semiconductor device formed using a method of manufacturing a semiconductor device according to example embodiments is illustrated.

[0046] In more detail, 4A to 4D They are FIG. 5A to FIG. 5D, which illustrates a second region of a semiconductor device on a semiconductor substrate on which a first region (cell region) and a second region (peripheral region) are provided. FIG. 5A to FIG. 5D is a plan view illustrating the second area. 4A to 4D as well as FIG. 5A to FIG. 5D The cross-hatching in the figures illustrates corresponding or similar areas between the figures rather than indicating material used for these areas.

[0047] Although not depicted in the drawings, the pattern may be repeatedly arranged at a set interval or a fixed interval in the first region of the semiconductor substrate along the second direction. The pattern having the second width may extend along the first direction.

[0048] Reference Figure 4A , the figure is throughout Figure 5A Referring to the cross section of line AA in FIG. 8 , a photoresist pattern 350 may be formed on the semiconductor substrate 310 having the lower structures 320 , 330 , and 340 .

[0049] The lower structures 320, 330 and 340 may be generated by forming at least one conductive layer 340 on at least one insulating interlayer 330 having at least one contact 320 and planarizing the conductive layer 340, but are not limited thereto. The lower structures 320, 330 and 340 may include other structures formed, for example, by a dual damascene process.

[0050] Can be used Figure 2 The photoresist pattern 350 is formed by using the exposure mask 100 of FIG. The photoresist pattern 350 includes a first line 351, a second line 353, and at least one bridge line 355, and the lines 351, 353, and 355 have a width L in common. The first line 351 extends along a first direction. The first line 351 is formed with a second width A narrower than the first width L. In this example, the second line 353 is formed at Figure 5A 351 and is shown as extending parallel to the first line 351 and spaced apart from the first line 351. The second line 353 is formed with a second width A. The bridge line 355 is connected between the first line 351 and the second line 353. In this example, the photoresist pattern 350 including the first line 351, the second line 353, and the bridge line 355 is repeatedly arranged in a second direction rotated 90 degrees relative to the first direction. The first line 351, the second line 353, and the bridge line 355 form a group that can be advantageously repeatedly arranged at a set interval or a fixed interval, for example, with a uniform gap or space between consecutive groups. The bridge line 355 can be configured to cover the upper surface or first surface of the contact 320 arranged along the first direction.

[0051] Reference Figure 4B , the figure is throughout Figure 5BBB in FIG. 5 , the conductive layer 340 may be patterned using the photoresist pattern 350 as an etching mask.

[0052] Reference Figure 4C , the figure is throughout Figure 5C In the cross section of line CC in FIG. 3 , an insulating layer 360 may be formed on the entire structure. Then, for example, the Figure 4C The insulating layer 360 above the uppermost surface of the segment 340 in the insulating layer 360 is formed so that the segment 370 of the insulating layer 360 remains as Figure 4D and Figure 5D For example, the planarization process may continue until the conductive layer 340 is exposed. The target pattern 380 is formed as shown in FIG. Figure 4D and Figure 5D The first width L is shown as being at least two times or at least double the second width A.

[0053] Therefore, a target pattern having a good quality profile is generated to have a first width that is wider than a second width, and can be formed using an optical device configured to form the second width.

[0054] The above embodiments of the present invention are intended to illustrate rather than limit the present invention. Various alternatives and equivalents are possible. The present invention is not limited to the embodiments described herein. The present invention is also not limited to any particular type of semiconductor device. Other additions, reductions, or modifications are obvious with respect to the present disclosure and are intended to fall within the scope of the appended claims.

[0055] CROSS-REFERENCE TO RELATED APPLICATIONS

[0056] This application claims the benefit of Korean Application No. 10-2023-0121600 filed on September 13, 2023 in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

Claims

1. An exposure mask for forming a pattern having a first width, the exposure mask comprising: a first line extending in a first direction, the first line having a second width narrower than the first width; a second line extending parallel to the first line and spaced apart from the first line, the second line having the second width; as well as At least one bridge line is connected between the first line and the second line.

2. The exposure mask according to claim 1, wherein The first line, the second line, and the at least one bridge line include a line group repeatedly arranged at set intervals along a second direction different from the first direction.

3. The exposure mask according to claim 1, wherein The first width is at least twice the second width.

4. A semiconductor device, comprising: A semiconductor substrate having a first region and a second region; a first target pattern formed in the first region and extending along a first direction, the first target pattern having a second width; as well as a second target pattern formed in the second region, the second target pattern being formed to have a first width wider than the second width; Wherein, the second target pattern includes: a first line, the first line extending along the first direction, the first line having the second width; a second line spaced apart from the first line in a second direction different from the first direction and extending in the first direction, the second line having the second width; and At least one bridge line is connected between the first line and the second line.

5. The semiconductor device according to claim 4, wherein: The first target patterns are repeatedly arranged along the second direction and are separated by gaps. 6 . The semiconductor device according to claim 4 , further comprising a contact having a surface in contact with at least one bridge line.

7. The semiconductor device according to claim 4, wherein: The second target patterns are repeatedly arranged along the second direction and are separated by gaps.

8. A semiconductor device, comprising: a lower structure comprising a plurality of contacts arranged along a first direction; a first line extending in the first direction over the lower structure along a first side of the contact, the first line having a second width; a second line extending in the first direction over the lower structure along a second side of the contact, the second line having the second width, wherein the first side of the contact is positioned opposite the second side of the contact; as well as A plurality of bridge wires contact the first surface of the contact, thereby connecting the first line and the second line.

9. The semiconductor device according to claim 8, wherein: The first line, the second line, and the bridge line are collectively formed to have a first width that is wider than the second width.

10. The semiconductor device according to claim 9, wherein The first width is at least twice the second width.

11. A method for manufacturing a semiconductor device, the method comprising the steps of: Providing a semiconductor substrate, the semiconductor substrate comprising a first region and a second region, the semiconductor substrate comprising a lower structure; forming a first target pattern on the lower structure in the first region, the first target pattern having a second width narrower than the first width; forming a photoresist pattern on the lower structure in the second region using an exposure mask, the exposure mask comprising: a first line extending in a first direction and having the second width; a second line extending parallel to the first line and spaced apart from the first line and having the second width; and at least one bridge line connected between the first line and the second line; and A layer of the lower structure below the photoresist pattern is patterned using the photoresist pattern to form a second target pattern having the first width.

12. The method according to claim 11, wherein: The lower structure includes at least one contact arranged in the first direction, wherein the bridge line is formed at a position corresponding to a position of the contact.

13. The method according to claim 11, wherein: The first width is at least twice the second width.

14. The method according to claim 11, further comprising the steps of: An insulating layer is formed on the lower structure, and the insulating layer is removed until the lower structure is exposed.

15. A semiconductor device, comprising: A semiconductor substrate, the semiconductor substrate comprising a first region and a second region; a first target pattern formed in the first region to have a first width; as well as a plurality of spaced-apart second target patterns formed in the second region, wherein each second target pattern is formed to have a second width and comprises: a first line extending in a first direction; a second line spaced apart from the first line along a second direction different from the first direction; At least one bridge line is connected between the first line and the second line.

16. The semiconductor device according to claim 15, wherein: The second target pattern is formed using a photoresist pattern.

Images