Continuous counting timer and timing method thereof

Abstract

The invention relates to the field of timers, and discloses a continuous counting timer and a timing method thereof, and the method comprises the steps: in a current slow clock period, when a clock synchronization counting module detects the change of a clock synchronization signal, the clock synchronization counting module adds 1 to the counting at the falling edge of each fast clock, when the rising edge of the next slow clock is in the previous fast clock period, the clock synchronous counting module stops counting and sends a new clock selection signal, and the clock switching module starts clock switching and completes clock switching when the rising edge of the next slow clock arrives. When the clock is switched, a switching point is adjusted to be within a fast clock period before a rising edge of a slow clock and is accessed by a low level, so that burr-free switching is ensured, and no obvious clock stop condition is ensured.

Description

Technical Field

[0001] The invention relates to the field of timers, and in particular to a continuous counting timer and a timing method thereof. Background Art

[0002] The driving clock of the timer generally uses one clock, and its frequency can be set and changed according to the needs. This situation is a homologous clock. However, when the driving clock used by the timer is a different clock, for example, the system uses a 32MHz fast clock in the working state, and uses a 32KHz clock output by the on-chip low-frequency clock generation circuit in the sleep state. The 32KHz slow clock and the 32MHz fast clock are different source clocks, that is, they come from two completely unrelated clock sources. At this time, the two clocks are completely asynchronous clocks, and the phases of the two clocks are completely random. When the clock is switched, in addition to ensuring that the clock switches without burrs, it is also necessary to try to ensure that the timer counting error during the switching process is low. Summary of the invention

[0003] In view of this, the present invention provides a continuous counting timer and a timing method thereof to solve the problem that the timer can still count accurately when different source clocks are switched.

[0004] In a first aspect, the present invention provides a continuous counting timer, comprising: a clock synchronization counting module, a clock switching module and a timing module, wherein the first input terminal and the second input terminal of the clock synchronization counting module input a slow clock and a fast clock, the third input terminal of the clock synchronization counting module inputs a clock synchronization signal, the first output terminal and the second output terminal of the clock synchronization counting module are connected to the first input terminal of the timing module and the third input terminal of the clock switching module; the first input terminal and the second input terminal of the clock switching module input a slow clock and a fast clock, and the output terminal of the clock switching module is connected to the second input terminal of the timing module; in the current slow clock cycle, if the clock synchronization counter When the counting module detects the change of the clock synchronization signal of the clock selection signal, the clock synchronization counting module adds 1 to the count at the falling edge of each fast clock. At the fast clock cycle before the rising edge of the next slow clock, the clock synchronization counting module stops counting and sends a new clock selection signal to the timing module and the clock switching module; when the clock switching module receives a new clock selection signal, the clock switching module starts clock switching and completes the clock switching before the rising edge of the next slow clock arrives; when the timing module receives a new clock selection signal, the timing module latches the current counting mode, and after the clock switching is completed, the timing module switches to the corresponding counting mode.

[0005] The present invention utilizes a new clock selection signal to select the driving clock of the timer during clock switching, and immediately switches the clock, wherein the switching point is adjusted to within a fast clock cycle before the rising edge of the slow clock, and is connected by a low level, thereby ensuring not only glitch-free switching but also no obvious clock stop.

[0006] In an optional embodiment, the continuous counting timer also includes: a clock frequency measurement module, wherein the first input terminal and the second input terminal of the clock frequency measurement module are respectively input with the fast clock and the slow clock, and the output terminal of the clock frequency measurement module is connected with the fourth input terminal of the clock synchronization counting module and the third input terminal of the timing module; the clock frequency measurement module is used to test the frequency ratio of the fast clock to the slow clock, and the frequency ratio is an integer. During the period when the slow clock switches to the fast clock, the timing module increases the timing by N at each rising edge of the slow clock, wherein N is the frequency ratio of the fast clock to the slow clock; during the period when the fast clock switches to the slow clock, the timing module increases the count by 1 at each rising and falling edge of the fast clock; when the clock switching is completed and driven by the fast clock, the timing module increases the count by 1 at each falling edge of the fast clock; when the clock switching is completed and driven by the slow clock, the timing module increases the timing by N at each rising edge of the slow clock.

[0007] The present invention uses the frequency ratio of the fast clock to the slow clock for timing when the slow clock is driven, thereby avoiding the situation where inaccurate timing is caused by the slow clock being affected by the system ambient temperature and the like.

[0008] In an optional embodiment, the timing module includes: an addend switching module, an adder and a register, wherein the first input end of the addend switching module is connected to the output end of the clock frequency measurement module, the second input end of the addend switching module inputs the value 1, the third input end of the addend switching module is connected to the first output end of the clock synchronization counting module, the output end of the addend switching module is connected to the first input end of the adder; the second input end of the adder is connected to the output end of the register, and the output end of the adder is connected to the input end of the register.

[0009] In an optional embodiment, the addend switching module includes: a multiplexer, wherein the first input terminal of the multiplexer is connected to the output terminal of the clock frequency measurement module, the second input terminal of the multiplexer inputs the value 1, the third input terminal of the multiplexer is connected to the first output terminal of the clock synchronization counting module, and the output terminal of the multiplexer is connected to the first input terminal of the adder.

[0010] In an optional implementation, the continuous counting timer further includes: a configuration module, wherein the configuration module is connected to the clock frequency measurement module and the register, and the configuration module is used to configure the test time of the clock frequency measurement module and the timing time of the timing module.

[0011] In a second aspect, the present invention provides a timing method for a continuous counting timer. The timing method for the continuous counting timer based on the first aspect and any optional implementation manner thereof includes: in the current slow clock cycle, determining whether the current clock selection signal is the same as the clock selection signal of the previous slow clock cycle; when the two are different, starting to count by 1 at the falling edge of each fast clock; in the fast clock cycle before the rising edge of the next slow clock, stopping counting and generating a new clock selection signal, and starting clock switching, and completing the clock switching before the rising edge of the next slow clock arrives; latching the current counting mode, and after the clock switching is completed, switching to the corresponding counting mode.

[0012] In an optional embodiment, the timing method of the continuous counting timer also includes: testing the frequency ratio of the fast clock to the slow clock; when accumulating the count under the drive of the fast clock, the timing is increased by 1 at each rising and falling edge of the fast clock; when accumulating the count under the drive of the slow clock, the timing is increased by N at each rising edge of the slow clock, where N is the frequency ratio of the fast clock to the slow clock.

[0013] In an optional implementation, the new clock selection signal is stored as a comparison signal with the clock selection signal of the next slow clock cycle.

[0014] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the timing method of a continuous counting timer of the above-mentioned second aspect or any corresponding embodiment thereof by executing the computer instructions.

[0015] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the timing method of a continuous counting timer of the above-mentioned second aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 This is a specific circuit structure diagram of the clock signal switching circuit of the related technology Figure 2 is a composition diagram of a continuous counting timer according to an embodiment of the present invention; Figure 3is a composition diagram of another continuous counting timer according to an embodiment of the present invention; Figure 4 It is a schematic diagram of the internal structure of the system; Figure 5 is a composition diagram of another continuous counting timer according to an embodiment of the present invention; Figure 6 is a waveform diagram of switching from a slow clock to a fast clock according to an embodiment of the present invention; Figure 7 is a waveform diagram of switching from a fast clock to a slow clock according to an embodiment of the present invention; Figure 8 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0019] Related technology For different source clock switching, because the switching time point is random and the phase of the two clocks is random, it is generally used Figure 1 Switching circuit or similar circuit to switch the clock, note: 1) Important principle of clock switching: first shut down the currently selected clock, then enable the newly selected clock.

[0020] 2) It is safer to switch when the current clock is low.

[0021] If the timer is driven by multiple clocks, the clock may disappear when the clock is switched. Figure 1 Commonly used clock switching circuits, this type of switching circuit will cause the clock after switching to have multiple target clock cycles without clock state, that is, the final clock output continues to be low level. After the clock switching is completed, the clock is restored and switched to the target clock. This will lead to serious consequences for application scenarios with very high timing accuracy requirements.

[0022] Based on this, a continuous counting timer is provided in this embodiment, such as Figure 2 As shown, it includes: a clock synchronization counting module, a clock switching module and a timing module.

[0023] like Figure 2As shown, the first input terminal and the second input terminal of the clock synchronization counting module input the slow clock and the fast clock, the third input terminal of the clock synchronization counting module inputs the clock synchronization signal, and the output terminal of the clock synchronization counting module is connected to the first input terminal of the timing module and the third input terminal of the clock switching module.

[0024] Specifically, when the system receives the clock selection signal, the system will synchronize the clock selection signal to the fast clock domain, and the synchronization time is about two fast clock cycles. The system may be an MCU chip or a SoC chip.

[0025] Specifically, the clock synchronization counting module will detect in real time whether the clock synchronization signal of the clock selection signal changes after each slow clock falling edge is delayed by a preset synchronization time. When a change is detected in the clock synchronization signal of the clock selection signal, the clock synchronization counting module starts timing. The preset synchronization time is the time for the slow clock to synchronize as a signal to the fast clock domain. Optionally, the preset synchronization time is at least two fast clock cycles.

[0026] Exemplarily, when the current slow clock is at a high level, the system receives a clock selection signal, and the clock synchronization counting module detects whether there is a change in the clock synchronization signal of the clock selection signal in two fast clock cycles after the falling edge of the current slow clock; when the current slow clock is at a low level, the system receives a clock selection signal, and the clock synchronization counting module detects whether there is a change in the clock synchronization signal of the clock selection signal in two fast clock cycles after the falling edge of the next slow clock.

[0027] Specifically, when the clock synchronization counting module does not detect any change in the clock synchronization signal of the clock selection signal, the clock synchronization signal of the clock selection signal of the current slow clock cycle is saved as a reference signal for the next slow clock cycle. The reference signal is used to compare with the clock synchronization signal of the clock selection signal of the next slow clock cycle. If the two have the same level, the clock synchronization counting module will not start. If the two have different levels, the clock synchronization counting module will start counting.

[0028] Specifically, when a change in the clock synchronization signal of the clock selection signal is detected, the clock synchronization counting module counts by 1 at the falling edge of each fast clock, and stops counting at the fast clock cycle before the rising edge of the next slow clock.

[0029] It should be noted that the clock synchronization counting module stops counting in a fast clock cycle before the rising edge of the next slow clock, where one fast clock cycle refers to a complete fast clock cycle.

[0030] like Figure 2 As shown, the first input terminal and the second input terminal of the clock switching module input the slow clock and the fast clock, and the output terminal of the clock switching module is connected to the second input terminal of the timing module.

[0031] In order to achieve glitch-free and continuous counting, the clock switching starts when the clock switching module receives a new clock selection signal, and the clock switching is completed when the next high level of the slow clock arrives. When the timing module receives a new clock selection signal, the timing module latches the current counting mode. After the clock switching is completed, the timing module switches to the corresponding counting mode, that is, in the process of switching from the slow clock to the fast clock, the timing module still maintains the counting mode driven by the slow clock, and in the process of switching from the fast clock to the slow clock, the timing module still maintains the counting mode driven by the fast clock.

[0032] Specifically, the counting method involves two types: clock switching completion and clock switching period: (1) During the period when the slow clock switches to the fast clock, the timing module accumulates counts when driven by the slow clock. During the period when the fast clock switches to the slow clock, the timing module accumulates counts when driven by the fast clock.

[0033] Specifically, in order to achieve that when the slow clock is driven, the timing module still accumulates counts under the slow clock drive, even in the fast clock cycle before the next slow clock arrives, even if the clock switching starts, the timing module still accumulates counts under the slow clock drive, and at this time it is necessary to latch the added value under the slow clock drive.

[0034] Similarly, in order to achieve that when the fast clock is driven, the timing module still accumulates counts under the fast clock drive, even when the fast clock before the next slow clock arrives, even if the clock switching starts, the timing module still accumulates counts under the fast clock drive, and at this time it is necessary to latch the added value driven by the fast clock.

[0035] (2) When the clock switching is completed, the timing module switches to the corresponding counting mode.

[0036] Specifically, when the clock switching is completed, when the clock is slow, the timing module accumulates the count under the drive of the slow clock, and when the clock is fast, the timing module accumulates the count under the drive of the fast clock.

[0037] In some optional embodiments, such as Figure 3 As shown, the continuous counting timer also includes: a clock frequency measurement module.

[0038] like Figure 3 As shown, the first input terminal and the second input terminal of the clock frequency measurement module are respectively input with the fast clock and the slow clock, and the output terminal of the clock frequency measurement module is connected with the fourth input terminal of the clock synchronization counting module and the third input terminal of the timing module; the clock frequency measurement module is used to test the frequency ratio of the fast clock to the slow clock before the fast clock switches to the slow clock, and the frequency ratio is an integer. Optionally, the clock frequency measurement module sets the time and number of the frequency ratio as needed, and is not limited here.

[0039] Specifically, in the current slow clock cycle, if the clock synchronization counting module detects that the clock synchronization signal of the clock selection signal has changed, the clock synchronization counting module adds 1 to the count at the falling edge of each fast clock. In the fast clock cycle before the rising edge of the next slow clock, the clock synchronization counting module stops counting and sends a new clock selection signal to the timing module and the clock switching module.

[0040] like Figure 4 As shown in the figure, the MCU chip or SoC chip generally integrates a low-frequency clock generation circuit (RCOSC), a CPU module (i.e., COU Sub-System), and a sleep timer (SleepTimer). The typical frequency of the low-frequency clock generation circuit is 32KHz, which is mainly used for the working clock of the MCU system in the sleep state, such as the sleep timer (SleepTimer) clock, the system wake-up (WakeUp) and other always-on modules (Always-On) working clocks, etc.

[0041] like Figure 4 As shown in the figure, there is at least one high-speed clock inside the MCU chip. This clock is input from the external crystal oscillator (i.e. Crystal Osc) into the chip and is used directly or through the on-chip PLL to generate a higher frequency clock. This type of clock has very high accuracy and the frequency deviation is generally below 10ppm. This type of clock can be regarded as a precise clock, which is mainly used as the working clock when the MCU chip is in working state. For MCU chips, the high-speed precise clock frequency is generally between 1MHz and 100MHz.

[0042] Based on this, in order to ensure that the timer can still accurately time when the system is in sleep state, that is, when driven by a slow clock, this embodiment calculates the number of fast clock cycles in a slow clock cycle when the system is asleep, that is, at each rising edge of the slow clock, the timing module accumulates N, where N is the number of fast clock cycles included in a slow clock cycle, that is, the frequency ratio. When the count reaches a preset threshold, the system is awakened. At the same time, when the system is in working state, the timing module can count by 1 at each rising and falling edge of the fast clock.

[0043] based on Figure 3 The structure shown, the counting method is: (1) When the slow clock switches to the fast clock, the timing module increases the timing by N at each rising edge of the slow clock; when the fast clock switches to the slow clock, the timing module increases the timing by 1 at each rising and falling edge of the fast clock.

[0044] (2) After the clock switch is completed and the fast clock is driven, the timing module increases the count by 1 at each rising and falling edge of the fast clock; after the clock switch is completed and the slow clock is driven, the timing module increases the count by N at each rising edge of the slow clock.

[0045] Based on the above counting method, it is determined whether the current clock selection signal is the same as the clock selection signal of the previous slow clock cycle. When the two are different, the count is increased by 1 at the falling edge of each fast clock; when the count reaches When N is an even number, the count reaches When N is an odd number, the stop counting value is The value to round down.

[0046] In some optional embodiments, such as Figure 5 As shown, the timing module includes: an addend switching module, an adder and a register.

[0047] like Figure 5 As shown, the first input end of the addend switching module is connected to the first output end of the clock frequency measurement module, the second input end of the addend switching module inputs the value 1, the third input end of the addend switching module is connected to the first output end of the clock synchronization counting module, and the output end of the addend switching module is connected to the first input end of the adder; the second input end of the adder is connected to the output end of the register, and the output end of the adder is connected to the input end of the register.

[0048] Specifically, refer to Figure 5 , the timing method is: (1) When the slow clock switches to the fast clock, the addend switching module outputs a frequency ratio to the adder; when the fast clock switches to the slow clock, the addend switching module outputs a value of 1 to the adder; (2) When the clock switching is completed and driven by a fast clock, the addend switching module outputs a value of 1 to the adder; when the clock switching is completed and driven by a slow clock, the addend switching module outputs a frequency ratio to the adder.

[0049] In some optional embodiments, the addend switching module includes: a multiplexer, wherein a first input terminal of the multiplexer is connected to an output terminal of the clock frequency measurement module, a second input terminal of the multiplexer inputs a numerical value 1, a third input terminal of the multiplexer is connected to a first output terminal of the clock synchronization counting module, and an output terminal of the multiplexer is connected to a first input terminal of the adder.

[0050] In some optional embodiments, the continuous counting timer also includes: a configuration module, wherein the configuration module is connected to the clock frequency measurement module and the timer, and the configuration module is used to configure the test time of the clock frequency measurement module, the timing time of the timing module, etc.

[0051] Based on the above method, the waveforms of switching from a slow clock to a fast clock and from a fast clock to a slow clock are as follows: Figure 6 , Figure 7 As shown, Figure 6 The waveforms from top to bottom are fast clock waveform, slow clock waveform, clock selection signal waveform, clock synchronization signal waveform of clock selection signal, clock synchronization counting module counting waveform, new clock selection signal waveform, clock switching module output waveform, timer counting waveform. Figure 7 The waveforms from top to bottom are the fast clock waveform, slow clock waveform, clock selection signal waveform, clock synchronization signal waveform of the clock selection signal, clock synchronization counting module counting waveform, new clock selection signal waveform, clock switching module output waveform, and timer counting waveform.

[0052] In this embodiment, a timing method of a continuous counting timer is provided. Based on the continuous counting timer of the above embodiment and any optional implementation manner thereof, the timing method includes: (1) In the current slow clock cycle, determine whether the current clock selection signal is the same as the clock selection signal of the previous slow clock cycle. If the two are different, start counting by 1 at the falling edge of each fast clock.

[0053] (2) At the fast clock cycle before the rising edge of the next slow clock, stop counting and generate a new clock selection signal, start clock switching, and complete the clock switching before the rising edge of the next slow clock arrives.

[0054] (3) Latch the current counting mode and switch to the corresponding counting mode after the clock switching is completed.

[0055] In some optional implementations, the timing method of the continuous counting timer further includes: Test the frequency ratio of the fast clock to the slow clock. When the count is accumulated under the fast clock drive, the timing is increased by 1 at each rising edge of the fast clock. When the count is accumulated under the slow clock drive, the timing is increased by N at each rising edge of the slow clock, where N is the frequency ratio of the fast clock to the slow clock.

[0056] In some optional implementations, the new clock selection signal is stored as a comparison signal with the clock selection signal of the next slow clock cycle.

[0057] Specifically, the timing method has been described in detail in the embodiments and implementation methods of the continuous counting timer, and will not be repeated here.

[0058] An embodiment of the present invention further provides a computer device having the above-mentioned continuous counting timer.

[0059] See also Figure 8 , Figure 8 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 8 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 8 A processor 10 is taken as an example.

[0060] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0061] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0062] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the use of a computer device based on the presentation of a small program landing page, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0063] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0064] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0065] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0066] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A continuous counting timer, characterized in that: include: Clock synchronization counting module, clock switching module and timing module, wherein: The first input terminal and the second input terminal of the clock synchronization counting module input the slow clock and the fast clock, the third input terminal of the clock synchronization counting module inputs the clock synchronization signal, and the first output terminal and the second output terminal of the clock synchronization counting module are connected to the first input terminal of the timing module and the third input terminal of the clock switching module; The first input terminal and the second input terminal of the clock switching module input the slow clock and the fast clock, and the output terminal of the clock switching module is connected to the second input terminal of the timing module; In the current slow clock cycle, if the clock synchronization counting module detects that the clock synchronization signal of the clock selection signal changes, the clock synchronization counting module counts by 1 at the falling edge of each fast clock, and in the fast clock cycle before the rising edge of the next slow clock, the clock synchronization counting module stops counting and sends a new clock selection signal to the timing module and the clock switching module; When the clock switching module receives the new clock selection signal, the clock switching module starts clock switching and completes the clock switching before the rising edge of the next slow clock arrives; When the timing module receives the new clock selection signal, the timing module latches the current counting mode, and after the clock switching is completed, the timing module switches to the corresponding counting mode.

2. The continuous counting timer according to claim 1, characterized in that: Also includes: Clock frequency measurement module, where The first input terminal and the second input terminal of the clock frequency measurement module are respectively input with the fast clock and the slow clock, and the output terminal of the clock frequency measurement module is connected with the fourth input terminal of the clock synchronization counting module and the third input terminal of the timing module; the clock frequency measurement module is used to test the frequency ratio of the fast clock to the slow clock, and the frequency ratio is an integer. During the period when the slow clock switches to the fast clock, the timing module increases the timing by N at each rising edge of the slow clock; during the period when the fast clock switches to the slow clock, the timing module increases the count by 1 at each rising and falling edge of the fast clock, where N is the frequency ratio of the fast clock to the slow clock; After the clock switching is completed and the fast clock is driven, the timing module counts up by 1 at each rising and falling edge of the fast clock; after the clock switching is completed and the slow clock is driven, the timing module counts up by N at each rising edge of the slow clock.

3. The continuous counting timer according to claim 2, characterized in that: The timing module includes: an addend switching module, an adder and a register, wherein: The first input end of the addend switching module is connected to the output end of the clock frequency measurement module, the second input end of the addend switching module inputs a value 1, the third input end of the addend switching module is connected to the first output end of the clock synchronization counting module, and the output end of the addend switching module is connected to the first input end of the adder; The second input terminal of the adder is connected to the output terminal of the register, and the output terminal of the adder is connected to the input terminal of the register.

4. The continuous counting timer according to claim 3, characterized in that: The addend switching module includes: a multiplexer, wherein: The first input end of the multiplexer is connected to the output end of the clock frequency measurement module, the second input end of the multiplexer inputs a value of 1, the third input end of the multiplexer is connected to the first output end of the clock synchronization counting module, and the output end of the multiplexer is connected to the first input end of the adder.

5. The continuous counting timer according to claim 3, characterized in that: Also includes: Configuration module, where The configuration module is connected to the clock frequency measurement module and the register, and is used to configure the test time of the clock frequency measurement module and the timing time of the timing module.

6. A timing method for a continuous counting timer, characterized in that: Based on the continuous counting timer according to any one of claims 1 to 5, the timing method comprises: In the current slow clock cycle, determine whether the current clock selection signal is the same as the clock selection signal of the previous slow clock cycle. If the two are different, start counting by 1 at the falling edge of each fast clock. At the fast clock cycle before the rising edge of the next slow clock, stop counting and generate a new clock selection signal, start clock switching, and complete clock switching before the rising edge of the next slow clock arrives; Latch the current counting mode, and switch to the corresponding counting mode after the clock switching is completed.

7. The timing method of a continuous counting timer according to claim 6, characterized in that: Also includes: Testing the frequency ratio of the fast clock to the slow clock; When the count is accumulated under the fast clock drive, the timing is increased by 1 at each rising and falling edge of the fast clock; When the count is accumulated under the driving of the slow clock, the timing increases by N at each rising edge of the slow clock, where N is the frequency ratio of the fast clock to the slow clock.

8. The timing method of a continuous counting timer according to claim 6, characterized in that: The new clock selection signal is stored as a comparison signal with the clock selection signal of the next slow clock cycle.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the timing method of the continuous counting timer according to any one of claims 6 to 8 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the timing method of the continuous counting timer according to any one of claims 6 to 8.

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