Memory system and method of operating memory system

Abstract

The present disclosure provides a memory system and a method of operating a memory system. The memory system is a memory system based on a 3D NAND flash memory having high capacity and / or capable of high efficiency. The memory system includes memory planes, each including a plane core and a particular set of resources. For each of the plurality of memory planes, the techniques provide a corresponding plane busy (PRDY) signal indicating a busy state or a ready state of a particular set of resources of the corresponding memory plane, and a corresponding plane in-operation (PIO #) signal indicating an in-operation state or an idle state of resources used by a plane core of the corresponding memory plane. Based on a state of one or more of the plurality of PRDY signals and the plurality of PIO # signals, issuing of memory commands by the controller and execution of memory commands for a memory plane of the plurality of memory planes are selectively permitted or rejected.

Description

Technical Field

[0001] The present disclosure relates to memory systems, and more particularly, to memories that support various types of memory operations. Background Art

[0002] In recent years, memory arrays (such as non-volatile memory arrays) have become increasingly dense and can store relatively more data. Typically, a memory (e.g., a relatively high-density memory) is divided into multiple physical segments, which may be referred to as memory planes. Thus, such a memory has multiple memory planes. Data stored in different planes may be unrelated (or may be related).

[0003] The challenge in such multi-plane memory is to provide overlapping access to different planes to the host. However, conventional memory operation command protocols typically prohibit issuing new embedded operation commands to non-operating planes, such as until the current embedded operation is completed or operating in the background in an operating plane. Summary of the invention

[0004] The present disclosure describes a memory technology (system) supporting multiple memory planes. Each memory plane includes a plane core and a corresponding specific resource set, and each memory plane is operable to (i) use the specific resource set of the corresponding memory plane and at least one of the resources of the plane core of the corresponding memory plane to perform a foreground operation and (ii) use the resources of the plane core of the corresponding memory plane to perform a background operation. The memory also includes: an input / output (I / O) interface for receiving a memory command from a host addressing one or more memory planes in the multiple memory planes; a state control circuit that generates a state bit corresponding to each memory plane in the multiple memory planes, the state bit indicating (i) one of a busy state and a ready state of the specific resource set used by the foreground operation of the corresponding memory plane and (ii) one of an operating state and an idle state of the resources of the plane core of the corresponding memory plane; and a control circuit that is operably coupled to the I / O interface, the state control circuit, and the multiple memory planes to perform memory operations using the multiple memory planes. When performing memory operations using one or more memory planes in the multiple memory planes, the control circuit generates a plurality of state bits corresponding to each memory plane in the state control circuit. In addition, the control circuit executes or refuses to execute the memory operation of the received memory command in response to the combination of the received memory command and multiple status bits in the status control circuit, including: executing or refusing to execute a first type of memory command, which depends on the combination of the busy state and ready state and the operating state and the idle state of all memory planes in the multiple memory planes; and executing or refusing to execute a second type of memory command addressed to a specific memory plane, which is irrelevant to the combination of the busy state and ready state and the operating state and the idle state of memory planes other than the specific memory plane in the multiple memory planes.

[0005] Furthermore, according to the present disclosure, foreground operations include operations involving at least one of: (i) a plane core of each memory plane controlling a specific set of resources for each memory plane; and (ii) resources of the plane core of each memory plane, and background operations (i) include operations involving resources of the plane core of each memory plane, and (ii) do not include operations involving the plane core of each memory plane controlling a specific set of resources for each memory plane in a plurality of memory planes.

[0006] According to the present disclosure, the specific resource set of each memory plane is a set of caches or specific registers of each memory plane, so that foreground operations prevent the host from accessing the caches or specific registers of each memory plane in multiple memory planes, and background operations do not prevent the host from accessing the caches or specific registers of each memory plane in multiple memory planes, wherein the caches or specific registers are not controlled by each plane core of each memory plane.

[0007] In addition, according to the present disclosure, the overlapping operation period is a period in which a new memory command is received by the control circuit while an existing background operation of a previous memory command is being executed, and the control circuit is configured so that during the overlapping operation period and when the new memory command has a higher priority than the previous memory command, the existing background operation is suspended to allow the foreground operation of the new memory command to be processed, and the suspended background operation is resumed after the foreground operation of the new memory command is completed.

[0008] According to the present disclosure, a new memory command with a higher priority may be a memory command that does not include a background operation.

[0009] In addition, according to the present disclosure, the overlapping operation period may be a period in which a new memory command is accepted by the control circuit while an existing background operation of a previous memory command is being executed, and the control circuit may be configured so that during the overlapping operation period and when the new memory command does not have a higher priority than the previous memory command, the foreground operation of the new memory command begins after the existing background operation is completed.

[0010] According to the present disclosure, a first type of memory command is used for a first selection type of operation. The first type of memory command is received by a control circuit to perform the first selection type of operation under the following circumstances: (i) the busy state and the ready state of a specific resource set used by the foreground operation in each memory plane among multiple memory planes are both ready; (ii) the operating state and the idle state of the resources of each plane core are both in operation according to another first type of memory command; and (iii) the first selection type of operation can be executed together with the existing background operation.

[0011] According to the present disclosure, a second type of memory command is used for a second type of operation on a target memory plane, and the second type of memory command is accepted by the control circuit to perform the second type of operation under the following circumstances: (i) the busy state and the ready state of a specific resource set used by a foreground operation in each memory plane of a plurality of memory planes are included in the ready state of the specific resource set in the target memory plane; and (ii) the operating state and the idle state of the resources of each plane core are included in the idle state of the resources of the plane core of the target memory plane.

[0012] In addition, according to the present disclosure, a second type of memory command is used for a second selected type of operation on a target memory plane, and the second type of memory command is accepted by the control circuit to perform the second selected type of operation under the following circumstances: (i) the busy state and the ready state of a specific resource set used by the foreground operation in each memory plane of a plurality of memory planes are included in the ready state of the specific resource set in the target memory plane; (ii) the operating state and the idle state of the resources of the plane core in the target memory plane are in operation according to another second type of memory command; and (iii) the second selected type of operation can be executed together with the existing background operation.

[0013] In addition, according to the present disclosure, a second type of memory command is used for a second selected type of operation on a target memory plane, and the second type of memory command is accepted by the control circuit to perform the second selected type of operation under the following circumstances: (i) the busy state and the ready state of a specific resource set used by the foreground operation in each memory plane of a plurality of memory planes are included in the ready state of the specific resource set in the target memory plane; (ii) the operating state and the idle state of the resources of the plane core in the target memory plane are in operation according to the first type of memory command; and (iii) the second selected type of operation can be executed together with the existing background operation.

[0014] According to the present disclosure, the first type of memory command is a synchronous chip operation (SCO), and the second type of memory command is an asynchronous independent plane operation (AIPO).

[0015] According to the present disclosure, a memory command includes a reset plane command for a target memory plane, wherein the reset plane command is accepted for execution by a control circuit when an operating state and an idle state of resources of a plane core in the target memory plane are in operation according to a second type of memory command, so that the ongoing second type of operation of the plane core of the target memory plane is terminated.

[0016] In addition, according to the present disclosure, a memory command includes a command that occupies a target memory plane among multiple memory planes and is accepted by the control circuit for execution when the busy state and the ready state include a ready state for a specific set of resources for the multiple memory planes, and when the operating state and the idle state include an operating state for resources of a plane core of the multiple memory planes.

[0017] According to the present disclosure, the plane core of one of the memory planes may be a 3D NAND flash memory.

[0018] In addition, according to the present disclosure, a plane core of one of the memory planes may be at least one of the following: a memory cell that stores data; an error free memory cell that includes an ECC circuit to correct data; a computation in memory (CIM) unit configured to perform data computing functions; and a memory cell configured to execute an in memory search (IMS) command.

[0019] According to the present disclosure, a memory system may be configured to execute an operation that occupies a target memory plane. During a first execution phase of the operation, the memory system may be configured to set the busy state and the ready state of the target memory plane to busy and set the operating state and the idle state of the target memory plane to operating for the foreground operation, regardless of the busy state and the ready state, the operating state and the idle state of multiple memory planes other than the target memory plane, and during a second execution phase of the operation, the memory system may be configured to change the busy state and the ready state of the target memory plane to ready for the background operation and keep the operating state and the idle state of the target memory plane as operating, regardless of the busy state and the ready state, the operating state and the idle state of multiple memory planes other than the target memory plane.

[0020] In addition, according to the present disclosure, during a pre-processing operation period of executing operations occupying a target memory plane that occurs before a first execution stage and a second execution stage, a busy state and a ready state of each memory plane in a plurality of memory planes may be set to busy and an operating state and an idle state of each memory plane in a plurality of memory planes may be set to operating.

[0021] According to the present disclosure, a method for operating a memory system is provided, wherein the memory system includes a plurality of memory planes, each memory plane includes a plane core and a corresponding specific resource set, and each memory plane is operable to (i) perform a foreground operation using the specific resource set of the corresponding memory plane and (ii) perform a background operation without the resource set of the corresponding memory plane. The method includes generating, for each memory plane of the plurality of memory planes, (i) a corresponding first status signal indicating a busy state or a ready state of a specific resource set used by a foreground operation of the corresponding memory plane, and (ii) a corresponding second status signal indicating an operating state or an idle state of the plane core of the corresponding memory plane.

[0022] Furthermore, according to the present disclosure, the method includes selectively allowing or denying execution of a memory command for a memory plane of the plurality of memory planes based on a state of one or more of the plurality of first state signals and the second state signal.

[0023] Other aspects and advantages of the present invention may be seen after reviewing the following figures, detailed description, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1A is a simplified block diagram of a data processing system having a multi-plane memory device as described herein.

[0025] Figure 1B is a simplified block diagram of an integrated circuit device having multiple planes with multiple bit states.

[0026] Figure 2A An example SCO operation is shown to access data from a memory array of two memory planes.

[0027] Figure 2B An example first type of SCO operation is shown.

[0028] Figure 3A Example AIPO operations are shown to access data from a memory array of two memory planes.

[0029] Figure 3B An example AIPO operation is shown.

[0030] Figure 4 An example memory system is shown that can perform background memory operations and foreground memory operations.

[0031] Figure 5 Example memory plane busy status signals (PxRDY) and example memory plane in-operation status signals (PxIO#) of various memory planes are symbolically shown.

[0032] Fig. 6A An example timing diagram of plane busy state signals and plane in-operation state signals in response to receiving an AIPO command is shown, where execution of the AIPO command includes a command pre-processing period during which all planes are in a busy (in-operation) state.

[0033] Figure 6B An example timing diagram of plane busy state signals and plane in-operation state signals in response to receiving an AIPO command is shown, wherein the AIPO command is executed without any command pre-processing period during which all planes are in the busy (in-operation) state.

[0034] Figure 7 An example timing diagram showing the plane busy status signal and the plane operating status signal in response to receiving a SCO command.

[0035] Fig. 8A An example timing diagram depicting issuing an AIPO memory command to an idle plane while another operating plane has a background operation in progress is shown, wherein Fig. 8A AIPO memory commands cause a command pre-processing period.

[0036] Figure 8B Another example timing diagram depicting issuing an AIPO memory command to an idle plane while another plane has a background operation in progress is shown, wherein Figure 8B The AIPO memory commands do not cause any command pre-processing period.

[0037] Fig. 9A and Fig. 9B An example timing diagram depicting the issuance of an AIPO memory command to a plane with an ongoing background operation is shown.

[0038] Fig.10 A timing diagram depicting the issuance of SCO memory commands and the resulting SCO background operations is shown.

[0039] Fig.11 An example timing diagram depicting ongoing SCO background operations and the issuance of AIPO commands and the issuance of SCO commands is shown.

[0040] Fig.12 A table summarizing the use of PxRDY and PxIO# for various memory operations is shown.

[0041] Fig.13 Shows the configuration (eg, cycle type) of the reset plane command.

[0042] Fig.14A and Fig. 14B A timing diagram depicting a scenario in which an AIPO memory command is issued to a memory plane that has no background operations in progress, while one or more other memory planes may have AIPO background operations in progress is shown.

[0043] Fig.15A and Fig. 15B Timing diagrams depicting various example scenarios for the issuance of AIPO commands are shown.

[0044] Fig.16A A timing diagram depicting an example of a SCO command is shown.

[0045] Fig. 16B Another timing diagram depicting an example of a SCO command is shown.

[0046] Fig.17 A timing diagram depicting other examples of SCO commands is shown, and also shows that some AIPO memory commands may not be issued when the plane is performing SCO background operations.

[0047] Fig.18A and Fig.18B A timing diagram depicting other examples of SCO commands is shown, and also depicts that some AIPO memory commands may be issued and executed concurrently with the plane performing SCO background operations.

[0048] Fig.19A , Fig.19B , Fig.19C as well as Fig.19D An example timing diagram of the plane busy state signals PxRDY of the planes P0 to P3 and the plane in-operation state signals PxIO# of the planes P0 to P3 in response to receiving each category of commands is shown.

[0049] Fig. 20 An example is shown in which a second SCO command is issued during the operation of a first SCO command.

[0050] Fig.21 An example is shown in which an AIPO command may be issued by the host and accepted at the memory device, suspending the operation of a previous SCO command.

[0051] Fig. 22 Commands accepting parameters and status signals showing an AIPO command sequence addressed to different planes.

[0052] Fig.23 The commands accepting parameters and status signals of an AIPO command sequence with overlapping operations are shown.

[0053] Fig.24 A command that calls an AIPO command sequence having a first stage foreground operation affecting multiple planes is shown accepting parameters and status signals.

[0054] Fig.25 A command that calls an AIPO command sequence having a first stage background operation affecting multiple planes is shown accepting parameters and status signals.

[0055] Fig.26 The command accepts parameters and status signals showing the SCO command sequence that invokes the foreground operation.

[0056] Fig. 27 The commands accepting parameters and status signals are shown for a SCO command sequence that invokes a background operation.

[0057] Fig.28 The command acceptance parameters and status signals of a SCO command sequence followed by an AIPO operation are shown.

[0058] Fig.29 is a flow chart illustrating control logic for accepting or rejecting commands and for updating status signals on an integrated circuit memory device as described herein.

[0059] Fig.30 is a flow chart illustrating an example of logic executed by a memory controller to issue commands depending on a status signal as described herein.

[0060] Fig.31 FIG. 1 is a flow chart showing example logic for accepting or rejecting SCO commands and AIPO commands.

[0061] Description of Reference Numerals

[0062] 10: Source device

[0063] 11, 12, 60: bus signal lines

[0064] 15, 16, 17, 18, 19, 20, 140: state control circuit

[0065] 50: Integrated circuit memory device

[0066] 51: Multi-plane NAND flash memory

[0067] 52: Bus interface

[0068] 55, 56, 57, 58: plane

[0069] 65: ΔR / B(I / I) line

[0070] 66. CE#: Chip enable line

[0071] 70: Controller Logic

[0072] 71: State Machine

[0073] 72: Multi-bit plane state control circuit / register

[0074] 73, 117: Command decoder

[0075] 74: Notification circuit

[0076] 100: Memory System

[0077] 101: Memory

[0078] 102a, 102b, 102c, 102d, ..., 102N, Pa~Pd: memory plane

[0079] 103a, 103b, ..., 103N: Planar core

[0080] 104a, 104b, 104c, 104d: memory array

[0081] 112a, 112b, ..., 112N: Cache

[0082] 116, 118: I / O interface

[0083] 119: Communication link

[0084] 120: Control circuit

[0085] 130: Host

[0086] 604a, 604b, 804, 904, 1104a, 1404a, 1404b, 1504a, 1504b, 1504c, 1604a, 1704b, 1804b, 1808b: AIPO command

[0087] 704a, 704b, 1004, 1104b, 1604b, 1604c, 1604d, 1704a, 1704c, 1804a, 1808a: SCO commands

[0088] 1400a, 1400b, 1500a, 1500b, 1600a, 1600b, 1700, 1800a, 1800b: Timing diagram

[0089] 1190: Table

[0090] 2900, 2901, 2902, 2903, 2910, 2911, 2912, 2913, 2920, 2922, 2923, 3000, 3001, 3002, 3003, 3010, 3020, 3021, 3022, 3023, 3024, 3050: Steps

[0091] 3100, 3102, 3104, 3106, 3108, 3110, 3112, 3114, 3118, 3120, 3122: Operation

[0092] CLK: Clock

[0093] I / O BUS1, I / O BUS2: bus

[0094] I / O[7:0]: data line

[0095] NAND 1, NAND 2, ..., NAND m, NAND n: multi-plane memory devices

[0096] OP1, OP2, OP3, OP4, OP5, OP6: Operation

[0097] PaIO#, PbIO#, PcIO#, PdIO#, PNIO#, PxIO#: Status signals in memory plane operation

[0098] PaRDY, PbRDY, PcRDY, PdRDY, PNRDY, PxRDY: Memory plane busy status signals

[0099] P0IO#, P1IO#, P0RDY, P1RDY: Status bits

[0100] RE#: Read Enable

[0101] t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t601a, t601b, t602a, t603a, t603b, t604a, t604b, t702, t706, t708, t802a, t802 b. t803a, t902a, t902b, t903a, t1001, t1002, t1003, t1104, t1402a, t1402b, t1403a, t1501a, t1502a, t1503a, t1504 a, t1505a, t1506a, t1507a, t1501b, 1503b, 1504b, 1506b, t1601a, t1602a, t1603a, t1604a, t1605a, t1605a1, t1606a, t1607a, t1701, t1702, t1703, t1704, t1801a, t1802a, t1803a, t1804a, t1806a, t1801b, t1802b, t1803b, t1806b: time DETAILED DESCRIPTION

[0102] A detailed description of embodiments of the present invention is provided with reference to the drawings.

[0103] Figure 1A 1 is a simplified diagram of a data processing system such as a memory system having a communication network with a bus topology to provide an example of a data processing system in which the present invention can be deployed. The system includes a source device 10 (e.g., a host communicating with a memory device) having a bus master interface for multiple buses I / O BUS1 and I / O BUS2, each of which includes a set of bus signal lines 11 and 12. The device may be a memory controller implementing, for example, a flash translation layer.

[0104] Figure 1AThe system shown in can be connected to an extensive network that maintains system data flow to and from the memory devices. For example, source device 10 can include a data port, such as a universal serial bus port, for connecting to an external computer.

[0105] A first group of multi-plane memory devices NAND 1, multi-plane memory devices NAND 2, ..., multi-plane memory devices NAND n are disposed on I / O BUS 1. A second group of multi-plane memory devices NAND 1, multi-plane memory devices NAND 2, ..., multi-plane memory devices NAND m are disposed on I / O BUS 2. Multi-plane memory devices NAND 1, multi-plane memory devices NAND 2, ..., multi-plane memory devices NAND n include a bus slave interface to a bus signal line on I / O BUS 1. Multi-plane memory devices NAND 1, multi-plane memory devices NAND 2, ..., multi-plane memory devices NAND n each have a state control circuit 15, a state control circuit 16, a state control circuit 17 to generate a plurality of state bits for each memory plane or for at least one of the memory planes in the device. Multi-plane memory devices NAND 1, multi-plane memory devices NAND 2, ..., multi-plane memory devices NAND m include a bus slave interface to a bus signal line on I / O BUS 2. The multi-plane memory devices NAND 1, NAND 2, ..., NAND m each have a state control circuit 18, a state control circuit 19, a state control circuit 20 to generate a plurality of state bits for each memory plane or for at least one of the memory planes in the device.

[0106] The bus signal lines on I / O BUS1 include a group of chip enable lines, marked as CE#, with one chip enable line for each device NAND 1, device NAND 2, ..., device NAND n in the first group. The bus signal lines on I / O BUS2 include a group of chip enable lines, marked as CE#, with one chip enable line for each device NAND 1, device NAND 2, ..., device NANDm in the second group.

[0107] The bus signal lines on I / O BUS1 include a set of ready / busy (in operation / idle) notification lines, labeled as ΔR / B(I / I) lines, one ready / busy (in operation / idle) notification line for each device NAND1, device NAND2, ..., device NAND n in the first group. The bus signal lines on I / O BUS2 include a set of ready / busy (in operation / idle) notification lines, labeled as ΔR / B(I / I) lines, one ready / busy (in operation / idle) notification line for each device NAND1, device NAND2, ..., device NAND m in the second group. In other embodiments, a set of devices on a given bus, such as device NAND1, device NAND2, ..., device NAND n in the first group, have notification pins connected to a shared single line on the bus, which can be identified as being generated by a specific device by, for example, combining with a chip enable line.

[0108] In some examples, device 10 may have only one connected multi-plane memory device.

[0109] A multi-plane NAND device or at least one thereof includes multiple memory planes, wherein each memory plane includes: (i) a specific set of resources, such as a cache or register set, for supporting memory operations using the corresponding memory plane; and (ii) resources of the plane core for supporting memory operations using the corresponding memory plane.

[0110] The source device 10 includes logic implemented by circuitry, such as a programmed processor, programmable logic, or dedicated logic circuits, or a combination thereof, to issue memory commands to connected memory devices. The logic to issue memory commands is responsive to the expected ready / busy (operating / idle) status of resources of a particular set (plane core) of each of a plurality of memory planes. In addition, the source device includes logic to issue commands to read the status in the connected memory devices to update the expected ready / busy (operating / idle) status. The expected ready / busy (operating / idle) status may be maintained by the logic by creating a table that is populated when issuing commands, the table in some cases having information provided by the ready / busy (operating / idle) notification pin.

[0111] In this example, the source device 10 includes: a bus interface including a plurality of lines for command, address, and data communications with a connected memory device; and an interface including lines for connection to a notification pin on the connected memory device to indicate a change in at least one current combination of a current ready / busy (operating / idle) state of a particular set of resources of a plurality of memory planes and a plane core. In a system including a notification pin, logic for issuing a command to read the status may respond to a signal on the notification pin. The result of the read of the status may be used to update the expected ready / busy (operating / idle) state at the device 10.

[0112] refer to Fig.30 An example of logic used to issue commands in this setting is described.The provided techniques enable the use of multiple commands in multiple combinations of ready / busy (operating / idle) states of planes in a multi-plane memory device, several examples of which are described herein.

[0113] Figure 1B 1 is a simplified block diagram of an integrated circuit memory device 50 including multi-plane NAND memory (e.g., a multi-plane device that may include multiple cores for searching in memory). The integrated circuit device 50 may be implemented on a single integrated circuit chip, or on multiple integrated circuit chips in a multi-chip package configuration. The integrated circuit memory device 50 in the example includes a multi-plane NAND flash memory 51. The memory has multiple planes (55, 56, 57, 58) labeled P[3:0]. The multi-plane NAND flash memory 51 is connected for data communication with a bus interface 52 or other type of input / output I / O circuitry. The bus interface 52 may be, for example, a bus slave interface, such as a reference Figure 1A Discussed. Figure 1B Further shown is a host 130 (such as Figure 1A The device 10) communicates with the integrated circuit memory device 50 using the communication link 119. The operations performed by the integrated circuit memory 50 and the host 130 can be categorized as follows: Figure 4 Detailed discussion of background and foreground operations.

[0114] In this example, bus signal lines 60 include bus control signals, such as clock CLK and read enable RE#. In addition, the bus signal lines include data lines I / O[7:0]. In this illustration, there are eight data lines. In other embodiments, there may be a different number of data lines and different types and quantities of control signal lines to suit a particular bus system configuration. The bus may include other signal lines not shown, such as a bus clock line and bus power and ground lines.

[0115] The bus interface 52 is connected to controller logic 70 on the integrated circuit device 50. In this example, the controller logic 70 includes a multi-bit plane state control circuit 72 and a command decoder 73.

[0116] The bus interface 52 includes pins or other connections for connecting to the bus signal line 60, to the chip enable CE# line 66, and to the ΔR / B (I / I) line 65 for ready / busy notification. The ready / busy notification is a signal generated in the notification circuit 74 after detecting a change in the combination of ready / busy status signals in the registers 72 of the multiple planes. The bus signal line 60, the chip enable CE# line 66, and the ΔR / B (I / I) line 65 can be part of the communication link 119. The communication link 119 can be used to convey additional information between the integrated circuit memory device 50 and the host 130.

[0117] The bus interface 52 receives commands from the bus and applies them to the command decoder 73. The controller logic applies the decoded command signal to the state machine 71, which operates. The state machine includes a register or other signal source to indicate the state of the operation being performed, and includes circuits to maintain state bits in the multi-bit plane state control circuit 72. The state machine 71 may include multiple instances of the state machine for a particular operation, such as one instance for each memory plane.

[0118] The controller logic 70 includes operational circuitry, such as a state machine and dedicated circuitry, to perform memory operations in response to commands received at the bus interface 52. The multi-bit plane state control circuitry 72 includes more than one state bit per plane in the plurality of planes 55, 56, 57, 58. Combinations of state bits for particular planes in the plurality of planes 55, 56, 57, 58 and for more than one of the planes and for all planes, along with the operation identified by the command received at the interface 52 and, in some embodiments, along with the type of operation currently being performed in the plurality of planes, may be applied by the controller logic 70 to accept and reject commands received at the bus interface 52 for execution, examples of which are described herein.

[0119] More generally, Figure 1BThe device 50 is an example of a memory device having an input / output (I / O) interface for receiving data and memory commands addressed to one or more memory planes of a plurality of memory planes and for outputting data; a state control circuit; and a control circuit operatively coupled to the I / O interface, the state control circuit, and the plurality of memory planes to perform memory operations (e.g., compute-in-memory (CIM) operations, search-in-memory (IMS) operations, etc.) using the plurality of memory planes. Even if not explicitly stated, all memory operations described herein may be operations including, for example, compute-in-memory (CIM) operations, search-in-memory (IMS) operations, etc. When performing memory operations using one or more memory planes of the plurality of memory planes, the control circuit generates a plurality of state bits in the state control circuit linked to each memory plane of the plurality of memory planes, the plurality of state bits linked to each memory plane indicating a particular set of resources of each memory plane of the plurality of memory planes and a plurality of different combinations of ready / busy (in-operation / idle) states of the plane core. In addition, the control circuit executes or refuses to execute the memory operation of the received memory command in response to the combination of the received memory command and the plurality of status bits. In the status control circuit, it includes: executing or refusing to execute a first type of memory command, which depends on the combination of the ready / busy (operating / idle) status of all memory planes in the plurality of memory planes; and executing or refusing to execute a second type of memory command addressed to a specific memory plane, and is irrelevant to the combination of the ready / busy (operating / idle) status of memory planes other than the specific memory plane in the plurality of memory planes.

[0120] refer to Fig.29 Examples of logic to receive and reject commands in this setting are described.The provided techniques enable the use of multiple commands in multiple combinations of ready / busy (operating / idle) states of planes in a multi-plane memory device, several examples of which are described herein.

[0121] Simultaneous chip operation (SCO) or parallel multi-plane operation

[0122] Figure 2A An example synchronous chip operation (SCO) is shown for accessing data from memory arrays 104b, 104d of two example memory planes 102b and 102d, respectively. In an example, the SCO operation is not limited to a specific memory plane or memory array, and may occupy multiple (such as, all) memory planes and / or memory arrays.

[0123] exist Figure 2AIn the example of , it is assumed that four memory planes 102a, ..., memory plane 102d (Pa to Pd) exist in a memory 101 (e.g., a multi-plane device that may include multiple cores for in-memory computing (CIM) and in-memory searching (IMS)), and the memory 101 receives commands and data from a host (not shown), wherein the memory array 104a of the memory plane 102a may store data, the memory array 104b of the memory plane 102b may store data, the memory array 104c of the memory plane may store data, and the memory array 104d of the memory plane 102d may store data. The data stored by the memory arrays 104a, 104b, 104c, and 104d may be any appropriate type of data.

[0124] For example, at time t0 and according to operation OP1, data is being accessed from memory plane 102a, memory plane 102b, and memory plane 102d. At time t1 and according to operation OP2, a request is issued to access data from memory plane 102a and memory plane 102c. However, Figure 2A SCO is shown, where operations performed in one memory plane depend on the state of other memory planes, for example due to one or more shared resources in memory 101. For example, if SCO is being executed in one memory plane, operations on one or more other planes cannot be executed. The host cannot read data from the idle memory plane until all internal operations are completed. After issuing the SCO command, the memory chip becomes busy and cannot accept new embedded operation commands during the busy period. Depending on the command, the memory chip will return to the ready state after the current embedded operation is completed or the cache data input / output for all planes is ready (idle). Only when the chip is ready and idle (that is, all planes are idle) after the SCO is completed, or when the chip is ready and operating (that is, all planes are ready and operating) in the case of SCO with background operation, the host can issue a new embedded operation command that can be executed by the memory chip. In order to determine whether to issue a command to call SCO, the host can check the chip (or plane) busy state PRDY and the chip (or plane) operating state PIO#. Since SCO occupies multiple planes in parallel, SCO is also called parallel multiple plane operation. Operation OP1 and operation OP2 may be any type of memory operation (eg, read, write, etc.).

[0125] Therefore, although operation OP2 is requesting access to data from memory plane 102a and memory plane 102c at time t1, the request cannot be executed immediately, for example, because SCO (e.g., accessing data) is currently being executed in memory plane 102a, memory plane 102b, and memory plane 102d according to operation OP1. Once access to data according to operation OP1 is completed at time t2, access to data from memory plane 102a and memory plane 102c according to operation OP2 begins at time t2.

[0126] Figure 2B An example of SCO is shown. In the example, the operation of each plane starts at the same time, that is, it is synchronized.

[0127] Specifically, if Figure 2B As shown in , starting at time t0, SCO OP1 (e.g., the same type of operation) is performed in each of memory plane a, memory plane b, and memory plane d. Once OP1 is completed in memory plane a, memory plane b, and memory plane d, OP2 may be performed in, for example, memory plane a and memory plane c. Other types of SCOs will be apparent to those skilled in the art.

[0128] Asynchronous Independent Plane Operation (AIPO) or Overlapped Independent Plane Operation

[0129] Figure 3A An example asynchronous independent plane operation (AIPO) is shown for accessing data from the memory array 104a of the memory plane 102a and the memory array 104c of the memory plane 102c. Figure 2A ,exist Figure 3A In the example of FIG. 1 , it is assumed that four memory planes 102 a, . . . , 102 d (Pa to Pd) exist in the memory 101, wherein the memory arrays 104 a, 104 b, 104 c, and 104 d store data. The data stored by the memory arrays 104 a, 104 b, 104 c, and 104 d may be any appropriate type of data.

[0130] From time t0 and according to operation OP1, data may be accessed from memory plane 102a. At time t1 and according to operation OP2, a request may be issued to access data from memory array 104c of memory plane 102c. Figure 3AAsynchronous independent plane operation (AIPO) (also referred to herein as overlapping independent plane operation) is shown, where operations can be performed in one memory plane without regard to or affecting the state of other memory planes. In AIPO, each plane can start any operation at any time as long as the selected plane is ready for the embedded operation command. Therefore, AIPO can be performed in the plane regardless of the state of other planes. That is, the host can issue an embedded operation command to a specific memory plane that can be executed by the memory as long as the specific plane is ready (and regardless of the readiness state of other planes). For AIPO, the host can treat each plane as an independent memory unit, and the host checks the plane busy status PRDY and the plane operating status PIO# for the progress of the operation in each plane. For example, if an AIPO operation is being performed in one memory plane, another AIPO operation on another memory plane can be performed in an overlapping manner. Therefore, AIPO memory operations allow operations to be performed overlappingly or at least partially simultaneously in more than one memory plane.

[0131] Therefore, when data is requested at time t1, the request is executed immediately, for example, when an AIPO (eg, accessing data) is currently being executed in memory plane 102a. Therefore, access to data from memory plane 102c begins at time t1, such as Figure 3A Thus, the host may access a non-busy plane (eg, plane 102c) for new data while another memory operation is still being performed in another busy plane (eg, plane 102a).

[0132] Figure 3B Example AIPO operations are shown. In the example, AIPO operations (OP1, OP2, OP3, OP4, OP5, and OP6) for different planes (memory plane a, memory plane b, memory plane c, and memory plane d) may start at different times (t0, t1, t2, t3, t4, and t5). For example, OP1 starts at time t0 in memory plane a, OP2 starts at time t1 in memory plane c, OP3 starts at time t2 in memory plane b, OP4 starts at time t3 in memory plane d, OP5 starts at time t4 in memory plane a, and OP6 starts at time t5 in memory plane b. As shown. AIPO operations are asynchronous in nature.

[0133] Supports both SCO and AIPO operation protocols

[0134] As will be discussed in greater detail later herein, in embodiments, the techniques described herein support both SCO operations and AIPO operations.

[0135] Background memory operations and foreground memory operations

[0136] Figure 4 An example memory system 100 is shown in order to explain the difference between background memory operations and foreground memory operations performed. The memory system 100 may be, for example, a multi-plane device that may include multiple cores for compute in memory (CIM) and search in memory (IMS), and may include error-free chips such as enabled by ECC circuits. Any memory system described herein may be the same type of memory system as the memory system 100. The IMS operation or command allows the host to input target data for data search, and the memory system 100 may search for matching or highly matching data in the target data area and then further report the data location to the host. One application of the IMS operation or command may include face recognition.

[0137] In the description Figure 4 Before the background operation of Figure 4 and Figure 5 The overall architecture of the memory system 100 shown in the two. The memory system 100 may include a memory system 101, wherein the memory system 101 includes a plurality of memory planes 102a, 102b, ..., 102N (similar to Figure 1B Integrated memory device 50).

[0138] Elements mentioned herein that have a common reference number followed by a number or letter may be collectively referred to by the reference number alone. For example, memory plane 102a, memory plane 102b, ..., memory plane 102N may be collectively and generally referred to as memory plane 102 in the plural (or as memory plane 102(aN)), and memory plane 102 in the singular.

[0139] The memory 101 may be distinct from another integrated circuit that includes the host 130. In another embodiment, the host 130 and the memory 101 are on the same single IC chip or multi-chip package.

[0140] Memory 101 may be of any suitable type, such as non-volatile NAND memory, non-volatile NOR memory, or the like. In an example, memory 101 is a three-dimensional (3D) memory including vertically stacked memory cells in individual planes. As an example, memory 101 may be a NAND flash memory.

[0141] Each memory plane 102 (memory plane 102a, memory plane 102b, ..., memory plane 102N) includes a corresponding plane core 103 (plane core 103a, plane core 103b, ..., plane core 103N). Each plane core 103 may be a memory unit for storing data, an error-free memory unit (which includes an ECC circuit for correcting data), a CIM unit for performing data calculation functions, a memory unit that can perform searches in memory, etc. Each plane core 103 communicates with each cache 112 (cache 112a, cache 112b, ..., cache 112N). The cache 112, which may be a cache memory or a register set, communicates with an I / O interface 116. Each cache 112 may store data from a host 130 or each plane core 103. The stored data may be original data or calculated data from a memory array. When cache 112 is a register set, a register set may be a group of registers that stores results from an operation, such as IMS results or CIM results. Each cache 112 may be referred to as a specific resource set.

[0142] If a specific resource set (e.g., cache 112a, which may be a cache memory or a register set) is controlled by a corresponding plane core (e.g., plane core 103a), the host 130 cannot access the memory plane (e.g., memory plane 102a). This may be referred to as a foreground operation period, during which the memory plane is busy (e.g., cache 112a is controlled by plane core 103a and plane core 103a is in operation). If the specific resource set is not being controlled by the corresponding plane core, the memory plane is ready (e.g., a background operation period or an idle period). In other words, the busy state and the ready state of the memory plane are specified by whether the corresponding plane core is controlling the specific resource set of the corresponding plane. If the specific resource set is being controlled, the memory plane is busy, and if the specific resource set is not being controlled, the memory plane is ready. If the plane core is in operation, the operating / idle state of the corresponding memory plane is "in operation" (foreground and / or background operation period), otherwise, the state of the corresponding memory plane is idle (idle period).

[0143] In this example, the memory plane is configured to have two sets of status indicators. In other embodiments, there may be more than two sets of status indicators, where each status indicator may be one or more bits.

[0144] The memory 101 also includes one or more status control circuits 140, for example, to generate one or more status signals for each plane (plane x, for a memory having N planes, x can be from 0 to N-1), such as a plane busy status (PxRDY), a plane operating status (PxIO#), etc., as will be discussed later herein. For each memory plane (e.g., memory plane 102a), the plane busy status (PxRDY) indicates busy (0) when a specific resource set (e.g., corresponding cache 112a) is controlled by a corresponding plane core (e.g., plane core 103a), and indicates ready (1) when the specific resource set is not controlled by the corresponding plane core. When the memory plane is busy, the host 130 cannot access the memory plane (e.g., during a foreground operation period). When the memory plane is ready (1), the host 130 can access the memory plane (e.g., during a background operation period or an idle period). In addition, for each memory plane (e.g., memory plane 102a), the operating status (PxIO#) indicates operating (0) when each plane core (e.g., plane core 103a) is in operation (foreground operation period or background operation period), and indicates idle (1) when the plane core is not in operation.

[0145] The memory 101 may further include one or more hardware notification pins dedicated to outputting the status of one or more signals.

[0146] The memory 101 also includes an input / output (I / O) interface 116 coupled to the caches 112a, ..., cache 112N (also referred to as a specific resource set). Each cache 112 receives data from the I / O interface 116 and writes the data to the corresponding plane core 103, and receives data from the corresponding plane core 103 and writes the data to the I / O interface 116.

[0147] In an example, the host 130 generates and transmits memory commands to the memory 101, stores data to the memory 101, and receives data from the memory 101. For example, the host may be a memory controller that implements a flash translation layer.

[0148] In an example, the memory 101 communicates with the host 130, for example, via a communication link 119. The communication link 119 may be any suitable communication link, such as a link over a wired connection. The host 130 includes an I / O interface 118, which is coupled to the I / O interface 116 of the memory 101 via the communication link 119. Thus, the host 130 stores data to and reads data from the memory array of the memory plane via the I / O interface 118, the communication link 119, the I / O interface 116, the corresponding cache 112, and the corresponding page buffer 108 associated with the memory plane.

[0149] In an embodiment, memory 101 also includes control circuitry 120 that controls various aspects of the operation of memory 101. In an embodiment, control circuitry 120 issues various memory status commands, as will be discussed later herein.

[0150] In this example, memory 101 includes a command decoder 117 in communication with I / O interface 116. Command decoder 117 decodes commands received at the I / O interface in cooperation with state control circuitry 140. Command decoder 117 signals control circuitry 120, which provides circuitry for performing the operation identified by the command.

[0151] The memory 101 has many other components that are not shown for purposes of clarity of illustration and so as not to obscure the description of the present disclosure.

[0152] As previously mentioned, the memory system 100 can perform background memory operations and foreground memory operations.

[0153] Background memory operations (also referred to as background operations) are those memory operations (of memory 101 of memory system 100) during which selected memory commands may be accepted while the resource set (cache 112) is not being controlled by the corresponding plane core. In other words, even though the corresponding plane core 103 may be executing a background operation, during the background operation (e.g., while the background operation is being executed), the host 130 may access or issue new commands to the memory plane 102 via, for example, cache 112. For example, the host 130 may provide new commands to cache 112 during the background operation. Furthermore, for example, the selected memory command (operation) may be accepted while PxRDY is ready (1), even though the background operation is still being executed and the corresponding plane core is in operation. Once the background operation is completed, any memory command may be accepted. During background operations, PxRDY indicates ready (1) because a particular set of resources (eg, cache 112) is not being controlled by the plane core, and PXIO# indicates in operation (0) because the plane core 103 is busy.

[0154] Foreground memory operations (also referred to as foreground operations) are those memory operations (of memory 101) during which only system management commands can be accepted because the resource set (cache 112) is being controlled by the plane core 103 (e.g., PxRDY=Busy(0)) and because the plane core is in operation (PxIO#=Operation(0)). During foreground operations, the host 130 cannot access or issue new commands to the memory plane 102 except for system management commands. For example, during foreground operations, the cache 112 cannot be accessed by the host 130 because the cache 112 may be occupied by the foreground operation. System management commands may be issued at any time.

[0155] Figure 5 Example memory plane busy status signals (PxRDY) and example memory plane in-operation status signals (PxIO#) of various memory planes are symbolically shown. Figure 5 All other reference components are Figure 4 The reference components are the same.

[0156] Acceptance / rejection of the first set of commands (or first commands) depends on the operation of all memory planes 102, and acceptance / rejection of the second set of commands (or second commands) depends on the operation of the target memory plane. Based on the fact that the memory system 100 may be aware of the ongoing operations being performed or executed thereon, commands may be accepted or rejected according to the following rules: (i) if there is no operation on any plane core 103 (i.e., all operating / idle status signals = idle), both SCO (Type 1) commands and AIPO (Type 2) commands may be accepted; (ii) if a SCO operation is still in progress (all operating / idle status signals = operating), the selected SCO command may be accepted if all memory planes are ready, or the selected AIPO command (without background operation) may be accepted to a memory plane identified as ready; and (iii) if an AIPO operation is still in progress (at least for one plane core, operating / idle status signal = operating), any AIPO command may be accepted for an idle plane core (for the target plane core, operating / idle status = idle), the selected AIPO command may be accepted for a ready memory plane with an operating plane core, and all SCO commands may be rejected.

[0157] Types of memory commands and memory operations

[0158] Table 1 below herein illustrates various example memory commands and their corresponding types and categories that may be implemented by the memory system 100 discussed throughout this disclosure.

[0159] Table 1

[0160]

[0161] The first row of Table 1 lists the serial numbers corresponding to various memory commands. The second row of Table 1 lists the memory commands. The third row of Table 1 indicates the type of operation, such as whether the memory command is AIPO or SCO. For example, a cache read random memory command (e.g., which can be used to read data from the cache) is an AIPO memory command.

[0162] The fourth row of Table 1 indicates whether the memory command includes, requires and / or causes background operations. If the operation is identified as "without" background operations, the operation does not include any background operations (but it does include foreground operations). For example, during an operation "without" background operations (e.g., foreground operations), new command acceptance is not allowed (except for system management commands), the busy status signal PxRDY indicates busy and the operating status signal PxIO# indicates operating. If the operation is identified as "with" background operations, the operation includes background operations. For example, during an operation "with" background operations (e.g., foreground operations), during the foreground operations, new command reception is not allowed (except for system management commands), the busy status signal PxRDY indicates busy and the operating status signal PxIO# indicates operating, then after the foreground operation is completed, for example, new command acceptance is allowed, the busy status signal PxRDY indicates ready, but the operating status signal PxIO# indicates operating.

[0163] The fifth row of Table 1 classifies each memory command into a corresponding one of five possible categories. The last column of Table 1 identifies the possible categories. For example, category 1 refers to SCO memory commands without (e.g., not including) background operations, category 2 refers to SCO memory commands with (e.g., including) background operations, category 3 refers to system management commands, category 4 refers to AIPO memory commands without (e.g., not including) background operations, and category 5 refers to AIPO memory commands with (e.g., including) background operations.

[0164] For example, when a background operation of a cache read operation is in progress: (i) a cache read random command may be issued / accepted, (ii) a cache read end random command may be issued / accepted, and (iii) a system management command (e.g., a reset plane command) may be issued / accepted. Furthermore, for example, when a background operation of a cache program operation is in progress: (i) a page program command may be issued / accepted, (ii) a cache program command may be issued / accepted, and (iii) a system management command (e.g., a reset command or a reset LUN command) may be issued / accepted.

[0165] Memory plane busy status signal (PxRDY) and memory plane operation status signal (PxIO#)

[0166] In an embodiment, various planes of memory 101 (or control circuit 120) issue various status signals, for example to indicate whether the first resource set and the second resource set in the corresponding memory plane 102 are ready to perform a new memory operation, or are busy performing a current memory operation and cannot accept a new memory operation.

[0167] For example, one such status signal is a memory plane busy status signal (PxRDY) issued for various memory planes Px, where the "x" in Px is the index of the corresponding memory plane. For example, for memory plane 102a, the memory plane busy status signal is PaRDY; for memory plane 102b, the memory plane busy status signal is PbRDY; for memory plane 102N, the memory plane busy status signal is PNRDY, and so on. In general, the signal PxRDY indicates whether the memory plane 102x is in a busy state or a ready state, as will be discussed in more detail later herein.

[0168] For example, when the PxRDY signal indicates that the memory plane is in a busy state (e.g., a value of 0), the plane cannot be accessed (while a foreground operation is in progress in the plane), and when the PxRDY signal indicates that the memory plane is not in a busy state (e.g., in a ready state; represented by a value of 1), the plane can be accessed and new commands received (no foreground operation is in progress in the plane). In other words, when a foreground operation is being executed, the PxRDY signal will indicate that a particular plane is in a busy state (e.g., a value of 0), and when a foreground operation is not being executed, the PxRDY signal will indicate that the particular plane is in a ready state (e.g., a value of 1).

[0169] Another such status signal is a memory plane in-operation status signal (PxIO#) issued for various memory planes, where the "x" in PxIO# is the index of the corresponding memory plane. For example, for memory plane 102a, the plane in-operation status signal is PaIO#; for memory plane 102b, the plane in-operation status signal is PbIO#; for memory plane 102N, the plane in-operation status signal is PNIO#, and so on. In general, the signal PxIO# indicates whether the memory plane is in operation or in idle. For example, when the PxIO# signal indicates that the memory plane is in operation (e.g., value 0), there is a foreground operation or background operation in progress in the selected plane, and when the PxIO# signal indicates that the memory plane is idle (e.g., not in operation; value 1), no operation is in progress in the memory plane.

[0170] Whether a particular memory plane can receive and execute new memory commands at any given time is based on the PxRDY and / or PxIO# of the particular memory plane, as well as the PxRDY and / or PxIO# of various other memory planes.

[0171] Figure 5The memory plane busy status signals (PxRDY) and the memory plane operating status signals (PxIO#) of the various memory planes 102 of the memory 101 of the system 100 are symbolically shown. This is only an example of the memory 101 providing the status signal PxRDY and the status signal PxIO#. As shown, each memory plane has a corresponding PxIO# signal and a PxARDY signal. It should be noted that in the example, the control circuit 120 or the memory plane 102 or another appropriate component of the memory 101 issues the PxRDY signal and the PxIO# signal of the memory plane 102.

[0172] The memory plane busy status signal (PxRDY) may also be referred to as a plane status signal, and the memory plane operating status signal (PxIO#) may also be referred to as a plane operating status signal.

[0173] In an example, bits representing the state signal PxRDY and the state signal PxIO# may be generated by the state control circuit 140 .

[0174] Generally speaking, if a background operation in the memory plane 102x is currently being executed (which has been previously described herein, for example, with respect to Figure 4 If the memory plane 102x is not undergoing any operation (e.g., any background operation), the corresponding PxIO# status signal is in an idle state, which is indicated by, for example, PxIO# being 1.

[0175] Therefore, for memory plane 102x:

[0176] PxIO#=0→indicates that the memory plane 102x is in an operating state because a foreground operation or a background operation is being executed in the plane; and

[0177] PxIO#=1→indicates that the memory plane 102x is in an idle state because no foreground or background operations are being executed in the plane.

[0178] For memory plane 102x:

[0179] PxRDY=0→indicates that the memory plane 102x is in a busy state, indicating that the memory plane cannot be accessed while a foreground operation is executing in the plane, and therefore new commands cannot be accepted while a foreground operation is executing; and

[0180] PxRDY=1→ indicates that the memory plane 102x is in a ready state, meaning that the memory plane is accessible and can accept new commands since no foreground operations are executing in the plane.

[0181] SCO memory commands and AIPO memory commands that do not include background operations (see Table 1) can be executed in specific scenarios, which are referred to below. Fig.12 Discussed in more detail. The scenario includes: PxRDY = Busy (0); and PxIO# = Operating (0). This configuration does not include: (i) PxRDY = Busy (0); PxIO# = Idle (1); and (ii) PxRDY = Ready (1); PxIO# = Operating (0).

[0182] SCO memory commands and AIPO memory commands including background operations (see Table 1, for example) may be executed in different status signal contexts, which are described below with reference to Fig.12 Discussed in more detail, those configurations include: (i) PxRDY = Busy (0); PxIO# = Operating (0); and (ii) PxRDY = Ready (1); PxIO# = Operating (0). These two configurations do not include: (i) PxRDY = Busy (0); PxIO# = Idle (1).

[0183] SCO memory commands and AIPO memory commands that can operate in an overlap period in background operation can be executed in the context of PXRDY = Busy (0) and PxIO# = Operating (0). The overlap operation period can start when the first new command is accepted by the chip during background operation, and it ends when there are no pending operations (pause or wait operations). During the overlap operation period, at least one pending operation is queued. If the pending operation has a higher priority, the ongoing operation will be suspended to execute the high priority operation (see Fig.21 ), and will resume after all higher priority operations complete. Otherwise, pending operations are executed after the current operation completes (see Fig. 20 ).

[0184] When no background operation is in progress (ie, PxRDY=PxIO#=Ready / Idle for a particular plane) and an AIPO command may be issued by the host to the particular plane and accepted at the memory device.

[0185] When no background operation is in progress in a specific plane (i.e., PxRDY=PxIO#=1 or Ready / Idle for the specific plane), the host 130 may issue an AIPO command to a non-busy specific plane that can be executed. That is, when PxRDY=PxIO#=1, the host 130 may issue an AIPO command to the memory plane 102x, and the AIPO command may be accepted by the memory plane 102x.

[0186] After an AIPO command is issued to a particular plane (e.g., plane 102a), there are one or more possible options for executing the AIPO command: e.g. Fig. 6A Option A shown in , and Figure 6B Option B shown in . Fig. 6A Option A or Figure 6B The choice of option B is implementation specific and may be selected based on the circuit design of memory 101 .

[0187] Fig. 6A Option A shown in : The plane ready state of all planes is transformed into a busy state (PxRDY=0 for x=a, ..., N) for a short time period to process the command. The "short time period" is also referred to as the "command pre-processing period" in this article, which is the first execution stage of the AIPO command. After this first stage, the plane busy state of the unselected plane (for example, the plane to which the AIPO command is not issued) represents the current state of the unselected plane and becomes independent of the selected plane. Therefore, after time t602a at the end of the command pre-processing period, for the selected or busy plane Pa to which the AIPO command is issued, PaRDY=0, and for all other unselected and non-busy memory planes, PbRDY, PcRDY and PdRDY=1. The length of the command pre-processing period is implementation specific, such as based on the design of the memory circuit and other implementation details.

[0188] Fig. 6A An example timing diagram of plane status signals and plane operating state signals in response to receiving an AIPO command 604a is shown, wherein the execution of the AIPO command 604a includes a command pre-processing period during which all planes are in a busy state or an operating state. Fig. 6A In the timing diagram of and various other diagrams, the dashed rectangle corresponds to the associated signal that is busy (or in operation), and the unshaded rectangle corresponds to the associated signal that is ready (i.e., not busy) (or idle), such as Fig. 6A The legend section shows the Fig. 6A In FIG. 1 , four memory planes 102a, 102b, 102c, and 102d are assumed, but any different number of memory planes may exist. Therefore, four plane status signals PaRDY, PbRDY, PcRDY, and PdRDY are shown, and four array status signals PaIO#, PbIO#, PcIO#, and PdIO# are shown. Fig. 6AIn the example, before time t601a, all of the signals PaRDY, PbRDY, PcRDY, PdRDY, PaIO#, PbIO#, PcIO#, and PdIO# are in a ready (idle) state.

[0189] At t601a, an AIPO command 604a for plane 102a is received. Fig. 6A In the example, immediately after receiving the AIPO command 604a for plane 102a, from time t601a to time t602a (which is referred to as the command preprocessing period or the first stage of the execution cycle of the AIPO command 604a), all plane status signals become busy and the plane operating status signal becomes operating.

[0190] Subsequently, at time t602a (e.g., when the AIPO command 604a is issued for the memory plane 102a), the plane busy status signals and the plane operating status signals of the planes 102b, 102c, and 102d become ready (idle). After time t602a, PaRDY and PaIO# continue to be busy (in operation). Therefore, the memory plane 102a including the corresponding memory array 104a is executing the AIPO command 604a. At time t603a, the memory plane 102a becomes ready to accept new commands, and PaRDY becomes ready. The time period between time t602a and time t603a is also referred to as the second stage of the execution cycle of the AIPO command 604a. It should be noted that the background operation for the AIPO command 604a may still be in progress in the memory plane 102a, and therefore, PaIO# is still in operation. Finally, the background operation for AIPO command 604a ends at time t604a, and array status signal PaIO# now transitions from in operation to idle. When only the background operation of AIPO command 604a is being executed, the time period between time t603a and time t604a is also referred to as the AIPO background operation phase or the third phase of the execution cycle of AIPO command 604a.

[0191] Figure 6B Option B shown in: In this option, the plane busy state and plane operating state of the selected plane (for example, the AIPO command is issued for it) become busy (operating) (PxRDY and PxIO# change from 1 to 0), and the plane ready state and plane operating state of other unselected planes are not affected. Therefore, unlike the above description of Fig. 6A Option A and Option B discussed do not have a command pre-processing period. Figure 6BAnother example timing diagram of plane status signals and plane in-operation status signals in response to receiving an AIPO command 604b is shown, wherein the execution of the AIPO command 604b does not have any command pre-processing period during which all planes are in a busy state. Fig. 6A In contrast, Figure 6B In the example of FIG. 6 , only the selected plane (for which the AIPO command 604b is issued) has its plane status signal and plane operating status signal (i.e., PaRDY and PaIO#) changed to busy (operating), and the signals of all other planes remain ready. Therefore, from t601b to t603b (which is the first stage of the execution cycle of the AIPO command 604b), PaRDY is busy. From t601b to t604b (e.g., as also described with respect to FIG. 6 ), the AIPO command 604b is issued. Fig. 6A As discussed) (which is the AIPO background operation phase or the second phase of the execution cycle of the AIPO command 604b), PaIO# is in operation.

[0192] Therefore, comparison Fig. 6A and Figure 6B ,exist Fig. 6A In the short period of time after the AIPO command 604a is issued (i.e., during the command pre-processing period), all plane busy signals and plane operating signals are busy (operating); however, in Figure 6B In the example, after the AIPO command 604b is issued, only the selected plane busy signal and the plane operation status signal become busy. Figure 6B Compared to Fig. 6A Achieve higher operating efficiency because Figure 6B The unselected plane is always available in . However, compared to Fig. 6A situation, implementation Figure 6B The timing diagram of the memory 101 requires a more complex circuit in the memory 101. Therefore, based on the design of the memory 101, whether Fig. 6A and Figure 6B The timing diagrams are implementation specific.

[0193] When no background operation is in progress (i.e., PxIO# is idle for all planes) and a SCO command is issued for a specific plane

[0194] In an example, when all planes are idle (e.g., PxIO#=1 for all planes), the host 130 may issue a SCO command to the memory 101. After the SCO command is issued, all planes become busy (PxRDY=PxIO#=Busy (Operation) for all planes), and other commands may not be issued by the host 130 and accepted at the memory device 101 until all planes become ready (PxRDY=Ready for all planes).

[0195] Figure 7 An example timing diagram of a plane busy status signal and a plane operating status signal in response to receiving a SCO command is shown. In this example, similar to Fig. 6A , assuming that in response to the AIPO command for plane 102a at time t601a, PaRDY is busy from t601a to t603a, PaIO# is in operation from t601a to t604a, and the plane busy status signal and plane operating status signal for other planes are busy (in operation) from t601a to t602a, for example, due to Fig. 6A The reasons discussed.

[0196] Assume that a SCO command 704a for plane 102c is issued between t602a and t603a. Since at least one plane is not ready (e.g., PaRDY is busy) at this time, the SCO command 704a for plane 102c is declared invalid because the host 130 can issue a SCO command to the memory 101 only when all planes are ready for new commands and there is no AIPO background operation.

[0197] Assume that after time t604a (e.g., at time t702), SCO command 704b for plane 102d is issued. Since all planes are now ready (idle) and there is no ongoing background operation, SCO command 704b for plane 102d is executed. Since time t702, all plane busy state signals and plane operating state signals are changed to busy state. The plane ready state remains busy from time t702 to time t706, wherein the time period between time t702 and time t706 is also referred to as "SCO foreground operation phase", "plane occupation period" or "first phase".

[0198] In an example, during the plane occupation period, the SCO occupies the resources of all memory planes (or occupies the common resources of the memory planes), so that no other operations can be performed - therefore, the PxRDY of all planes is busy during this period. In an example, during the plane occupation period, the PxRDY of all planes is busy and all planes are drawn as occupied to avoid any command input until the memory 101 is ready for the next command. It should be noted that any AIPO (or SCO) command issued during the plane occupation period is declared invalid (as also described later in this document with respect to Fig.16A discussed).

[0199] At time t706, the cached (e.g., non-background) operation associated with the SCO command 704b for plane 102d may be completed, and thus, the plane busy status signal may be ready for all planes from time t706 (e.g., PxRDY=Ready for x=a, ..., d). However, while the background operation may be in progress in the selected plane 102d, all plane in-operation status signals for all planes may still be busy (e.g., PxIO#=Busy for x=a, ..., d). At time t708, the SCO command 704b for plane 102d may be completed, and thus, all plane in-operation status signals for all planes may become idle (e.g., PxIO#=Idle for x=a, ..., d).

[0200] Therefore, during the time period between time t706 and time t708, the plane operating state signal is in operation for all planes, and the plane busy state signal is ready for all planes. This period is referred to as the SCO background operation phase or the second phase of the execution cycle of the SCO command in this article.

[0201] When a background operation is in progress for at least one plane (i.e., PxIO#=Operation) and an AIPO command is issued for a specific plane that does not have an ongoing background operation

[0202] Assume that a background operation is in progress for at least one plane, such as plane 102a, that is, PaIO#=0 (e.g., in operation) for the plane. One or more other planes, such as at least plane 102b, do not have a background operation in progress (e.g., PbRDY=PbIO#=1 or ready (idle)). That is, one or more other planes, such as at least plane 102b, are idle planes or ready. In this scenario, the host 130 may issue an AIPO command to the idle plane.

[0203] Fig. 8A An example timing diagram depicting issuing an AIPO memory command to an idle plane while another operating plane has a background operation in progress is shown, wherein Fig. 8A AIPO memory commands cause a command preprocessing period. For example, Fig. 8A6 , only before time t802a, background operations are in progress in plane 102a (i.e., PaIO#=operating), and the other planes are ready (e.g., PyRDY=PyIO#=Ready(Idle), where y=b, c, d). At time t802a, an AIPO command 804 for plane 102b is issued by the host 130. Therefore, from t802a to t803a, PxRDY and PxIO# (where x=a, ..., d) of all planes become busy (operating) within a short time period (i.e., the command pre-processing period). After the command pre-processing period (discussed with respect to FIG. 6 ), PaRDY, PcRDY, PdRDY, PcIO#, and PdIO# become ready (idle). Due to the execution of the AIPO command 804 for plane 102b, PbRDY and PbIO# remain busy (operating). Due to the execution of the previous AIPO command for plane 102a, PaIO# remains operational.

[0204] Figure 8B Another example timing diagram depicting issuing an AIPO memory command to an idle plane while another plane has a background operation in progress is shown, wherein Figure 8B The AIPO memory commands do not cause any command preprocessing period c Figure 8B and Fig. 8A Similar - the difference between these two figures is that Figure 8B In FIG. 8 , after the AIPO command 804 for plane 102b is issued at time t802b, only the signal of plane 102b becomes busy. Therefore, Figure 8B There is no command pre-processing period. Therefore, the signal corresponding to the unselected plane does not become busy (in operation), as also related to Figure 6B Discussed.

[0205] When an AIPO background operation is in progress in a specific plane (i.e., PxRDY=Ready and PxIO#=Operating) and an AIPO command is issued for a specific plane with an ongoing background operation

[0206] Assume that a background operation is in progress for at least one plane, such as plane 102a, i.e., PaRDY=1 (e.g., ready) and PaIO#=0 (e.g., operating) for that plane. In this scenario, host 130 may issue selected (but not all) AIPO commands to the plane with background operation.

[0207] Fig. 9A An example timing diagram depicting issuing an AIPO memory command to a plane with an ongoing background operation is shown. Fig. 9AIn FIG. 1 , only before time 902a, background operations are in progress in plane 102a (i.e., PaRDY=Ready, PaIO#=Operating), and the other planes are ready (e.g., PyRDY=PyIO#=Ready(Idle), where y=b, c, d). At time 902a, an AIPO command 904 for plane 102a is issued by host 130. Therefore, from time t902a to time t903a, PxRDY and PxIO# (where x=a, ..., d) become busy (operating) for a short time period (i.e., command preprocessing period). Fig. 6A After that, PbRDY, PcRDY, PdRDY, PbIO#, PcIO#, and PdIO# become ready (idle). Due to the execution of AIPO command 904 for plane 102a, PaRDY and PaIO# remain busy (in operation).

[0208] Fig. 9B Another example timing diagram depicting issuing an AIPO memory command to a plane with an ongoing background operation is shown. Fig. 9B and Fig. 9A Similar - the difference between these two figures is that Fig. 9B In the example, after the AIPO command 904 for the plane 102a is issued at time t902b, only the signal of the plane 102a becomes busy (operating) (e.g., Fig. 9B The signal corresponding to the unselected plane does not become busy within a short period of time, as also described with respect to Figure 6B Discussed.

[0209] It should be noted that Fig. 9A and Fig. 9B In , only some selected types of AIPO memory commands that keep plane 102a busy before time t902a may be allowed. Examples of some such selected AIPO memory commands include cache read random commands. For example, cache read random commands are selected AIPO memory commands that may be accepted during the background operation period of cache read (random) operations. Therefore, Fig. 9A and Fig. 9B The AIPO command 904 may be, for example, a cache read random command.

[0210] However, there are some other example AIPO memory commands that cannot be issued to a plane that has an ongoing background operation. For example, a page read command is an AIPO memory command that is not acceptable during the background operation period of a cache read (random) operation (i.e., it can only be executed when there is no existing background operation in progress). Therefore, Fig. 9A and Fig. 9BThe AIPO command 904 may not be, for example, a page read command.

[0211] There are some commands that can be issued by the host at any time and accepted at the memory device (e.g., system management commands, see Table 1). One example of such a command is a reset command, which can be issued by the host at any time and accepted at the memory device to terminate ongoing operations in one or more planes.

[0212] SCO and AIPO back-end operations and execution of SCO back-end operations

[0213] Fig.10 1001, a SCO command 1004 for plane 102a is issued by host 130. The PxRDY signals of all planes are between time period t1001 and time period t1002 (also referred to herein as the plane occupation period or the first phase of the execution cycle of the SCO memory command (see Figure 7 )) becomes busy. Phase 1 may include SCO foreground operations (phases) in which the plane core is performing operations involving the cache. In phase 1, since the cache is busy and the host cannot read data from the cache / write data to the cache, PRDY and PIO#=0 (busy, in operation). After phase 1, the cache is idle and the host can read data from the cache / write data to the cache, so PRDY returns to 1 and PIO# remains 0. Therefore, after time t1002, the PxRDY signals of all planes are transitioned to the ready state. However, the plane in-operation status signals PxIO# of all planes remain in operation until the SCO is completed at t1003, for example, regarding Figure 7 As also discussed Figure 7 As discussed, the time period between time t1002 and time t1003 is referred to as a background operation phase, or phase 2, in which the host may read from / write to the cache.

[0214] It should be noted that during the SCO background operation phase of the SCO memory command, the PxIO# of all planes are in operation, such as Fig.10 In contrast, for AIPO, the corresponding AIPO background operation phase (see Fig. 6A ) keeps PxIO# operational only for the selected planes (i.e., for which AIPO has been issued), such as Fig. 6A and Figure 6B As shown in .

[0215] Therefore, SCO background operations are associated with SCO memory commands, and any such operations will occupy all planes (ie, PxIO#=operating for all planes), such as Fig.10 In contrast, AIPO background operations are associated with AIPO memory commands, and any such operation will occupy a specific plane (ie, for a specific plane, PxIO#=operation), as shown in FIG. Fig. 6A and Figure 6B As shown in .

[0216] When a SCO background operation is in progress (i.e., PxRDY = Ready and PxIO# = Operating for all planes) and (i) an AIPO command is issued (which becomes invalid) and (ii) a SCO command is issued

[0217] Fig.11 Shows the SCO background operation in progress (for examples of SCO background operations, see Fig.10 , that is, for all planes, PxRDY=Ready and PxIO#=Operating) and an example timing diagram of the issuance of an AIPO command 1104a and the issuance of a SCO command 1104b.

[0218] It should be noted that while SCO background operations are in progress (for further discussion of SCO background operations, see Fig.10 ), the host 130 may only issue the selected operation command. For example, when the SCO background operation is in progress, the host 130 may not issue the selected type of AIPO command 1104a (other selected types of AIPO commands may be issued, as discussed below), and therefore, Fig.11 The AIPO command 1104a of the present invention is declared invalid. This shows an example of a method in which a second type of memory command (e.g., an AIPO command) is received by the memory while the memory is executing a first type of memory command (e.g., a SCO command) for occupying multiple planes simultaneously; and in response to receiving the second type of memory command during the execution of the first type of memory command, the execution of the second type of memory command is refused. However, while the SCO background operation is in progress, the host 130 can effectively issue a SCO command 1104b at t1004, such as Fig.11 As shown in Fig.11 As shown in FIG. 1 , the states of various signals after time t1104 have changed with respect to Fig.10 Be discussed.

[0219] Overview of the memory plane ready status signal (PxRDY) and the memory array ready status signal (PxIO#)

[0220] refer to Fig.12According to Table 1190 in FIG. 11 , in an embodiment, the host 130 may check the plane busy status signal PxRDY and the plane operating status signal PxIO# for the operation.

[0221] If there is no operation in progress in any plane of memory 101 (all PxRDY and PxIO#=1), host 130 may issue any command to the chip.

[0222] If there is an ongoing AIPO operation in the memory 101, the host 130 must check the PxRDY and PxIO# of the selected plane. If the selected plane is idle (PxRDY and PxIO#=1, where 102x is the selected plane), the host can issue any AIPO command to the selected plane. If the selected plane is busy and in operation (PxRDY and PxIO#=0, where 102x is the selected plane), the command issued by the host 130 will not be executed. If the selected plane is ready but there is a background operation (that is, PxRDY=1 and PxIO#=0, where 102x is the selected plane), the host 130 can issue the selected AIPO command to the selected plane.

[0223] If there is a SCO operation in progress in the chip, the host 130 must check the PxRDY and PxIO# of the selected plane. If the selected plane is busy and in operation (i.e., PxRDY and PxIO#=0, where 102x is the selected plane), the host may not issue any command that will be accepted by the selected plane. If the selected plane is ready but there is a background operation (PxRDY=1 and PxIO#=0, where 102x is the selected plane), the host may only issue the selected SCO command or AIPO command (not all SCO commands or AIPO commands) to the selected plane.

[0224] In an embodiment, SCO system management commands may be issued by the host at any time and accepted at the memory device. AIPO system management commands may not be issued when there is an ongoing background SCO operation, but AIPO system management commands may be issued by the host and accepted at the memory device when there is an ongoing AIPO operation.

[0225] Table 1190 summarizes the use of the PxRDY state signal and the PxIO# state signal for various memory operations, some of which are discussed above.

[0226] As discussed previously herein, each plane has its own ready state - PxRDY and PxIO#. Thus, the ready state of an individual memory plane includes two status bits, one each for PxRDY and PxIO#.

[0227] PxRDY specifies whether the plane can execute the next command input. For a given memory plane, if PxRDY is busy (PxRDY=0), then this plane may not receive other commands. On the other hand, if PxRDY is ready (PxRDY=1), then this plane may selectively receive new commands (or may not receive new commands) based on the command type and other status signals of other planes.

[0228] In an example, when all planes are ready (idle) (all PxRDY=1 and PxIO#=1), the memory 101 may receive a SCO operation command, as previously discussed herein.

[0229] In an example, when the selected particular plane is ready (PxRDY=1) and the plane is not in SCO background operation (see, for example, Fig.11 , where the AIPO operation command 1104a is invalid), the memory 101 can receive an AIPO operation command for a specific plane.

[0230] When the plane undergoes SCO background operations (e.g., for all planes, PxRDY=1 and PxIO#=0, see Fig.11 ), only limited or selected types of new commands may be received. AIPO operation commands may not be included in these limited or selected types of commands (for example, see Fig.11 , where AIPO operation command 1104a is invalid).

[0231] As discussed, PxIO# provides the plane operating status of the corresponding memory operation. If PxIO# is in operation (PxIO#=0) for a particular plane, the memory operation of this plane is still in progress. If PxIO# is idle (PxIO#=1) for a particular plane, the plane is not undergoing any operation.

[0232] Reset Plane Command

[0233] A "reset plane" command may be supported by memory 101, wherein the reset plane command will abort any AIPO executing in the selected plane where the reset plane command is issued. Fig.13 Shows the configuration (e.g., cycle type) of the reset plane command. Fig.13As shown in , the reset plane command includes one command cycle followed by one or more (e.g., three) address cycles, where the addresses contained in the address cycles indicate one or more addresses (e.g., column addresses) of the memory plane to be reset. In an example, after the memory 101 receives this command, the memory 101 aborts any AIPO executed in the memory plane identified by the address in the address cycle. The reset plane command can be issued by the host and accepted by the memory device when the PxRDY status signal and the PxIO# status signal indicate a busy state in the presence of an ongoing AIPO operation, rather than in the presence of an ongoing SOC operation. The plane reset command can also be issued during a foreground operation period or a background operation period.

[0234] AIPO memory commands issued to a memory plane that does not have background operations in progress (other planes may have AIPO background operations)

[0235] Fig.14A and Fig. 14B Timing diagrams 1400a and 1400b are shown, respectively, depicting a scenario where an AIPO memory command is issued to a memory plane that has no background operations in progress while one or more other memory planes may have AIPO background operations in progress.

[0236] exist Fig.14A In the example of FIG. 1402, an AIPO command 1404a is issued for plane 102b at time t1402a. Prior to time t1402a, PaRDY is busy and PaIO# is in operation, indicating that AIPO is performed in plane 102a. AIPO command 1404a is issued to a non-busy plane, such as plane 102b, where PbRDY=ready when AIPO command 1404a is issued. In an example, AIPO command 1404a may be any suitable AIPO command listed in Table 1 discussed previously, such as a page read operation.

[0237] As previously mentioned Fig. 6A As discussed, Fig.14A In the example of FIG. 14 , after issuing AIPO command 1404a, all planes become busy for a short time period (e.g., between time t1402a and time t1403a), which is a command pre-processing period. After the command pre-processing period, PxRDY and PxIO# of plane 102c and plane 102d become ready (idle). Memory plane 102b begins processing AIPO command 1404a commands from time t1403a. Plane 102a remains busy due to ongoing operations that started before time 1402a.

[0238] In an embodiment, new commands are not allowed to be issued by host 130 during the command pre-processing period. As discussed, after the command pre-processing period, the plane busy status signals of plane 102c and plane 102d are again transitioned to the ready state.

[0239] Fig. 14B Showing alternative embodiments (for example, it may be Fig.14A For example, in Fig.14A In , there is a command pre-processing period immediately following the issuance of the AIPO command 1404a, during which all planes become busy (e.g., PxRDY and PxIO# for x=a, ..., d). In contrast, Fig. 14B There is no preprocessing period for this command. For example, Fig. 14B In the embodiment of FIG. 1404, only the selected plane (to which the AIPO command 1404b is issued at time t1402b) becomes busy from time t1402b. The other unselected planes (e.g., plane 102c, plane 102d) remain ready—that is, the PcRDY status signal, the PdRDY status signal, the PcIO# status signal, and the PdIO# status signal are not affected by the AIPO command 1404b, and these status signals remain available.

[0240] In the example, Fig.14A Examples of Fig. 14B The embodiments are relatively easier to implement in circuits (e.g. because Fig.14A ) However, in Fig.14A There may be a slight performance loss in the embodiment of FIG. 1 because the host 130 needs to wait during the command pre-processing period, during which any new commands issued by the host 130 will not be executed.

[0241] Other Examples of AIPO Memory Commands

[0242] If an AIPO background operation is in progress in a particular plane (such as the first plane, where PxRDY=Ready and PxIO#=Operating for the first plane), an AIPO command (such as a page read or cache read command) can be issued by the host to another plane (such as the second plane) that does not have any background operations (for the second plane, PxRDY=PxIO#=Ready (Idle)) and accepted at the memory device.

[0243] If an AIPO background operation is in progress in a particular plane (such as a first plane, where PxRDY=Ready and PxIO#=Operating for the first plane), only selected AIPO commands (such as cache read commands) may be issued by the host to the first plane with background operations and accepted at the memory device. For example, referring to Table 1 discussed previously herein, a cache read random command is an AIPO command allowed during a background operation period.

[0244] There may be other AIPO memory commands, such as page read commands, that may not be issued to a plane with an AIPO background operation in progress.The types of commands that may be issued by the host and accepted at the memory device during AIPO background operations may depend on the specific implementation of the memory device.

[0245] If an AIPO background operation is in progress, SCO commands (eg, block erase commands) are not allowed.

[0246] Fig.15A and Fig. 15B Sequence diagrams 1500a and 1500b depicting various example scenarios for the issuance of AIPO commands are shown, respectively. Note that Fig.15A The AIPO command is followed by a command pre-processing period. Fig. 15B There is no command pre-processing period.

[0247] refer to Fig.15A , before time t1501a, none of the planes are busy (i.e., PxRDY=PxIO#=idle for all planes). At time t1501a, an AIPO command 1504a for plane 102a is issued. Thus, there is a command pre-processing period between time t1501a and time t1502a, during which all planes are busy (i.e., PxRDY=PxIO#=operating for all planes).

[0248] At time t1502a, plane 102b, plane 102c, and plane 102d become ready (idle). At time t1503a, plane 102a becomes ready (e.g., regarding Fig. 6A (as discussed in t603a).

[0249] At t1504a, the host 130 issues another AIPO command 1804b for plane 102b. Similar to the previous discussion, there is a command pre-processing period between time t1504a and time t1505a, during which all planes are busy (i.e., PxRDY=PxIO#=Busy (Operation) for all planes). At time t1505a, plane 102a, plane 102c, and plane 102d are ready (i.e., PaRDY=PcRDY=PdRDY=Ready), but background operations are still in progress in plane 102a for execution of AIPO command 1504a.

[0250] At t1506a, the host 130 issues another AIPO command 1504c for plane 102a. Similar to the previous discussion, there is a command pre-processing period between time t1506a and time t1507a, during which all planes are busy (i.e., PxRDY=PxIO#=Busy (Operation) for all planes). At time t1507a, planes 102c and 102d are ready (i.e., PcRDY=PdRDY=Ready (Idle)), but operations are still in progress in planes 102a and 102b for execution of AIPO command 1504c and AIPO command 1504b, respectively.

[0251] Thus, as previously discussed, if an AIPO background operation is in progress in a particular plane (such as the first plane, where PxRDY=Ready and PxIO#=Operating for the first plane), an AIPO command (such as a page read or cache read command) may be issued by the host to another plane (such as the second plane) that does not have any background operations (for the second plane, PxRDY=PxIO#=Ready (Idle)) and accepted at the memory device. The AIPO command 1504b for plane 102b issued at time t1504a is an example of such an AIPO command.

[0252] Also as previously discussed, if an AIPO background operation is in progress in a particular plane (such as the first plane, where PxRDY=Ready, and PxIO#=Operating for the first plane), only selected AIPO commands (such as a cache read random command or another Class 5 command from Table 1 discussed previously herein) may be issued by the host to the first plane with the background operation and accepted at the memory device. For example, an AIPO command 1504c is issued at time t1506a for plane 102a while plane 102a is still undergoing an AIPO background operation (i.e., PaRDY=Ready, PaIO#=Operating). Thus, the AIPO command 1504c may be a cache read random command or another Class 5 command from Table 1, but may not be a page read or another Class 4 command from Table 1.

[0253] Fig. 15B The timing diagram 1500b is partially similar to Fig.15A The difference between these two timing diagrams is Fig.15A The timing diagram 1500a includes a command pre-processing period, Fig. 15B The timing diagram 1 500b does not have the command pre-processing period. For example, similar to Figure 6B , Fig. 15B The timing diagram 1500b does not have a command pre-processing period. Fig.15A and Figure 6B Discussion Fig. 15B The timing diagram 1500b will be apparent to those skilled in the art. Fig. 15B Contains time t1501b, time 1503b, time 1504b and time 1506b, which are Fig.15A Corresponding to similar times in .

[0254] Other Examples of SCO Storage Commands

[0255] If no background operation is in progress, a SCO command (e.g., a page program command or a block erase command) can be issued by the host and received at the memory device only when all planes are ready (idle) (i.e., PxRDY=PxIO#=Ready (idle) for all planes). After the SCO command is issued, all planes will become busy (operating) (i.e., PxRDY=PxIO#=Busy (operating) for all planes).

[0256] Fig.16AA timing diagram 1600a depicting an example of a SCO command is shown. At t1601a, an AIPO command 1604a is issued for plane 102a. This is followed by a command pre-processing period between time t1601a and time t1602a (although in another example, there may be no such command pre-processing period, as described with respect to FIG. 1 ). Figure 6B 1604a). Therefore, after time t1602a, PaRDY=PaIO#=busy (operating), and all other status signals are ready. At time t1604a, the execution of AIPO command 1604a for plane 102a is completed, and both PaRDY and PaIO# become ready (idle) at time t1604a. It should be noted that although Fig.16A In this example, both PaRDY and PaIO# become ready (idle) at the same time, but PaIO# may become idle after PaRDY becomes ready, such as Fig. 6A As seen in.

[0257] Also Fig.16A As shown in FIG. 1 , at time t1603a (e.g., between time t1602a and time t1604a), a SCO command 1604b for plane 102b is issued. Since not all planes are ready at time t1603a (e.g., PaRDY=busy at time t1603a), the SCO command 1604b for plane 102b is invalid and is not executed by memory 101.

[0258] After all planes are ready (idle) from time t1604a, another SCO command 1604c is issued for plane 102b at time t1605a. It should be noted that at this time, all planes are ready. Therefore, SCO command 1604c is valid and SCO command 1604c is executed from time t1605a.

[0259] As about Figure 7 As discussed, Fig.16A , once the SCO command 1604c is issued, all planes will become busy (in operation), for example, during the plane occupation period between time t1605a and time t1606a (i.e., for x=a, ..., d, PxRDY=PxIO#=Busy (in operation)). At t1606a (i.e., after the plane occupation period ends), all planes become ready (i.e., for x=a, ..., d, PxRDY=Ready), but the SCO background operation is in progress in all planes (i.e., for x=a, ..., d, PxIO#=In operation). Finally, at time t1607a, the SCO background operation is completed and for x=a, ..., d, PxIO#=Idle.

[0260] It should be noted that between time t1605a and time t1606a, during the plane occupied period, all planes are depicted as busy (i.e., PxRDY=busy for x=a, ..., d), but the SCO command 1604c is for a specific plane 102b. That is, although planes 102a, 102c, 102d may not actively participate in the SCO command 1604c, planes 102a, 102c, 102d are still depicted as being busy or in operation to avoid any command input until the memory 101 is ready for the next command. Therefore, the time period between time t1605a and time t1606a when the plane is depicted as occupied is also referred to herein as a plane occupied period to avoid any command input until the memory 101 is ready for the next command.

[0261] It should be noted that any AIPO (or SCO) operations issued during the plane occupation period are declared invalid. Fig.16A In FIG. 1604, an AIPO command 1604d for a plane is issued at time t1605a1, which is during the plane occupation period. Therefore, this command is declared invalid.

[0262] Fig. 16B Another timing diagram 1600b is shown depicting an example of a SCO command.

[0263] Fig. 16B The timing diagram 1600b is partially similar to Fig.16A The difference between these two timing diagrams is Fig.16A The timing diagram 1600a includes a command pre-processing period, Fig. 16B The timing diagram 1600b does not have the command preprocessing period. For example, similar to Figure 6B , Fig. 16B The timing diagram 1600b does not have a command pre-processing period. Fig.16A and Figure 6B Discussion Fig. 16B The timing diagram 1600b will be apparent to those skilled in the art.

[0264] Fig.17A timing diagram 1700 is shown depicting other examples of SCO commands, and also shows that some AIPO memory commands may not be issued when a plane is performing a SCO background operation. In timing diagram 1700, a SCO command 1704a for plane 102a is issued at time t1701, whereby all planes become busy (operating) during the previously discussed plane occupation period (which occurs between time t1701 and time t1702). At time t1702, PxRDY transitions to ready for x=a, ..., d, i.e., all planes become ready. It should be noted that the SCO background operation is still in progress after time t1702, and therefore, for x=a, ..., d, PxIO#=operating.

[0265] At time t1703 (e.g., while the SCO background operation is still in progress), an AIPO command 1704b for plane 102b is issued. It may be noted that if the SCO background operation is in progress, the memory 101 may not be able to execute an AIPO memory command, such as a page read command. Therefore, the AIPO command 1704b for plane 102b is invalid.

[0266] However, if a SCO background operation is in progress, the memory 101 may be able to execute a selected SCO memory command, such as the cache programming command of Table 1 discussed previously herein or another Class 2 SCO command. It should be noted that if a SCO background operation is in progress, a Class 1 SCO command may not be effectively received and executed.

[0267] For example, at time t1704 (e.g., while the SCO background operation is still in progress), a SCO command 1704c (such as the cache programming command of Table 1 or another Class 2 SCO command) is issued for plane 102b. This command is valid and is executed by memory 101. For example, during the corresponding plane occupation period starting at time t1704, all planes become busy (in operation). The portion of the timing diagram after time t1704 is similar to that regarding Fig. 16B The discussed parts, and therefore, are not discussed in further detail.

[0268] Fig.18A and Fig.18B Timing diagrams 1800a and 1800b are shown depicting other examples of SCO commands, and also depict some AIPO memory commands that may be issued and executed concurrently with a plane performing SCO background operations.

[0269] It should be noted that Fig.18A and Fig.18B Shown with Fig.17 For example, in Fig.17In the case of a plane that is performing a SCO background operation, the AIPO command 1704b is not allowed. Fig.18A and Fig.18B In the example above, AIPO command 1804b is allowed while the plane is performing SCO background operations.

[0270] For example, implementing Fig.17 The circuitry within the memory 101 in the context of the embodiment may be different from that of the embodiment of Fig.18A and Fig.18B Therefore, whether to allow AIPO memory commands when the plane is performing SCO background operations is implementation specific - based on the design of memory 101, memory 101 can support selectively allowing (or denying) AIPO memory commands when the plane is performing SCO background operations.

[0271] In another example, Fig.17 The AIPO command 1704b differs from Fig.18A AIPO Order 1804. Therefore, it is allowed Fig.18A AIPO command 1804b (e.g., category 4 command of Table 1), while rejecting Fig.17 AIPO command 1704b (e.g., category 5 command of Table 1).

[0272] In timing diagram 1800a, at time t1801a, SCO command 1804a is issued for plane 102a, whereby all planes become busy during the previously discussed plane occupation period (which occurs between time t1801a and time t1802a). At time t1802a, PxRDY transitions to ready for x=a, ..., d, i.e., all planes become ready. It should be noted that the SCO background operation is still in progress after time t1802a, and therefore, for x=a, ..., d, PxIO#=operating.

[0273] At time t1803a (e.g., while SCO background operations are still ongoing), an AIPO command 1804b is issued for plane 102b. Fig.18A In the example of Fig.17 102b). Contrary to the discussion above, if a SCO background operation is in progress, memory 101 may be able to execute AIPO memory commands, such as page read commands. Therefore, AIPO command 1804b for plane 102b is allowed. Depending on the implementation of the memory system, page read commands may or may not be issued / accepted during the cache programming background operation period. During the cache read background operation, page read commands cannot be issued.

[0274] Thus, from time 1803a, all planes become busy during the command pre-processing period until time t1804a, after which planes 102a, 102c, and 102d become available. Note that SCO background operations are ongoing in all planes, e.g., to execute SCO command 1804a for plane 102a. At time t1806a, plane 102b is ready (e.g., PbRDY), e.g., with respect to Fig. 6A It should be noted that the SCO background operation may still be ongoing in all planes after time t1806a.

[0275] Fig.18B The timing diagram 1800b is partially similar to Fig.18A The difference between these two timing diagrams is Fig.18A The timing diagram 1800a includes a command pre-processing period, Fig.18B The timing diagram 1800b does not have the command preprocessing period. For example, similar to Figure 6B , Fig.18B The timing diagram 1800b does not have a command pre-processing period. Fig.18A and Figure 6B Discussion Fig.18B The timing diagram 1800b will be apparent to those skilled in the art. Fig.18B It includes a SCO command 1808a for plane 102a, an AIPO command 1808b for plane 102b, and time t1801b, time t1802b, time t1803b, and time t1806b.

[0276] FIG. 19A to FIG. 19D An example timing diagram of the plane busy state signal PxRDY of planes P0 to P3 and the plane operating state signal PxIO# of planes P0 to P3 in response to receiving various types of commands that can be implemented in various embodiments is shown. It should be noted that in FIG. 19A to FIG. 19D In the timing diagram of , as in the previous figures, the dashed rectangles correspond to associated signals that are busy, and the unshaded rectangles correspond to associated signals that are ready (ie, not busy), as shown in the legend.

[0277] Fig.19A The timing of the status signals of a SCO command (such as Class 1 in Table 1) to be executed without background operation is shown. When a SCO command for plane P0 is received, all status signals are in the Ready (Idle) state. During the execution of the command, all status signals are in the Busy (Operational) state until the command is completed. The Plane Busy status signals and the Plane Operational status signals of all planes are in the Busy (Operational) state during the operation period.

[0278] Fig.19B The timing of the status signals of a SCO command (such as Class 2 in Table 1) that can be executed with background operation is shown, which has two operation periods. When a SCO command for plane P0 is received, all status signals are in the ready (idle) state. After receiving the command, the plane busy status signals of all planes are changed to the busy state during the busy period and changed to the ready state at the end of the busy period (this busy period is part of the plane occupation period, which can include both the foreground operation period and the background operation period of the SCO command). During the background operation period, the plane operating status signal remains in the operating state during a longer interval after the end of the busy period.

[0279] Fig.19C The timing of the status signals of an AIPO command (such as category 4 of Table 1) to be executed without background operation is shown, which has two operation stages. When an AIPO command for plane P0 is received, all status signals are in the ready (idle) state. After receiving the command, the plane busy status signals of all planes are changed to the busy state. In addition, after receiving the command, the plane operating status signals of all planes are changed to the operating state. At the end of the command processing interval (command pre-processing period), the plane busy signal and the plane operating signal of the unselected plane are changed to the ready (idle) state. The plane busy status signal and the plane operating status signal of the selected plane P0 remain busy (operating) during the operation interval.

[0280] Fig.19DThe timing of the status signals of an AIPO command (e.g., category 5 of Table 1) that can be executed with background operation is shown, which has three operation phases, including: a command processing phase, in which all plane busy status signals and plane operating status signals are busy (operating); a data transfer phase, in which for unselected planes, the plane busy status signals and the plane operating status signals are ready (idle), and the plane busy status signals and the plane operating status signals of the selected plane remain busy (operating); and a background operation phase, in which the plane busy status signal of the selected plane changes to ready and the plane operating status signal of the selected plane remains operating until completion. When an AIPO command for plane P0 is received, all status signals are in the ready (idle) state. After receiving the command, the plane busy status signals of all planes change to the busy state. In addition, after receiving the command, the plane operating status signals of all planes change to the operating state. At the end of the cache operation interval, the plane busy status signal of the selected plane P0 changes to the ready state. However, the plane operating status signal of the selected plane remains operating for a longer operation interval. The plane busy status signal of the unselected plane and the plane operating status signal of the unselected plane are changed to the ready (idle) state at the end of the command processing interval.

[0281] Fig. 20 An example of issuing a second SCO command during the operation of a first SCO command is shown. After issuing SCO command 1, the chip becomes busy (all PxRDY=0) only during phase 1, and then the chip returns to ready (all PxRDY=1) after phase 1 is completed. A new SCO command 2 can be issued by the host and accepted at the memory device even if phase 2 for the previous command is still in progress. However, the second SCO operation does not start unless the first command operation ends, so it still meets the SCO criteria. In other words, there is an "overlapping operation" period during which the second SCO operation does not start before the first command operation ends.

[0282] Fig.21 Another example is shown where an AIPO command may be issued by the host and accepted at the memory device, which suspends the operation of a previous SCO command. After issuing SCO command 1, the chip becomes busy (all PxRDY=0) only within phase 1, then the chip returns to ready (all PxRDY=1) after phase 1 is completed. A new AIPO command 2 may be issued by the host and accepted at the memory device, even though phase 2 for the previous command is still in progress. In this case, there is an overlapping operation period where the previous operation is suspended to execute the new command and the old operation is automatically resumed after the new operation is completed. This may be a special case that applies when one command has a higher priority than another command.

[0283] Various example configurations that can be supported by embodiments of the plane busy status signal and the plane operating status signal are described herein. One example can be characterized as follows:

[0284] 1. If there is no background operation (PxRDY=PxIO#=1).

[0285] i. If the selected plane is ready (idle) (PxRDY=PxIO#=1), AIPO commands (including “with” and “without” background operation AIPO commands) may be issued by the host and received at the memory device for the selected plane.

[0286] ii If all planes are ready (idle) (PxRDY=PxIO#=1), SCO commands (including “with” and “without” background operation SCO commands) may be issued by the host and accepted at the memory device.

[0287] 2. If background operation exists (PxRDY=1 and PxIO#=0).

[0288] i. If the background operation is a "with" background operation AIPO operation for the selected plane, then the selected AIPO command may be issued by the host and accepted at the memory device for the selected plane.

[0289] ii. If the background operation is a "with" background operation AIPO operation for an unselected plane, then for the selected plane, AIPO commands (including "with" and "without" background operation AIPO commands) may be issued by the host and accepted at the memory device.

[0290] iii. If the background operation is a "with" background operation SCO operation, then the selected SCO or AIPO command may be issued by the host and accepted at the memory device.

[0291] iv. Please note that the selected commands mentioned here are not only "have" (SCO / AIPO) commands, but also "do not have" (SCO / AIPO) commands.

[0292] 3. If the selected plane is busy (in operation) (PxRDY=PxIO#=0), then AIPO or SCO commands may not be issued by the host to the selected plane and accepted at the memory device.

[0293] Thus, in some configurations, both "with" and "without" background operation commands may be issued by the host and accepted at the memory device when no background operation is in progress (PxRDY=PxIO#=1).

[0294] Furthermore, selected commands may be issued by the host during background operation (PxRDY=I and PxIO#=0) and accepted at the memory device, including commands that are not "with" background operation commands.

[0295] The techniques described herein include a chip device having multiple planes (e.g., a memory system described herein) that supports synchronous chip commands for type 1 operations (first type of operation, select first type of operation, first type of command, etc.) and asynchronous independent commands for type 2 operations (second type of operation, select second type of operation, second type of command, etc.). Example commands include commands to continue or abort read operations and write operations of a memory array.

[0296] Type 1 commands select one or more planes for a Type 1 operation. Type 2 commands select only one plane for a Type 2 operation.

[0297] Both type 1 operations and type 2 operations include foreground operations, and some of the type 1 operations and type 2 operations include additional background operations.

[0298] Type 1 operations may be synchronous chip operations SCO, where only one operation is performed at a time for one or more selected planes, and the operation starts and ends simultaneously for all selected planes. Type 2 operations may be asynchronous plane operations AIPO, where the operation for each plane is performed asynchronously and independently from the operations for other planes.

[0299] In the examples described herein, each plane provides: one busy status signal PxRDY ready for new command to indicate that the plane is ready for the next command when PxRDY is ready; and another idle status signal PxIO# to indicate that there is no operation in progress when PxIO# is ready. For type 1 operation, since it is a chip-based operation, all planes including both operating (busy) planes and idle (ready) planes have the same status signals for both PxRDY (busy / read) and PxIO# (operating / idle). For type 2 operation, except for the first stage of the foreground operation period for some embodiments, the plane busy status signal PxRDY and the plane operating status signal PIO# of one plane are independent of the state of another plane.

[0300] The type 2 operation may be an asynchronous plane operation AIPO, in which the operation for each plane is performed asynchronously and independently from the operations for the other planes. The type 2 operation may have a first embodiment in which only foreground operations are performed and a second embodiment in which background operations are performed. The type 2 operation begins after the chip receives a type 2 command sequence with a selected plane (target plane). The type 2 operation begins with a foreground operation of the selected plane, and during the foreground operation period, for the selected plane, the plane busy status signal PxRDY is set to busy and the plane operating status signal PxIO# is set to operating (refer to Fig. 22 and Fig.23 After the foreground operation is completed, some operations are completed, and the plane busy status signal PxRDY returns to ready and the plane operating status signal PxIO# returns to idle ( Fig. 22 Some operations continue in the background, PxRDY returns to ready and PxIO# remains in operation ( Fig.23 ). After the background operation is complete, PxIO# returns to Idle.

[0301] Allows new Type 2 commands to be issued to unselected planes while a Type 2 operation is in progress for a selected plane. Fig. 22 ). New Type 2 commands are prohibited from being issued to the selected plane during the foreground operation period of the selected plane (PxRDY is busy). The selected Type 2 commands are allowed to be issued to the selected plane during the background operation period of the selected plane (PxRDY is ready but PIO# is in operation) Fig.23 ).exist Fig.23 In FIG. 1 , the overlap operation period is a portion of the period between t4 and t6. During the overlap operation period, both PRDY and PIO# are busy.

[0302] Fig. 22 1 is a diagram showing logic for accepting and rejecting commands for planes P0 to P3 in the upper portion of the diagram, and showing the ready / busy (idle / operating) states of the status bits PxRDY and PxIO# for the following situations in the lower portion of the diagram: a type 2 command (AIPO) for plane P0 that does not include background operations is received at time t0, and a second type 2 command for P1 that does not include background operations is received at time t1. Prior to time t0, all status bits are in the ready (idle) state, and the control logic on the memory device can accept any type of command. At time t0, the device starts at the foreground operation in plane P0, and sets the status bits P0RDY and P0IO# of plane P0 to the busy (operating) state. The status bits of planes P1 to P3 remain in the ready (idle) state.

[0303] Between time t0 and time t1, the logic for accepting and rejecting commands may accept other Type 2 commands for planes P1 to P3. Commands for plane P0 will not be accepted. Type 1 commands will be rejected during this interval.

[0304] At time t1, a second Type 2 command for plane P1 is received. The device accepts the command and starts at the foreground operation in plane P1. In addition, the device sets the status bit P1RDY and status bit P1IO# of plane P1 to the busy (operating) state. The status bits of planes P2 to P3 remain in the ready (idle) state. The status bit of plane P0 remains in the busy (operating) state corresponding to the execution of the foreground operation of the first command. Commands for plane P0 or plane P1 will not be accepted. Type 1 commands will be rejected during this interval.

[0305] At time t2, the foreground operation of the first command is completed and the status bit P0RDY and status bit P0IO# of plane P0 are changed to the ready (idle) state, thereby allowing type 2 commands for plane P0. The foreground operation of the second command is completed at a later time, and the status bits and logic for accepting and rejecting commands are changed in a manner similar to that described for the first command.

[0306] Fig.23 1 is a diagram showing logic for accepting and rejecting commands for planes P0 to P3 in the upper portion of the diagram, and showing the ready / busy (idle / in operation) status of the status bit PxRDY and the status bit PxIO# in the lower portion for the following cases: a type 2 command (AIPO) for plane P0 including both foreground and background operations is received at time t0, a second type 2 command for P1 including both foreground and background operations is received at time t1, and a third type 2 command for P0 including both foreground and background operations is received at time t4. Prior to time t0, all status bits are in the ready (idle) state, and the control logic on the memory device can accept any type of command.

[0307] At time t0, the device starts at foreground operation in plane P0 and sets the status bit P0RDY and status bit P0IO# of plane P0 to the busy (operating) state. Background operation starts at or during the start of the operating state of P0IO#. The status bits of planes P1 to P3 remain in the ready (idle) state. The device cannot accept new commands for plane P0. The device can accept new type 2 commands for planes P1 to P3.

[0308] At time t1, the device begins foreground operation in plane P1 and sets the status bit P1RDY and status bit P1IO# of plane P1 to the busy (operating) state. Background operation begins at or during the start of the operating state of P1IO#. The status bits of planes P2 and P3 remain in the ready (idle) state. The status bit of P0 remains unchanged. The device cannot accept new commands for planes P0 or P1. The device can accept new type 2 commands for planes P2 and P3.

[0309] At time t2, the foreground operation in plane P0 is completed, and the P0RDY status bit changes to the ready state. The status bits of planes P1 to P3 remain unchanged. At this time, the device can accept a select type 2 command for plane P0.

[0310] At time t3, the foreground operation in plane P1 is completed, and the P1RDY status bit changes to the ready state. The status bits of planes P0, P2, and P3 remain unchanged. At this point, the device can accept a select type 2 command for plane P1.

[0311] At time t4, a third type 2 command for plane P0 is received. The device begins an overlapping operation period, in which the operation foreground of P0 is reserved until the background operation of the first type 2 command for plane P0 is completed, and the status bit P0RDY and status bit P0IO# of plane P0 are set to the busy (operating) state. In this example, the background operation of the first type 2 command for plane P0 has not yet been completed. Therefore, there is an overlap between the operation sequences of the first command and the third command. When the memory operation executed according to the first command releases resources, the foreground operation of the third command is started during the busy state of P0RDY. The status bits of planes P2 and P3 remain in the ready (idle) state. The status bit of P1 remains unchanged. The device cannot accept new commands for plane P0. The device can accept a selection type 2 command for plane P1. The device can accept new type 2 commands for planes P2 and P3.

[0312] At time t5, the background operation in plane P1 is completed, and the P1IO# status bit changes to the ready state. The status bits of plane P0, plane P2, and plane P3 remain unchanged. At this time, the device can accept type 2 commands for plane P1.

[0313] At time t6, the foreground operation executed in response to the third command in plane P0 is completed, and the P0RDY status bit changes to the ready state. The status bits of planes P1, P2, and P3 remain unchanged. At this point, the device can accept the Select Type 2 command for plane P0 and the Type 2 commands for planes P1, P2, and P3. The background operation executed in response to the third command continues until it is completed, at which time (not shown) the P0IO# status bit will change to the idle state.

[0314] In reference Fig. 22 and Fig.23 In the described embodiment, the foreground operation is performed without changing the state of the unselected planes to a busy (operating) state. In another embodiment, the foreground operation is performed in a manner that requires changing the state of the unselected planes to a busy (operating) state during the first phase of the operation for which the execution of the command may require shared resources (such as command processing resources).

[0315] Fig.24 and Fig.25 Represents logic for accepting and rejecting commands and for setting and resetting status signals for Type 2 commands, where foreground operations are performed in a manner that requires changing the state of unselected planes to a busy (operating) state during the first phase of the foreground operation.

[0316] Fig.24 1 is a diagram showing logic for accepting and rejecting commands for planes P0 to P3 in the upper portion of the diagram, and showing the ready / busy (idle / in operation) states of status bits PxRDY and status bits PxIO# for the following cases in the lower portion: a type 2 command (AIPO) for plane P0 that does not include background operations is received at time t0, and a second type 2 command for P1 that does not include background operations is received at time t2. Prior to time t0, all status bits are in the ready (idle) state, and the control logic on the memory device can accept any type of command. At time t0, the device starts at foreground operations in plane P0, and sets status bits PxRDY and status bits PxIO# for planes P0 to P3 to the busy (in operation) state.

[0317] At time t1 , the first stage of the operation of the command for plane P0 is completed, and the status bits of planes P1 to P3 are changed to the ready (idle) state.

[0318] Between time t0 and time t1 , the logic for accepting and rejecting commands rejects all commands.

[0319] At time t1, the logic may accept other Type 2 commands for planes P1 to P3. Commands for plane P0 will not be accepted. Type 1 commands will be rejected during this interval.

[0320] At time t2, a second Type 2 command for plane P1 is received. The device accepts the command and starts at the foreground operation in plane P1. In addition, the device sets the status bits PxRDY and PxIO# of planes P2 and P3 to the busy (operating) state. The status bits of plane P0 remain in the busy (operating) state corresponding to the execution of the foreground operation of the first command. Commands for plane P0, plane P1, plane P2, or plane P3 will not be accepted.

[0321] At time t3, the first phase of the operation for the command for plane P1 is completed, and the status bits of planes P2 and P3 are changed to the ready (idle) state. The status bit of plane P0 remains unchanged due to the ongoing operation.

[0322] Between time t2 and time t3, the logic for accepting and rejecting commands rejects all commands.

[0323] At time t3, the logic may accept other Type 2 commands for Plane P2 and Plane P3. Commands for Plane P0 to Plane P1 will not be accepted. Type 1 commands will be rejected during this interval.

[0324] At time t4, the foreground operation of the first command is completed and the status bit P0RDY and status bit P0IO# of plane P0 are changed to the ready (idle) state, thereby allowing acceptance of type 2 commands for plane P0. The foreground operation of the second command is completed at a later time, and the status bits and logic for accepting and rejecting commands are changed in a manner similar to that described for the first command.

[0325] Fig.25 1 is a diagram showing logic for accepting and rejecting commands for planes P0 to P3 in the upper portion of the diagram, and showing the ready / busy (idle / in operation) states of the status bits PxRDY and PxIO# for the following cases in the lower portion of the diagram: a type 2 command (AIPO) for plane P0 including both foreground and background operations is received at time t0, a second type 2 command for P1 including both foreground and background operations is received at time t2, and a third type 2 command for P0 including both foreground and background operations is received at time t6. Prior to time t0, all status bits are in the ready (idle) state, and the control logic on the memory device can accept any type of command.

[0326] At time t0, the device starts at foreground operation in plane P0 and sets the status bits PxRDY and PxIO# of all planes to the busy (operating) state. Background operation starts at or during the start of the operating state of P0IO#. The device cannot accept new commands for planes P0 to P3.

[0327] At time t1 , the first stage of the operation of the command for plane P0 is completed, and the status bits of planes P1 to P3 are changed to the ready (idle) state.

[0328] Between time t0 and time t1 , the logic for accepting and rejecting commands rejects all commands.

[0329] At time t1, the logic may accept other Type 2 commands for planes P1 to P3. Commands for plane P0 will not be accepted. Type 1 commands will be rejected during this interval.

[0330] At time t2, the device begins foreground operation in plane P1 in response to the second command for plane P1, and sets the status bits of planes P1 to P3 to the busy (operating) state. Background operation begins at or during the start of the operating state of P1IO#. The status bits of P0 remain unchanged. The device cannot accept new commands for plane P0, plane P1, plane P2, or plane P3.

[0331] At time t3, the first stage of the operation of the command for plane P1 is completed, and the status bits of plane P2 and plane P3 are changed to the ready (idle) state.

[0332] Between time t2 and time t3, the logic for accepting and rejecting commands rejects all commands.

[0333] At time t3, the logic may accept other Type 2 commands for planes P2 and P3. Commands for planes P0 and P1 will not be accepted. Type 1 commands will be rejected during this interval.

[0334] At time t4, the foreground operation in plane P0 is completed, and the P0RDY status bit changes to the ready state. The status bits of planes P1 to P3 remain unchanged. At this time, the device can accept a select type 2 command for plane P0.

[0335] At time t5, the foreground operation in plane P1 is completed and the P1RDY status bit changes to the ready state. The status bits of plane P0, plane P2, and plane P3 remain unchanged. At this time, the device can accept select type 2 commands for plane P0 and plane P1.

[0336] At time t6, a third type 2 command for plane P0 is received. The device begins an overlapping operation period, in which the foreground operation of P0 is in reserve until the background operation of the first type 2 command for plane P0 is completed, and the status bits of planes P0 to P4 are set to the busy (operating) state. In this example, the background operation of the first type 2 command for plane P0 and the background operation of the second type 2 command for plane P1 have not yet been completed. Therefore, there is an overlap between the background operation sequence of the first command and the third command for plane P0. When the memory operation executed according to the first command releases resources, the operation of the third command is started during the busy state of P0RDY. The device cannot accept new commands for planes P0 to plane P3.

[0337] At time t7, the first stage of the operation of the third command for plane P0 is completed, and the status bits of planes P2 to P3 are changed to the ready (idle) state. Due to the background operation performed in response to the second command, the P1IO# status bit of plane P1 remains in operation. Between time t6 and time t7, the logic for accepting and rejecting commands rejects all commands.

[0338] At time t7, the logic may accept other Type 2 commands for planes P2 and P3. Select Type 2 commands for plane P1 may be accepted. Commands for plane P0 will not be accepted. Type 1 commands will be rejected during this interval.

[0339] At time t8, the foreground operation executed in response to the third command in plane P0 is completed, and the P0RDY status bit changes to the ready state. The status bits of planes P1, P2, and P3 remain unchanged. At this point, the device can accept select type 2 commands for planes P0 and P1, and all type 2 commands for planes P2 and P3. The background operation executed in response to the third command continues until it is completed, at which time (not shown) the P0IO# status bit will change to the idle state.

[0340] At time t9, the background operation in plane P1 is completed, and the P1IO# status bit changes to the idle state. The status bits of planes P0, P2, and P3 remain unchanged. At this time, the device can accept type 2 commands for planes P1, P2, and P3. Only select type 2 commands for plane P0 are accepted.

[0341] Fig.261 is a diagram showing logic for accepting and rejecting commands for planes P0 to P3 in the upper portion of the diagram, and showing the ready / busy (idle / operating) states of status bits PxRDY and status bits PxIO# for the following situations in the lower portion of the diagram: a sequence of type 1 commands without background operations is received. A first type 1 command (SCO command) for planes P0 and P1 is received at time t0, and a second type 1 command for plane P2 is received at time t2. Prior to time t0, all status bits are in the ready (idle) state, and the control logic on the memory device can accept any type of command. At time t0, the device begins operation, and the status bits PxRDY and status bits PxIO# for all planes P0 to P3 are set to the busy (operating) state.

[0342] At time t1, the operation of the first command is completed, and the status bits PxRDY and PxIO# of all planes P0 to P3 are in the ready (idle) state. Between time t0 and time t1, the logic for accepting and rejecting commands may reject all commands.

[0343] At time t2, a second type 1 command without background operation is received for plane P2. The device accepts the command and starts at foreground operation in plane P2. In addition, the device sets the status bits PxRDY and PxIO# of all planes P0 to P3 to the busy (operating) state. In the interval after time t2, all commands will be rejected until the status bits change.

[0344] Fig. 27 1 is a diagram showing logic for accepting and rejecting commands for planes P0 to P3 in the upper portion of the diagram, and showing the ready / busy (idle / operating) states of status bits PxRDY and status bits PxIO# for the following situations in the lower portion of the diagram: A sequence of type 1 commands is received. A first type 1 command (SCO command) with background operation for planes P0 and P1 is received at time t0, and a second type 1 command for plane P1 is received at time t2. Prior to time t0, all status bits are in the ready (idle) state, and the control logic on the memory device can accept any type of command. At time t0, the device begins operation, and the status bits PxRDY and status bits PxIO# for all planes P0 to P3 are set to the busy (operating) state.

[0345] At time t1, the foreground operation of the first command is completed and the status bits PxRDY of all planes P0 to P3 are in the ready state, while the status bits PxIO# of all planes P0 to P3 remain in the operating state while the background operation is being performed. Between time t0 and time t1, the logic for accepting and rejecting commands may reject all commands.

[0346] At time t2, a second Type 1 command with no background operation for plane P1 is received. The device accepts the command and begins an overlapped operation period in which the foreground operation of the second command is retained until the background operation of the first command is completed. In addition, the device sets the status bits PxRDY and PxIO# of all planes P0 to P3 to the busy (operating) state. Between time t1 and time t2, logic for accepting and rejecting commands may allow for the selection of commands.

[0347] At time t3, the foreground operation of the second command is completed. Also in this example, the background operation of the first command is completed before time t3, thereby allowing the status bits PxRDY and status bits PxIO# of all planes P0 to P3 to return to the ready (idle) state at time t3. In the interval between time t2 and time t3, all commands will be rejected.

[0348] Fig.28 1 is a diagram showing logic for accepting and rejecting commands for planes P0 to P3 in the upper portion of the diagram, and showing the ready / busy (idle / operating) states of the status bits PxRDY and PxIO# for the following situations in the lower portion of the diagram: a sequence of type 1 (e.g., SCO) commands and type 2 (e.g., AIPO) commands are received. A first type 1 command (SCO command) with background operations for planes P0 and P1 is received at time t0, and a second type 2 command without background operations for plane P2 is received at time t2. Prior to time t0, all status bits are in the ready (idle) state, and the control logic on the memory device can accept any type of command. At time t0, the device begins operation, and the status bits PxRDY and PxIO# of all planes P0 to P3 are set to the busy (operating) state.

[0349] At time t1, the foreground operation of the first command is completed and the status bits PxRDY of all planes P0 to P3 are changed to the ready (idle) state, while the status bits PxIO# of all planes P0 to P3 remain in the busy (operating) state while the background operation is being performed. Between time t0 and time t1, the logic for accepting and rejecting commands may reject all commands.

[0350] At time t2, a second type 2 command without background operation is received for plane P1. Between time t1 and time t2, the logic for accepting and rejecting commands may allow selection of commands. The command received is one of the selected commands allowed by this combination of status bits and current operation. The device accepts the command and begins an overlapping operation period in which the background operation of the first command is suspended and the foreground operation of the second command is started because this foreground operation has a higher priority than the suspended background operation. The status bit P1RDY of plane 1 changes to a busy state. The status bits PxRDY of planes P0, plane P2, and plane P3 remain in a ready state. While the background operation of the first command is executing, the status bits PxIO# of all planes P0 to plane P3 remain in an operating state.

[0351] At time t3, the foreground operation of the second command is completed and the background operation of the first command is automatically resumed. The status bit P1RDY of plane P1 changes to the ready state. The status bits PxRDY of plane P0, plane P2, and plane P3 remain in the ready state. When the background operation of the first command is executed, the status bits PxIO# of all planes P0 to plane P3 remain in the operating state. In the interval between time t2 and time t3, only the selection type 2 command for plane P0, plane P2, and plane P3 will be accepted.

[0352] In this example, the background operation of the first command continues to time t4, allowing the status bits PxRDY and PxIO# of all planes P0 to P3 to return to the ready (idle) state at time t4. In the interval between time t2 and time t3, all commands for plane P1 will be rejected.

[0353] Fig.29 To illustrate the above mentioned Figure 1B 2900 ). A flow chart of logic executed by control logic in a system similar to that of FIG. 2901 . In this example, a new command is received ( 2900 ) and applied to a command decoder. The logic circuitry may include a state machine and registers that provide signals indicating the current operation being performed, whether the current operation utilizes a first set of resources or a second set of resources, or both, and other state information. The control logic determines which foreground operation and / or background operation is currently being performed ( 2901 ), and accesses state control circuitry ( 2902 ) of the plane states of multiple planes in the device. This information is then applied to determine whether the new command received at ( 2900 ) is a valid command, which may be accepted or rejected by the logic at step ( 2903 ). If the command is not valid, the command may be rejected and the logic returns to step 2900 to await a subsequent command.

[0354] If the command is valid (e.g., accepted) at step 2903, the logic sets the plane status and operating / idle bits (e.g., PxRDY and PxIO#) to busy and operating 2910 and initiates the foreground operation for the command 2911. The timing of the initiation of the foreground operation and the setting of the status bits may be reversed, or they may be performed simultaneously.

[0355] In conjunction with the foreground operation, the logic determines whether the foreground operation is complete at step 2912. If the operation is not complete, the algorithm waits for completion. If the operation is complete, the logic sets the plane status bit (e.g., PxRDY) to ready (2913). The timing of the initiation of the background operation and the setting of the status bit can be reversed, or they can be performed simultaneously.

[0356] At step 2923, a determination is made as to whether the background operation can be started. If the background operation cannot be started, step 2923 sets the operating / idle state to idle. If the background operation can be started (determined in step 2923), the background operation is started in step 2920. In conjunction with the background operation, the logic determines at step 2922 whether the background operation is complete. If the operation is not complete, the algorithm waits for completion. If the operation is complete, the logic sets the operating / idle state bit to idle (e.g., PxIO#) (2923).

[0357] More generally, Fig.29 An example of a method for operating a memory including a plurality of memory planes, each of the plurality of memory planes including a specific set of resources for storing data from / to the corresponding memory plane. The method includes generating, for each of the plurality of memory planes: (i) a corresponding first status signal indicating a busy state or a ready state of the specific set of resources in the corresponding memory plane; and (ii) a corresponding second status signal indicating a busy state or a ready state of the corresponding memory plane. In addition, the method may include selectively allowing or denying execution of a memory command for a memory plane in the plurality of memory planes based on a state of one or more of the plurality of first status signals and the second status signal.

[0358] Fig.30 is a flow chart of logic executed by a host device or a source device, examples of which are described above with respect to Figure 1ADescribed. In this example, the program executed by the logic starts after receiving a request for a memory read / write operation from an external system source (3000). The logic then translates the request into the target plane / device and memory command format required by the connected multi-plane memory device under its control (3001). Next, the translated command is added to the command queue to be sent to the connected memory device (3002). The logic determines the state of the target device for the top command of the queue (3003). The state of the target device can be maintained as expected state data by the source node, which is stored in a memory accessible by the logic (3050). The expected state data can be updated using commands for reading states from various connected devices and using local information about the issued commands. Through the state of the target device and the top command of the queue, the logic determines whether the command and state are a valid combination (3020). If valid, the logic can issue a command (3021). If it is not a valid combination, the logic can issue a read state command for the target device (3024). In response to the read state command, the current state of the target device is returned. This information may be used to maintain the expected status data 3050. Additionally, this information may be used at step 3020 to determine whether the command and status bits returned by the read status command form a valid combination.

[0359] After issuing the command, in some embodiments, the host logic may check the ready / busy (operating / idle) notification pin (3022) on the target device (if used in the target device). The logic determines at step 3023 whether the change notification has been asserted. If the change notification has been asserted, the logic may make the next command in the queue the top of the queue (3010) and return to step 3003. In addition, the expected status data may be updated. If the change notification has not been asserted, the logic may issue a read status command for the target device (3024). In response to the read status command as discussed above, the current status of the target device is returned. This information may be used to maintain the expected status data (3050). In addition, this information may be used at step 3020 to determine whether the command and the status bits returned by the read status command form a valid combination.

[0360] While the source device or host performs memory system operations, logic may continue to complete commands in the queue.

[0361] Fig.31 1 is a flow chart showing an example logic of accepting or rejecting SCO commands and AIPO commands. Specifically, Fig.31 The logic is shown starting at operation 3100 (eg, a control circuit may receive a memory command for execution). At operation 3102, a determination is made as to whether the new memory command is a SCO command or an AIPO command. The SCO command path will be described first, and the AIPO command path will be described second.

[0362] If the new memory command is a SCO command operation, 3104 will determine whether the chip is idle (for example, PxIO#=Ready for all memory planes on the chip). If operation 3104 determines yes (YES), the SCO command will be accepted for execution in operation 3112. If operation 3104 determines no (NO), operation 3106 will determine whether the chip is ready (for example, PxRDY=Ready for all memory planes on the chip). If operation 3106 determines no, operation 3114 will reject the SCO command. If operation 3106 determines yes, operation 3108 will determine whether the SCO command includes a background operation. If operation 3108 determines no, operation 3114 will reject the SCO command. If operation 3108 determines yes, operation 3110 will determine whether the SCO command is a selected command that can be executed, for example, with existing background operations (see Fig.12 3110 and its example description). If operation 3110 determines no, operation 3114 will reject the SCO command. If operation 3110 determines yes, operation 3112 will accept the SCO command for execution. After operation 3112 and operation 3114, the program will end until a new memory command is received.

[0363] If the new memory command is an AIPO command operation, 3118 will determine whether the target plane of the chip is idle (for example, PxIO#=Ready for the target plane). If operation 3118 determines yes, the AIPO command will be accepted for execution in operation 3112. If operation 3118 determines no, operation 3120 will determine whether the target plane of the chip is ready (for example, PxRDY=Ready for the specific target plane). If operation 3120 determines no, operation 3114 will reject the AIPO command. If operation 3120 determines yes, operation 3122 will determine whether the AIPO command is a selected command that can be executed, for example, with existing background operations (see Fig.12 3122 and its example description). If operation 3122 determines no, operation 3114 will reject the AIPO command. If operation 3122 determines yes, operation 3112 will accept the AIPO command for execution. After operation 3112 and operation 3114, the program will end until a new memory command is received.

[0364] Described herein are multiple flow charts showing logic executed by a memory controller or by a memory device. The logic can be implemented using a processor programmable using a computer program stored in a memory accessible to a computer system, and can be executed by a processor, by dedicated logic hardware (including field programmable integrated circuits), and by a combination of dedicated logic hardware and computer programs. Through all the flow charts herein, it will be understood that many steps can be combined, executed in parallel, or executed in different sequences without affecting the functions implemented. In some cases, as will be understood by those skilled in the art, the reconfiguration steps will achieve the same results as long as certain other changes are also made. In other cases, as will be understood by those skilled in the art, the reconfiguration steps will achieve the same results as long as certain conditions are met. In addition, it will be understood that the flow charts herein only illustrate steps related to understanding the present invention, and it will be understood that a large number of additional steps for implementing other functions can be performed before, after, and between the illustrated steps.

[0365] Although the present invention is disclosed with reference to the preferred embodiments and examples described above, it should be understood that these examples are intended to be illustrative rather than restrictive. It is expected that those skilled in the art will easily come up with modifications and combinations that are within the spirit of the present invention and the scope of the claims.

Claims

1. A memory system, comprising: a plurality of memory planes, each memory plane comprising a plane core and a corresponding specific set of resources, each memory plane being operable to perform foreground operations using at least one of the specific set of resources of the corresponding memory plane and resources of the plane core of the corresponding memory plane and to perform background operations using the resources of the plane core of the corresponding memory plane; an input / output (I / O) interface for receiving memory commands from a host addressed to one or more memory planes of the plurality of memory planes; a state control circuit that generates a state bit corresponding to each memory plane of the plurality of memory planes, the state bit indicating one of a busy state and a ready state of the particular set of resources used by a foreground operation of the corresponding memory plane and one of an operating state and an idle state of the resources of the plane core of the corresponding memory plane; as well as a control circuit operatively coupled to the I / O interface, the state control circuit, and the plurality of memory planes to perform memory operations using the plurality of memory planes; wherein when performing a memory operation using one or more memory planes of the plurality of memory planes, the control circuit generates a plurality of state bits corresponding to each memory plane of the plurality of memory planes in the state control circuit; and wherein the control circuitry executes or refuses to execute a memory operation of the received memory command in response to a combination of a received memory command and the plurality of status bits in the status control circuitry, comprising: executing or refusing to execute a memory command of a first type, which depends on a combination of the busy state and the ready state and the operating state and the idle state of all the memory planes in the plurality of memory planes; and executing or refusing to execute a second type of memory command addressed to a specific memory plane regardless of a combination of the busy state and the ready state and the operating state and the idle state of memory planes other than the specific memory plane among the plurality of memory planes.

2. The memory system according to claim 1, wherein the foreground operation includes an operation involving at least one of: a plane core of each memory plane controlling the particular set of resources of each memory plane; and the resources of the plane core of each memory plane, and Wherein the background operations include operations involving the resources of the plane core of the each memory plane and do not include operations involving the plane core of the each memory plane that controls the specific set of resources of the each memory plane.

3. The memory system according to claim 2, wherein the specific resource set of each memory plane is a set of cache memories or temporary registers of each memory plane, such that the foreground operation prevents the host from accessing the cache memories or temporary registers of each memory plane in the plurality of memory planes, and The background operation does not prevent the host from accessing the cache memory or register of each of the plurality of memory planes, wherein the cache is not controlled by each plane core of each of the memory planes.

4. The memory system according to claim 1, wherein the first type of memory command is used for a first type of operation, and the control circuit accepts the first type of memory command to perform the first type of operation in response to the following circumstances: the busy state and the ready state of the specific resource set used by the foreground operation in each memory plane of the multiple memory planes are both in ready; and the operating state and the idle state of the resources of each plane core are both in idle.

5. A memory system according to claim 1, wherein the first type of memory command is used for a first selection type of operation, and the control circuit accepts the first type of memory command to perform the first selection type of operation under the following circumstances: the busy state and the ready state of the specific resource set used by the foreground operation in each memory plane of the multiple memory planes are both ready; the operating state and the idle state of the resources of each plane core are both in operation according to another first type of memory command; and the first selection type of operation can be executed together with the existing background operation.

6. The memory system according to claim 1, wherein the overlapping operation period is a period during which a new memory command is accepted by the control circuit while an existing background operation of a previous memory command is being executed, and The control circuit is configured such that during the overlapping operation period and when the new memory command has a higher priority than the previous memory command, the existing background operation is suspended to allow the foreground operation of the new memory command to be processed, and the suspended background operation is resumed after the foreground operation of the new memory command is completed. 7 . The memory system of claim 6 , wherein the new memory command having the higher priority is a memory command that does not include a background operation.

8. The memory system according to claim 1, wherein the overlapping operation period is a period during which a new memory command is accepted by the control circuit while an existing background operation of a previous memory command is being executed, and Wherein the control circuit is configured such that during the overlapping operation period and when the new memory command does not have a higher priority than the previous memory command, a foreground operation of the new memory command begins after the existing background operation is completed.

9. A memory system according to claim 1, wherein the second type of memory command is used for a second type of operation on a target memory plane, and the control circuit accepts the second type of memory command to perform the second type of operation in the following circumstances: the busy state and the ready state of the specific resource set used by the foreground operation in each memory plane of the multiple memory planes include the ready state in the specific resource set of the target memory plane; and the operating state and the idle state of the resources of each plane core include the idle state in the resources of the plane core of the target memory plane.

10. A memory system according to claim 1, wherein the second type of memory command is used for an operation of a second selected type for a target memory plane, and the control circuit accepts the second type of memory command to perform the operation of the second selected type in the following circumstances: the busy state and the ready state of the specific resource set used by the foreground operation in each memory plane of the multiple memory planes include the ready state of the specific resource set of the target memory plane; the operating state and the idle state of the resources of the plane core in the target memory plane are in operation according to another second type of memory command; and the operation of the second selected type can be executed together with the existing background operation.

11. A memory system according to claim 1, wherein the second type of memory command is used for a second selected type of operation on a target memory plane, and the second type of memory command is accepted by the control circuit to perform the second selected type of operation in the following circumstances: the busy state and the ready state of the specific resource set used by the foreground operation in each memory plane of the multiple memory planes include the ready state of the specific resource set of the target memory plane; the operating state and the idle state of the resources of the plane core in the target memory plane are in operation according to the first type of memory command; and the second selected type of operation can be executed together with the existing background operation.

12. The memory system according to claim 1, wherein: The first type of memory commands are synchronous chip operations, and the second type of memory commands are asynchronous independent plane operations.

13. The memory system of claim 1 , wherein the memory command comprises a reset plane command for a target memory plane, and when the operating state and the idle state of the resources of the plane core in the target memory plane are in operation according to a second type of memory command, the reset plane command is accepted by the control circuit for execution, so that the ongoing second type of operation of the target memory plane is terminated.

14. The memory system of claim 1, wherein the plane core of one of the memory planes is 3D NAND flash memory.

15. A memory system according to claim 1, wherein the plane core of one of the memory planes is at least one of the following: a memory cell that stores data; an error-free memory cell that includes an ECC circuit to correct the data; an in-memory computing unit configured to perform data computing functions; and a memory cell configured to execute an in-memory search command.

16. The memory system of claim 1, wherein: The memory system is configured to perform operations that occupy a target memory plane; and During the first execution phase of the operation, the memory system is configured to set the busy state and the ready state of the target memory plane to busy and set the operating state and the idle state of the target memory plane to operating for a foreground operation, regardless of the busy state and the ready state and the operating state and the idle state of the multiple memory planes other than the target memory plane.

17. The memory system of claim 16, wherein during the second execution phase of the operation, the memory system is configured to change the busy state and the ready state of the target memory plane to ready and maintain the operating state and the idle state of the target memory plane as operating for a background operation, regardless of the busy state and the ready state and the operating state and the idle state of the multiple memory planes other than the target memory plane.

18. The memory system of claim 17 , wherein during a pre-processing operation period occurring before the first execution stage and the second execution stage to execute the operation occupying the target memory plane, the busy state and the ready state of each memory plane in the plurality of memory planes are set to busy and the operating state and the idle state of each memory plane in the plurality of memory planes are set to operating.

19. A method of operating a memory system, the memory system comprising a plurality of memory planes, each memory plane comprising a plane core and a corresponding specific resource set, each memory plane being operable to perform foreground operations using the specific resource set of the corresponding memory plane and to perform background operations without the specific resource set of the corresponding memory plane, the method comprising: A corresponding first status signal indicating a busy state or a ready state of the specific resource set used by a foreground operation of the corresponding memory plane and a corresponding second status signal indicating an operating state or an idle state of the plane core of the corresponding memory plane are generated for each memory plane of the plurality of memory planes.

20. The method of operating a memory system according to claim 19, further comprising: Execution of a memory command directed to a memory plane of the plurality of memory planes is selectively permitted or denied based on a state of one or more of the plurality of first state signals and the second state signal.

Images