Memory system and control method thereof

Abstract

The invention provides a storage system capable of improving reliability and a control method thereof. A memory system according to an embodiment includes: a memory device having a plurality of memory cells; and a memory controller. The memory controller measures an error bit number of data read from the plurality of memory cells, and controls a write distribution interval in a threshold voltage distribution of the plurality of memory cells according to the measured error bit number.

Description

Related Applications

[0001] This application claims the priority of Japanese Patent Application No. 2023-148724 (filing date: September 13, 2023) as a basic application. The present application incorporates the entire contents of the basic application by reference. Technical Field

[0002] The present embodiment relates to a storage system and a control method thereof. Background Art

[0003] Some storage devices have storage devices including multiple storage cells. With the large capacity of storage devices in recent years, the amount of data that can be stored in one storage cell is increased by multi-valued storage. As an example of multi-valued storage, there is the storage of data using QLC (Quad-Level Cell). However, in QLC, since the threshold voltage of each storage cell after writing is one of 16 types, the threshold voltage distribution will be refined. Due to the change in the threshold voltage distribution caused by the stress on the storage cell, the reduction in reliability will become a problem. Summary of the invention

[0004] Provided are a storage system capable of improving reliability and a control method thereof.

[0005] The storage system of this embodiment includes: a storage device having a plurality of storage cells; and a memory controller that measures the number of error bits of data read from the plurality of storage cells and controls a write distribution interval in a threshold voltage distribution of the plurality of storage cells according to the measured number of error bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 This is a block diagram showing the configuration of the information processing system according to the first embodiment. Figure 2 This is a block diagram showing the configuration of a memory cell according to the first embodiment. Figure 3 : is a circuit diagram showing the configuration of a memory cell array according to the first embodiment. Figure 4 This is a block diagram showing the functional configuration of the CPU according to the first embodiment. Figure 5 This is a block diagram showing the contents stored in the ROM according to the first embodiment. Figure 6 It is a diagram showing the threshold voltage distribution of the memory cell according to the first embodiment. Figure 7 1 is a diagram showing the number of error bits in the memory cell according to the first embodiment. Figure 8 Graph showing the number of error bits of memory cells per word line according to the first embodiment. Fig. 9 This is a flowchart showing the operation of the storage system according to the first embodiment. Fig.10 It is a diagram showing the contents of the parameter list according to the first embodiment. Fig.11 This is a diagram showing an example in which the write distribution interval between two adjacent threshold voltage distributions in the threshold voltage distributions of the Er state to the G state according to the first embodiment is increased. Fig.12 This is a diagram showing an example in which the write distribution interval between two adjacent threshold voltage distributions in the threshold voltage distributions of the Er state to the G state according to the first embodiment is reduced. Fig.13 It is a diagram showing the contents of the setting table according to the first embodiment. Fig.14 This is a flowchart showing the operation of the storage system according to the first embodiment. Fig.15 This is a flowchart showing the operation of the storage system according to the first embodiment. Fig.16 This is a block diagram showing the structure of a memory according to the second embodiment. Fig.17 This is a flowchart showing the operation of the storage system according to the second embodiment. Fig.18 It is a diagram showing the contents of a setting table according to the second embodiment. Fig.19 This is a flowchart showing the operation of the storage system according to the second embodiment. Fig. 20 This is a flowchart showing the operation of the storage system according to the second embodiment. DETAILED DESCRIPTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the specification and the drawings, the same elements are denoted by the same reference numerals.

[0008] (First Embodiment) Figure 1 This is a block diagram showing the configuration of the information processing system according to the first embodiment.

[0009] The information processing system of the first embodiment includes a storage system 1 and a host device 2. The storage system 1 is, for example, a memory card, a UFS (Universal Flash Storage) or an SSD (Solid State Drive). The storage system 1 functions as, for example, an external storage device of the host device 2. The host device 2 is an information processing device. The host device 2 is, for example, a personal computer, a server device, or a mobile device. The host device 2 can issue access requests (read requests, write (program) requests, and erase requests) to the storage system 1.

[0010] The storage system 1 includes a memory controller 11 and a memory 12 .

[0011] The memory controller 11 is a semiconductor device that controls the memory 12. The memory controller 11 controls various operations of the memory system 1. For example, the memory controller 11 controls the reading of data from the memory 12 according to a received read request. In addition, the memory controller 11 controls the writing of data to the memory 12 according to a received write request. In addition, the memory controller 11 controls the erasure of data from the memory 12 according to a received erase request.

[0012] The memory 12 (storage device) has a plurality of storage units. The memory 12 is, for example, a binary memory. A binary memory refers to a memory capable of storing two values ​​in each storage unit. Alternatively, the memory 12 is, for example, a multi-value memory. A multi-value memory is a memory capable of storing more than two types of values ​​in each storage unit. For example, when the memory 12 is a 16-value memory, each storage unit can store 16 values. As the 16 values, there are, for example, values ​​from 0 to 15 (0000 to 1111 in binary).

[0013] The memory controller 11 includes a CPU (Central Processing Unit) 11a, a RAM (Random Access Memory) 11b, a ROM (Read Only Memory) 11c, an ECC (Error Correcting Code) circuit 11d, a memory I / F (Interface) controller 11e, and a host I / F controller 11f. The memory controller 11 may also include a storage device storing software.

[0014] The CPU 11 a is a processor that executes various programs.

[0015] The RAM 11b is a volatile memory capable of reading and writing data. The RAM 11b provides a work area for the CPU 11a.

[0016] The ROM 11c is a memory from which data can be read and stores various data necessary for the operation of the CPU 11a.

[0017] The ECC circuit 11d is a circuit that performs processing related to error correction. When data is written to the memory 12 (write data), the ECC circuit 11d encodes the write data. The encoding of the write data means that an error correction code is assigned to the write data. When reading data from the memory 12, the ECC circuit 11d also corrects errors contained in the read data based on the error correction code.

[0018] The memory I / F controller 11e is a circuit that manages the interface between the memory controller 11 and the memory 12. The memory I / F controller 11e controls data transfer between the memory controller 11 and the memory 12 under the control of the CPU 11a.

[0019] The host I / F controller 11f is a circuit that manages the interface between the memory controller 11 and the host device 2. The host I / F controller 11f controls data transfer between the memory controller 11 and the host device 2 under the control of the CPU 11a.

[0020] The memory 12 includes one or more memory units 12a. As an example, Figure 1 The memory 12 is shown as having three memory cells 12a. The memory cell 12a is a memory chip or a memory die. The memory cell 12a has a memory cell array including a plurality of memory cells. The memory cell array functions as a storage area capable of storing data. The details of the memory cell array will be described later. The memory 12 is, for example, a NAND flash memory.

[0021] Figure 2 It is a block diagram showing the configuration of the memory unit 12 a according to the first embodiment.

[0022] Each memory cell 12a of this embodiment has an I / O (Input / Output) signal processing circuit 31, a control signal processing circuit 32, a chip control circuit 33, a RY / BY generation circuit 34, a command register 35, an address register 36, a row decoder 41, a column decoder 42, a data register 43, a sense amplifier 44, and a storage cell array 45.

[0023] The I / O signal processing circuit 31 processes input signals to the memory unit 12a and output signals from the memory unit 12a. The I / O signal processing circuit 31 functions as a buffer. The command, address, and data latched by the I / O signal processing circuit 31 are respectively distributed to the command register 35, the address register 36, and the data register 43.

[0024] The control signal processing circuit 32 processes the control signal to the memory unit 12a. The control signal processing circuit 32 controls the above-mentioned allocation by the I / O signal processing circuit 31 according to the control signal to the memory unit 12a. The control signal input to the control signal processing circuit 32 is, for example, a CE (chip enable) signal, a CLE (command latch enable) signal, an ALE (address latch enable) signal, a WE (write enable) signal, a RE (read enable) signal, and a WP (write protect) signal. The control signal processing circuit 32 also transmits the control signal to the chip control circuit 33.

[0025] The chip control circuit 33 controls the memory unit 12a. The chip control circuit 33 controls the operation of the memory unit 12a according to the control signal transmitted from the control signal processing circuit 32. The operation of the chip control circuit 33 changes, for example, when the state of the chip control circuit 33 changes according to the control signal.

[0026] The RY / BY generation circuit 34 outputs a RY (ready) signal and a BY (busy) signal. The RY / BY generation circuit 34 selectively outputs the RY signal and the BY signal under the control of the chip control circuit 33. When the memory cell 12a is in a non-operating state (ready state), the RY signal is output. When the memory cell 12a is in an operating state (busy state), the BY signal is output.

[0027] The command register 35 is a circuit for storing commands. The commands stored in the command register 35 are read by the chip control circuit 33.

[0028] The address register 36 is a circuit for storing an address. The address stored in the address register 36 is read by the chip control circuit 33, the row decoder 41, and the column decoder 42.

[0029] The row decoder 41 is a circuit that performs control related to the word line of the memory cell array 45. The row decoder 41 applies a voltage to the word line of the memory cell array 45 according to the row address read from the address register 36.

[0030] The column decoder 42 is a circuit that performs control related to the latch circuit of the data register 43. The column decoder 42 selects the latch circuit of the data register 43 based on the column address read from the address register 36.

[0031] The data register 43 is a circuit for storing data. The data register 43 stores data from the I / O signal processing circuit 31 and data from the sense amplifier 44 .

[0032] The sense amplifier 44 is a circuit that performs an operation related to the bit line of the memory cell array 45. The sense amplifier 44 detects data read from the bit line of the memory cell array 45. The row decoder 41, the column decoder 42, the data register 43, and the sense amplifier 44 function as an interface for read operation, write operation, and erase operation with respect to the memory cell array 45.

[0033] The memory cell array 45 is a region where a plurality of memory cells are arranged in an array. The memory cell array 45 is, for example, a three-dimensional memory where memory cells are arranged in a three-dimensional array. The memory cell array 45 functions as a storage region capable of storing data. Further details of the memory cell array 45 will be described later.

[0034] Figure 3 2 is a circuit diagram showing the configuration of the memory cell array 45 according to the first embodiment.

[0035] The memory cell array 45 includes a plurality of blocks. As an example of a plurality of blocks, Figure 3 The block BLK0 and the block BLK1 are shown. The configuration of the blocks in this embodiment will be described below using the block BLK0. The other blocks including the block BLK1 have the same configuration as the block BLK0.

[0036] Block BLK0 includes multiple string units SU0~SU3. String units SU0~SU3 each include p bit lines BL0~BLp-1, a cell source line CELSRC, and p NAND strings STR (p is an integer greater than 2). The NAND string STR has storage cell transistors (storage cells) MT0~MT15 on word lines WL0~WL15, respectively. In addition, the NAND string STR has selection transistors (selection gates) ST0 and DT0 on selection lines SGSL0 and SGDL0, respectively. The selection line SGSL0 is called the source side selection line. The selection line SGDL0 is called the drain side selection line. Other NAND strings STR also have the same structure.

[0037] Figure 4 It is a block diagram showing the functional configuration of the CPU 11 a according to the first embodiment.

[0038] The CPU 11a includes a main control unit 51, a patrol read execution unit 52, a setting table recording unit 53, and an interval parameter control unit 54. For example, the firmware stored in the ROM 11c is expanded in the RAM 11b and executed by the CPU 11a, thereby realizing these functions. In addition, some of these functions can also be realized by dedicated hardware.

[0039] The main control unit 51 receives a command from the host device 2, and sends the command to the memory 12. The command includes, for example, a program command or a read command.

[0040] The patrol read execution unit 52 executes patrol read processing of the storage unit. The patrol read processing is, for example, a data reading processing performed to grasp the change status of the threshold voltage distribution of the written data. The patrol read execution unit (error bit measurement unit) 52 measures the error bit number of the data read from the plurality of storage units through the patrol read processing. The patrol read execution unit 52 stores the measured error bit number in the RAM 11b.

[0041] The setting table recording unit 53 converts the measured number of error bits into an adjustment amount for the write distribution interval with reference to the parameter list 61 described later. The write distribution interval is the interval between two adjacent threshold voltage distributions. The threshold voltage represents a certain data retention state for multiple storage cells. The interval between two threshold voltage distributions corresponds to the interval of the threshold voltage distribution between two different data retention states. The adjustment amount for the write distribution interval is an amount indicating the degree of change relative to the initially set write distribution interval. The setting table recording unit 53 records the converted adjustment amount for the write distribution interval in the setting table 62 described later. The setting table recording unit (adjustment amount storage control unit) 53 generates the adjustment amount for the write distribution interval from the measured number of error bits according to the parameter list 61, and records the generated adjustment amount in the setting table 62. The setting table recording unit 53 records the settings of the parts where the write distribution interval needs to be adjusted in the setting table 62.

[0042] The interval parameter control unit (distribution interval control unit) 54 adjusts the write distribution interval in the threshold voltage distribution according to the measured number of error bits. In addition, the interval parameter control unit 54 controls the write distribution interval according to the parameter list 61 and the measured number of error bits. The interval parameter control unit 54 sets the adjustment amount of the write distribution interval recorded in the setting table 62 in the memory 12. The write distribution interval is related to the reliability of the data stored in the memory cell array 45. The larger the word line with the larger number of error bits, the wider the interval parameter control unit 54 sets the write distribution interval. In this way, the reliability of the stored data can be improved.

[0043] Figure 5 This is a block diagram showing the contents stored in the ROM 11c according to the first embodiment.

[0044] The ROM 11 c stores a parameter list 61 and a setting table 62 .

[0045] The parameter list 61 is information including the correspondence between the number of error bits and the adjustment amount of the write distribution interval. The parameter list 61 is set in advance at least before the storage system 1 is operated.

[0046] The setting table 62 is information recording the location where the write distribution interval is adjusted and the amount of adjustment. The items of the setting table 62 are recorded by the setting table recording unit 53.

[0047] Figure 6 This is a diagram showing an example of threshold voltage distribution of memory cells according to the first embodiment. Figure 6 The vertical axis represents the number of storage cells showing a certain bit value (data value). Figure 6 The horizontal axis represents the threshold voltage of the memory cell. Figure 6 , multiple threshold voltage distributions are shown in a manner that does not overlap with each other.

[0048] When the memory cell operates in TLC (Triple-Level Cell) mode, the threshold voltage of the memory cell forms 8 threshold voltage distributions. The 8 threshold voltage distributions are respectively called Er state, A state, B state, C state, D state, E state, F state, and G state from low to high threshold voltage. In the TLC mode, the threshold voltage distributions of Er state to G state are respectively assigned three different bits of data.

[0049] Figure 7 1 is a diagram showing an example of the number of error bits of a memory cell according to the first embodiment. Figure 7 The vertical axis represents the number of storage cells showing a certain bit value (data value). Figure 7 The horizontal axis represents the threshold voltage of the memory cell. Figure 7 The state where the threshold voltage distribution of the A state and the threshold voltage distribution of the B state overlap with each other is shown.

[0050] The threshold voltage distribution varies depending on various factors and may overlap. The number of error bits is determined by the area of ​​the overlapping diagonal line. The number of error bits between state A and state B is called FBC. B The number of bit errors between any state X and a state Y whose threshold voltage distribution is adjacent to state X and has a higher voltage than state X is called FBC. Y That is, the number of error bits between the Er state and the A state is called FBC A The number of error bits between the B state and the C state is called FBC C The number of error bits between the C state and the D state is called FBC DThe number of error bits between the D state and the E state is called FBC E The number of error bits between the E state and the F state is called FBC F The number of error bits between the F state and the G state is called FBC G .

[0051] Figure 8 Graph showing the number of error bits of memory cells per word line according to the first embodiment. Figure 8 The vertical axis represents the measurement result of the average number of bit errors. Figure 8 The horizontal axis of represents the word line (WL). The ECC correction limit is the limit of the number of error bits in the correction process performed by the ECC circuit 11d. Figure 8 In the example shown, the number of error bits does not exceed the ECC correction limit. Figure 8 As shown, the number of error bits fluctuates in each word line.

[0052] Next, the operation of recording in the setting table 62 performed by the storage system 1 will be described.

[0053] Fig. 9 This is a flowchart showing the operation of the storage system 1 according to the first embodiment. Fig. 9 The following diagram shows the operation recorded in the setting table 62. In the first embodiment, the operation recorded in the setting table 62 is started (start) in response to the execution of the read process for the written block.

[0054] An example of a read process for a written block is a patrol read process performed by the patrol read execution unit 52. The patrol read process is, for example, a data read process performed in order to grasp the change in the threshold voltage distribution of the written data. The patrol read process is sometimes performed at regular intervals (for example, once a day). In addition, the patrol read process is sometimes performed at regular intervals every time the number of programming / erasing reaches a specified number of times (for example, 500 times). The execution frequency of the patrol read process is determined in consideration of the capacity of the memory 12, etc. Another example of a read process for a written block is a read process based on a read request from the host device 2. The read process based on the read request from the host device 2 is sometimes performed, for example, periodically.

[0055] The patrol read execution unit 52 measures the number of error bits in each state (Er state to G state) for the written block (S10). The patrol read execution unit 52 stores the measured number of error bits in the RAM 11b.

[0056] After storing the measured number of error bits in the RAM 11b, the patrol read execution unit 52 sends a signal to the setting table recording unit 53 (S20).

[0057] When receiving the signal from the patrol read execution unit 52, the setting table recording unit 53 reads the measured number of error bits from the RAM 11b (S30).

[0058] The setting table recording section 53 counts the number of error bits read out for each word line (S40). The setting table recording section 53 stores the statistical value of the number of error bits in the RAM 11b.

[0059] After the number of error bits is counted for each word line, the setting table recording unit 53 creates a word line group including a plurality of word lines (S50). A word line group refers to a group including a plurality of word lines having similar values ​​of the number of error bits. A word line group may be created in advance. In addition, a word line group may also be created by a read process based on a read request from the host device 2.

[0060] The setting table recording section 53 obtains the statistical value of the number of error bits in each state (Er state to G state) from the RAM 11 b for each created word line group ( S60 ).

[0061] The setting table recording unit 53 compares the acquired statistical value of the number of error bits with the parameter list 61 (S70). The setting table recording unit 53 determines whether the write distribution interval needs to be adjusted (S80).

[0062] If the write distribution interval does not need to be adjusted (No in S80), the setting table recording unit 53 ends. Fig. 9 A series of processing (end).

[0063] If the write distribution interval needs to be adjusted (Yes in S80), the setting table recording unit 53 records the adjustment amount of the write distribution interval pre-recorded in the parameter list 61 in the setting table 62 (S90). After processing S90, the setting table recording unit 53 ends. Fig. 9 A series of processing (end).

[0064] Fig.10 This is a diagram showing an example of the content of the parameter list 61 according to the first embodiment.

[0065] Fig.10 The measured number of error bits (bit / 4KB) and the adjustment amount Δ of the write distribution interval are shown. The adjustment amount Δ is the change in the write distribution interval relative to the initial setting before the write distribution interval is adjusted. When the adjustment amount Δ is positive, the write distribution interval is expanded relative to the initial setting. When the adjustment amount Δ is negative, the write distribution interval is narrowed relative to the initial setting. Adjustment amount ΔVCG A represents the adjustment amount of the write distribution interval between the Er state and the A state. Similarly, the adjustment amount ΔVCG BIndicates the adjustment amount of the write distribution interval between state A and state B. Adjustment amount ΔVCG C Indicates the adjustment amount of the write distribution interval between the B state and the C state. Adjustment amount ΔVCG D Indicates the adjustment amount of the write distribution interval between the C state and the D state. Adjustment amount ΔVCG E Indicates the adjustment amount of the write distribution interval between the D state and the E state. Adjustment amount ΔVCG F Indicates the adjustment amount of the write distribution interval between the E state and the F state. Adjustment amount ΔVCG G Indicates the adjustment amount of the write distribution interval between the F state and the G state.

[0066] Fig.10 The "FBC A ≥20" and "ΔVCG A = +0.01". This indicates the number of error bits FBC between the Er state and the A state. A When the bit is 20 bits or more, increase the write distribution interval by 0.01.

[0067] Fig.10 The "FBC A ≥50" and "ΔVCG A = +0.02". This means the number of error bits FBC between Er state and A state A When the data size is 50 bits or more, the write distribution interval is increased by 0.02.

[0068] Fig.10 The "FBC A <10” and “ΔVCG A = -0.01". This means the number of error bits FBC between Er state and A state A When the bit size is less than 10 bits, reduce the write distribution interval by 0.01.

[0069] Fig.11 This is a diagram showing an example in which the write distribution interval between two adjacent threshold voltage distributions in the threshold voltage distributions of the Er state to the G state according to the first embodiment is increased.

[0070] The memory system 1 can expand the interval of the threshold voltage distribution when the number of error bits is large.

[0071] Fig.12 This is a diagram showing an example in which the write distribution interval between two adjacent threshold voltage distributions in the threshold voltage distributions of the Er state to the G state according to the first embodiment is reduced.

[0072] The memory system 1 can narrow the interval of the threshold voltage distribution with a small number of error bits.

[0073] Fig.13 It is a diagram showing the contents of the setting table 62 according to the first embodiment.

[0074] The setting represents the position of the die, block (BLock), word line (WL), and the adjustment amount Δ of the write distribution interval associated with each state (Er state ~ G state). The die represents the multiple memory chips (memory cells 12a) that constitute the memory 12. The position of the die is expressed by specifying the parameters ch, ce, and lun. The symbol * in the block and word line represents random (arbitrary value). The adjustment amount Δ includes the adjustment amount ΔVCG A ~Adjustment amount ΔVCG G .

[0075] Fig.13 The first row of the illustrated settings table 62 indicates that the adjustment amount Δ is applied to the entire block "2010". Fig.13 The second row of the setting table 62 shown indicates that the adjustment amount Δ is applied to the word line group “54-57” of the block “3673”. Fig.13 The third row of the illustrated settings table 62 indicates that the adjustment amount Δ is applied to the entire die. Fig.13 The fourth row of the illustrated setting table 62 indicates that the adjustment amount Δ is applied to the word line group "15-27".

[0076] Next, the operation of the storage system 1 during programming will be described.

[0077] Fig.14 This is a flowchart showing the operation of the storage system 1 according to the first embodiment. Fig.14 Shows the actions during programming.

[0078] After receiving the write request from the host device 2 (S110), the main control unit 51 initializes the word line to be programmed (S120). The initialized word line to be programmed is word line "0".

[0079] After setting the access target, the interval parameter control unit 54 searches the setting table 62 for an entry related to the access target (S130). The entry indicates an item recorded in the setting table 62.

[0080] When the entry to be accessed is found (Yes in S140), the interval parameter control unit 54 sets the parameter of the adjustment amount Δ of the entry as the write distribution interval of the word line to be accessed (S150). The parameter of setting the adjustment amount Δ is to update the write distribution interval with the parameter.

[0081] After the parameters of the adjustment amount Δ are set, the main control unit 51 executes programming ( S160 ).

[0082] When the entry of the access target is not found (No in S140 ), the process S160 is executed.

[0083] When the word line to be accessed is not the last word line (No in S170), the next word line after the current word line is incremented by 1 is set as the access target, and the processes S130 to S160 are executed again.

[0084] When the word line to be accessed is the last word line (Yes in S170 ), the main control unit 51 and the interval parameter control unit 54 end the operation during programming (END).

[0085] like Fig.14 As shown, the interval parameter control unit 54 controls the write distribution interval according to the adjustment amount of the write distribution interval recorded in the setting table 62. The main control unit 51 performs programming of a plurality of memory cells at the controlled write distribution interval.

[0086] Next, the operation when the storage system 1 performs reading will be described.

[0087] During the read operation, the read voltage Vth is corrected according to the adjustment amount Δ. The read voltage Vth is a voltage obtained by adding the adjustment amount Δ recorded in the setting table 62 to the read voltage before correction.

[0088] Fig.15 This is a flowchart showing the operation of the storage system 1 according to the first embodiment. Fig.15 Here, an example of sequentially reading data stored in a certain block from word line 0 is described.

[0089] When receiving a read request from the host device 2 (S210), the main control unit 51 initializes the word line to be read (S220). The initialized word line to be read is word line "0".

[0090] After setting the access target, the interval parameter control unit 54 searches the setting table 62 for an entry related to the access target ( S230 ).

[0091] When the entry to be accessed is found (Yes in S240 ), the interval parameter control unit 54 corrects the read voltage Vth of the word line to be accessed according to the adjustment amount Δ of each state (Er state to G state) of the entry ( S250 ).

[0092] After that, the main control unit 51 executes reading (S260).

[0093] When the entry of the access target is not found (No in S240 ), the process S260 is executed.

[0094] When the word line to be accessed is not the last word line (No in S270), the next word line after the current word line is incremented by 1 is set as the access target, and the processes S230 to S260 are executed again.

[0095] When the word line to be accessed is the last word line (Yes in S270 ), the main control unit 51 and the interval parameter control unit 54 terminate the operation during reading (Terminate).

[0096] As described above, according to the first embodiment, the patrol read execution unit 52 measures the number of error bits of the storage cell. The interval parameter control unit 54 controls the write distribution interval in the threshold voltage distribution of the storage cell according to the measured number of error bits. Thus, the write distribution interval can be adjusted according to the quality deviation of the memory 12. In addition, the storage system 1 involved in the first embodiment can optimize the write distribution interval for each word line. For example, by expanding the write distribution interval in the word line with relatively low quality, stress tolerance can be improved. As a result, reliability can be improved. In addition, by narrowing the write distribution voltage in the word line with relatively surplus reliability, power saving can be further achieved.

[0097] By creating a word line group, a plurality of word lines can be collectively managed. This can reduce the required storage capacity and shorten the time required to refer to data. In addition, as a variation, word lines may be managed one by one without creating a word line group.

[0098] In addition, the interval parameter control unit 54 may refer to the parameter table 61 after the patrol read process and immediately set the adjustment amount Δ and the read voltage Vth in the memory 12. Thus, the adjustment is immediately performed when the appropriate adjustment amount Δ and the read voltage Vth are found. In this case, the setting table 62 is not used.

[0099] (Second Embodiment) Fig.16 1 is a block diagram showing the configuration of the memory 12 according to the second embodiment. The second embodiment is different from the first embodiment in that the write distribution interval for each die is adjusted according to the quality variation of the die.

[0100] like Fig.16 As shown, multiple dies are constructed continuously.

[0101] Fig.17 This is a flowchart showing the operation of the storage system 1 according to the second embodiment. Fig.17 This shows the operation recorded in the setting table 62. In the second embodiment, the operation recorded in the setting table 62 is started (started) at an arbitrary timing during the operation of the storage system 1.

[0102] The main control unit 51 programs and reads the test block (S310). The test block is a block that is experimentally read and written in order to confirm the quality of the bare chip.

[0103] After programming and reading the test block, the main control unit 51 measures the number of error bits in each state (Er state to G state) for the test block (S320). The measured number of error bits is stored in the RAM 11b.

[0104] The processes S310 and S320 are performed on all the dies in the test block.

[0105] In addition, in the processes S310 and S320, as a variation, sometimes the same Fig. 9 The same process as the process S10 shown in the figure. In the processes S310 and S320 for performing the patrol read process, the test block is not used but an arbitrary written block is used.

[0106] The main control unit 51 or the patrol read execution unit 52 stores the measured number of error bits in the RAM 11b, and then sends a signal to the setting table recording unit 53 (S330).

[0107] When receiving a signal from the main control unit 51 or the patrol read execution unit 52, the setting table recording unit 53 reads the measured number of error bits from the RAM 11b (S340).

[0108] The setting table recording unit 53 counts the number of error bits in each state read for each die (S350). By counting the number of error bits, the worst number of error bits in each state for each die is obtained.

[0109] The setting table recording unit 53 compares the worst error bit number of each state with the parameter list (S360). The setting table recording unit 53 determines whether the write distribution interval needs to be adjusted (S370). In addition, the processing after S370 is the same as Fig. 9 The processes after the process S80 shown are the same.

[0110] Fig.18 It is a diagram showing the contents of the setting table 62 according to the second embodiment.

[0111] exist Fig.18 In the figure, it is shown that Fig.16 The adjustment amount Δ of the write distribution interval associated with each state for two dies, die “0” and die “1”, is shown.

[0112] Next, the operation of the storage system 1 during programming will be described.

[0113] Fig.19This is a flowchart showing the operation of the storage system 1 according to the second embodiment. Fig.19 Shows the actions during programming.

[0114] When the main control unit 51 receives a write request from the host device 2 ( S410 ), the interval parameter control unit 54 searches the setting table 62 for an entry related to the access target ( S420 ).

[0115] When the entry to be accessed is found (Yes in S430 ), the interval parameter control unit 54 sets the parameter of the adjustment amount Δ of the entry as the write distribution interval of the die to be accessed ( S440 ).

[0116] After setting the parameter of the adjustment amount Δ, the main control unit 51 initializes the word line to be programmed (S450). Here, the word line to be programmed is, for example, word line "0".

[0117] When the entry of the access target is not found (No in S430 ), the process S450 is executed.

[0118] After initialization of the word line, the main control section 51 performs programming ( S460 ).

[0119] When the word line to be accessed is not the last word line (No in S470), the next word line after the current word line is incremented by 1 is set as the access target, and the processes S420 to S460 are executed again.

[0120] When the word line to be accessed is the last word line (Yes in S470 ), the main control unit 51 and the interval parameter control unit 54 end the operation during programming (END).

[0121] Next, the operation when the storage system 1 performs reading will be described.

[0122] Fig. 20 This is a flowchart showing the operation of the storage system 1 according to the second embodiment. Fig. 20 Here, an example of sequentially reading data stored in a certain block from word line 0 is described.

[0123] When the main control unit 51 receives a read request from the host device 2 ( S510 ), the interval parameter control unit 54 searches the setting table 62 for an entry related to the access target ( S520 ).

[0124] When the entry to be accessed is found (Yes in S530 ), the interval parameter control unit 54 corrects the read voltage Vth of the word line to be accessed according to the adjustment amount Δ of each state of the entry ( S540 ).

[0125] After that, the main control unit 51 initializes the word line to be read (S550). Here, the word line to be read is word line "0".

[0126] When the entry of the access target is not found (No in S530 ), the process S560 is executed.

[0127] After initialization of the word line, the main control section 51 performs reading ( S560 ).

[0128] When the word line to be accessed is not the last word line (No in S570), the next word line after the current word line is incremented by 1 is set as the access target, and the processes S520 to S560 are executed again.

[0129] When the word line to be accessed is the last word line (Yes in S570 ), the main control unit 51 and the interval parameter control unit 54 terminate the operation during reading (Terminate).

[0130] According to the second embodiment, the write distribution interval can be optimized for each die.

[0131] As in the second embodiment, the write distribution interval for each die may be adjusted according to the quality variation of the die. The storage system 1 of the second embodiment can obtain the same effects as the first embodiment.

[0132] The above-described embodiments are illustrative, and the scope of the invention is not limited thereto. For example, the component unit for adjusting the write distribution interval is not limited to the word line described in the first embodiment or the memory chip (bare die) described in the second embodiment, but may be other component units such as blocks. [Explanation of Reference Numerals]

[0133] 1 Storage System 2 Host device 11 Memory Controller 11a CPU 11b RAM 11c ROM 11d ECC circuit 11e Memory I / F Controller 11f Host I / F Controller 12 Memory 12a Memory unit 31I / O signal processing circuit 32 Control signal processing circuit 33 Chip control circuit 34RY / BY generation circuit 35 Command Register 36 Address register 41 Line Decoder 42 column decoder 43 Data register 44 Sense Amplifier 45 Memory Cell Array 51 Main control unit 52 Patrol Read Execution Unit 53 Setting table recording section 54 Interval parameter control unit 61 Parameter list 62 Setting table

Claims

1. A storage system comprising: A memory device having a plurality of memory cells; and A memory controller measures the number of error bits of data read from the plurality of memory cells and controls a write distribution interval in a threshold voltage distribution of the plurality of memory cells according to the measured number of error bits.

2. The storage system according to claim 1, wherein: The memory controller controls the write distribution interval according to the corresponding relationship between the number of error bits and the adjustment amount of the write distribution interval and the measured number of error bits.

3. The storage system according to claim 2, wherein: The memory controller generates an adjustment amount of the write distribution interval by applying the measured number of error bits to the correspondence and stores the adjustment amount in a storage unit, and controls the write distribution interval according to the adjustment amount of the write distribution interval stored in the storage unit.

4. The storage system according to claim 1, wherein: The memory controller controls the write distribution interval in a predetermined unit including the plurality of memory cells.

5. The storage system according to claim 4, wherein: The specified unit includes a memory chip, a block, or a word line.

6. The storage system according to claim 1, wherein: The memory controller performs programming of the plurality of memory cells at the controlled write distribution intervals.

7. The storage system according to claim 1, wherein: The memory controller controls a read voltage of the memory cell according to an adjustment amount of the write distribution interval.

8. The storage system according to claim 1, wherein: The memory controller measures the number of error bits by periodically performing a read process on the plurality of memory cells.

9. A control method, which is a method for controlling a storage device having a plurality of storage units, comprising: measuring the number of error bits of data read from the plurality of storage cells; as well as According to the measured number of error bits, a write distribution interval in the threshold voltage distribution of the plurality of memory cells is controlled.

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