A method, device, storage medium and electronic device for reducing chip configuration pins

Abstract

A method for reducing chip configuration pins provided by the present invention divides chips into an active loading mode and a passive loading mode based on the chip loading method; analyzes the loading timings of different loading methods in the active loading mode or the passive loading mode, finds out the differences in the loading timings of different loading methods under the same type of loading mode, and modifies the corresponding data streams at the points where the loading timings of different loading methods under the same type of loading mode are different in the loading data stream when generating the loading data stream on the host computer; if the data streams of different loading methods under the same type of loading mode can be merged into one type of data stream after modification, then different loading methods under the same type of loading mode can share the same mode pins for chip configuration. The present invention also provides a device for reducing chip configuration pins, a computer-readable storage medium, and an electronic device.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and particularly relates to a method, device, storage medium and electronic device for reducing chip configuration pins. Background Art

[0002] A Field Programmable Gate Array (FPGA) is a large-scale programmable device that solves the deficiencies of custom circuits. Users can describe the required functions through a hardware description language, then compile the description language into a data stream file through software, and finally implement the configuration of the FPGA. The advantages of programmability, reconfigurability, and simplicity of use make FPGAs widely used in various fields.

[0003] For an FPGA chip based on SRAM technology, an external configuration data stream file needs to be loaded during the power-on process. The external configuration data stream file is generated by an FPGA compilation tool. The configuration data stream file is stored in an external flash memory, eeprom (electrically erasable programmable read-only memory), SD card, or host computer. The FPGA chip based on SRAM technology can load these data stream files in an active or passive manner, and load the corresponding data stream files through various interfaces. Each method of loading the data stream is different, and it can be determined by the configuration pins of the FPGA. With the continuous progress of FPGA technology, the FPGA is updated very quickly, and the configuration modes are ever-changing. At this time, the corresponding configuration pins will be more and more. Taking the current mainstream FPGAs as an example, the general configuration modes include active serial, active parallel, SPI, BPI, JTAG, passive serial, passive parallel, daisy chain, etc. Taking the above 8 configuration modes as an example, at least 3-bit configuration pins are required. When more configuration modes need to be supported, more configuration pins are required. In some large-scale FPGA applications, due to the large number of pins, the extra configuration pins have little impact. However, for some miniaturized FPGA applications, the extra configuration pins will occupy additional resources, which is not conducive to the application of the system.

[0004] Not only for the loading of FPGA chips, but also for some chips with multiple loading methods, in order to meet the needs of different loading methods, multiple different mode pins are set to distinguish different loading methods during chip loading. When there are more loading methods, the number of required mode pins is also more. The extra mode pins will occupy more hardware resources, which is not only not conducive to the application of the system, but also not conducive to the miniaturization process of the chip. Summary of the Invention

[0005] The present invention provides a method, apparatus, storage medium, and electronic device for reducing the number of chip configuration pins. By modifying the data stream, multiple loading methods use the same type of data stream, and a chip can be loaded and configured through a single mode pin, thereby reducing the number of pins.

[0006] Other objects and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0007] To achieve one or part or all of the above objects or other objects, a method for reducing the number of chip configuration pins provided by one technical solution of the present invention classifies chips into an active loading mode and a passive loading mode based on the chip loading method; analyzes the loading timings of different loading methods in the active loading mode or the passive loading mode, finds the differences in the loading timings of different loading methods in the same type of loading mode, and when generating a loading data stream on the host computer, modifies the corresponding data stream at the points where the loading timings of different loading methods in the same type of loading mode are different in the loading data stream; if the data streams of different loading methods in the same type of loading mode can be merged into one type of data stream after modification, then different loading methods in the same type of loading mode can share the same mode pin for chip configuration.

[0008] According to whether the FPGA sends a loading clock signal to an external device, the chip loading method is divided into an active loading mode and a passive loading mode.

[0009] Modifying the corresponding data stream at the points where the loading timings of different loading methods in the same type of loading mode are different includes adding invalid data streams at the points of different timings.

[0010] For the mergeable data streams, define a unified data frame format, compare the loading timings of different loading methods in the same type of loading mode with the unified data frame format, and add invalid data streams at the positions of the data streams corresponding to different timing points.

[0011] Modifying the corresponding data stream at the points where the loading timings of different loading methods in the same type of loading mode are different includes shifting the data stream keywords at different timing points backward.

[0012] For the mergeable data streams, define a unified data frame format, compare the loading timings of different loading methods in the same type of loading mode with the unified data frame format, shift the data streams corresponding to different timing points backward, and fill the vacancies of the data streams after shifting with invalid data streams according to the unified data frame format.

[0013] Sharing the same mode pin for chip configuration includes sharing one mode pin for data transfer and sharing one mode pin for data output.

[0014] Another technical solution of the present invention provides a device for reducing the number of chip configuration pins, including a timing analysis module for classifying different chip loading methods and analyzing the loading timings of different chip loading methods in the same type of loading method to find out the difference points of the loading timings of different chip loading methods in the same type of loading method; a data stream generation module for generating a configuration data stream based on the loading method; a data stream modification module for modifying the data stream that can be merged according to the data stream corresponding to the difference points of the loading timings of different chip loading methods in the same type of loading method analyzed by the timing analysis module; and a pin allocation module for allocating the same mode pins to different loading methods in the same type of loading mode that can be merged into one type of data stream for chip configuration.

[0015] For different loading methods in the same type of loading mode with small timing differences, the data stream modification module defines a unified data frame format, compares the loading timings of different loading methods in the same type of loading mode with the unified data frame format, and adds invalid data streams to the data stream positions corresponding to different timing points.

[0016] For different loading methods in the same type of loading mode with small timing differences, the data stream modification module defines a unified data frame format, compares the loading timings of different loading methods in the same type of loading mode with the unified data frame format, shifts the data streams corresponding to different timing points backward, and fills the vacancies in the data streams after the shift with invalid data streams according to the unified data frame format.

[0017] Another technical solution of the present invention provides a computer-readable storage medium, in which program codes are stored, and the program codes are called by a processor to execute the method for reducing chip configuration pins as described above.

[0018] Another technical solution of the present invention provides an electronic device, including one or more processors; a memory; one or more application programs, wherein the one or more application programs are stored in the memory and configured to be executed by the one or more processors, and the one or more application programs are configured to execute the method for reducing chip configuration pins as described above.

[0019] Compared with the prior art, the beneficial effects of the present invention mainly include: by classifying various loading methods of the chip into an active loading mode and a passive loading mode, analyzing the loading timings of different loading methods in the same type of loading mode, for loading methods with similar timings, merging the data streams of multiple loading methods into one type of data stream by modifying the data stream, and using one configuration pin for data transmission for multiple loading methods merged into one type of data stream.

[0020] To make the above and other objects, features, and advantages of the present invention more apparent and understandable, preferred embodiments are specifically exemplified below and described in detail in conjunction with the accompanying drawings as follows. Description of the Drawings

[0021] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0022] Figure 1 It is a timing diagram of active parallel loading for the first embodiment of the present invention.

[0023] Figure 2 It is a timing diagram of active SD card loading for the first embodiment of the present invention.

[0024] Figure 3 It is the data stream after merging the active parallel loading and active SD loading methods in the first embodiment of the present invention. Detailed Embodiment

[0025] Regarding the foregoing and other technical contents, features, and effects of the present invention, they will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the reference drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0026] Embodiment 1

[0027] Embodiment 1 provides a method for reducing the chip configuration pins. Based on the chip loading method, the chip is divided into an active loading mode and a passive loading mode; the loading timings of different loading methods in the active loading mode or the passive loading mode are analyzed to find out the differences in the loading timings of different loading methods in the same type of loading mode. When generating the loading data stream on the host computer, the corresponding data streams at the points where the loading timings of different loading methods in the same type of loading mode are different are modified in the loading data stream; if the data streams of different loading methods in the same type of loading mode can be merged into one type of data stream after modification, then different loading methods in the same type of loading mode can share the same mode pins for chip configuration.

[0028] As an alternative implementation, according to whether the FPGA sends a loading clock signal to an external device, the chip loading method is divided into an active loading mode and a passive loading mode. When the chip is in the active mode, the chip sends a loading clock to an external device, and after the external storage device receives the loading clock, it sends data to the chip. Therefore, according to whether the chip sends a loading clock to the external storage device before loading, the loading method is classified, and it is more reasonable to merge the pins of the loading methods under the same type of loading mode.

[0029] As an alternative implementation, the corresponding data streams at different points of the loading timings of different loading methods under the same type of loading mode are modified, including adding invalid data streams at different points of the timings.

[0030] Specifically, for the data streams that can be merged, a unified data frame format is defined. Here, a unified data frame format is defined according to whether the loading timings are similar. The loading timings of different loading methods under the same type of loading mode are compared with the unified data frame format, and invalid data streams are added to the corresponding data stream positions at different timing points. In this way, different loading methods can share the same type of data stream, and the data stream lengths used by different loading methods are the same, making the data streams of different loading methods consistent. When the chip reads this data stream, the data stream at the invalid position will be ignored, and the chip configuration will be completed according to the data stream at the valid position. This can ensure that multiple loading methods with mergeable data streams can be recognized and the data loading can be completed. At the same time, the data streams of the chip loading methods with mergeable data streams are of the same type, and a single mode pin can be used to enable the chip to recognize multiple data streams of the same type.

[0031] As an alternative implementation, for the modification of the data stream in the first embodiment, the corresponding data stream keywords at different points of the loading timings of different loading methods under the same type of loading mode can also be shifted backward.

[0032] Specifically, for the data streams that can be merged, a unified data frame format is defined. The loading timings of different loading methods under the same type of loading mode are compared with the unified data frame format, the data streams corresponding to different timing points are shifted backward, and invalid data streams are filled in the vacancies of the data streams after the shift according to the unified data frame format. By shifting the keywords, the key timing points can be kept consistent, and by adding invalid data streams, the format of the data stream can be ensured to be consistent, which is convenient for configuration with a single mode pin.

[0033] As an alternative implementation, the same mode pin is shared for chip configuration, including sharing one mode pin for data transfer and sharing one mode pin for data output. Although some configuration methods require multiple pins to implement data output and data input, in the first embodiment, the number of pins for different chip configuration methods that can be combined is limited, so that multiple loading methods share the same mode pin for chip loading.

[0034] At the same time, when merging data streams, factors such as the size of the merged data stream and the complexity of generating the merged data stream by the host computer need to be considered. The merged data stream should at least have the characteristics of operability and simplicity.

[0035] See Figure 1 and Figure 2 , taking the example that the active parallel loading and active SD card loading of the FPGA chip share the same mode pin in the first embodiment, the inventive points of the present invention are explained.

[0036] Active parallel is a commonly used configuration method for FPGAs. Its interface timing is simple. The FPGA provides a loading clock signal clock, and an external prom device (programmable read-only memory) provides data output. The clock signal output by the FPGA does not interrupt, and the output data does not interrupt either. Its interface timing is as Figure 1 shown.

[0037] Active SD card loading is also a commonly used configuration method for FPGAs. The difference from the active parallel loading method is that active SD card loading requires sending corresponding command instructions. Therefore, there is a separate command pin used to transmit the corresponding instructions. After the SD card receives the relevant instructions and addresses, it then transmits the corresponding data. Its interface timing is as Figure 2 shown.

[0038] Since the active parallel loading and the active SD card loading can be unified as the active loading mode in terms of the external mode pin definition, there is no need for a mode pin to distinguish them. Therefore, one mode pin can identify two loading methods. Since the external mode pins are the same, the corresponding data streams of the active parallel loading and the active SD card loading can be obtained using one mode pin. Although the data streams of both loading methods can be obtained hardware-wise, for the convenience of chip identification, the data streams of the two loading methods need to be modified. Taking the active parallel loading and the active SD card loading as examples, since both are in the active loading mode, the FPGA sends out the clock signal and the external storage device sends out the data, and the FPGA takes the next action based on the received data. First, analyze the timing difference between the active parallel loading and the active SD card loading. At the beginning, the active SD card will send out a command instruction and output a fixed byte (byte) address at the same time. However, during this period, the FPGA is still in the state of receiving data in the active parallel mode. Therefore, when generating the active parallel loading configuration data stream, the data stream corresponding to the period when the active SD card sends out the command instruction is generated as an invalid data stream. At the same time, the data streams at other timings are modified so that the lengths of the two data streams are the same. After such modification, the data stream of the active parallel loading is an invalid data stream in the interval when the active SD card outputs the loading command instruction. At this time, the two data streams can be kept consistent, and the two data streams are unified into one type of data stream and configured using a unified mode pin. At this time, the FPGA can receive and correctly parse the data streams of the two loading methods to complete the loading. The generated active parallel loading data stream is as Figure 3 shown.

[0039] The above description is based on the active parallel loading method and the active SD card loading method in the active loading mode. The method of merging the mode pins for the passive loading mode is the same as the method of merging the active parallel loading method and the active SD card loading method above, and will not be elaborated here in detail.

[0040] Embodiment 2

[0041] Embodiment 2 provides a device for reducing chip configuration pins, including the following modules: a timing analysis module, which is used for classifying different chip loading methods, classifying different chip loading methods into an active loading mode and a passive loading mode according to whether an FPGA issues a loading clock signal, analyzing the loading timings of different chip loading methods in the same type of loading method, and finding out the difference points of the loading timings of different chip loading methods in the same type of loading method; a data stream generation module, which generates a configuration data stream based on the loading method; a data stream modification module, which modifies the data stream that can be merged according to the data stream corresponding to the difference points of the loading timings of different chip loading methods in the same type of loading method analyzed by the timing analysis module; a pin assignment module, which assigns the same mode pins to different loading methods in the same type of loading mode that can be merged into one type of data stream for chip configuration.

[0042] The device for reducing chip configuration pins in Embodiment 2 is used to implement the method for reducing chip configuration pins in Embodiment 1 above.

[0043] As an optional method, the data stream modification module defines a unified data frame format for different loading methods in the same type of loading mode with small timing differences, compares the loading timings of different loading methods in the same type of loading mode with the unified data frame format, and adds invalid data streams to the data stream positions corresponding to different timing points.

[0044] As an optional method, the data stream modification module defines a unified data frame format for different loading methods in the same type of loading mode with small timing differences, compares the loading timings of different loading methods in the same type of loading mode with the unified data frame format, shifts the data streams corresponding to different timing points backward, and fills the vacant positions of the data streams after shifting with invalid data streams according to the unified data frame format.

[0045] Embodiment 3

[0046] Embodiment 3 provides a computer-readable storage medium, in which program code is stored, and the program code is called by a processor to execute the method for reducing chip configuration pins in Embodiment 1. By cooperating with the program code through the computer-readable storage medium to execute the method for reducing chip configuration pins in Embodiment 1, the configuration efficiency can be improved.

[0047] Embodiment 4

[0048] Embodiment 4 provides an electronic device, including one or more processors; a memory; one or more application programs, where one or more application programs are stored in the memory and are configured to be executed by one or more processors, and one or more application programs are configured to execute the method for reducing chip configuration pins in Embodiment 1.

[0049] The above has introduced in detail a method, device, storage medium and electronic device for reducing chip configuration pins. In this article, specific examples are used to elaborate on the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can still be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for reducing chip configuration pins, characterized in that: The chip loading mode is divided into active loading mode and passive loading mode based on the chip loading configuration; Analyze the loading timing of different loading modes in the active loading mode or the passive loading mode, find out the different loading timing points between different loading modes under the same loading mode, and when the upper computer generates the loading data stream, modify the corresponding data stream at the different loading timing points between different loading modes under the same loading mode in the loading data stream, including adding invalid data streams at different timing points or moving the data stream keywords at different timing points backward; If the data streams of different loading modes under the same loading mode can be combined into one type of data stream after modification, the different loading modes under the same loading mode share the same mode pin for chip configuration; Different loading methods merged into one type of data stream share the same type of data stream.

2. A method for reducing chip configuration pins according to claim 1, characterized in that: Depending on whether the FPGA sends a loading clock signal to an external device, the chip loading mode is divided into an active loading mode and a passive loading mode.

3. The method for reducing chip configuration pins according to claim 1, characterized in that: For the mergeable data streams, a unified data frame format is defined, the loading timings of different loading methods under the same loading method are compared with the unified data frame format, and invalid data streams are added to the corresponding data stream positions at different timing points.

4. The method for reducing chip configuration pins according to claim 1, characterized in that: For data streams that can be merged, a unified data frame format is defined, and the loading timings of different loading methods under the same loading method are compared with the unified data frame format. The corresponding data streams at different timing points are shifted back, and compared with the unified data frame format, the gaps in the data streams after the shift are filled with invalid data streams.

5. The method for reducing chip configuration pins according to claim 1, characterized in that: Sharing the same mode pin for chip configuration includes sharing a mode pin for data transmission and sharing a mode pin for data output.

6. A device for reducing chip configuration pins, characterized in that: It includes a timing analysis module, which is used to classify the loading methods of chip loading configurations, and analyze the loading timings of different chip loading methods in the same loading method, and find out the differences in the loading timings between different chip loading methods in the same loading method; A data flow generation module generates a configuration data flow based on the loading mode; The data stream modification module modifies the mergeable data streams and the data streams corresponding to the difference points of the loading timings of different chip loading modes under the same loading mode analyzed by the timing analysis module, including adding invalid data streams at different timing points or moving the data stream keywords at different timing points backward; The pin allocation module allocates the same mode pins to different loading modes under the same type of loading modes that can be combined into one type of data stream to configure the chip, and the different loading modes combined into one type of data stream share the same type of data stream.

7. The device for reducing chip configuration pins according to claim 6, characterized in that: The data flow modification module defines a unified data frame format for different loading methods under the same loading method with small timing differences, compares the loading timing of different loading methods under the same loading method with the unified data frame format, and adds invalid data flow to the corresponding data flow positions at different timing points.

8. The device for reducing chip configuration pins according to claim 6, characterized in that: The data flow modification module defines a unified data frame format for different loading methods under the same loading method with small timing differences, compares the loading timing of different loading methods under the same loading method with the unified data frame format, shifts the corresponding data streams at different timing points backward, and fills the gaps in the data streams after the shift with invalid data streams according to the unified data frame format.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program codes, and the program codes are called by a processor to execute the method for reducing chip configuration pins according to any one of claims 1 to 5.

10. An electronic device, characterized in that: comprising one or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the method for reducing chip configuration pins as described in any one of claims 1-5.

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