Host-based error correction

Abstract

Systems, devices, and methods related to host-based error correction are described. Error correction operations may be performed on a host computing system rather than on a memory system. For example, data containing error bits may be transferred from a memory system to a host computing system, and error correction operations may be performed using circuitry residing on the host computing system. In an example, a method may include receiving, by a host computing system, data including a plurality of uncorrected bits from a memory system coupleable to the host computing system; determining an acceptable error range for the data based at least in part on an application associated with the data; and performing an initial error correction operation on the data based at least in part on the acceptable error range using error correction logic residing on the host computing system.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application, and its parent application is an invention patent application with an application date of June 12, 2020, application number 202010533795.8, and invention name “Host-based error correction”. Technical Field

[0003] The present disclosure relates generally to semiconductor memories and methods, and more particularly to devices, systems, and methods for host-based error correction. Background Art

[0004] Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic systems. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data (e.g., host data, error data, etc.), and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), etc. Non-volatile memory can provide permanent data by saving stored data when power is not supplied, and may include NAND flash memory, NOR flash memory, and resistance variable memory, such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), etc.

[0005] The memory device may be coupled to a host (e.g., a host computing device) to store data, commands, and / or instructions for use by the host while the computer or electronic system is in operation. For example, data, commands, and / or instructions may be transferred between the host and the memory device during operation of the computing or other electronic system. Summary of the invention

[0006] One aspect of the present disclosure provides a method for host-based error correction, wherein the method includes: receiving, by a host computing system, data including a plurality of uncorrected bits from a memory system that can be coupled to the host computing system; determining an acceptable error range for the data based at least in part on an application associated with the data; and performing an initial error correction operation on the data based at least in part on the acceptable error range using error correction logic resident on the host computing system.

[0007] Another aspect of the present disclosure provides an apparatus for host-based error correction, wherein the apparatus includes: an error correction component comprising hardware deployed on a host computing system, wherein the error correction component is configured to execute instructions to perform the following operations: receive data including a plurality of uncorrected bits from a memory device including a plurality of self-selected memory cells that can be coupled to the host computing system; determine an acceptable error range for the data based at least in part on an application associated with the data; and perform an initial error correction operation on the data including the plurality of uncorrected bits based at least in part on the acceptable error range.

[0008] Another aspect of the present disclosure provides an apparatus for host-based error correction, wherein the apparatus includes: a memory device; and a media controller coupled to the memory device, wherein the media controller is configured to: request data including a plurality of uncorrected bits from the memory device, wherein the data contains at least one error; cause the data including the plurality of uncorrected bits to be transmitted to error correction logic, wherein the error correction logic includes circuitry external to the memory device and the media controller; determine an acceptable error range for the data based at least in part on an application associated with the data; and send a command to the error correction logic to cause the error correction component to initiate an initial error correction operation on the data including the plurality of uncorrected bits based at least in part on the acceptable error range. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a functional block diagram of a computing system including a device having a memory system according to several embodiments of the present disclosure.

[0010] Figure 2A is a functional block diagram of a device including error correction components according to several embodiments of the present disclosure.

[0011] Figure 2B is another functional block diagram in the form of a device including error correction components according to several embodiments of the present disclosure.

[0012] Figure 3 is a flow chart representing an example method for host-based error correction according to several embodiments of the present disclosure. DETAILED DESCRIPTION

[0013] Systems, devices, and methods related to host-based error correction are described. Error correction operations may be performed on a host computing system rather than on a memory system. For example, data containing error bits may be transferred from a memory system to a host computing system, and error correction operations may be performed using circuitry resident on the host computing system. In an example, a method may include receiving, by a host computing system, data including a plurality of uncorrected bits from a memory system that may be coupled to the host computing system; determining an acceptable error range for the data based at least in part on an application associated with the data; and performing an initial error correction operation on the data based at least in part on the acceptable error range using error correction logic resident on the host computing system.

[0014] Memory devices such as flash memory devices may be used to store data in a computing system and to transfer such data between hosts associated with the computing system. The data stored in the memory device may be important or even critical to the operation of the computing system. Flash memory devices are utilized as non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a single transistor memory cell that allows for high memory density, high reliability, and low power consumption.

[0015] Two common types of flash memory array architectures include the "NAND" and "NOR" architectures, named for the logical form in which the basic memory cell configuration of each is arranged. In the NOR array architecture, the floating gate memory cells of the memory array are typically arranged in a matrix.

[0016] The gate of each floating gate memory cell of the array matrix is ​​typically coupled to a word select line in a row and its drain is coupled to a column bit line. A NOR architecture floating gate memory array is accessed by activating a row of floating gate memory cells by selecting the word select line coupled to the gate of the memory cell. The row selected memory cell then places its data value on the column bit line by flowing different currents depending on whether the particular cell is in a programmed state or an erased state.

[0017] The NAND array architecture also arranges its array of floating gate memory cells in a matrix so that the gate of each floating gate memory cell of the array is coupled to a word select line in a row. However, each memory cell is not directly coupled to a column bit line through its drain. Instead, the memory cells of the array are coupled together in series in a source-to-drain manner between a source line and a column bit line.

[0018] The memory cells in the NAND array architecture can be configured, for example, to be programmed to a desired state. That is, charge can be placed on or removed from the floating gate of the memory cell to place the cell in a number of stored states. For example, a single-level cell (SLC) can represent two binary states, such as 1 or 0. Flash memory cells can also store more than two binary states, such as 00, 01, 10, or 11. Such cells may be referred to as multi-state memory cells, multi-bit cells, or multi-level cells (MLCs). MLCs can allow the manufacture of higher density memories without increasing the number of memory cells because each cell can represent more than one bit. MLCs can have more than one programmed state, for example, a cell capable of representing two bits can have three programmed states and an erased state.

[0019] Reading of a memory cell may be accomplished by applying appropriate voltages to the control gate and drain and comparing the drain-to-source current, which may be indicative of the voltage threshold (Vt) of the cell, to a reference current (e.g., a "trip point") to determine the state of the memory cell. In an example data read operation, 0 volts may be applied to a selected word line, e.g., to the control gates of one or more cells in the selected word line. A read pass voltage of approximately 5 volts may be applied to unselected word lines, e.g., to the control gates of cells in the unselected word lines. The drain-to-source current, e.g., the "cell current" or "drain current" flowing through the cells on the selected word line indicates the binary logic state of the cell.

[0020] Thus, when the cell current of a particular memory cell is above the trip point, the memory cell is read as having a particular state, such as an erased state or a programmed state. When the cell current of a particular memory cell is below the trip point, the memory cell is read as having a different state. Thus, the desired configured state of the memory cell, such as 00, 01, 10, or 11, depends on whether the cell current is above or below the trip point.

[0021] A memory cell having a state other than its desired / expected configured state (e.g., the state it was programmed into) indicates a data error in the data being read. Many memory devices employ error checking techniques such as correction code (ECC) checking to detect bit errors in the data, such as cells having incorrect states. ECC codes may be associated with a group of cells such as a memory block, a memory segment, or a memory sector, and may reduce read failures by detecting and possibly correcting bit errors. Examples of ECC codes include Hamming codes, Reed-Solomon (RS) codes, Bose-Chaudhuri-Hochquenghem (BCH) codes, cyclic redundancy check (CRC) codes, Golay codes, Reed-Muller codes, Goppa codes, and Denniston codes, among others.

[0022] A read failure occurs when a data bit being accessed, such as a memory cell representing information retrieved by a processor, has an incorrect state. Reducing read failures increases the operational reliability of a memory device and / or system. Error checking / correction techniques may be unable to correct more than a threshold number of erroneous bits. Furthermore, even multiple error checking techniques may be unable to detect more than a certain number of erroneous bits for a given group of cells, such as a data word or data sector.

[0023] In some approaches, these and other error checking techniques are performed on a memory device by, for example, a controller located on the memory device. The memory device controller may be a media controller, such as a non-volatile memory express (NVMe) controller tightly coupled to a memory device (e.g., a memory cell, block, sector, etc. of the memory device).

[0024] As the size and amount of data stored by a memory device increases, the number of error bits in the data stored by the memory device (e.g., a cell group, block, or sector of the memory device) may also increase. As the number of error bits increases, more time and / or processing resources may be consumed in detecting and correcting the error bits. For example, in some approaches, a doubling of the number of error bits may approximately double the need to decode the data and extract the correct data. Furthermore, in some approaches, a doubling of the number of error bits may increase the amount of processing resources used in decoding the data to extract the correct data.

[0025] Because the amount of space available on a memory device (and therefore, the amount of space available to provide processing resources) may be limited due to various constraints such as physical size, cell density, memory array architecture, power limitations, and / or desired storage capacity, it may be difficult to provide sufficient processing resources on a memory device to perform error correction on data stored by the memory device. Therefore, due to physical size and / or power consumption limitations, the performance efficiency of the memory device may be limited in some approaches.

[0026] Additionally, process variability in memory device manufacturing can negatively impact memory device lifetime. For example, process variability can cause a memory device to have additional error bits compared to other memory devices over a given lifetime. As process technology trends toward smaller and smaller memory cells, the effects of process variability can become even more pronounced. To account for the effects of process variability and the effects of smaller and smaller memory cells on process variability, the desire to error correct memory devices can become increasingly greater, which can result in a loss of data throughput for the memory device.

[0027] Therefore, in methods where error correction is performed on a memory device (e.g., using a controller or other circuitry resident on the memory device), the amount of time used for error correction may be undesirably large because processing resources may not be sufficient to quickly provide error correction for erroneous bits in the data. In addition, because the available processing resources on the memory device may not be sufficient to perform error correction operations, especially in memory devices capable of storing large amounts of data, erroneous bits present in the data may not be accurately corrected, which may cause incorrect data to be provided to the computing system or, in some cases, cause a computing system failure. As used herein, the term "residing on..." refers to something being physically located on a particular component. For example, performing error correction on "something resident on a memory device" refers to a situation in which error correction is physically performed on the memory device. The term "residing on..." may be used interchangeably herein with other terms such as "deployed on..." or "located on..."

[0028] These effects may become more pronounced as the storage capacity of memory devices increases, as the memory devices are able to store more and more data, thereby increasing the number of erroneous bits introduced into the data. These effects may be further exacerbated by limitations of some approaches to error correction provided on the memory devices described above, particularly in terms of the amount of data stored therein and the speed at which data retrieval is expected.

[0029] In contrast, embodiments herein are directed to performing error correction operations using circuitry external to the memory device. For example, in some embodiments, error correction may be performed by a host (e.g., a host computing device) coupled to the memory device. The host may include specialized circuitry (e.g., hardware, logic, integrated circuits, etc.) in the form of error correction components for performing error correction operations on data received from the memory device.

[0030] Embodiments herein may allow data to be transferred from a memory device to a host for error correction. Thus, in some embodiments, the memory device may not further perform error correction on the stored data. By performing error correction on the host, in some approaches error correction circuitry disposed on the memory device may be reduced or eliminated, thereby increasing the limited space available on the memory device for other components (e.g., for additional storage devices, etc.).

[0031] As described herein, a host may perform error correction operations (e.g., initial error correction operations) that are performed by a memory device or memory system in some approaches, as well as or in place of error correction operations that may be performed by the host in some approaches. As used herein, "initial error correction operations" refer to error correction operations performed on raw data that have not yet had any class of error correction operations performed on them. For example, initial error correction operations may include operations for correcting errors on data stored by a memory system or memory device that are due to the nature of the storage characteristics of the memory system or memory device. Initial error correction operations are distinguished from post-error correction operations in which the data triggers one or more post-error correction operations to detect or correct residual errors (e.g., undetectable and / or uncorrectable errors) that may be present in the data after the initial error correction operations are performed.

[0032] In some approaches, the host may perform post-error correction operations, such as operations for detecting and / or correcting undetectable and / or uncorrectable errors present in the data after error correction performed by the memory device. However, in embodiments described herein, the host may perform the initial error correction operations performed by the memory device in some approaches, as well as post-error correction operations, such as operations for detecting and / or correcting undetectable and / or uncorrectable errors in the data on which the initial error correction operations have been performed.

[0033] Additionally, because the host may, in some embodiments, include more powerful processing resources than the memory device, error correction may be performed more quickly and / or more thoroughly on the host than in approaches where error correction is performed on the memory device. This may improve the performance of the computing system by allowing improved throughput of data from the memory device as compared to approaches where error correction is performed on the memory device, which in some approaches may be lost due to using limited resources available to the memory device for an aggressive and / or time-consuming error correction process.

[0034] In the following detailed description of the present disclosure, reference is made to the accompanying drawings which form a part of the present disclosure and in which are shown by way of illustration the manner in which one or more embodiments of the present disclosure may be practiced. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the embodiments of the present disclosure, and it is understood that other embodiments may be utilized and process, electrical and structural changes may be made without departing from the scope of the present disclosure.

[0035] As used herein, designators such as "N", "M", etc., specifically with respect to the reference numerals in the drawings, indicate that several specific features so specified may be included. It should also be understood that the terms used herein are only for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the context clearly stipulates otherwise, the singular forms "one" and "the" may include both singular and plural indicators. In addition, "several", "at least one" and "one or more" (e.g., several memory devices) may refer to one or more memory devices, while "multiple" is intended to refer to more than one of such things. In addition, throughout this application, the words "may" and "can" are used in a permissive sense (i.e., with the potential to be able to), rather than in a mandatory sense (i.e., must). The term "including" and its derivatives mean "including but not limited to". Depending on the context, the term "coupled / coupling" means physically directly or indirectly connected or accessing and moving (transmitting) commands and / or data. The terms "data" and "data value" may be used interchangeably herein and may have the same meaning, depending on the context.

[0036] The figures herein follow a numbering convention in which the first one or more digits correspond to the figure number and the remaining digits identify the element or component in the figure. Similar elements or components between different figures may be identified by using similar numerals. For example, 106 may represent Figure 12, and similar elements may be represented as 206 in FIG. 2. A single element symbol may generally be used herein to refer to multiple similar elements or components or groups of elements or components. For example, multiple reference elements 112-1, 112-2, ..., 112-N (e.g., 112-1 to 112-N) may be generally labeled 112. As will be appreciated, elements shown in various embodiments herein may be added, exchanged, and / or removed to provide several additional embodiments of the present disclosure. In addition, the proportions and / or relative dimensions of the elements provided in the figures are intended to illustrate certain embodiments of the present disclosure and should not be considered in a limiting sense.

[0037] Figure 1 1 is a functional block diagram in the form of a computing system 100 including a device having a memory system 104 according to several embodiments of the present disclosure. As used herein, "device" may refer to, but is not limited to, any of a variety of structures or combinations of structures, such as a circuit or circuit system, one or more dies, one or more modules, one or more devices, or one or more systems. The memory system 104 may be, for example, a solid-state drive (SSD), and may include a host interface 108, a controller 110 (e.g., a processor and / or other control circuitry), and a number of memory devices 112-1 to 112-N that provide storage capacity for the memory system 104, such as solid-state memory devices, such as NAND flash devices. In several embodiments, the controller 110, the memory devices 112-1 to 112-N, and / or the host interface 108 may be physically located on a single die or within a single package (e.g., a managed NAND application). Moreover, in several embodiments, the memory (e.g., the memory devices 112-1 to 112-N) may include a single memory device.

[0038] like Figure 1 , the controller 110 may be coupled to the host interface 108 and coupled to the memory devices 112-1 to 112-N via one or more channels and may be used to transfer data between the memory system 104 and the host 102. The interface 108 may be in the form of a standardized interface. For example, when the memory system 104 is used for data storage in the computing system 100, the interface 108 may be a Serial Advanced Technology Attachment (SATA), a Peripheral Component Interconnect Express (PCIe), or a Universal Serial Bus (USB), a Double Data Rate (DDR) interface, and other connectors and interfaces. However, in general, the interface 108 may provide an interface for transferring control, address, data, and other signals between the memory system 104 and the host 102 having a compatible acceptor for the interface 108.

[0039] The host 102 may be a host system, such as a personal laptop computer, a desktop computer, a digital camera, a mobile phone, a device with Internet of Things (IoT) capabilities, or a memory card reader, a graphics processing unit (e.g., a video card), and various other types of hosts. The host 102 may include a system motherboard and / or a backplane and may include a number of memory access devices, such as a number of processing resources (e.g., one or more processors, microprocessors, or some other type of control circuit). A person of ordinary skill in the art will understand that a "processor" may be one or more processors, such as a parallel processing system, a plurality of coprocessors, etc. The host 102 may be coupled to a host interface 108 of the memory system 104 via a communication channel 103.

[0040] In some embodiments, host 102 may be responsible for executing an operating system for computing system 100 including memory system 104. Thus, in some embodiments, host 102 may be responsible for controlling the operation of memory system 104. For example, host 102 may execute instructions (e.g., in the form of an operating system) that manage the hardware of computing system 100 (e.g., scheduling tasks, executing applications, controlling peripherals, etc.).

[0041] The computing system 100 may include separate integrated circuits, or the host 102, the memory system 104, the error correction component 106, the host interface 108, the controller 110, and / or the memory devices 112-1 to 112-N may be on the same integrated circuit. For example, the system 100 may be a server system and / or a high performance computing (HPC) system and / or a portion thereof. Although Figure 1 The example shown in illustrates a system having a Von Neumann architecture, but embodiments of the present disclosure may be implemented in a non-Von Neumann architecture, which may not include one or more components (e.g., CPU, ALU, etc.) typically associated with a Von Neumann architecture.

[0042] In some approaches, the memory system 104 (e.g., the controller 110) may determine whether data (e.g., memory cells and / or groups of cells, such as data words, or sectors) stored in the memory devices 112-1 to 112-N are erroneous, such as having an incorrect state, using error checking techniques such as error correction codes (ECC). An error or incorrect state may refer to a state of a memory cell other than the state to which it was programmed or written. For example, a non-volatile memory cell may be programmed into a specific logic state, such as 1 or 0, and may undergo a program verification operation for confirming that the cell is programmed into the desired correct state. In such approaches, if an error bit is detected, an error correction operation may be performed on the data by the memory system 104.

[0043] In contrast, Figure 1 As shown, the host 102 may include an error correction component 106 that may determine whether data (e.g., memory cells and / or groups of cells, such as data words, or sectors) of the memory devices 112-1 to 112-N are erroneous using error checking techniques such as ECC. The error correction component 106 may include, for example, a number of components in the form of hardware and / or firmware (e.g., one or more integrated circuits), and / or software for performing error correction operations on data received by the host 102 from the memory system 104. The error correction component 106 may include one or more subcomponents, such as an error correction code (ECC) encoding component 214 and / or an ECC decoding component 216 as illustrated and described herein in conjunction with FIG.

[0044] The error correction component 106 may include hardware and / or firmware that performs error correction operations according to a Bose, Chaudhuri, and Hocquenghem (BCH) error correction scheme, a low-density parity check (LDPC) error correction scheme, a Hamming error correction scheme, a classification code error correction scheme, and / or other types of error correction schemes that may, for example, facilitate error correction on data transferred between the memory devices 112-1 to 112-N and the host 102.

[0045] In some embodiments, error correction component 106 can receive data from memory system 104 via, for example, host interface 108. The data can be encoded according to one or more ECC schemes before being transferred from memory system 104 to host 102 and ultimately to error correction component 106. For example, in some embodiments, controller 110 can encode the data according to one or more ECC schemes before transferring the data to error correction component 106. If error correction component 106 receives data that has been previously encoded according to one or more ECC schemes by memory system 104, error correction component 106 can decode the data according to the one or more ECC schemes as part of performing an error correction operation.

[0046] However, the embodiments are not limited thereto, and in some embodiments, the error correction component 106 may receive unencoded data from the memory system 104 without encoding and / or subsequently decoding the data according to one or more ECC schemes. Thus, the error correction component 106 may be responsible for performing all (or at least a portion) of the error correction operations for the computing system 100. That is, in some embodiments, error correction may not be performed on the data by the memory system 104, and instead, the data may be error corrected only on the host 102, for example, by an error correction component 106 that resides on the host 102 (e.g., tightly coupled to the host 102). As used herein, the term "resides on..." refers to something being physically located on a particular component. For example, an error correction component "resides on the host" refers to a condition in which the error correction component is physically connected to the host. The term "resides on..." may be used interchangeably herein with other terms such as "deployed on..." or "located on..."

[0047] However, embodiments are not limited to an "all or nothing" approach in which all error correction operations are performed on the host 102, and in some embodiments, data may be selectively transferred to the host 102 for error correction. For example, in some embodiments, certain data may be selectively transferred to the host 102 for error correction, while other data may be error corrected on the memory system 104. This may allow data that requires a high level of accuracy (e.g., critical data), data that may take more than a threshold amount of time to error correct, etc. to be error corrected on the host 102, while data that requires a lower level of accuracy and / or may be error corrected in less than a threshold amount of time is error corrected on the memory system 104. Furthermore, by selectively error correcting certain data on the host 102 and error correcting other data on the memory system 104, data that is more likely to contain more than a threshold number of errors may be error corrected on the host 102, while data that is less likely to contain more than a threshold number of errors may be error corrected on the memory system 104. Additionally, this may allow parallel error correction to be performed on different data (e.g., different memory cells and / or cell groups, data words, or sectors) of memory devices 112-1 to 112-N, which may increase the error correction throughput of the data compared to an approach in which error correction is performed only on memory system 104.

[0048] In a non-limiting example, the error correction component 106 may determine that some data to be error corrected requires a higher level of error correction (e.g., higher accuracy, etc.) than other data stored by the memory system 104. For example, the error correction component 106 may determine that a first block of data is critical to the performance of the computing system 100 and a second block of data is less critical to the performance of the computing system 100. The error correction component 106 may assign a higher error correction priority to the first block of data and perform an error correction operation on the first block of data in response to the determination. Depending on the criticality of the second block of data, in this example, the error correction component 106 may perform the error correction operation on the second block of data after performing the error correction operation on the first block of data, or the error correction component 106 may instruct the memory device 104 to perform the error correction operation on the second block of data in parallel with performing the error correction operation on the first block of data.

[0049] In the above examples, as part of determining which data to prioritize in error correction or which data to be error corrected by error correction component 106 and / or memory system 104, error correction component 106 may assign scores or rankings to data stored by memory device 104. These scores may be based on the criticality of the data, the amount of time allowed to perform error correction operations (e.g., if a longer amount of time is allowed to perform error correction, error correction component 106 may perform error correction using a higher number of repetitions than memory system 104), etc.

[0050] By ranking the data and selectively performing error correction on the data based on the ranking using the error correction component 106, error correction reliability may be improved compared to methods in which error correction is performed only by the memory system 106. For example, by utilizing additional processing resources available to the host 102 when performing error correction, higher error correction accuracy may be achieved compared to methods in which error correction is performed using only circuitry available on the memory system 104. Furthermore, by selectively performing some error correction using the error correction component 106 and performing some error correction using the memory system 104 (e.g., the controller 110 on the memory system 104), error correction may be performed on data stored by the memory system 104 simultaneously (e.g., in parallel), which may improve data throughput compared to methods in which error correction is performed using only the memory system 104.

[0051] In some embodiments, by performing error correction operations (e.g., initial error correction operations) using an error correction component 106 resident on the host 102, a greater amount of processing resources may be available for use in performing error correction operations than in approaches in which the error correction operations are performed on the memory system 104. For example, due to space constraints typically associated with a memory system, such as the memory system 104, hardware resources may be more limited than hardware resources available to a host computing system, such as the host 102. The constrained hardware resources available to the memory system 104 may create a tradeoff between speed, power consumption, and / or accuracy (e.g., reduced residual bit error rate (RBER)), as well as other factors, when performing error correction operations using the memory system 104.

[0052] In contrast, by performing error correction operations on the host 102 (e.g., on uncorrected data) using the error correction component 106 described herein, increased hardware resources may be available to perform the error correction operations, which may mitigate or, in some embodiments, eliminate the trade-offs of approaches in which error correction operations are performed on the memory system 104, thereby resulting in improved error correction performance and / or improved data throughput. That is, as described herein, by performing error correction operations on the host 102 using the error correction component 106, more hardware resources may be made available to perform error correction operations than would otherwise be available when the error correction operations were performed on the memory system 104, which may reduce the amount of time to perform error correction operations, reduce RBER, and / or provide improved data accuracy compared to approaches in which error correction operations are performed on the memory system 104.

[0053] In some embodiments, the error correction component 106 may perform operations for detecting and / or correcting undetectable or uncorrectable errors in data received from the memory system 104. However, the error correction operations performed by the error correction component 106 described herein may be different from operations for detecting and / or correcting undetectable or uncorrectable errors in data received from the memory system 104. For example, in an approach in which the memory system 104 (e.g., the controller 110) performs error correction operations, uncorrectable and / or undetectable errors may be handled by the host 102 or other circuitry deployed on the host 102.

[0054] In contrast, embodiments herein may allow for error correction operations to be performed prior to performing operations to detect and / or correct uncorrectable and / or undetectable errors using error correction component 106. Thus, error correction component 106 may perform error correction operations (e.g., initial error correction operations) performed by memory system 104 in some approaches as well as operations to detect and / or correct undetectable and / or uncorrectable errors (e.g., final error correction operations).

[0055] In some embodiments, the error correction component 106 may perform operations as well as error correction operations. For example, the error correction component 106 may perform error detection operations. For example, the error correction component 106 may perform a cyclic redundancy check (CRC) to detect unexpected changes in the data. The CRC may include a check value representing redundancy attached to the data to be error checked. The CRC may additionally include a cyclic code to generate a check value and / or an expected check value. The check value may be compared to an expected check value (e.g., a check value calculated using a cyclic code) to detect errors in the data, if the check value attached to the data does not match the expected check value, then the data contains one or more errors.

[0056] For example, the error correction component 106 may verify that a check value attached to the data matches an expected check value. In some embodiments, the check value may be attached to the data by the memory system 104 (e.g., by the controller 110) before the data is transmitted to the host 102, and the error correction component 106 may calculate the expected check value and compare the calculated expected check value with the check value received with the data to verify that the expected check value matches the check value attached to the data. However, embodiments are not limited thereto, and in some embodiments, the error correction component 106 may attach a check value to the data received from the memory system 104 and then calculate the expected check value, which may then be compared to the check value attached by the error correction component 106 to verify that the expected check value matches the check value attached to the data by the error correction component 106. In some embodiments, the error correction component 106 may perform an error correction operation on the data in response to determining that the expected check value does not match the check value attached to the data (e.g., data containing an error bit).

[0057] In some embodiments, the error correction component 106 may also control wear leveling operations for the memory system 104. For example, the error correction component 106 may track which sectors of the memory system 104 (e.g., sectors of the memory devices 112-1 through 112-N) cause data to be written and / or data to be read during operation of the memory system 104. The error correction component 106 may use this information to communicate with the memory system 104 to instruct the memory system 104 to write data to, or read data from, specific sectors of the memory devices 112-1 through 112-N to provide wear leveling for the memory system 104. By using the error correction component 106 to control the wear leveling operations, circuitry present on the memory system 104 to control the wear leveling operations in some approaches may be reduced or eliminated, which may free up additional space on the memory system 104 for other purposes, such as additional storage.

[0058] After the error correction component 106 performs an error correction operation (e.g., an initial error correction operation and / or a post error correction operation) on the data, the host 102 may use the error-corrected data when performing host computing operations. However, embodiments are not limited thereto, and in some embodiments, once the error correction component 106 has performed an error correction operation on the data, the error correction component 106 may cause the data to be transferred back to the memory system 104 for storage by the memory device 112.

[0059] The controller 110 may communicate with the memory devices 112-1 to 112-N to control data read, write, and erase operations, among other operations. The controller 110 may include, for example, a number of components in the form of hardware and / or firmware (e.g., one or more integrated circuits, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA)), and / or software for controlling access to the number of memory devices 112-1 to 112-N and / or for facilitating data transfer between the host 102 and the memory devices 112-1 to 112-N. The controller 110 may include various components for controlling data read, write, erase, etc. operations that are not described in order not to obscure the embodiments of the present disclosure. Such components may not be components of the controller 110, and in some embodiments, for example, components for controlling data read, write, erase, etc. operations may be non-dependent components located within the memory system 104.

[0060] Memory devices 112-1 to 112-N may include several arrays of memory cells. For example, the array may be a flash array having a NAND architecture. However, embodiments are not limited to a particular type of memory array or array architecture. Memory cells may, for example, be grouped into multiple blocks including multiple physical pages. Multiple blocks may be included in a plane of memory cells, and the array may include multiple planes.

[0061] Memory devices 112-1 to 112-N may include volatile memory and / or non-volatile memory. In several embodiments, memory devices 112-1 to 112-N may include multi-chip devices. Multi-chip devices may include multiple different memory types and / or memory modules. For example, a memory system may include non-volatile or volatile memory on any type of module. In embodiments where memory devices 112-1 to 112-N include non-volatile memory, memory devices 112-1 to 112-N may be flash memory devices, such as NAND or NOR flash memory devices. However, embodiments are not limited thereto, and the memory devices 112-1 to 112-N may include other nonvolatile memory devices, such as nonvolatile random access memory devices (e.g., NVRAM, ReRAM, FeRAM, MRAM, PCM), "emerging" memory devices, such as resistance variable (e.g., 3-D cross point (3D XP)) memory devices, memory devices including self-select memory (SSM) cell arrays, etc., or combinations thereof. The resistance variable memory device may combine a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, compared to multiple flash-based memories, the resistance variable nonvolatile memory may perform write-in-place operations, where the nonvolatile memory cells may be programmed without pre-erasing the nonvolatile memory cells. Compared to flash-based memories and resistance variable memories, the self-select memory cells may include memory cells having a single chalcogenide material that acts as both a switch and a storage element of the memory cell.

[0062] The memory devices 112-1 to 112-N may provide main memory for the computing system 100 or may be used as additional memory or storage devices throughout the computing system 100. Each memory device 112-1 to 112-N may include memory cells, such as one or more arrays of volatile and / or non-volatile memory cells. For example, the arrays may be flash arrays having a NAND architecture. Embodiments are not limited to a particular type of memory device. For example, the memory devices may include RAM, ROM, DRAM, SDRAM, PCRAM, RRAM, and flash memory, among others.

[0063] In some embodiments, the memory system 104 may include a processing unit 111, which may include a memory resource 113. The processing unit may be a processor, one or more co-processors, a reduced instruction set computing (RISC) device, etc. that may be configured to perform operations on data stored in the memory devices 112-1 to 112-N. In embodiments where the processing unit 111 is a RISC device, the RISC device may be a processing resource that may employ a reduced instruction set architecture (ISA), such as a RISC-V ISA, however, embodiments are not limited to the RISC-V ISA and other processing devices and / or ISAs may be used.

[0064] The processing unit 111 may be configured to perform operations on data stored in the memory devices 112-1 to 112-N. For example, the processing unit 111 may receive data (e.g., uncorrected bits or data that have not yet been subjected to error correction operations) from the memory devices 112-1 to 112-N and may perform operations on blocks of data in which at least some of the data is sorted, reordered, removed, or discarded to selectively remove or otherwise alter portions of the data before the data is transmitted to the error correction component 106 and / or the host 102.

[0065] In some embodiments, memory resource 113 may be a memory resource, such as a random access memory (e.g., RAM, SRAM, etc.). However, embodiments are not limited thereto, and memory resource 113 may include various registers, caches, buffers, and / or memory arrays (e.g., 1T1C, 2T2C, 3T, etc. DRAM arrays). Memory resource 113 may be configured to receive uncorrected data blocks, such as from memory devices such as memory devices 112-1 to 112-N. In some embodiments, memory resource 113 may have a size of approximately 256 kilobytes (KB), however, embodiments are not limited to this particular size, and memory resource 113 may have a size greater or less than 256 KB.

[0066] In some embodiments, processing unit 111 may provide data-driven execution of operations on the uncorrected data received from memory devices 112-1 to 112-N. For example, processing unit 111 may begin to perform operations on the data received from memory devices 112-1 to 112-N in response to receiving the data (e.g., operations such as reducing the size of a data block, extracting relevant information from a data block, removing irrelevant information from the data, etc.).

[0067] For example, due to the uncertain nature of data transfer from memory devices 112-1 to 112-N to processing unit 111 (e.g., because some blocks of data may take a longer time to reach processing unit 111 due to operations performed by controller 110 before the data is transferred to processing unit 111, etc.), performing operations on the data in a data-driven manner may improve computing performance compared to methods that are not performed in a data-driven manner.

[0068] In some embodiments, the operations may be performed by selectively moving data in the memory resource 113 to extract relevant data from the uncorrected data or to remove irrelevant data from the data. In a non-limiting example where two columns of data A and B are requested from the uncorrected data containing three columns of data A, B, and C, the uncorrected data containing all three columns may be transferred to the first partition of the memory resource 113.

[0069] Processing unit 111 may execute instructions to cause the first two columns A and B containing three columns of uncorrected data (e.g., requested or relevant data) to be selectively moved to different partitions of memory resource 113. At this stage, the "filtered" uncorrected data containing only the relevant or requested columns A and B may be transmitted to circuitry external to processing unit 111, such as host 102 and / or error correction component 106 for performing error correction operations. Although described above in the context of "filtered" blocks of data, embodiments are not limited thereto, and processing unit 111 may perform other operations on the uncorrected data in a similar manner, such as operations in which at least some of the data is sorted, reordered, removed, or discarded, arithmetic operations, and / or logical operations.

[0070] Figure 1 Embodiments of the present disclosure may include additional circuitry that is not described to avoid obscuring the embodiments of the present disclosure. For example, the memory system 104 may include address circuitry to latch address signals provided on I / O connections through I / O circuitry. The address signals may be received and decoded by row decoders and column decoders to access the memory devices 112-1 to 112-N. Those skilled in the art will appreciate that the number of address input connections may depend on the density and architecture of the memory devices 112-1 to 112-N.

[0071] Figure 2A and 2B 2 is a functional block diagram of a device 201 including an error correction component 206 according to several embodiments of the present disclosure. The error correction component 206 may be similar to the one described herein. Figure 1 The error correction component 106 described in Figure 2A As shown in , the error correction component 206 may include an error correction code (ECC) encoding component 214 and an ECC decoding component 216. Figure 2BAs shown in FIG. 1 , the ECC encoding component 214 further includes an outer ECC encoder 218 and an inner ECC encoder 220, while the ECC decoding component 216 further includes an outer ECC decoder 222 and an inner ECC decoder 224. The error correction component 206 may reside in (eg, be physically deployed on) a processor such as a processor. Figure 1 On a host of the host 102 described in .

[0072] The ECC encoding component 214 and the ECC decoding component 216 may include, for example, a plurality of components in the form of hardware and / or firmware (e.g., one or more integrated circuits, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA)), and / or for performing operations on a host (e.g., Figure 1 ) and a memory device (e.g., Figure 1 Several components in the form of software that perform error correction operations on data transferred between the memory devices 112-1 to 112-N) illustrated in FIG.

[0073] The ECC encoding component 214 may be implemented as a BCH encoder and / or an iterative encoder, such as an LDPC encoder, or other suitable encoder that encodes data received from a memory system as part of performing an error correction operation on the received data. Similarly, the ECC decoding component 216 may be implemented as a BCH decoder and / or an iterative decoder, such as an LDPC decoder, or other suitable decoder that decodes data received from a memory system as part of performing an error correction operation on the received data.

[0074] As described above, the error correction component 206 can retrieve the error information from the memory system (e.g., Figure 1 The memory system 104 described in FIG. 1 receives data and performs error correction operations on the data. Performing error correction operations may include implementing one or more error correction codes (ECCs) to correct errors in the data and / or implementing CRCs to detect errors in the data.

[0075] In some embodiments, the ECC encoding component 214 and / or the ECC decoding component 216 may implement multiple levels of encoding and / or decoding. For example, the ECC encoding component 214 and / or the ECC decoding component 216 may include one or more external ECC encoders 218 and / or external ECC decoders 222 and one or more internal ECC encoders 220 and / or internal ECC decoders 224. For example, the ECC encoding component 214 may include an external ECC encoder 218 in the form of a BCH encoder and an internal ECC encoder 220 in the form of an LDPC encoder. Similarly, the ECC decoding component 216 may include an external ECC decoder 222 in the form of a BCH decoder and an internal ECC decoder 224 in the form of an LDPC decoder. However, embodiments of the present disclosure are not limited to the above-mentioned specific number and / or type of code encoders / decoders, and may include additional encoders / decoders, and / or encoding / decoding of types or orderings different from those described above.

[0076] According to various embodiments of the present disclosure, the ECC encoding component 214 and / or the ECC decoding component 216 may selectively implement all LDPC ECC schemes (e.g., using the ECC encoding component 214 and the ECC decoding component 216) or a tandem ECC scheme with an internal LDPC code and an external BCH code (e.g., using the external ECC encoder 218, the internal ECC encoder 220, the external ECC decoder 222, and the internal ECC decoder 224). In the tandem ECC scheme, the LDPC decoder may perform, for example, 1 or 2 repetitions. Errors remaining after 1 or 2 repetitions may be corrected by implementing, for example, a component of an external BCH code.

[0077] Rich precision LDPC decoder can be used so that the LDPC decoder can be controlled to the repetition of the desired number. All LDPC ECC schemes can support higher residual bit error rate (RBER) performance in both hard mode and soft mode for specific applications compared with tandem ECC schemes (such as LDPC code and outer / inner code tandem), provided that multiple repetitions can be performed as needed. Depending on the number of LDPC decoder repetitions and available hardware resources, all LDPC ECC schemes can provide variable throughput rates. However, all LDPC ECC schemes can require more decoders to repeat to achieve the same RBER performance and use more complex ECC decoding components 216 compared with tandem ECC schemes. Higher decoder repetitions are converted into higher decoder power consumption.

[0078] For example, a concatenated ECC scheme implementing 1 or 2 repetitions by an LDPC decoder may be implemented with a relatively less complex ECC encoding component 214 and / or ECC decoding component 216 than an all LDPC ECC scheme, may require fewer repetitions, may use less power, and may provide sustained throughput (for some applications). However, the concatenated ECC scheme does not provide as high RBER performance at the RBER region corresponding to the end-of-life RBER after cycling and retention effects on flash memory as compared to an all LDPC ECC scheme.

[0079] According to some embodiments, for applications that are limited to 1 or 2 repetitions of the LDPC decoder, for example due to power and hardware constraints, the concatenated ECC scheme performs better than all LDPC ECC schemes, and for applications that are not limited to 1 or 2 repetitions of the LDPC decoder, all LDPC ECC schemes perform better than the concatenated ECC scheme.

[0080] In some methods, for example, in which a memory system (e.g., Figure 1 104) using, for example, a media controller (e.g., Figure 1 In the method of performing error correction operations by the controller 110 described in the embodiment of the present invention, the above considerations (e.g., the trade-offs between power consumption, RBER performance, time allowed for performing ECC repetitions, available hardware resources, etc.) may be critical due to the limited power, time, hardware resources and / or space available for the memory system. In contrast, by performing error correction operations on a host (e.g., Figure 1 By using the error correction component 206 to perform error correction operations on the host 102 described in the embodiment of the present invention, the resources (e.g., time, power, hardware resources, etc.) available for performing error correction operations can be increased compared to the method in which the error correction operations are performed on the memory system. This can improve the robustness of the error correction operations, which can result in a reduction in RBER and an increase in data integrity.

[0081] Figure 3 3 is a flow chart representing an example method 330 for host-based error correction according to several embodiments of the present disclosure. At block 332, the method 330 may include receiving, by a host computing system, data including a plurality of uncorrected bits from a resistance variable memory system (e.g., a phase change memory system, a resistive memory system, a three-dimensional cross point (3D XP) memory system, etc.) that may be coupled to the host computing system. The host computing system may be similar to that described herein. Figure 1 The host 102 described in , and the 3D XP memory system can be similar to the one described herein. Figure 1. However, embodiments are not limited to resistance variable memory devices, and in some embodiments, the memory device may be a flash-based memory system or an "emerging" memory system, such as a memory device including a self-selected memory cell array.

[0082] At block 333, method 330 may include determining an acceptable error range for the data based at least in part on an application associated with the data. In some embodiments, determining an acceptable error range for the data may include determining a desired quality level for the data. The desired quality level may include a maximum number of uncorrectable bits, a maximum acceptable residual bit error rate, or other suitable data error quality metrics.

[0083] For example, if the data is expected to contain as few errors as possible (e.g., if the data is critical to the operation of the computing system, if the data is being used in an application that requires stringent data quality, etc.), then as described at block 334, the data may be error corrected using error correction logic resident on the host. In some embodiments, the acceptable error range for the data may correspond to whether the host requests the data or a different component of the computing system requests the data. For example, if the host requests the data, then the acceptable error range for the data may be relatively low, and therefore, as described at block 334, the data may be error corrected using error correction logic resident on the host. By dynamically determining whether the data will be error corrected using error correction logic resident on the host, embodiments herein may allow high performance error correction to be performed on data requested by the host (e.g., using error correction logic resident on the host), while data that does not require such stringent error correction may be performed elsewhere (e.g., using a memory controller on a memory device coupled to the host).

[0084] At block 334, method 330 may include performing an initial error correction operation on the data based at least in part on the acceptable error range using error correction logic resident on the host computing system. In some embodiments, the error correction operation may be performed by error correction logic resident on the host computing system (e.g., as described herein). Figure 1 2 and 3. The initial error correction operation may be an error correction operation performed on a plurality of uncorrected bits (e.g., data / bits that were not error corrected prior to being received by the host computing system) as described above. In some embodiments, method 330 may include encoding the received data by the host computing system as part of performing the error correction operation, and decoding the encoded data by the host computing system as part of performing the error correction operation. In some embodiments, the data may be received by, for example, Figure 2A and 2BThe ECC encoding component 214 described in the embodiment of the present invention is used to encode the data, and the data may be encoded by, for example, Figure 2A and 2B The ECC decoding component 216 performs decoding.

[0085] As described above in conjunction with FIG. 2 , encoding the received data may include encoding the data according to a first error correction scheme, and decoding the encoded data may include decoding the encoded data according to the first error correction scheme. However, embodiments are not limited thereto, and in some embodiments, encoding the received data may include encoding the data according to a first error correction scheme, and decoding the encoded data may include decoding the encoded data according to a second error correction scheme. That is, in some embodiments, the error correction scheme used to encode the data may be different from the error correction scheme used to decode the data.

[0086] In some embodiments, method 330 may include using a processing device coupled to a three-dimensional cross-point memory array to perform operations on data in which at least some of the data is ordered, reordered, removed, or discarded prior to performing initial error correction. For example, a memory system (e.g., Figure 1 The memory system 104 described in may include a processing unit that can be configured to perform operations on data (e.g., a plurality of uncorrected bits) in which at least some of the data is ordered, reordered, removed, or discarded to selectively remove or otherwise alter portions of the data before the data is transmitted to error correction logic and / or a host computing system.

[0087] Method 330 may further include performing the error correction operation further including performing the error correction operation by the host computing device without using the memory system to perform the error correction operation. For example, as described above, the host computing system may receive the uncorrected data from the memory system and perform the error correction operation on the uncorrected received data. In some embodiments, performing the error correction operation without using the memory system to perform the error correction operation may include performing the error correction operation on the host computing device without requiring the memory system to perform the error correction operation before the host computing system receives the data (e.g., without requiring, for example, Figure 1 10 (a controller of the controller 110 described in ) performs any error correction on the data.

[0088] Although specific embodiments have been illustrated and described herein, it will be appreciated by those skilled in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It should be understood that the above description is provided in an illustrative manner and is not restrictive. Upon reviewing the above description, the combination of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art. The scope of one or more embodiments of the present disclosure includes other applications in which the above structures and processes are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the attached claims and the full scope of equivalents to which such claims are assigned.

[0089] In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of simplifying the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the disclosed embodiments of the disclosure must use more features than are expressly recited in each claim. On the contrary, as reflected in the appended claims, the subject matter of the invention lies in less than all features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims

1. A method for host-based error correction, comprising: receiving data from a memory device (112) by an error correction component (106) including an error correction code (ECC) encoding component (214) and an ECC decoding component (216); and An initial error correction operation is performed on the data by the error correction component (106). 2 . The method of claim 1 , wherein the error correction component is deployed on a host computing system coupled to the memory device.

3. The method according to claim 1 or claim 2, further comprising: as part of performing the initial error correction operation, encoding the data according to at least one of a first error correction scheme ECS and a second ECS; and As part of performing the initial error correction operation, the data encoded is decoded according to the at least one of the first ECS and the second ECS.

4. The method of claim 1, further comprising performing, by the error correction component, the initial error correction operation without performing error correction operations using the memory device or a media controller associated with the memory device.

5. An apparatus for host-based error correction, comprising: A host computing system (102); and An error correction component (106) disposed on the host computing system (102), wherein the error correction component (106) includes an error correction code (ECC) encoding component (214) and an ECC decoding component (216), and wherein the error correction component (106) is configured to: receive data; and An initial error correction operation is performed on the data.

6. The apparatus of claim 5, wherein the error correction component is further configured to cause the error-corrected data to be transferred to a memory device coupled to the host computing system.

7. Apparatus according to claim 5 or claim 6, wherein: the ECC encoding component being configured to encode the data according to at least one of a first error correction scheme (ECS) and a second ECS as part of performing the initial error correction operation, or As part of performing the initial error correction operation, the data encoded is decoded according to the at least one of the first ECS and the second ECS.

8. The apparatus of claim 5 or claim 6, wherein the initial error correction operation is performed by the error correction component without performing error correction operations using a media controller associated with a memory device coupled to the host computing system.

9. A system for host-based error correction, comprising: a memory device (112); a host computing system (102) coupled to the memory device (112); and An error correction component (106) disposed on the host computing system (102), wherein the error correction component (106) includes an error correction code (ECC) encoding component (214) and an ECC decoding component (216), and wherein the error correction component (106) is configured to: receiving data from the memory device (112); and An initial error correction operation is performed on the data.

10. The system of claim 9 or claim 10, wherein the memory device is coupled to a media controller, and wherein the initial error correction operation is performed by the error correction component without using the media controller to perform error correction operations.

11. The system of claim 9, wherein the ECC encoding component is configured to encode the data according to at least one of a first error correction scheme (ECS) and a second ECS as part of performing the initial error correction operation, and the ECC decoding component is configured to decode the encoded data according to the at least one of the first ECS and the second ECS as part of performing the initial error correction operation.

12. The system of claim 9, wherein the initial error correction operation is performed by the error correction component without using the memory device to perform error correction operations.

13. The system of claim 9, wherein the error correction component is configured to: receiving encoded data from the memory device; and As part of performing the initial error correction operation, the data is decoded according to an error correction scheme.

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