Data processing method and device and electronic equipment

Abstract

The embodiment of the invention provides a data processing method and device and electronic equipment. The method comprises the steps of judging whether a current address memory unit exists or not based on a first preset condition; the address of one data memory unit is stored in the current address memory unit; if the current address memory unit exists, determining a target address memory unit according to the current address memory unit, and determining a target data memory unit according to the address of the data memory unit stored in the current address memory unit; writing the to-be-written data into the target data memory unit as storage data, and storing the address of the target data memory unit in the target address memory unit; and updating the target address memory unit to the address memory unit meeting the first preset condition, and updating the current address memory unit to the address memory unit not meeting the first preset condition. Therefore, even erasing of the address memory unit and the data memory unit is guaranteed, and redundancy of erasing times in the life cycle of the erasable memory is guaranteed.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a method, device and electronic equipment for data processing. Background Art

[0002] At present, some erasable memories have data writing and reading functions. However, the erasable memories currently have a limited number of times they can be erased and written. At the same time, in related technologies, data at a single fixed location is sometimes repeatedly erased and written, which may cause the erasable memory to exceed the upper limit during the life cycle of the erasable memory. And when reading the stored data in the erasable memory, if the currently stored data is invalid, it is very likely that no data can be read. Summary of the invention

[0003] In view of this, the present application provides a data processing method, device and electronic device to ensure the redundancy of the number of hardware erase and write times during the life cycle of the controller, and to realize that when reading the stored data in the erasable memory, if the current stored data fails, the historical stored data can also be read.

[0004] In a first aspect, an embodiment of the present application provides a method for data processing, the method is applied to a rewritable memory, the rewritable memory includes m address memory units and n data memory units; m>1, n>1 and m≥n; the method includes:

[0005] Based on a first preset condition, determining whether there is a current address memory unit; the current address memory unit is an address memory unit among the m address memory units that meets the first preset condition, and the address of a data memory unit is stored in the current address memory unit;

[0006] If there is a current address memory unit, determining the target address memory unit according to the current address memory unit, and determining the target data memory unit according to the address of the data memory unit stored in the current address memory unit;

[0007] Writing the data to be written into the target data memory unit as storage data, and the address of the target data memory unit is stored in the target address memory unit;

[0008] The target address memory unit is updated to an address memory unit that meets the first preset condition, and the current address memory unit is updated to an address memory unit that does not meet the first preset condition; wherein the m address memory units are fixed in sequence as the target address memory units, and the n data memory units are fixed in sequence as the target data memory units.

[0009] In some implementations of the first aspect, if the current address memory unit does not exist, the method further includes:

[0010] Selecting an address memory unit from the m address memory units as a target address memory unit, and selecting a data memory unit from the n data memory units as a target data memory unit;

[0011] Writing the data to be written into the target data memory unit, and storing the address of the target data memory unit in the target address memory unit;

[0012] The target address memory unit is updated to an address memory unit that meets the first preset condition.

[0013] In some implementations of the first aspect, the first preset condition is that a first address and a first check value matching the first address are stored in the address memory unit, and the first address is the address of the data memory unit.

[0014] In some implementations of the first aspect, updating the target address memory unit to an address memory unit that meets the first preset condition includes:

[0015] Calculating a first address in a target address memory unit using a preset algorithm to obtain a first check value matching the first address;

[0016] The first verification value is written into the target address memory unit, so that the target address memory unit is updated to an address memory unit that meets the first preset condition.

[0017] In some implementations of the first aspect, updating the current address memory unit to an address memory unit that does not meet the first preset condition includes:

[0018] At least a portion of the first address stored in the current address memory unit is changed, and / or at least a portion of the first check value matching the first address in the current address memory unit is changed, so that the current address memory unit is updated to an address memory unit that does not meet the first preset condition.

[0019] In some implementations of the first aspect, determining a target address memory unit according to a current address memory unit includes:

[0020] Get the number of the memory unit at the current address;

[0021] The number of the target address memory unit is determined according to the number of the current address memory unit, and the target address memory unit is determined according to the number of the target address memory unit.

[0022] In some implementations of the first aspect, the m address memory units are numbered as consecutive integers and the starting number is 0; and determining the number of the target address memory unit according to the number of the current address memory unit includes:

[0023] Add 1 to the number of the memory unit at the current address and take the remainder of m, the remainder is the number of the memory unit at the target address; or,

[0024] Add (m-1) to the number of the memory unit at the current address and take the remainder of m. The remainder is the number of the memory unit at the target address.

[0025] In some implementations of the first aspect, determining a target data memory unit according to an address of a data memory unit stored in a current address memory unit includes:

[0026] Determine the number of the current data memory unit according to the address of the data memory unit stored in the current address memory unit, the current data memory unit being the data memory unit pointed to by the address of the data memory unit stored in the current address memory unit;

[0027] The number of the target data memory unit is determined according to the number of the current data memory unit, and the target data memory unit is determined according to the number of the target data memory unit.

[0028] In some implementations of the first aspect, the n data memory units are numbered as consecutive integers and the starting number is 0; and determining the number of the target data memory unit according to the number of the current data memory unit includes:

[0029] Add 1 to the number of the current data memory unit and take the remainder modulo n, the remainder is the number of the target data memory unit; or,

[0030] Add (n-1) to the number of the memory unit at the current address and take the modulus of n. The remainder obtained is the number of the target data memory unit.

[0031] In some implementations of the first aspect, the method further includes:

[0032] Get the current address memory unit;

[0033] Determine the current read data memory unit according to the address of the data memory unit stored in the current address memory unit;

[0034] Based on the second preset condition, determining whether the currently read data memory unit is the data memory unit to be read;

[0035] If the data memory unit currently being read is the data memory unit to be read, the stored data in the data memory unit currently being read is read; wherein the data memory unit to be read is a data memory unit among the n data memory units that meets the second preset condition.

[0036] In some implementations of the first aspect, the second preset condition is that the data memory unit currently being read includes stored data and a second check value matching the stored data.

[0037] In some implementations of the first aspect, if the data memory unit currently being read is not the data memory unit to be read, the method further includes:

[0038] According to a preset search rule, a target read data memory unit is obtained from other data memory units of the n data memory units except the currently read data memory unit;

[0039] Based on a second preset condition, determining whether the target read data memory unit is a to-be-read data memory unit;

[0040] If the target read data memory unit is the data memory unit to be read, the stored data in the target read data memory unit is read.

[0041] In some implementations of the first aspect, according to a preset search rule, obtaining a target read data memory unit from other data memory units of n data memory units except a currently read data memory unit includes:

[0042] Based on the serial number of the current read data memory unit, determine the serial number of the target read data memory unit according to the first serial number search rule;

[0043] According to the number of the target read data memory unit, the target read data memory unit is obtained from other data memory units among the n data memory units except the current read data memory unit.

[0044] In some implementations of the first aspect, the order in which the numbers of the target read data memory units are determined according to the first numbering search rule is opposite to the order in which the n data memory units are sequentially used as the target data memory units.

[0045] In some implementations of the first aspect, the n data memory units are numbered as consecutive integers and the starting number is 0; the first number search rule is: add 1 to the number of the currently read data memory unit and then take the remainder of n, and the remainder obtained is the number of the target read memory unit,

[0046] The order of n data memory units as target data memory units is as follows: add (n-1) to the number of the current data memory unit and take the remainder of n, and the remainder is the number of the target memory unit;

[0047] Or, the first number search rule is: add (n-1) to the number of the current read data memory unit and then take the remainder of n, and the remainder is the number of the target read memory unit,

[0048] The order in which the n data memory units are sequentially used as target data memory units is: add 1 to the number of the current data memory unit and then take the modulus of n, and the remainder obtained is the number of the target memory unit.

[0049] In some implementations of the first aspect, m is an integer multiple of n.

[0050] In a second aspect, an embodiment of the present application provides a data processing device, including:

[0051] A judging unit, used to judge whether there is a current address memory unit based on a first preset condition; the current address memory unit is an address memory unit among the m address memory units that meets the first preset condition, and the address of a data memory unit is stored in the current address memory unit;

[0052] A determination unit, used to determine a target address memory unit according to the current address memory unit if there is a current address memory unit, and determine a target data memory unit according to the address of the data memory unit stored in the current address memory unit;

[0053] A storage unit, used for writing the data to be written into a target data memory unit as storage data, the address of the target data memory unit is stored in the target address memory unit, the target address memory unit is updated to an address memory unit that meets a first preset condition, and the current address memory unit is updated to an address memory unit that does not meet the first preset condition; wherein the m address memory units are fixed in sequence as the target address memory units, and the n data memory units are fixed in sequence as the target data memory units.

[0054] In a third aspect, an embodiment of the present application provides an electronic device, comprising a memory for storing computer program instructions and a processor for executing the program instructions, wherein when the computer program instructions are executed by the processor, the electronic device is triggered to execute the method of the first aspect of the embodiment of the present application.

[0055] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, the computer-readable storage medium including a stored program, wherein when the program is running, the device where the computer-readable storage medium is located is controlled to execute the method of the embodiment of the present application.

[0056] By adopting the solution provided in the embodiment of the present application, when the erasable memory is written more than m times, each of the m address memory units can be written, and each of the n data memory units can be written, thereby ensuring the synchronization loss of different areas in the erasable memory, and then ensuring the redundancy of the number of erasures and writes within the life cycle of the erasable memory. And when reading the erasable memory, if the current stored data fails, the historical stored data can also be read. For example, when the vehicle-mounted terminal needs to read the data before its sleep from the erasable memory, if the latest stored data during sleep fails, the next latest stored data with the smallest difference between the write time and the write time of the latest stored data can be read. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0058] Figure 1 A schematic diagram of a data processing method provided in an embodiment of the present application;

[0059] Figure 2 A schematic diagram of a method for determining a target address memory unit provided in an embodiment of the present application;

[0060] Figure 3 A schematic diagram of a method for determining a target data memory unit provided in an embodiment of the present application;

[0061] Figure 4 A schematic diagram of a method for updating a target address memory unit provided in an embodiment of the present application;

[0062] Figure 5 A schematic diagram of a data processing method provided in an embodiment of the present application;

[0063] Figure 6 A schematic diagram of a method for acquiring a target read data memory unit provided in an embodiment of the present application;

[0064] Figure 7 A schematic diagram of a writing process in an exemplary data processing method provided in an embodiment of the present application;

[0065] Figure 8 for Figure 7 A schematic diagram of a reading process in the data processing method shown;

[0066] Fig. 9 A schematic diagram of a data processing device provided in an embodiment of the present application;

[0067] Fig.10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0068] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0069] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0070] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0071] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0072] Before a detailed introduction to the embodiments of the present application, the terms that are applied or may be applied to the embodiments of the present application are first explained.

[0073] In the related art, when the erasable memory is written with data in batches, data from different batches can be stored in different areas of the erasable memory. However, in the related art, data from different batches are usually written to the same area of ​​the erasable memory, causing the area to be repeatedly erased, so that the number of erases in the area quickly reaches the upper limit and other areas are basically not erased. Therefore, in the related art, the storage capacity of the erasable memory is wasted. In addition, since the data is repeatedly erased only in some areas of the erasable memory, when reading the data stored in the erasable memory, even if the latest written data can be read, the second-most recently written data is often lost. For example, when the vehicle-mounted terminal needs to read the data before its sleep from the erasable memory, if the latest stored data is invalid during sleep, and the second-most recently stored data with the smallest difference in write time from the latest stored data has been erased, the vehicle-mounted terminal is basically unable to obtain the data before sleep.

[0074] In response to the above problems, an embodiment of the present application provides a data processing method, so that when the erasable memory is written more than m times, each of the m address memory units can be written, and each of the n data memory units can be written, thereby ensuring the synchronization loss of different areas in the erasable memory, and then ensuring the redundancy of the number of erasures and writes within the life cycle of the erasable memory. And when reading the erasable memory, if the current stored data fails, the historical stored data can also be read. For example, when the vehicle-mounted terminal needs to read the data before its sleep from the erasable memory, if the latest stored data during sleep fails, the next latest stored data with the smallest difference between the write time and the write time of the latest stored data can be read. The following is a detailed description.

[0075] See also Figure 1 , is a schematic diagram of a data processing method provided in an embodiment of the present application. Figure 1 As shown, an embodiment of the present application provides a method for data processing, the method is applied to a rewritable memory, the rewritable memory includes m address memory units and n data memory units; m>1, n>1 and m≥n; the method includes:

[0076] Step S101: Based on a first preset condition, determine whether a current address memory unit exists; if so, execute step S102a; if not, execute step S102b; wherein the current address memory unit is an address memory unit among the m address memory units that meets the first preset condition, and the address of a data memory unit is stored in the current address memory unit.

[0077] That is, since the address of a data memory unit is stored in the current address memory unit, if there is a current address memory unit that meets the first preset condition, a data memory unit can be found according to the address of the data memory unit stored in the current address memory unit, and the data memory unit to be written can be determined based on the found data memory unit.

[0078] In some embodiments, m address memory units may be traversed to determine whether there is a current address memory unit that meets the first preset condition. It is also possible to start searching from any address memory unit to determine whether the address memory unit currently being searched is the current address memory unit. If so, the search is stopped. If not, the search is continued until the current address memory unit is found, and the search is stopped. If the address memory unit that meets the first preset condition is not found after searching the m address memory units, the current address memory unit does not exist, and step S102b is executed at this time.

[0079] It should be noted that the first preset condition needs to be set to a condition that can find only one current address memory unit. For example, in step S101, the first preset condition is that the address memory unit stores a first address and a first check value matching the first address, and the first address is the address of the data memory unit.

[0080] That is, if there is an address memory unit among the m address memory units that stores a first address and stores a first check value that matches the first address, then the address memory unit is the current address memory unit. Since the first address and the first check value can usually be determined by a simpler numerical calculation to determine whether the two match, the current address memory unit can be found more quickly according to the first preset condition, thereby improving the writing efficiency of the erasable memory.

[0081] In some embodiments, the first check value may be a check value calculated using a preset calculation rule. For example, the first check value may be a CRC16 check value.

[0082] In some embodiments, the address memory unit may include multiple storage locations, some of which are used to store a first check value, and the remaining storage locations are used to store a first address, that is, the remaining storage locations are used to store the address of the data memory unit. For example, as shown in Table 1, the erasable memory includes 30 continuous fixed storage locations, and each continuous 3 storage locations form a group. In this way, the 30 continuous fixed storage locations are divided into 10 groups, and the 10 groups serve as 10 address memory units in the erasable memory. The 10 address memory units are numbered from 0 to 9, and the data width of each address pointer is 48. As shown in Table 1, the upper 4 bytes of each address memory unit store the address of a data memory unit, and the lower 2 bytes of each address memory unit store the first check value of the upper 4 bytes storage value of the address memory unit.

[0083] Table 1 Schematic diagram of storage contents of address memory unit

[0084]

[0085] It should be noted that, at the same time, among the m address memory units, only one address memory unit stores a first address that matches the first check value stored in the address memory unit. For example, the address of a data memory unit is stored in each of the m address memory units, that is, a first address is stored in each of the m address memory units, and at the same time, only one of the m address memory units has a correct first check value in the address memory unit, thereby ensuring the uniqueness of the current address memory unit, and further ensuring the uniqueness of the target data memory unit, that is, in the subsequent steps, only one data memory unit is writable at the same time, thereby ensuring that the current address memory unit is not written when writing, and the data memory unit corresponding to the first address stored in the current address memory unit is not written, that is, the same position in the erasable memory is not repeatedly erased, thereby ensuring that the number of erases and writes at each position in the erasable memory is balanced, so as to increase the number of erases and writes of the erasable memory.

[0086] It should also be noted that the above only provides an example of how a first preset condition can be realized, and is not exhaustive. In fact, any condition that can be met to find a unique current address memory unit is an acceptable first preset condition for this application.

[0087] Step S102a: If there is a current address memory unit, determine the target address memory unit according to the current address memory unit, and determine the target data memory unit according to the address of the data memory unit stored in the current address memory unit. The order of m address memory units as target address memory units is fixed, and the order of n data memory units as target data memory units is fixed.

[0088] That is, if the current address memory unit exists, it means that data has been written before, so a data memory unit that can currently write data can be determined as a target data memory unit according to the current address memory unit, so as to write data in the target data memory unit in the next step.

[0089] It should be noted that the numbering order of the m address memory units as target address memory units in sequence may be consistent with the numbering order of the n data memory units as target data memory units in sequence. The numbering order of the m address memory units as target address memory units in sequence may be inconsistent with the numbering order of the n data memory units as target data memory units in sequence. For example, the numbering order of the m address memory units as target address memory units in sequence may be from the address memory unit with the initial number to the address memory unit with the last number, and the numbering order of the n data memory units as target data memory units in sequence may be from the data memory unit with the last number to the data memory unit with the initial number.

[0090] In the embodiment of the present application, the method of obtaining the target address memory unit according to the current address memory unit is not limited. For example, m address memory units can be pre-set as the order of the target address memory unit. In this way, the target address memory unit can be determined according to the current address memory unit and the pre-set order. For another example, the target address memory unit can also be determined according to the number of the current address memory unit, that is, Figure 2 As shown, in step S102a, determining the target address memory unit according to the current address memory unit includes:

[0091] Step S12a1: obtaining the number of the memory unit at the current address;

[0092] Step S12a2: Determine the number of the target address memory unit according to the number of the current address memory unit, and determine the target address memory unit according to the number of the target address memory unit.

[0093] That is, since the number of the address memory unit is unique, the number of the current address memory unit is obtained, and the number of the target address memory unit can be determined based on the number of the current address memory unit, and then the target address memory unit is determined. Since the number of the address memory unit is usually short, the amount of calculation required to determine the current address memory unit or the target memory unit based on the number of the address memory unit is smaller, which can improve the efficiency of determining the target address memory unit.

[0094] In some embodiments, the m address memory units all store numbers of corresponding address memory units.

[0095] In some embodiments, none of the m address memory units stores the address memory unit number, and a number-to-address correspondence table is pre-set, wherein the number-to-address correspondence table reflects the mapping relationship between the address memory unit number and the address memory unit. Obtaining the number of the current address memory unit includes: determining the number of the current address memory unit according to the number-to-address correspondence table and the address of the current address memory unit.

[0096] In some embodiments, the m address memory units are numbered as consecutive integers and start numbering at 0. For example, as shown in Table 1, there are 10 address memory units in the erasable memory, and the 10 address memory units are numbered 0-9.

[0097] In step S12a2, the number of the target address memory unit is determined according to the number of the current address memory unit, including:

[0098] Add 1 to the number of the memory unit at the current address and take the remainder of m, the remainder is the number of the memory unit at the target address; or,

[0099] Add (m-1) to the number of the memory unit at the current address and take the remainder of m. The remainder is the number of the memory unit at the target address.

[0100] That is, the numbers of the m address memory units are sequentially used as the numbers of the target address memory units from the initial number to the end number, or the numbers of the m address memory units are sequentially used as the numbers of the target address memory units from the end number to the initial number. In this way, the m address memory units can be erased evenly and the m address memory units can be synchronously lost, so as to ensure the redundancy of the erase times in the life cycle of the erasable memory.

[0101] When the numbers of m address memory units are sequentially used as the number of the target address memory unit from the initial number to the last number, for example, when there are 10 address memory units in the erasable memory, among which the 10 address memory units are numbered 0-9, if the current address memory unit is numbered 5, then 1 is added to 5 to obtain 6, and 6 is 6 modulo 10, that is, the target address memory unit is numbered 6; if the current address memory unit is numbered 9, then 1 is added to 9 to obtain 10, and 10 is 0 modulo 10, that is, the target address memory unit is numbered 0.

[0102] Or, when the numbers of the m address memory units are sequentially used as the number of the target address memory unit from the last number to the initial number, for example, when there are 10 address memory units in the erasable memory, among which the 10 address memory units are numbered 0-9, if the current address memory unit is numbered 5, then 5 plus (10-1) is 14, and 14 is 4 when the remainder is 10, that is, the target address memory unit is numbered 4; if the current address memory unit is numbered 0, then 0 plus (10-1) is 9, and 9 is 9 when the remainder is 10, that is, the target address memory unit is numbered 9.

[0103] It can be seen that in the embodiments of the present application, the calculation method of adding 1 or (m-1) to the current address memory unit number and taking the remainder of m is mainly to make the target address memory calculated to be the address memory unit with the initial number when the current address memory unit is the address memory unit with the last number, or to make the target address memory calculated to be the address memory unit with the last number when the current address memory unit is the address memory unit with the initial number. In this way, the m address memory units are written cyclically according to the number, and the synchronous loss of the m address memory units is achieved.

[0104] In the embodiments of the present application, the method of determining the target data memory unit according to the address of the data memory unit stored in the current address memory unit is not limited. For example, n data memory units can be pre-set as the order of the target data memory units. In this way, the target data memory unit can be determined according to the current data memory unit and the pre-set order. For another example, the target data memory unit can be determined according to the number of the current data memory unit, that is, Figure 3 As shown, in step S102a, the target data memory unit is determined according to the address of the data memory unit stored in the current address memory unit, including:

[0105] Step S12a1′: determining the serial number of the current data memory unit according to the address of the data memory unit stored in the current address memory unit, the current data memory unit being the data memory unit pointed to by the address of the data memory unit stored in the current address memory unit;

[0106] Step S12a2': determine the number of the target data memory unit according to the number of the current data memory unit, and determine the target data memory unit according to the number of the target data memory unit.

[0107] That is, since the number of the data memory unit is unique, the number of the current data memory unit is first determined according to the current address memory unit, and then the target address memory unit can be determined according to the number of the current data memory unit. Since the numbering calculation amount is small, this can improve the efficiency of determining the target data memory unit.

[0108] In some embodiments, the current address memory unit stores the address of the current data memory unit and the number of the current data memory unit.

[0109] In some embodiments, the current address memory unit stores the address of the current data memory unit but does not store the number of the current data memory unit, and a number-data correspondence table is pre-set, wherein the number-data correspondence table reflects the mapping relationship between the number of the data memory unit and the data memory unit. Determining the number of the current data memory unit according to the address of the data memory unit stored in the current address memory unit includes: determining the number of the current data memory unit according to the number-data correspondence table and the address of the data memory unit stored in the current address memory unit.

[0110] In some embodiments, the n data memory units are numbered as consecutive integers and start numbering at 0; for example, as shown in Table 2, there are 5 data memory units in the erasable memory, where the 5 data memory units are numbered 0-4.

[0111] Table 2 Schematic diagram of data memory unit storage content

[0112]

[0113] In some embodiments, in step S12a2′, determining the number of the target data memory unit according to the number of the current data memory unit includes:

[0114] Add 1 to the number of the current data memory unit and take the remainder modulo n, the remainder is the number of the target data memory unit; or,

[0115] Add (n-1) to the number of the memory unit at the current address and take the modulus of n. The remainder obtained is the number of the target data memory unit.

[0116] That is, the numbers of the n data memory units are sequentially used as the numbers of the target data memory units from the initial number to the last number, or the numbers of the n data memory units are sequentially used as the numbers of the target data memory units from the last number to the initial number. In this way, the n data memory units can be erased and written uniformly, and the n data memory units are synchronously lost, so as to ensure the redundancy of the erase and write times in the life cycle of the erasable memory.

[0117] When n data memory units are numbered in sequence from the initial number to the last number as the target data memory unit number, for example, when there are 5 data memory units in the erasable memory, among which the 5 data memory units are numbered 0-4, if the current data memory unit is numbered 3, then 1 is added to 3 to get 4, and 4 modulo 5 is 4, that is, the target data memory unit is numbered 4; if the current data memory unit is numbered 4, then 1 is added to 4 to get 5, and 5 modulo 5 is 0, that is, the target data memory unit is numbered 0.

[0118] Or, when n data memory units are numbered in sequence from the last number to the initial number as the target data memory unit number, for example, when there are 5 data memory units in the erasable memory, among which the 5 data memory units are numbered 0-4, if the current data memory unit is numbered 4, then 4 plus (5-1) is 8, and 8 modulo 5 is 3, that is, the target data memory unit is numbered 3; if the current data memory unit is numbered 0, then 0 plus (5-1) is 4, and 4 modulo 5 is 4, that is, the target data memory unit is numbered 4.

[0119] It can be seen that in the embodiments of the present application, the calculation method of setting the number of the current data memory unit plus 1 or (n-1) and taking the remainder of n is mainly to calculate the target data memory unit as the data memory unit with the initial number when the current data memory unit is the data memory unit with the last number, or to calculate the target data memory unit as the data memory unit with the initial number when the current data memory unit is the data memory unit with the initial number. In this way, the data memory units are written cyclically according to the numbers, and the synchronous loss of n data memory units is realized.

[0120] S103: writing the data to be written into the target data memory unit as storage data, storing the address of the target data memory unit in the target address memory unit, updating the target address memory unit to an address memory unit that meets the first preset condition, and updating the current address memory unit to an address memory unit that does not meet the first preset condition.

[0121] That is, the data to be written is written into the target data memory unit. In this way, since each data memory unit is sequentially used as the target data memory unit to achieve synchronization loss of each data memory unit, the address of the target data memory unit is stored in the target address memory unit, so that the data memory unit can be found according to the address memory unit when writing next time, that is, the target address memory unit and the target data memory unit of the data writing this time are used as the current address memory unit and the current data memory unit when writing next time. In this way, the target address memory unit is updated to an address memory unit that meets the first preset condition, so that the corresponding current address memory unit can be found according to the first preset condition when writing next time, and the current address memory unit is updated to an address memory unit that does not meet the first preset condition, so that the address memory unit that meets the first preset condition is unique when writing next time.

[0122] It should be noted that the total memory occupied by m address memory units is usually much smaller than the total memory occupied by n data memory units. In this way, even if m address memory units are set in the erasable memory, only a small amount of memory in the erasable memory is occupied, but the effect of erasing and writing balance is achieved. For example, in some embodiments, the data processing method provided in the embodiments of the present application is applied to the vehicle controller of the vehicle (such as the VCU vehicle controller). The vehicle controller needs to rely on the EEPROM to dynamically store relevant vehicle operation data so that the vehicle can obtain the data before hibernation after resuming work from hibernation, thereby maintaining the normal operation of the vehicle. At this time, the data stored in the n data memory units can be data with larger memory such as cumulative mileage, cumulative loss, average loss, historical route information, historical music information, etc., while the first address and the first check value stored in the m memory units occupy a smaller memory.

[0123] In some embodiments, the address of the target data memory unit may be stored in a fixed position of the target address memory unit, for example, as shown in Table 1, the address of the target data memory unit is written into the upper 4 bytes of the address memory unit.

[0124] It should be noted that the address of the target data memory unit is stored in the target address memory unit, and there may be no need to perform a write operation. For example, when m=10, n=5, and the address memory units are numbered 0-9 and the data memory units are numbered 0-4, the address memory units numbered 0 and 5 store the address of the data memory unit numbered 0, the address memory units numbered 1 and 6 store the address of the data memory unit numbered 1, the address memory units numbered 2 and 7 store the address of the data memory unit numbered 2, the address memory units numbered 3 and 8 store the address of the data memory unit numbered 3, and the address memory units numbered 4 and 9 store the address of the data memory unit numbered 4. In this way, if each write only changes the first check value stored in the current address memory unit, and does not change the address of the data memory unit stored in the current address memory unit, the address of the target data memory unit has been saved in the target address memory unit, so there is no need to perform an operation of writing the address of the target data memory unit.

[0125] It should also be noted that the operations in step S103 do not distinguish between sequential steps and can be performed simultaneously.

[0126] Since a setting method of the first preset condition is mentioned above, when the first preset condition mentioned above is used in the embodiment of the present application to determine whether there is a current address memory unit, the target address memory unit is updated to an address memory unit that meets the first preset condition in the following manner: Figure 4 As shown, in step S103, updating the target address memory unit to an address memory unit that meets the first preset condition includes:

[0127] Step S131: using a preset algorithm to calculate a first address in a target address memory unit to obtain a first check value matching the first address;

[0128] Step S132: writing the first verification value into the target address memory unit, so that the target address memory unit is updated to an address memory unit that meets the first preset condition.

[0129] That is, if the address of the target data memory unit is not saved in the target address memory unit, the address of the target data memory unit and the first verification value are written into the target address memory unit; if the address of the target data memory unit is saved in the target address memory unit, the first verification value corresponding to the address of the target data memory unit is written into the target address memory unit, so that the target address memory unit meets the first preset condition, so that the current address memory unit can be found according to the first preset condition when writing next time.

[0130] In some embodiments, as shown in Table 1, the target address memory unit includes 6 bytes, wherein the upper 4 bytes store the address of the target data memory unit, that is, the upper 4 bytes store the first address, and the lower 2 bytes store the first check value matching the first address.

[0131] Since a setting method of the first preset condition is mentioned above, therefore, when the first preset condition mentioned above is used in the embodiment of the present application to determine whether there is a current address memory unit, the current address memory unit is updated to an address memory unit that does not meet the first preset condition in the following manner: that is, in step S103, the current address memory unit is updated to an address memory unit that does not meet the first preset condition, including:

[0132] At least a portion of the first address stored in the current address memory unit is changed, and / or at least a portion of the first check value matching the first address in the current address memory unit is changed, so that the current address memory unit is updated to an address memory unit that does not meet the first preset condition.

[0133] That is, changing at least part of the first address stored in the current address memory unit, and / or changing at least part of the first check value matching the first address in the current address memory unit can make the current address memory unit fail to meet the first preset condition. Therefore, one of the above update methods or all of the above change methods can be selected according to needs to change the current address memory unit.

[0134] It should be noted that in the embodiment of the present application, the first address can be changed to any data that is not the first address, and the first check value that matches the first address can be changed to any data that does not match the first address. For example, part or all of the first address and / or the first check value can be changed to 0xFFFFFFFFFFFF.

[0135] In some embodiments, as shown in Table 1, the target address memory unit includes a total of 6 bytes, wherein the upper 4 bytes store the address of the target data memory unit, and the address of the target memory unit is stored in two parts in the upper 4 bytes, and the lower 2 bytes store a first check value matching the first address. In this way, when the current address memory unit is changed to an address memory unit that does not meet the first preset condition, all the target memory unit addresses in the upper 4 bytes can be changed, and the addresses of some target memory units in the upper 4 bytes can also be changed, and part or all of the first check value can also be changed.

[0136] In some embodiments, m is an integer multiple of n. As can be seen from the above, in a write operation, it is necessary to change the data stored in the current address memory unit, and write the address and the first check value of the data memory unit to the target data memory unit, that is, when writing the data to the target data memory unit, the target data memory unit is erased and written once; but the corresponding address memory unit is erased and written twice, one erase and write is to update the target address memory unit to an erase and write that meets the first preset condition, and one erase and write is to update the current address memory unit to an erase and write that does not meet the first preset condition. In this way, the total number of erase and write times for the address memory unit is greater than the total number of erase and write times for the data memory unit, so that when the m address memory units are cyclically written once, the corresponding n data memory units are cyclically written more than once, so m being an integer multiple of n can narrow the gap between the number of erase and write times of an address memory unit and a data memory unit. And because m is an integer multiple of n, in some embodiments, when the m address memory units are written in a cycle multiple times, the address of the data memory unit stored in each address memory unit may remain unchanged. Therefore, when the current address memory unit is updated to an address memory unit that does not meet the first preset condition, the first address in the current address memory unit may not be erased, that is, only the first check value in the current address memory unit needs to be erased, so as to reduce the erasure operation and further improve the writing efficiency.

[0137] In some embodiments, m is twice n. m being twice n ensures that the address memory unit and the data memory unit reach the upper limit of erasable times at the same time as much as possible, that is, both the address memory unit and the data unit are fully utilized, avoiding the waste of storage space in the erasable memory.

[0138] In step S102a, the operation when there is an address memory unit has been mentioned. However, in the actual data processing process, it also includes the situation when there is no address memory unit, for example, Figure 1As shown, step S102b: if the current address memory unit does not exist, then select an address memory unit from the m address memory units as the target address memory unit, and select a data memory unit from the n data memory units as the target data memory unit;

[0139] Writing the data to be written into the target data memory unit, and storing the address of the target data memory unit in the target address memory unit;

[0140] The target address memory unit is updated to an address memory unit that meets the first preset condition.

[0141] That is, if the current address memory unit does not exist, it means that the m address memory units have not been written before. Therefore, there is no current address memory unit that meets the first preset condition at this time. At this time, you can write in any address memory unit and any data memory unit, store the address of the target data memory unit in the target address memory unit, and update the target address memory unit to an address memory unit that meets the first preset condition, which can facilitate finding the current address memory unit when writing data next time.

[0142] In some embodiments, selecting an address memory unit from m address memory units as a target address memory unit and selecting a data memory unit from n data memory units as a target data memory unit includes: selecting an address memory unit with a preset address number as the target address memory unit and selecting a data memory unit with a preset data number as the target data memory unit.

[0143] In some embodiments, selecting an address memory unit from m address memory units as a target address memory unit and selecting a data memory unit from n data memory units as a target data memory unit includes: randomly selecting any address memory unit from m address memory units as a target address memory unit and randomly selecting any data memory unit from n data memory units as a target data memory unit.

[0144] It should be noted that if step S102b is executed, there is no need to execute the subsequent step S103.

[0145] See also Figure 5 , is a schematic diagram of a data processing method provided in an embodiment of the present application. Figure 6 As shown, an embodiment of the present application provides a method for data processing, the method is applied to a rewritable memory, the rewritable memory includes m address memory units and n data memory units; m>1, n>1 and m≥n; the method includes:

[0146] Step S201: Determine whether the erasable memory is currently being written or read; if reading, execute step S202a; if writing, execute step S202b.

[0147] Step S202a: Obtain the current address memory unit.

[0148] That is, in the erasable and writable memory, the read operation can be realized only if the data has been written once. According to the above description of the data writing process in the erasable and writable memory, it is obvious that as long as the data has been written, the current address memory unit exists.

[0149] The current address memory unit may be obtained based on the first preset condition, and details may be referred to step S101, which will not be described in detail here.

[0150] Step S203: determining the current read data memory unit according to the address of the data memory unit stored in the current address memory unit.

[0151] That is, since it is mentioned above that the address of a data memory unit is stored in the current address memory unit, the address is the currently read data memory unit.

[0152] The current read data memory unit is determined according to the address of the data memory unit stored in the current address memory unit. For details, please refer to step S102, which will not be repeated here.

[0153] Step S204: Based on the second preset condition, determine whether the data memory unit currently being read is the data memory unit to be read; wherein the data memory unit to be read is the data memory unit that meets the second preset condition among the n data memory units. If the data memory unit currently being read is the data memory unit to be read, execute step S205a; if the data memory unit currently being read is not the data memory unit to be read, execute step S205b.

[0154] That is, as long as the current address memory unit exists, a current read data memory unit can be found according to the address of the data memory unit stored in the current address memory unit. However, whether there is data stored in the current data memory unit, or whether the data stored in the current data memory unit is readable, needs to be verified based on the second preset condition to avoid reading incomplete stored data.

[0155] It should be noted that the second preset condition needs to be set to verify whether the storage data is saved in the current data memory unit and whether the storage data is complete. For example, in step S204, the second preset condition is that the current read data memory unit includes storage data and a second verification value matching the storage data.

[0156] That is, if the currently read data memory unit includes the stored data and the second verification value matching the stored data, it means that the stored data in the currently read data memory unit is complete, so it can be determined that the current data memory unit is the data memory unit to be read.

[0157] It should be noted that the second preset condition is only judged for the currently read data memory unit, and among the n data memory units, other data memory units except the current data memory unit may also have stored data and a second check value matching the stored data. That is, there may be multiple data memory units at the same time.

[0158] It should also be noted that the above only provides an example of how a second preset condition can be implemented, and is not exhaustive. In fact, any preset condition that can satisfy the determination of whether there is stored data in the current data memory unit and whether the stored data is complete is a second preset condition that can be accepted by the embodiments of the present application.

[0159] Step S205a: If the current data memory unit is the data memory unit to be read, then the stored data in the current data memory unit is read.

[0160] That is, if the currently read data memory unit is the data memory unit to be read, it means that the currently read data memory unit includes storage data, and the storage data meets the second preset condition. At this time, the storage data in the currently read data memory unit is complete and lossless storage data. At this time, reading the storage data can restore the erasable memory to the state before sleep.

[0161] It should be noted that if step S205a is executed, there is no need to execute subsequent steps.

[0162] Step S205b: If the currently read data memory unit is not the to-be-read data memory unit, then according to a preset search rule, a target read data memory unit is obtained from the n data memory units except the currently read data memory unit.

[0163] That is, if the currently read data memory unit is not the data memory unit to be read, it means that there may be no data or the data is incomplete in the currently read data memory unit, then the currently read data memory unit is unreadable. At this time, the target read data memory unit can be obtained to subsequently determine whether the target read data memory unit is readable.

[0164] It should be noted that the preset search rule is a rule for finding the target read memory unit according to the demand, and different demands may correspond to different preset search rules.

[0165] In some embodiments, the target read data memory unit can be determined in combination with the serial number, for example, Figure 6 As shown, in step S205b, according to a preset search rule, a target read data memory unit is obtained from other data memory units of n data memory units except the currently read data memory unit, including:

[0166] Step S25b1: based on the serial number of the current read data memory unit, determine the serial number of the target read data memory unit according to the first serial number search rule;

[0167] Step S25b2: According to the serial number of the target read data memory unit, obtain the target read data memory unit from the n data memory units except the currently read data memory unit.

[0168] That is, by determining the number of the target read data memory unit according to the first number search rule, the number of the target read data unit can be found, and a unique target read data memory unit can be found according to the number of the target read data unit. In this way, searching for the target read data memory unit according to the number can reduce the amount of calculation and improve the efficiency of obtaining the target read data memory unit.

[0169] In some embodiments, determining the number of the target read data memory unit according to the first number search rule includes: determining the number of the target read data memory unit from a preset first number table according to the first number search rule.

[0170] In some embodiments, in step S25b1, the order in which the numbers of the target read data memory units are determined according to the first numbering search rule is opposite to the order in which the n data memory units are sequentially used as the target data memory units.

[0171] That is, as mentioned above, when writing data, the order in which the n data memory units are sequentially used as target data memory units is fixed. Therefore, by determining the target read data memory unit in the order opposite to the order in which the n data memory units are sequentially used as target data memory units, the read data memory unit closest to the write time of the current read data memory unit can be read. That is, if the current stored data is lost, the latest historical storage data can be read from the stored historical storage data that is still valid.

[0172] In some embodiments, the n data memory units are numbered as consecutive integers and the starting number is 0. For example, as shown in Table 2, there are 5 data memory units in the erasable memory, wherein the 5 data memory units are numbered 0 to 4. Part of the position of each data memory unit stores data, and part of the position stores a second check value.

[0173] As mentioned above, the order in which n data memory units are sequentially used as target data memory units can be divided into two cases, that is, n data memory units are sequentially used as target data memory units from the data memory unit with the initial number to the data memory unit with the last number, or n data memory units are sequentially used as target data memory units from the data memory unit with the last number to the data memory unit with the initial number. Then the corresponding first number search rule is also divided into two cases, that is, the first number search rule is: add 1 to the number of the currently read data memory unit and then take the remainder of n, and the remainder obtained is the number of the target read memory unit,

[0174] The order of n data memory units as target data memory units is as follows: add (n-1) to the number of the current data memory unit and take the remainder of n, and the remainder is the number of the target memory unit;

[0175] Or, the first number search rule is: add (n-1) to the number of the current read data memory unit and then take the remainder of n, and the remainder is the number of the target read memory unit,

[0176] The order in which the n data memory units are sequentially used as target data memory units is: add 1 to the number of the current data memory unit and then take the modulus of n, and the remainder obtained is the number of the target memory unit.

[0177] It should be noted that, usually, the first number search rule is determined before the erasable memory is initially written.

[0178] Step S206: Based on the second preset condition, determine whether the target read data memory unit is the data memory unit to be read. If the target read data memory unit is the data memory unit to be read, execute step S207; if the target read data memory unit is not the data memory unit to be read, update the target read data memory unit to the current data memory unit, and execute step S205b until the number of executions of step S206b is greater than n-1 times.

[0179] That is, as long as the target address memory unit exists, a target read data memory unit can be found according to the address of the data memory unit stored in the target address memory unit. However, whether there is data stored in the target data memory unit, or whether the data stored in the target data memory unit is readable, needs to be verified based on the second preset condition to avoid reading incomplete stored data.

[0180] For the rest of the details, please refer to step S204, which will not be described in detail here.

[0181] Step S207: If the target read data memory unit is a to-be-read data memory unit, then read the stored data in the target read data memory unit.

[0182] That is, if the target read data memory unit is the data memory unit to be read, it means that the target read data memory unit includes storage data, and the storage data meets the second preset condition. At this time, the storage data in the target read data memory unit is complete and lossless storage data. At this time, reading the storage data can restore the erasable memory to the state before sleep.

[0183] For the rest of the details, please refer to step S205a, which will not be described again here.

[0184] Step S202b: Execute the writing step.

[0185] If the writing step is performed, S203 further includes: updating the target data memory unit to a data memory unit that meets the second preset condition.

[0186] That is, the target data memory unit is updated to a data memory unit that meets the second preset condition, so that when reading the erasable and writable memory, it can be determined according to the second preset condition whether the currently read data memory unit is the data memory unit to be read.

[0187] It should be noted that if step S202a is executed, there is no need to execute subsequent steps.

[0188] For the rest of the details, please refer to steps S101-S103, which will not be described again here.

[0189] See also Figure 7 , is a schematic diagram of a writing process in an exemplary data processing method provided in an embodiment of the present application. Figure 7 As shown, an embodiment of the present application provides a method for data processing, which is applied to an erasable and writable memory, the erasable and writable memory includes 10 address memory units and 5 data memory units, and the structure of the address memory unit is shown in Table 1, the structure of the data memory unit is shown in Table 2, and the data processing method includes a writing process, and the writing process includes:

[0190] Get the number of the current address memory unit and the number of the current data memory unit: traverse the 10 address memory units, find the first group of first check values ​​calculated based on the upper 4 bytes and the value stored in the lower 2 bytes, and get the number of the current address memory unit; the value corresponding to the upper 4 bytes is the address of the current data memory unit, and thus get the number of the corresponding current data memory unit. If none of the 10 address memory units meet the above conditions, it is considered to be the initial state and no data has been stored.

[0191] Storage of the first check value: Erase all the corresponding values ​​in the current address memory unit obtained (i.e. write 0xFFFFFFFFFFFF), and add 1 to the number of the current address memory unit modulo 10 to get the number of the target address memory unit written this time. Add 1 to the number of the current data memory unit obtained in step 2 modulo 5 to get the number of the target data memory unit where the actual data is written this time, and get the address of the target data memory unit accordingly. Store the address of the target data memory unit and the first check value calculated based on it into the corresponding position in the target address memory unit. If no data has been written, both the target address memory unit and the target data memory unit are written starting from number 0.

[0192] Storage of the data to be written and the second verification value: Calculate the second verification value from the data to be written and store it in the target data unit, and store the data to be written in the target data unit.

[0193] like Figure 8 As shown, an exemplary data processing method provided in an embodiment of the present application also includes a reading process, and the reading process includes:

[0194] Get the address of the current target data memory unit: traverse the 10 address memory units, find the first group where the first check value calculated based on the upper 4 bytes is consistent with the value stored in the lower 2 bytes, get the number of the current address memory unit, and get the number of the current data memory unit based on the number of the current address memory unit. If none of the 10 address memory units meet the above conditions, it is considered to be the initial state and no data has been written.

[0195] Get stored data: Determine whether the data stored in the current data memory unit and the second check value meet the second check result. If they meet, the data segment is considered valid and the stored data is read successfully. If they do not meet, add 4 to the number of the current data memory unit and then take the modulus of 5 to get the address of the previous data memory unit (target data memory unit), and read the value of the previous data memory unit (target data memory unit); Determine whether the data stored in the previous data memory unit (target data memory unit) and the second check value meet the second check result. If they meet, read the stored data. If they do not meet, continue forward, and so on, for a total of 5 segments of data. If all 5 segments of data are inconsistent, it is determined that the current and historical data are all invalid.

[0196] See also Fig. 9 , is a schematic diagram of a data processing device provided in an embodiment of the present application. Fig. 9 As shown, the device comprises:

[0197] The judging unit 901 is used to judge whether there is a current address memory unit based on a first preset condition; the current address memory unit is an address memory unit among the m address memory units that meets the first preset condition, and the address of a data memory unit is stored in the current address memory unit;

[0198] A determining unit 902 is used to determine a target address memory unit according to the current address memory unit if there is a current address memory unit, and determine a target data memory unit according to the address of the data memory unit stored in the current address memory unit;

[0199] Storage unit 903 is used to write the data to be written into the target data memory unit as storage data, the address of the target data memory unit is stored in the target address memory unit, the target address memory unit is updated to an address memory unit that meets the first preset condition, and the current address memory unit is updated to an address memory unit that does not meet the first preset condition; wherein, the m address memory units are fixed in sequence as the target address memory units, and the n data memory units are fixed in sequence as the target data memory units.

[0200] The determination unit 902 is also used to select an address memory unit from the m address memory units as the target address memory unit, and select a data memory unit from the n data memory units as the target data memory unit if the current address memory unit does not exist; write the data to be written into the target data memory unit, and store the address of the target data memory unit in the target address memory unit; and update the target address memory unit to an address memory unit that meets the first preset condition.

[0201] The determination unit 902 is also used to calculate the first address in the target memory unit using a preset algorithm to obtain a first check value matching the first address; write the first check value into the target address memory unit to update the target address memory unit to an address memory unit that meets the first preset condition.

[0202] The determination unit 902 is also used to change at least part of the first address stored in the current address memory unit, and / or to change at least part of the first check value matching the first address in the current address memory unit, so that the current address memory unit is updated to an address memory unit that does not meet the first preset condition.

[0203] The determination unit 902 is further configured to obtain the number of the current address memory unit; determine the number of the target address memory unit according to the number of the current address memory unit, and determine the target address memory unit according to the number of the target address memory unit.

[0204] Determination unit 902 is also used to add 1 to the number of the current address memory unit and then take the modulus of m, and the remainder obtained is the number of the target address memory unit; or, add (m-1) to the number of the current address memory unit and then take the modulus of m, and the remainder obtained is the number of the target address memory unit.

[0205] Determination unit 902 is also used to determine the number of the current data memory unit according to the address of the data memory unit stored in the current address memory unit, the current data memory unit being the data memory unit pointed to by the address of the data memory unit stored in the current address memory unit; determine the number of the target data memory unit according to the number of the current data memory unit, and determine the target data memory unit according to the number of the target data memory unit.

[0206] Determination unit 902 is also used to add 1 to the number of the current data memory unit and then take the modulus of n, and the remainder obtained is the number of the target data memory unit; or, add (n-1) to the number of the current address memory unit and then take the modulus of n, and the remainder obtained is the number of the target data memory unit.

[0207] In some embodiments, the data processing device provided by the present application also includes: a reading unit, the reading unit is used to obtain a current address memory unit; determine the current read data memory unit according to the address of the data memory unit stored in the current address memory unit; based on a second preset condition, determine whether the current read data memory unit is a data memory unit to be read; if the current read data memory unit is a data memory unit to be read, read the stored data in the current read data memory unit; wherein the data memory unit to be read is a data memory unit among the n data memory units that meets the second preset condition.

[0208] The reading unit is also used for: if the currently read data memory unit is not the data memory unit to be read, then according to a preset search rule, obtaining a target read data memory unit from n data memory units other than the currently read data memory unit; based on a second preset condition, determining whether the target read data memory unit is the data memory unit to be read; if the target read data memory unit is the data memory unit to be read, reading the stored data in the target read data memory unit.

[0209] The reading unit is also used to: determine the number of the target read data memory unit according to the first number search rule based on the number of the current read data memory unit; and obtain the target read data memory unit from other data memory units among n data memory units except the current read data memory unit according to the number of the target read data memory unit.

[0210] The reading unit is also used for: adding 1 to the number of the data memory unit currently being read and taking the modulus of n, the remainder obtained is the number of the target memory unit being read, and the order in which the n data memory units are sequentially used as the target data memory units is: adding (n-1) to the number of the current data memory unit and taking the modulus of n, the remainder obtained is the number of the target memory unit; or, the first numbering search rule is: adding (n-1) to the number of the data memory unit currently being read and taking the modulus of n, the remainder obtained is the number of the target memory unit being read, and the order in which the n data memory units are sequentially used as the target data memory units is: adding 1 to the number of the current data memory unit and taking the modulus of n, the remainder obtained is the number of the target memory unit.

[0211] Corresponding to the above embodiments, the present application also provides an electronic device. Fig.10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present invention, the electronic device 110 may include: a processor 111, a memory 112 and a communication unit 113. These components communicate through one or more buses. Those skilled in the art can understand that the structure of the electronic device shown in the figure does not constitute a limitation on the embodiment of the present invention, it can be a bus structure or a star structure, and can also include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0212] The communication unit 113 is used to establish a communication channel so that the electronic device can communicate with other devices, receive user data sent by other devices or send user data to other devices.

[0213] The processor 111 is the control center of the electronic device. It uses various interfaces and lines to connect various parts of the entire electronic device. It runs or executes software programs and / or modules stored in the memory 112, and calls data stored in the memory to perform various functions of the electronic device and / or process data. The processor can be composed of an integrated circuit (IC), for example, it can be composed of a single packaged IC, or it can be composed of multiple packaged ICs with the same or different functions. For example, the processor 111 can include only a central processing unit (CPU). In an embodiment of the present invention, the CPU can be a single computing core or multiple computing cores.

[0214] The memory 112 is used to store the execution instructions of the processor 111. The memory 112 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0215] When the execution instructions in the memory 112 are executed by the processor 111, the electronic device 110 can execute Fig. 9 Some or all of the steps in the illustrated embodiments.

[0216] In a specific implementation, the present invention further provides a computer storage medium, wherein the computer storage medium may store a program, and when the program is executed, the program may include some or all of the steps in each embodiment of the data processing method provided by the present invention. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0217] Those skilled in the art can clearly understand that the technology in the embodiments of the present invention can be implemented by means of software plus a necessary general hardware platform. Based on this understanding, the technical solution in the embodiments of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which can be stored in a storage medium such as ROM / RAM, a disk, an optical disk, etc., and includes a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention or some parts of the embodiments.

[0218] In this specification, the same or similar parts between the various embodiments can be referred to each other. In particular, for the device embodiment and the terminal embodiment, since they are basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description in the method embodiment.

Claims

1. A method for data processing, characterized in that: The method is applied to an erasable and writable memory, wherein the erasable and writable memory comprises m address memory units and n data memory units; m>1, n>1 and m≥n; the method comprises: Based on a first preset condition, determining whether there is a current address memory unit; the current address memory unit is an address memory unit among the m address memory units that meets the first preset condition, and the address of a data memory unit is stored in the current address memory unit; If the current address memory unit exists, determining the target address memory unit according to the current address memory unit, and determining the target data memory unit according to the address of the data memory unit stored in the current address memory unit; Writing the data to be written into the target data memory unit as storage data, the address of the target data memory unit being stored in the target address memory unit; The target address memory unit is updated to the address memory unit that meets the first preset condition, and the current address memory unit is updated to the address memory unit that does not meet the first preset condition; wherein the m address memory units are fixed in sequence as the target address memory units, and the n data memory units are fixed in sequence as the target data memory units.

2. The method according to claim 1, characterized in that If the current address memory unit does not exist, the method further includes: Selecting one of the m address memory units as a target address memory unit, and selecting one of the n data memory units as a target data memory unit; Writing the data to be written into the target data memory unit, and storing the address of the target data memory unit in the target address memory unit; The target address memory unit is updated to the address memory unit that meets the first preset condition.

3. The method according to claim 1, characterized in that The first preset condition is that a first address and a first check value matching the first address are stored in the address memory unit, and the first address is the address of the data memory unit.

4. The method according to claim 3, characterized in that The updating of the target address memory unit to the address memory unit meeting the first preset condition comprises: Calculating a first address in the target address memory unit using a preset algorithm to obtain a first check value matching the first address; The first verification value is written into the target address memory unit, so that the target address memory unit is updated to the address memory unit that meets the first preset condition.

5. The method according to claim 3, characterized in that: The updating of the current address memory unit to the address memory unit that does not meet the first preset condition includes: At least a portion of the first address stored in the current address memory unit is changed, and / or at least a portion of the first check value matching the first address in the current address memory unit is changed, so that the current address memory unit is updated to the address memory unit that does not meet the first preset condition.

6. The method according to claim 1, characterized in that The step of determining the target address memory unit according to the current address memory unit comprises: Obtain the number of the memory unit at the current address; The number of the target address memory unit is determined according to the number of the current address memory unit, and the target address memory unit is determined according to the number of the target address memory unit.

7. The method according to claim 6, characterized in that The m address memory units are numbered as consecutive integers and the starting number is 0; and the step of determining the number of the target address memory unit according to the number of the current address memory unit includes: Add 1 to the number of the memory unit at the current address and take the remainder of m, the remainder obtained is the number of the memory unit at the target address; or, The number of the memory unit at the current address is added to (m-1), and then the remainder is calculated as m, and the remainder obtained is the number of the memory unit at the target address.

8. The method according to claim 1, characterized in that The step of determining a target data memory unit according to the address of the data memory unit stored in the current address memory unit comprises: Determine the serial number of the current data memory unit according to the address of the data memory unit stored in the current address memory unit, the current data memory unit being the data memory unit pointed to by the address of the data memory unit stored in the current address memory unit; The number of the target data memory unit is determined according to the number of the current data memory unit, and the target data memory unit is determined according to the number of the target data memory unit.

9. The method according to claim 8, characterized in that The n data memory units are numbered as consecutive integers and the starting number is 0; and the step of determining the number of the target data memory unit according to the number of the current data memory unit includes: Add 1 to the number of the current data memory unit and take the modulus of n, the remainder obtained is the number of the target data memory unit; or, The number of the memory unit at the current address is added with (n-1) and then the remainder is calculated as n, and the remainder obtained is the number of the target data memory unit.

10. The method according to any one of claims 1 to 9, characterized in that: The method further comprises: Obtain the current address memory unit; Determine the current read data memory unit according to the address of the data memory unit stored in the current address memory unit; Based on the second preset condition, determining whether the currently read data memory unit is the data memory unit to be read; If the currently read data memory unit is the data memory unit to be read, the stored data in the currently read data memory unit is read; wherein the data memory unit to be read is the data memory unit among the n data memory units that meets the second preset condition.

11. The method according to claim 10, characterized in that The second preset condition is that the currently read data memory unit includes the stored data and a second check value matching the stored data.

12. The method according to claim 10, characterized in that If the currently read data memory unit is not the to-be-read data memory unit, the method further includes: According to a preset search rule, a target read data memory unit is obtained from the other data memory units of the n data memory units except the currently read data memory unit; Based on a second preset condition, determining whether the target read data memory unit is a to-be-read data memory unit; If the target read data memory unit is a to-be-read data memory unit, the stored data in the target read data memory unit is read.

13. The method according to claim 12, characterized in that The step of obtaining a target read data memory unit from the n data memory units except the currently read data memory unit according to a preset search rule comprises: Based on the serial number of the current read data memory unit, determine the serial number of the target read data memory unit according to the first serial number search rule; According to the serial number of the target read data memory unit, a target read data memory unit is obtained from the other data memory units among the n data memory units except the current read data memory unit.

14. The method according to claim 13, characterized in that The order of determining the numbers of the target read data memory units according to the first numbering search rule is opposite to the order in which the n data memory units are sequentially used as the target data memory units.

15. The method according to claim 14, characterized in that The n data memory units are numbered as consecutive integers and the starting number is 0; the first number search rule is: add 1 to the number of the currently read data memory unit and then take the remainder of n, and the remainder obtained is the number of the target read memory unit, The order of the n data memory units as the target data memory units is: add (n-1) to the number of the current data memory unit and then take the remainder of n, and the remainder is the number of the target memory unit; Or, the first number search rule is: add (n-1) to the number of the currently read data memory unit and then take the remainder of n, and the remainder obtained is the number of the target read memory unit, The order in which the n data memory units are sequentially used as the target data memory units is: add 1 to the number of the current data memory unit and take the modulus of n, and the remainder obtained is the number of the target memory unit.

16. The method according to claim 1, characterized in that m is an integer multiple of n.

17. A data processing device, characterized in that: include: A judging unit, configured to judge whether there is a current address memory unit based on a first preset condition; The current address memory unit is an address memory unit that meets the first preset condition among the m address memory units, and the address of a data memory unit is stored in the current address memory unit; a determining unit, configured to determine a target address memory unit according to the current address memory unit if there is a current address memory unit, and determine a target data memory unit according to the address of the data memory unit stored in the current address memory unit; A storage unit, used for writing the data to be written into the target data memory unit as storage data, the address of the target data memory unit is stored in the target address memory unit, the target address memory unit is updated to the address memory unit that meets the first preset condition, and the current address memory unit is updated to the address memory unit that does not meet the first preset condition; wherein the m address memory units are fixed in sequence as the target address memory units, and the n data memory units are fixed in sequence as the target data memory units.

18. An electronic device, characterized in that: It comprises a memory for storing computer program instructions and a processor for executing the program instructions, wherein when the computer program instructions are executed by the processor, the electronic device is triggered to execute the data processing method described in any one of claims 1-16.

19. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute the data processing method according to any one of claims 1 to 16.

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