Processor communication method, device, electronic device and storage medium

Abstract

This application provides a communication method, apparatus, electronic device, and storage medium for a processor, relating to the field of communication technology. The processor's communication method includes: acquiring data for multiple first services; identifying multiple target transmit GPIO pins among multiple transmit GPIO pins that do not conflict; and using the multiple target transmit GPIO pins to send the data for multiple first services to the inputs of multiple bus transceivers, so that the multiple bus transceivers send the data for multiple first services to multiple external devices respectively. By using multiple target transmit GPIO pins in the processor to communicate with multiple bus transceivers, the data for multiple first services can be simultaneously sent to multiple external devices through multiple target transmit GPIO pins that do not conflict and multiple bus transceivers. The entire process uses the transmit GPIO pins in the processor for data transmission, saving the cost of the processor communicating with peripherals through multiple buses.

Description

Technical Field

[0001] This application relates to the field of communication technology, and more specifically, to a communication method, apparatus, electronic device, and storage medium for a processor. Background Technology

[0002] In embedded systems, numerous buses are used for interconnection between devices. A typical bus consists of a physical layer, a data link layer, and a transport layer. In industrial control scenarios, the use of buses is extensive, and the variety of bus protocols presents challenges for controller design, making it difficult to find a single processor suitable for diverse industrial embedded applications.

[0003] In related technologies, the processor communicates with many peripherals through multiple buses. For example, if five buses are to be used, a common and flexible method for implementing buses is usually implemented by modules with parallel processing capabilities, such as FPGA (Field-Programmable Gate Array) chips. Each bus is hardware independent and does not affect the others.

[0004] However, in related technologies, when the processor communicates with peripherals through multiple buses, additional chips are required, leading to increased costs. Summary of the Invention

[0005] The purpose of this application is to provide a processor communication method, apparatus, electronic device, and storage medium to address the shortcomings of the prior art and solve the aforementioned technical problems.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0007] In a first aspect, embodiments of this application provide a communication method for a processor, the processor including: a plurality of transmit input / output GPIO pins; the plurality of transmit GPIO pins are respectively communicatively connected to the input terminals of a plurality of bus transceivers, the method including:

[0008] Acquire data from multiple primary business processes;

[0009] Among the multiple transmit GPIO pins, identify multiple target transmit GPIO pins that do not conflict;

[0010] Multiple target transmit GPIO pins are used to send multiple data of the first service to the input terminals of multiple bus transceivers, so that the multiple bus transceivers send the multiple data of the first service to multiple external devices respectively.

[0011] Optionally, the processor further includes: a plurality of receive GPIO pins, wherein the plurality of receive GPIO pins are respectively communicatively connected to the receiving ends of the plurality of bus transceivers, and the method further includes:

[0012] Multiple receive GPIO pins are used to receive data from multiple second services sent by the outputs of multiple bus transceivers.

[0013] Optionally, the method of using multiple receive GPIO pins to receive data from multiple second services transmitted by the outputs of multiple bus transceivers includes:

[0014] Using multiple receive GPIO pins, data of multiple second services sent by the output terminals of multiple bus transceivers are received according to the operating frequency, delay and service priority corresponding to the types of multiple second services.

[0015] Optionally, the step of using multiple target transmit GPIO pins to send multiple data of the first service to the input terminals of multiple bus transceivers includes:

[0016] Using multiple target transmit GPIO pins, data of multiple first services are transmitted to the input terminals of multiple bus transceivers according to the operating frequency, delay, and service priority corresponding to the types of multiple first services.

[0017] Optionally, the service types include: hard real-time service type, high real-time service type, and ordinary real-time service type;

[0018] Among them, the service priority of the hard real-time service type is higher than that of the high real-time service type; the service priority of the high real-time service type is higher than that of the ordinary real-time service type.

[0019] Optionally, the method of using multiple receive GPIO pins to receive data from multiple second services transmitted by the outputs of multiple bus transceivers includes:

[0020] Based on the data of the multiple first services transmitted by the multiple transmit GPIO pins and the data of the multiple second services transmitted by the multiple receive GPIO pins, conflict detection is performed on the multiple transmit GPIO pins to obtain conflict detection results;

[0021] If the collision detection result indicates that some of the transmit GPIO pins among the multiple transmit GPIO pins are in conflict, a collision indication message is sent to the bit switch corresponding to the partial transmit GPIO pin, so as to turn off the bit switch corresponding to the partial transmit GPIO pin based on the collision indication message.

[0022] Optionally, determining the multiple target transmit GPIO pins that do not conflict among the multiple transmit GPIO pins includes:

[0023] Determine whether the multiple bit switches corresponding to the multiple transmit GPIO pins are turned on;

[0024] If there is an unactivated bit switch among the multiple bit switches corresponding to the multiple transmit GPIO pins, then the transmit GPIO pin corresponding to the unactivated bit switch and the transmit function corresponding to the target bus transceiver connected to the communication are turned off.

[0025] Among the remaining active bit switches, a plurality of target transmit GPIO pins are identified.

[0026] Optionally, after receiving data from multiple second services transmitted by the outputs of multiple bus transceivers using multiple receive GPIO pins, the method further includes:

[0027] Determine whether the data of each of the second services is complete;

[0028] If complete, an acknowledgment signal is sent to the multiple acknowledgment switches corresponding to the multiple sending GPIO pins.

[0029] Optionally, the step of using multiple target transmit GPIO pins to send multiple data of the first service to the input terminals of multiple bus transceivers includes:

[0030] If all bit switches corresponding to multiple target transmit GPIO pins are turned on, and all acknowledgment switches corresponding to multiple target transmit GPIO pins receive the acknowledgment signal, then multiple data of the first service are sent to the input terminals of multiple bus transceivers using multiple target transmit GPIO pins.

[0031] Secondly, embodiments of this application also provide a communication device for a processor, the processor including: a plurality of transmit input / output GPIO pins; the plurality of transmit GPIO pins are respectively communicatively connected to the input terminals of a plurality of bus transceivers, the device comprising:

[0032] The acquisition module is used to acquire data from multiple primary business processes.

[0033] The determining module is used to determine, among the plurality of transmit GPIO pins, a plurality of target transmit GPIO pins that do not conflict;

[0034] The transmitting module is used to transmit multiple data of the first service to the input terminals of multiple bus transceivers using multiple target transmitting GPIO pins, so that the multiple bus transceivers transmit the multiple data of the first service to multiple external devices respectively.

[0035] Optionally, the processor further includes: a plurality of receive GPIO pins, wherein the plurality of receive GPIO pins are respectively communicatively connected to the receiving ends of the plurality of bus transceivers; the device further includes:

[0036] The receiving module is used to receive data of multiple second services sent by the output terminals of multiple bus transceivers using multiple receiving GPIO pins.

[0037] Optionally, the receiving module is specifically used to receive data of multiple second services sent by the output terminals of multiple bus transceivers, based on the operating frequency, delay, and service priority corresponding to the types of multiple second services, using multiple receiving GPIO pins.

[0038] Optionally, the transmitting module is specifically used to use multiple target transmitting GPIO pins to transmit multiple first service data to the input terminals of multiple bus transceivers according to the operating frequency, delay and service priority corresponding to the types of multiple first services.

[0039] Optionally, the service types include: hard real-time service type, high real-time service type, and ordinary real-time service type;

[0040] Among them, the service priority of the hard real-time service type is higher than that of the high real-time service type; the service priority of the high real-time service type is higher than that of the ordinary real-time service type.

[0041] Optionally, the receiving module is specifically configured to perform conflict detection on the multiple transmitting GPIO pins based on the data of the multiple first services transmitted by the multiple transmitting GPIO pins and the data of the multiple second services transmitted by the multiple receiving GPIO pins, and obtain a conflict detection result; if the conflict detection result indicates that some of the multiple transmitting GPIO pins are in conflict, send conflict indication information to the bit switch corresponding to the partial transmitting GPIO pins, so as to close the bit switch corresponding to the partial transmitting GPIO pins based on the conflict indication information.

[0042] Optionally, the determining module is specifically used to determine whether multiple bit switches corresponding to multiple transmit GPIO pins are turned on; if there are unturned bit switches among the multiple bit switches corresponding to multiple transmit GPIO pins, then the transmit GPIO pin corresponding to the unturned bit switch and the transmit function corresponding to the target bus transceiver connected to the communication are turned off; among the transmit GPIO pins corresponding to the remaining turned-on bit switches, multiple target transmit GPIO pins are determined.

[0043] Optionally, the device further includes:

[0044] The judgment module is used to determine whether the data of multiple second services is complete;

[0045] The transmitting module is further configured to, if complete, send an acknowledgment signal to multiple acknowledgment switches corresponding to the multiple transmitting GPIO pins.

[0046] Optionally, the transmitting module is specifically configured to transmit multiple data of the first service to the input terminals of multiple bus transceivers using multiple target transmitting GPIO pins if all bit switches corresponding to multiple target transmitting GPIO pins are turned on and multiple acknowledgment switches corresponding to multiple target transmitting GPIO pins receive the acknowledgment signal.

[0047] Thirdly, embodiments of this application also provide an electronic device, including: a memory and a processor, wherein the memory stores a computer program executable by the processor, and the processor executes the computer program to implement the communication method of the processor described in any of the first aspects above.

[0048] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when read and executed, implements the communication method of the processor described in any of the first aspects above.

[0049] The beneficial effects of this application are as follows: This application provides a communication method for a processor, which includes multiple transmit input / output GPIO pins. These multiple transmit GPIO pins are communicatively connected to the inputs of multiple bus transceivers. The method includes: acquiring data for multiple first services; identifying multiple target transmit GPIO pins among the multiple transmit GPIO pins that do not conflict; and using the multiple target transmit GPIO pins to send the data for the multiple first services to the inputs of the multiple bus transceivers, so that the multiple bus transceivers send the data for the multiple first services to multiple external devices respectively. By using multiple target transmit GPIO pins in the processor to communicate with multiple bus transceivers, the data for multiple first services can be simultaneously sent to multiple external devices through multiple target transmit GPIO pins that do not conflict and multiple bus transceivers, without the need for additional chips. The entire process uses the transmit GPIO pins in the processor for data transmission, saving the cost of the processor communicating with peripherals through multiple buses. Attached Figure Description

[0050] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 A flowchart illustrating a processor communication method provided in this application embodiment. Figure 1 ;

[0052] Figure 2 A schematic diagram of the system architecture on which a processor communication method provided in an embodiment of this application is based;

[0053] Figure 3 A flowchart illustrating a processor communication method provided in this application embodiment. Figure 2 ;

[0054] Figure 4 A flowchart illustrating a processor communication method provided in this application embodiment. Figure 3 ;

[0055] Figure 5 A flowchart illustrating a processor communication method provided in this application embodiment. Figure 4 ;

[0056] Figure 6 A schematic diagram of the structure of a processor communication device provided in an embodiment of this application;

[0057] Figure 7This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.

[0059] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0060] In the description of this application, it should be noted that if the terms "upper", "lower", etc. appear to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of this application is usually placed in, it is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0061] Furthermore, the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0062] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.

[0063] This application provides a communication method for a processor, applied to a processor in an electronic device. The processor includes: multiple transmit GPIO (General Purpose Input Output) pins; the multiple transmit GPIO pins are respectively communicatively connected to the input terminals of multiple bus transceivers.

[0064] There is a one-to-one correspondence between the transmit GPIO pin and the input of the bus transceiver; that is, one transmit GPIO pin is connected to one input of the bus transceiver.

[0065] In some implementations, the processor has a first group of GPIO pins, which includes multiple GPIO pins. When the first group of GPIO pins is configured as an output, the multiple GPIO pins in the first group of GPIO pins are configured as multiple transmit GPIO pins, and each transmit GPIO pin is connected to the input of each bus transceiver.

[0066] The following explains a communication method for a processor provided by an embodiment of this application.

[0067] Figure 1 A flowchart illustrating a processor communication method provided in this application embodiment. Figure 1 ,like Figure 1 As shown, the method may include:

[0068] S101, Obtain data from multiple primary business processes.

[0069] In some implementations, data from multiple first services is read from a transmit buffer, the unit of measurement for the multiple first service data being bytes; the unit of the multiple first service data is converted to obtain the converted data of the multiple first services; the unit of the converted data of the multiple first services is bits.

[0070] It should be noted that the converted data of a first service is transmitted serially through the same target GPIO pin, while the converted data of different first services are transmitted serially through different targets GPIO pins.

[0071] S102. Among multiple transmit GPIO pins, identify multiple target transmit GPIO pins that do not conflict.

[0072] Among them, multiple transmit GPIO pins are connected to multiple bus transceivers through multiple buses.

[0073] Optionally, the multiple buses may include low-speed buses and / or high-speed buses. For example, low-speed buses may include at least one of the following: UART (Universal Asynchronous Receiver / Transmitter), SPI (Serial Peripheral Interface), and IIC (Inter-Integrated Circuit, actually short for IICBus, so it should be called Integrated Circuit Bus in Chinese). High-speed buses may include at least one of the following: eth (Ethernet, a computer networking technology used to connect devices in a local area network and transmit data via cable or wirelessly) and PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard).

[0074] In this embodiment, a conflicting transmit GPIO pin among multiple transmit GPIO pins refers to a transmit GPIO pin whose corresponding bus is occupied and cannot be used to transmit data. Therefore, it is necessary to identify multiple target transmit GPIO pins that do not conflict, whose corresponding buses are not occupied and can transmit data.

[0075] S103. Multiple target transmit GPIO pins are used to send multiple first service data to the input terminals of multiple bus transceivers, so that multiple bus transceivers can send the data of multiple first services to multiple external devices respectively.

[0076] Among them, multiple target transmit GPIO pins can be all or some of the multiple transmit GPIO pins.

[0077] In some implementations, when the number of multiple target transmit GPIO pins is greater than the number of multiple first services, a target transmit GPIO pin, matching the number of the multiple first services, is selected from the multiple target transmit GPIO pins to transmit the data of the multiple first services. When the number of multiple target transmit GPIO pins is less than the number of multiple first services, the data of the multiple first services is transmitted in batches using the multiple target transmit GPIO pins according to the priority of the multiple first services.

[0078] In practical applications, data for the same primary service is serially transmitted to the corresponding bus via the same target transmit GPIO pin, and then transmitted through the bus to the input of a bus transceiver that is communicatively connected to the target transmit GPIO pin. The bus transceiver then transmits the data of the primary service to the bus controller, which in turn sends the data to an external device.

[0079] In summary, this application provides a communication method for a processor, which includes multiple transmit input / output GPIO pins. These multiple transmit GPIO pins are communicatively connected to the inputs of multiple bus transceivers. The method includes: acquiring data for multiple first services; identifying multiple target transmit GPIO pins among the multiple transmit GPIO pins that do not conflict; and using the multiple target transmit GPIO pins to send the data for the multiple first services to the inputs of the multiple bus transceivers, so that the multiple bus transceivers send the data for the multiple first services to multiple external devices respectively. By using multiple target transmit GPIO pins in the processor to communicate with multiple bus transceivers, data for multiple first services can be simultaneously sent to multiple external devices through multiple target transmit GPIO pins and multiple bus transceivers without adding additional chips. The entire process uses the transmit GPIO pins in the processor for data transmission, saving the cost of the processor communicating with peripherals through multiple buses.

[0080] Optionally, Figure 2 A schematic diagram of the system architecture on which a processor communication method provided in this application embodiment is based, as shown below. Figure 2 As shown, the processor may include multiple transmit GPIO pins such as GPIOA0, GPIOA1, GPIOA2, GPIOA3, and GPIOA4. Multiple bus transceivers include Can0, Can1, Can2, Can3, and Can4. Among these, GPIOA0, GPIOA1, GPIOA2, GPIOA3, and GPIOA4 constitute the first group of GPIO pins and can be referred to as GPIOA pins.

[0081] Specifically, the GPIOA0 pin is connected to Can0T (T refers to the input terminal), the GPIOA1 pin is connected to Can1T, the GPIOA2 pin is connected to Can2T, the GPIOA3 pin is connected to Can3T, and the GPIOA4 pin is connected to Can4T.

[0082] certainly, Figure 2 This is merely an example; the number of multiple transmit GPIO pins and the number of multiple bus transceivers are not specifically limited in this embodiment.

[0083] Optionally, the processor further includes: multiple receive GPIO pins, which are respectively communicatively connected to the receiving ends of multiple bus transceivers; the method further includes:

[0084] It employs multiple receive GPIO pins to receive data from multiple secondary services transmitted from the outputs of multiple bus transceivers.

[0085] In some implementations, the outputs of multiple bus transceivers send multiple second service data to multiple receive GPIO pins via multiple buses. Specifically, the data for one second service is transmitted serially through the same bus transceiver and the same receive GPIO pin.

[0086] In this embodiment of the application, the processor has a second group of GPIO pins, which includes multiple GPIO pins. When the second group of GPIO pins is configured as an input, the multiple GPIO pins in the second group of GPIO pins are configured as multiple receive GPIO pins, and each receive GPIO pin is connected to the output terminal of each bus transceiver.

[0087] It should be noted that by mapping all transmit GPIO pins to the first group of GPIO pins and all receive GPIO pins to the second group of GPIO pins, multiple transmit GPIO pins can be controlled to output bus waveforms simultaneously, or multiple receive GPIO pins can be used to sample multiple buses at the same time.

[0088] like Figure 2 The processor may include multiple transmit GPIO pins such as GPIOB0, GPIOB1, GPIOB2, GPIOB3, and GPIOB4. Multiple bus transceivers include Can0, Can1, Can2, Can3, and Can4. Among these, GPIOB0, GPIOB1, GPIOB2, GPIOB3, and GPIOB4 constitute the second group of GPIO pins, which can be referred to as GPIOB pins.

[0089] Specifically, the GPIOB0 pin is connected to Can0R (R refers to the input terminal), the GPIOB1 pin is connected to Can1R, the GPIOB2 pin is connected to Can2R, the GPIOB3 pin is connected to Can3R, and the GPIOB4 pin is connected to Can4R.

[0090] certainly, Figure 2 This is merely an example; the number of multiple receive GPIO pins and the number of multiple bus transceivers are not specifically limited in this embodiment.

[0091] Optionally, the process described above, which uses multiple receive GPIO pins to receive data from multiple second services transmitted by the outputs of multiple bus transceivers, may include:

[0092] Using multiple receive GPIO pins, the system receives data from multiple second services sent by the outputs of multiple bus transceivers, based on the operating frequency, delay, and service priority corresponding to the types of multiple second services.

[0093] In some implementations, the task of receiving data from multiple second services is designated as the first hard real-time service, with a scheduling period of 1 / 5 of the minimum baud rate of the external bus, i.e., a scheduling period of 200 ns (nanoseconds). Multiple receive GPIO pins are uniformly controlled by this first hard real-time service. For example... Figure 2 As shown, the first hard real-time service operates at the highest sampling rate through multiple receive GPIO pins and parallel port inputs.

[0094] Furthermore, after receiving data from multiple secondary services, the data from these secondary services can be filtered to obtain filtered data from each secondary service. This filtering process can eliminate interference from signal noise.

[0095] In this embodiment of the application, the data of multiple second services received by multiple receive GPIO pins are converted into units. The unit of measurement for the data of the multiple second services is bits, and the unit of measurement for the converted data of the multiple second services is bytes. The converted data of the multiple second services is output to the receive buffer, and each receive GPIO pin corresponds to one bit in the receive buffer.

[0096] like Figure 2 As shown, the unit is converted from bit to byte. The number of multiple second services can be 5. The converted data of the multiple services includes: B1byte (byte), B2byte, B3byte, B4byte, and B5byte.

[0097] Optionally, the process in S103 above, which uses multiple target transmit GPIO pins to send multiple first service data to the inputs of multiple bus transceivers, may include:

[0098] Multiple target transmit GPIO pins are used to send multiple first service data to the input terminals of multiple bus transceivers according to the operating frequency, delay and service priority corresponding to the types of multiple first services.

[0099] Different business types have different operating frequencies, delays, and business priorities.

[0100] In this embodiment, the task of sending data for multiple first services is a second hard real-time task, with a scheduling period of 1µs (microseconds) of the minimum baud rate of the external bus. Multiple target GPIO pins are uniformly controlled by the second hard real-time service. For example... Figure 2 As shown, the second hard real-time service sends GPIO pins to parallel outputs through multiple targets, operating at the highest baud rate.

[0101] In this embodiment of the application, the converted data unit of the multiple first services is bits, and each bit of the converted data of the multiple first services corresponds to a transmit GPIO pin, and the data of the multiple first services in the transmit buffer is output to the multiple target transmit GPIO pins.

[0102] like Figure 2 As shown, data from multiple first-level services is obtained from ordinary real-time services, higher-level protocol frames, and application-layer tasks. The unit of data from these first-level services is bytes. For example, if there are five first-level tasks, they are: B1byte, B2byte, B3byte, B4byte, and B5byte. After converting the unit from bytes to bits, multiple transmit GPIO pins are used for transmission.

[0103] It's important to note that in scenarios with multiple buses operating simultaneously, latency, a key performance indicator, is typically affected by both hardware and software resources. Hardware resource impact primarily includes processor processing speed and pin toggle speed. Software resource impact primarily includes the operating system (OS) and scheduling algorithms.

[0104] Therefore, regardless of whether it is a scenario where multiple receiving GPIO pins receive data from multiple second services, or a scenario where multiple target transmitting GPIO pins transmit data from multiple first services, the embodiments of this application classify the services and use different operating frequencies, delays, and service priorities to transmit service data according to different service types, so as to ensure that different types of service data can be transmitted reliably and meet actual needs.

[0105] Optionally, the service types include: hard real-time service type, high real-time service type, and ordinary real-time service type.

[0106] Among these, hard real-time services have a higher priority than high real-time services; high real-time services have a higher priority than ordinary real-time services. Hard real-time services are guaranteed by hardware real-time processors, high real-time services run without consuming processor resources, and ordinary real-time services run without consuming processor resources for either hard or high real-time services.

[0107] In this application embodiment, hard real-time service type services include: data output, data acquisition, etc.; high real-time service type services include: conflict detection, ACK (Acknowledge character), error checking and integrity detection, etc.; ordinary real-time service type services include: message framing, message filtering, retransmission control, etc.

[0108] In some implementations, hard real-time services operate at a higher frequency than high real-time services, and the maximum latency of hard real-time services is lower than that of high real-time services. Ordinary real-time services are triggered by high real-time services, operate on a packet-by-packet basis, and have a flexible operating frequency; their operating frequency is lower than that of high real-time services. For example... Figure 2 As shown, for high real-time services, the baud rate is used as the minimum working cycle.

[0109] For example, the operating frequency of hard real-time services can be 25MHz, and the maximum latency of hard real-time services can be 40ns; the operating frequency of high real-time services can be 1MHz, and the maximum latency of high real-time services can be 1us; the operating frequency of ordinary real-time services is less than 1MHz.

[0110] It is important to note that hard real-time services must be prioritized. These services primarily involve hardware operations and have relatively simple functions. In this embodiment, a hardware clock interrupt ensures the highest priority for hard real-time services; each time the clock arrives, the hard real-time service is executed first.

[0111] Optionally, Figure 3 A flowchart illustrating a processor communication method provided in this application embodiment. Figure 2 ,like Figure 3 As shown, multiple receive GPIO pins are used to receive data from multiple second services transmitted from the outputs of multiple bus transceivers, including:

[0112] S201. Based on the data of multiple first services transmitted by multiple transmit GPIO pins and the data of multiple second services transmitted by multiple receive GPIO pins, perform conflict detection on the multiple transmit GPIO pins and obtain the conflict detection result.

[0113] The collision detection result is used to indicate whether there is a collision among the multiple transmit GPIO pins.

[0114] In some implementations, the data of multiple first services output by multiple transmit GPIO pins and the data of multiple second services read by multiple receive GPIO pins are compared to determine whether they are equal, thereby obtaining the conflict detection result for multiple transmit GPIO pins.

[0115] S202. If the collision detection result indicates that some of the multiple transmit GPIO pins are in conflict, send collision indication information to the bit switch corresponding to the partial transmit GPIO pins, so as to close the bit switch corresponding to the partial transmit GPIO pins based on the collision indication information.

[0116] Among them, some transmit GPIO pins can be: at least one transmit GPIO pin from a plurality of transmit GPIO pins. For example Figure 2 As shown, after multiple transmit GPIO pins receive data from multiple first services, collision detection is performed, and collision indication information is sent to the bit switches corresponding to some transmit GPIO pins.

[0117] In this embodiment, each transmit GPIO pin has a corresponding bit switch. For conflicting transmit GPIO pins, a conflict indicator can be sent to the conflicting pins, effectively disabling the bit switch corresponding to them. This prevents conflicting transmit GPIO pins from participating in data transmission, making the method of transmitting data to multiple bus transceivers via multiple transmit GPIO pins more reliable.

[0118] Optionally, Figure 4 A flowchart illustrating a processor communication method provided in this application embodiment. Figure 3 ,like Figure 4 As shown, the process of determining multiple target transmit GPIO pins that do not conflict among multiple transmit GPIO pins in S102 above may include:

[0119] S301. Determine whether multiple bit switches corresponding to multiple transmit GPIO pins are turned on.

[0120] It should be noted that for transmit GPIO pins with conflicting signals, the bit switch is off; for transmit GPIO pins without conflicting signals, the bit switch is on. The bit switch is turned off based on the conflict indication.

[0121] S302. If among the multiple bit switches corresponding to multiple transmit GPIO pins, there is a bit switch that is not turned on, then turn off the transmit GPIO pin corresponding to the bit switch that is not turned on, as well as the transmit function corresponding to the target bus transceiver connected to the communication.

[0122] In this embodiment, the transmit GPIO pin corresponding to the unactivated bit switch is a conflicting transmit GPIO pin. This means the bus between the conflicting transmit GPIO pin and the target bus transceiver is occupied. Disabling the conflicting transmit GPIO pin and the corresponding transmit function of the target bus transceiver avoids the unreliable data transmission problem caused by using the bus for data transmission when the target bus transceiver is occupied.

[0123] S303. Among the remaining active bit switches, identify multiple target transmit GPIO pins.

[0124] It is worth noting that if the number of transmit GPIO pins corresponding to the remaining enabled bit switches is less than or equal to the number of multiple first services, then the transmit GPIO pins corresponding to the remaining enabled bit switches will be directly used as multiple target transmit GPIO pins.

[0125] In addition, if the number of transmit GPIO pins corresponding to the remaining enabled bit switches is greater than the number of multiple first services, then select pins from the transmit GPIO pins corresponding to the remaining enabled bit switches that are equal in number to the number of multiple first services as multiple target transmit GPIO pins.

[0126] Optionally, Figure 5 A flowchart illustrating a processor communication method provided in this application embodiment. Figure 4 ,like Figure 5 As shown, after the above process of using multiple receive GPIO pins to receive data from multiple second services transmitted by the outputs of multiple bus transceivers, the method may further include:

[0127] S401. Determine whether the data of multiple second services is complete.

[0128] The process of determining whether data from multiple secondary services is complete falls under the category of high real-time services. For high real-time services, processing information within a single bit can be triggered using a lightweight RTOS (Real-Time Operating System) or bare-core hardware.

[0129] In some implementations, multiple receive GPIO pins are used to read data from the outputs of multiple bus transceivers via multiple buses, transmitting data for multiple second services. The data for these multiple second services is measured in bits, and it is simultaneously packaged into multiple arrays to form received information corresponding to multiple buses. This received information refers to data for multiple second services measured in bytes. Whenever a byte is filled, a data integrity check is immediately performed.

[0130] like Figure 2 As shown, for multiple second-service data units of byte: B1byte, B2byte, B3byte, B4byte, and B5byte, after integrity checks are performed, they enter the processes of ordinary real-time services, higher-level protocol frames, and application layer tasks.

[0131] It should be noted that the integrity of data from multiple second services can be determined sequentially, simultaneously, or in any other order. This application does not impose any specific limitations on this.

[0132] S402. If complete, send an acknowledgment signal to multiple acknowledgment switches corresponding to multiple transmit GPIO pins.

[0133] Each transmit GPIO pin has a corresponding acknowledgment switch.

[0134] In this embodiment, there is a one-to-one correspondence between multiple transmit GPIO pins and multiple receive GPIO pins, and a transmit GPIO pin and a GPIO pin with a corresponding relationship are respectively connected to the input and receiver of the same bus transceiver.

[0135] It is worth noting that if the data of a second service received by a receive GPIO pin is complete, an acknowledgment signal is sent to the acknowledgment switch corresponding to the transmit GPIO pin. Conversely, if the data of a second service received by a receive GPIO pin is incomplete, an error signal is sent to the acknowledgment switch corresponding to the transmit GPIO pin.

[0136] Optionally, the process in S103 above, which uses multiple target transmit GPIO pins to send multiple first service data to the inputs of multiple bus transceivers, may include:

[0137] If the bit switches corresponding to multiple target transmit GPIO pins are all turned on, and the multiple acknowledgment switches corresponding to multiple target transmit GPIO pins have all received acknowledgment signals, then multiple target transmit GPIO pins are used to send multiple first service data to the input terminals of multiple bus transceivers.

[0138] In this embodiment, when the bit switch corresponding to the target transmit GPIO pin is turned on, it indicates that there is no conflict with the target transmit GPIO pin, and the bus corresponding to the target transmit GPIO pin is in an unoccupied state. When the acknowledgment switch corresponding to the target transmit GPIO pin receives an acknowledgment signal, it indicates that the receive GPIO pin corresponding to the target transmit GPIO pin can accurately and completely receive the data transmitted by the bus transceiver through the bus. By sampling multiple such target transmit GPIO pins and sending multiple first service data to the input terminals of multiple bus transceivers through multiple buses, efficient, accurate, and reliable parallel transmission of multiple first service data can be achieved.

[0139] In summary, this embodiment integrates the same functions of multiple buses into a single module, using multiple GPIO pins of the processor as the transmitting hardware for these buses, enabling simultaneous transmission or reception of signals from multiple buses. Furthermore, the simd instruction (Single Instruction Multiple Data, a parallel instruction) allows simultaneous manipulation of multiple parameters. For example, after multiple receive GPIO pins receive multiple complete bytes of data for a second task, this data can be simultaneously added to various arrays.

[0140] Furthermore, based on the different real-time requirements of the bus protocols, the functional modules are divided into hard real-time services (data output, data sampling), high real-time services (collision detection, ACK, error checking), and ordinary real-time tasks (message framing, message filtering, retransmission control). A task scheduling scheme is designed to ensure the real-time requirements of each priority task. At the same time, the processor's GPIO group contains multiple pins, and the SIMD instruction can operate on multiple operands simultaneously, so as to realize the simultaneous operation of multiple data lines and meet the real-time requirements of multiple buses, thereby maximizing the processor's capabilities.

[0141] The following describes the communication device, electronic device, and storage medium of the processor used to execute the communication method of the processor provided in this application. For the specific implementation process and technical effects, please refer to the relevant content of the above-mentioned processor communication method, which will not be repeated below.

[0142] Figure 6 This is a schematic diagram of a communication device for a processor provided in an embodiment of this application. The processor includes: multiple transmit input / output GPIO pins; the multiple transmit GPIO pins are respectively communicatively connected to the input terminals of multiple bus transceivers, such as... Figure 6 As shown, the device includes:

[0143] The device includes:

[0144] Module 101 is used to acquire data from multiple primary services;

[0145] The determining module 102 is used to determine, among the plurality of transmit GPIO pins, a plurality of target transmit GPIO pins that do not conflict;

[0146] The transmitting module 103 is used to transmit multiple data of the first service to the input terminals of multiple bus transceivers using multiple target transmitting GPIO pins, so that the multiple bus transceivers transmit the data of the multiple first services to multiple external devices respectively.

[0147] Optionally, the processor further includes: a plurality of receive GPIO pins, wherein the plurality of receive GPIO pins are respectively communicatively connected to the receiving ends of the plurality of bus transceivers; the device further includes:

[0148] The receiving module is used to receive data of multiple second services sent by the output terminals of multiple bus transceivers using multiple receiving GPIO pins.

[0149] Optionally, the receiving module is specifically used to receive data of multiple second services sent by the output terminals of multiple bus transceivers, based on the operating frequency, delay, and service priority corresponding to the types of multiple second services, using multiple receiving GPIO pins.

[0150] Optionally, the transmitting module 103 is specifically used to use multiple target transmitting GPIO pins to transmit multiple first service data to the input terminals of multiple bus transceivers according to the operating frequency, delay and service priority corresponding to the types of multiple first services.

[0151] Optionally, the service types include: hard real-time service type, high real-time service type, and ordinary real-time service type;

[0152] Among them, the service priority of the hard real-time service type is higher than that of the high real-time service type; the service priority of the high real-time service type is higher than that of the ordinary real-time service type.

[0153] Optionally, the receiving module is specifically configured to perform conflict detection on the multiple transmitting GPIO pins based on the data of the multiple first services transmitted by the multiple transmitting GPIO pins and the data of the multiple second services transmitted by the multiple receiving GPIO pins, and obtain a conflict detection result; if the conflict detection result indicates that some of the multiple transmitting GPIO pins are in conflict, send conflict indication information to the bit switch corresponding to the partial transmitting GPIO pins, so as to close the bit switch corresponding to the partial transmitting GPIO pins based on the conflict indication information.

[0154] Optionally, the determining module 102 is specifically used to determine whether multiple bit switches corresponding to multiple transmit GPIO pins are turned on; if there are unturned bit switches among the multiple bit switches corresponding to multiple transmit GPIO pins, then the transmit GPIO pin corresponding to the unturned bit switch and the transmit function corresponding to the target bus transceiver connected to the communication are turned off; among the transmit GPIO pins corresponding to the remaining turned-on bit switches, multiple target transmit GPIO pins are determined.

[0155] Optionally, the device further includes:

[0156] The judgment module is used to determine whether the data of multiple second services is complete;

[0157] The sending module 103 is further configured to send an acknowledgment signal to multiple acknowledgment switches corresponding to the multiple sending GPIO pins if the condition is met.

[0158] Optionally, the transmitting module 103 is specifically used to transmit multiple data of the first service to the input terminals of multiple bus transceivers using multiple target transmitting GPIO pins if all bit switches corresponding to multiple target transmitting GPIO pins are turned on and multiple acknowledgment switches corresponding to multiple target transmitting GPIO pins receive the acknowledgment signal.

[0159] The above-described device is used to execute the method provided in the foregoing embodiments, and its implementation principle and technical effect are similar, so they will not be described again here.

[0160] These modules can be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), one or more digital signal processors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs). Alternatively, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together as a system-on-a-chip (SOC).

[0161] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, such as... Figure 7 As shown, the electronic device may include: a processor 201 and a memory 202.

[0162] The memory 202 is used to store programs, and the processor 201 calls the programs stored in the memory 202 to execute the above method embodiments. The specific implementation and technical effects are similar, and will not be described in detail here.

[0163] Optionally, this application also provides a program product, such as a computer-readable storage medium, including a program that, when executed by a processor, performs the above-described method embodiments.

[0164] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0165] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0166] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units.

[0167] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0168] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A communication method for a processor, characterized in that, The processor includes: multiple transmit input / output GPIO pins; the multiple transmit GPIO pins are respectively communicatively connected to the input terminals of multiple bus transceivers; the method includes: Acquire data from multiple primary business processes; Among the multiple transmit GPIO pins, identify multiple target transmit GPIO pins that do not conflict; Multiple target transmit GPIO pins are used to send multiple data of the first service to the input terminals of multiple bus transceivers, so that the multiple bus transceivers send the multiple data of the first service to multiple external devices respectively; The processor further includes: multiple receive GPIO pins, wherein the multiple receive GPIO pins are respectively communicatively connected to the receiving ends of the multiple bus transceivers; the method further includes: Multiple receive GPIO pins are used to receive data from multiple second services sent by the outputs of multiple bus transceivers; The method employs multiple receive GPIO pins to receive data from multiple second services transmitted from the outputs of multiple bus transceivers, including: Based on the data of the multiple first services transmitted by the multiple transmit GPIO pins and the data of the multiple second services transmitted by the multiple receive GPIO pins, conflict detection is performed on the multiple transmit GPIO pins to obtain conflict detection results; If the collision detection result indicates that some of the transmit GPIO pins among the multiple transmit GPIO pins are in conflict, a collision indication message is sent to the bit switch corresponding to the partial transmit GPIO pin, so as to turn off the bit switch corresponding to the partial transmit GPIO pin based on the collision indication message.

2. The method according to claim 1, characterized in that, The method employs multiple receive GPIO pins to receive data from multiple second services transmitted from the outputs of multiple bus transceivers, including: Using multiple receive GPIO pins, data of multiple second services sent by the output terminals of multiple bus transceivers are received according to the operating frequency, delay and service priority corresponding to the types of multiple second services.

3. The method according to claim 1, characterized in that, The step of using multiple target transmit GPIO pins to send multiple data points of the first service to the input terminals of multiple bus transceivers includes: Using multiple target transmit GPIO pins, data of multiple first services are transmitted to the input terminals of multiple bus transceivers according to the operating frequency, delay, and service priority corresponding to the types of multiple first services.

4. The method according to claim 2 or 3, characterized in that, Service types include: hard real-time service type, high real-time service type, and ordinary real-time service type; Among them, the service priority of the hard real-time service type is higher than that of the high real-time service type; the service priority of the high real-time service type is higher than that of the ordinary real-time service type.

5. The method according to claim 1, characterized in that, The step of determining, among the plurality of transmit GPIO pins, multiple target transmit GPIO pins that do not conflict includes: Determine whether the multiple bit switches corresponding to the multiple transmit GPIO pins are turned on; If there is an unactivated bit switch among the multiple bit switches corresponding to the multiple transmit GPIO pins, then the transmit GPIO pin corresponding to the unactivated bit switch and the transmit function corresponding to the target bus transceiver connected to the communication are turned off. Among the remaining active bit switches, a plurality of target transmit GPIO pins are identified.

6. The method according to claim 5, characterized in that, After receiving data from multiple second services transmitted by the outputs of multiple bus transceivers using multiple receive GPIO pins, the method further includes: Determine whether the data of each of the second services is complete; If complete, an acknowledgment signal is sent to the multiple acknowledgment switches corresponding to the multiple sending GPIO pins.

7. The method according to claim 6, characterized in that, The step of using multiple target transmit GPIO pins to send multiple data points of the first service to the input terminals of multiple bus transceivers includes: If all bit switches corresponding to multiple target transmit GPIO pins are turned on, and all acknowledgment switches corresponding to multiple target transmit GPIO pins receive the acknowledgment signal, then multiple data of the first service are sent to the input terminals of multiple bus transceivers using multiple target transmit GPIO pins.

8. A communication device for a processor, characterized in that, The processor includes: multiple transmit input / output GPIO pins; the multiple transmit GPIO pins are respectively communicatively connected to the input terminals of multiple bus transceivers; the device includes: The acquisition module is used to acquire data from multiple primary business processes. The determining module is used to determine, among the plurality of transmit GPIO pins, a plurality of target transmit GPIO pins that do not conflict; The transmitting module is used to transmit multiple data of the first service to the input terminals of multiple bus transceivers using multiple target transmitting GPIO pins, so that the multiple bus transceivers transmit the multiple data of the first service to multiple external devices respectively; The processor further includes: multiple receive GPIO pins, each of which is communicatively connected to the receiving end of a multiple bus transceiver; the device further includes: The receiving module is used to receive data of multiple second services sent by the output terminals of multiple bus transceivers using multiple receiving GPIO pins; The receiving module is specifically configured to perform conflict detection on the multiple transmitting GPIO pins based on the data of the multiple first services transmitted by the multiple transmitting GPIO pins and the data of the multiple second services transmitted by the multiple receiving GPIO pins, and obtain a conflict detection result; if the conflict detection result indicates that some of the multiple transmitting GPIO pins are in conflict, a conflict indication message is sent to the bit switch corresponding to the partial transmitting GPIO pins, so as to close the bit switch corresponding to the partial transmitting GPIO pins based on the conflict indication message.

9. An electronic device, characterized in that, include: A memory and a processor, the memory storing a computer program executable by the processor, wherein the processor, when executing the computer program, implements the communication method of the processor according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when read and executed, implements the communication method of the processor according to any one of claims 1-7.

Images