Storage device supporting multiple hosts and quickly establishing links and electronic system

Abstract

A storage device and an electronic system that support a plurality of hosts and quickly establish a link are provided. The storage device includes: a memory configured to store first protocol data and first link data corresponding to a first host; and a switch connected to the memory and configured to read the first protocol data from the memory based on second protocol data received from the first host, and perform link connection processing with the first host by using first link data based on the first protocol data matching the second protocol data.

Description

Technical Field

[0001] The present disclosure relates to a storage device and an electronic system that supports multiple hosts and quickly establishes links. Background Art

[0002] Semiconductor devices include interfaces for sending and receiving data to and from other semiconductor devices, and these interfaces can be implemented according to a variety of specifications. For example, among interfaces for connecting semiconductor devices to each other, high-speed PCI (PCI Express, PCIe) interfaces have been applied to a variety of fields of high-speed data transmission. The PCIe interface is an interface in the form of serial transmission, and is defined by the PCIe specification, and provides a bidirectional connection that can send and receive data simultaneously.

[0003] In this manner, in order for semiconductor devices to exchange data with each other through an interface, it may be necessary to perform processes such as establishing a link at a physical layer of the interface and selecting parameter values ​​that can be set at the physical layer. Summary of the invention

[0004] One or more embodiments provide a storage device and an electronic system that support multiple hosts and quickly establish links.

[0005] According to one aspect of the embodiment, a storage device includes: a memory configured to store first protocol data and first link data corresponding to a first host; and a switch connected to the memory and configured to: read the first protocol data from the memory based on second protocol data received from the first host, and perform link-up processing with the first host by using the first link data matched with the second protocol data based on the first protocol data.

[0006] According to another aspect of the embodiment, a storage device includes: a non-volatile memory configured to store first protocol data and first link data corresponding to a first host in a switch area; a switch connected to the first host and configured to determine whether the first protocol data and the second protocol data match based on second protocol data received from the first host, and based on determining that the first protocol data and the second protocol data match, perform link connection processing to establish a link with the first host by using the first link data; and a controller configured to receive a packet from the first host through the link, and perform data operations on the non-volatile memory based on the packet.

[0007] According to another aspect of the embodiment, an electronic system includes: a plurality of hosts; a memory configured to store link data corresponding to at least one of the plurality of hosts; a switch configured to establish a link with the at least one host based on the link data and to receive commands and data from the at least one host when the link is established; and a storage device configured to perform data operations based on the commands and the data storage. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects and features will become more apparent from the following description of embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 is a schematic block diagram of an electronic system according to an embodiment.

[0010] Figure 2 is a schematic block diagram of an electronic system according to an embodiment.

[0011] Figure 3 is a block diagram illustrating the operation of an electronic system including a semiconductor device according to an embodiment.

[0012] Figure 4 is a simplified diagram of a link training and status state machine (LTSSM) included in a semiconductor device according to an embodiment.

[0013] Figure 5 is a simplified diagram of an LTSSM included in a semiconductor device according to an embodiment.

[0014] Figure 6 and Figure 7 is a diagram for illustrating the operation of a system including a semiconductor device according to an embodiment.

[0015] Figure 8 is a block diagram of a storage device according to an embodiment.

[0016] Fig. 9 is a flow chart of a link connection method of a switch according to an embodiment.

[0017] Fig.10 is a flow chart of a host monitoring method of a switch according to an embodiment.

[0018] Fig.11 is a block diagram of a storage device according to an embodiment.

[0019] Fig.12 is a block diagram of a storage device according to an embodiment.

[0020] Fig.13 is a schematic block diagram of an electronic system according to an embodiment.

[0021] Fig.14is a block diagram of a computing system according to an embodiment.

[0022] Fig.15 is a block diagram of a vehicle system according to an embodiment. DETAILED DESCRIPTION

[0023] Embodiments will be described more fully below with reference to the accompanying drawings. Each embodiment provided in the following description does not exclude association with one or more features of another example or another embodiment that is also provided herein or is not provided herein but is consistent with the present disclosure. In the following detailed description, certain embodiments are shown and described only by way of example. As will be appreciated by those skilled in the art, the described embodiments may be modified in a variety of different ways, all of which do not depart from the spirit or scope of the present invention.

[0024] Therefore, the drawings and description are considered to be illustrative and not restrictive in nature. Throughout the specification, the same reference numerals represent the same elements. In the method described with reference to the drawings, the order of operations may be changed, several operations may be combined, some operations may be separated, and specific operations may not be performed.

[0025] In addition, unless an explicit expression such as "one" or "single" is used, an expression written in the singular may be understood as the singular or the plural. Terms including common numbers (such as first and second) are used to describe various constituent elements, but these constituent elements are not limited by these terms. These terms may be used to distinguish one component from another.

[0026] Figure 1 is a schematic block diagram of an electronic system according to an embodiment.

[0027] refer to Figure 1 According to an embodiment, the electronic system 10 includes a plurality of hosts 50 and a storage device 300. The plurality of hosts 50 include a first host 100 to an nth host 200, where n may be an integer greater than 1. The plurality of hosts 50 may be connected to the storage device 300, and may read data from the storage device 300, erase data from the storage device 300, or write data to the storage device 300. The plurality of hosts 50 may be implemented as a central processing unit (CPU), an application processor (AP), a system on chip (SoC), etc. In some embodiments, the electronic system 10 may be provided in a vehicle to form an electronic system. For example, the plurality of hosts 50 may be an electronic control unit (ECU) that controls various functions related to vehicle operation.

[0028] The storage device 300 may be implemented as various types of storage devices, such as a solid state drive (SSD), an embedded multimedia card (eMMC), universal flash storage (UFS), compact flash (CF), secure digital (SD), micro secure digital (Micro-SD), mini secure digital (Mini-SD), extreme digital (xD), or a memory stick.

[0029] In an embodiment, when the storage device 300 is an SSD, the storage device 300 may be a device that complies with the high-speed non-volatile memory (Non-Volatile Memory express, NVMe) standard. When the storage device 300 is an embedded memory or an external memory, the storage device 300 may be a device that complies with the UFS standard or the eMMC standard. Multiple hosts 50 and storage devices 300 may each generate and send packets according to the adopted standard protocol.

[0030] In some embodiments, multiple hosts 50 and storage devices 300 may use a high-speed peripheral component interconnect (PCIe) interface protocol. The PCIe interface protocol is a serial transmission type interface established by the Peripheral Component Interconnect Special Interest Group (PCI-SIG) and provides a bidirectional connection that allows data to be sent and received simultaneously. The bidirectional connection includes a simplex transmission path and a simplex reception path. In order to emphasize this structure, the bidirectional connection model adopted by the PCIe interface protocol is sometimes referred to as a dual-simplex connection model.

[0031] The storage device 300 can send and receive data by using the PCIe interface protocol. In this case, the transmission path and the receiving path along which the data travel are defined as a link, and the link may include one or more pairs of transmission paths and receiving paths. In addition, the paired transmission paths and receiving paths are defined as channels, and the number of channels forming a link is defined as the link width. The storage device 300 can establish a link at the physical layer of the PCIe interface protocol to send and receive data. For ease of description, multiple hosts 50 and storage devices 300 are described as utilizing the PCIe interface protocol, but the embodiment is not necessarily limited thereto, and multiple hosts 50 and storage devices 300 can be implemented using various interface protocols. For example, multiple hosts 50 and storage devices 300 can use interface protocols such as serial advanced technology attachment (SATA), fast SATA (SATAe), serial attached small computer system interface (SCSI), fast non-volatile memory (NVMe), advanced host controller interface (AHCI) or multimedia card (MMC).

[0032] The storage device 300 may perform a link connection process to establish links with the plurality of hosts 50. The storage device 300 according to an embodiment may include a switch 310 and a memory 320.

[0033] The switch 310 can perform link connection processing for multiple hosts 50. The link connection processing can include signal integrity (SI) training. The switch 310 includes a link training and status state machine (LTSSM) that represents various states of the link when performing the link connection processing. The LTSSM can determine the link width, data rate, voltage level and conversion rate of the signal carrying data, the number of data channels, channel number, channel polarity, and the boundary between consecutive bits.

[0034] When the switch 310 completes the link connection process to establish links with multiple hosts 50, the protocol data and link data of the multiple hosts 50 may be stored in the memory 320. The protocol data may include data for identifying the multiple hosts 50. For example, the protocol data may include identifiers (IDs), port numbers, version information, etc. of the multiple hosts 50. The link data is a parameter set in the link connection process, and may include a preset value set by the LTSSM in the recovery state during the link connection process. The preset value may include different coefficient values, voltage ratio values, etc., for the transmission equalizer to implement pre-shooting and de-emphasis. For example, the switch 310 may store the first protocol data and the first link data of the first host 100 in the memory 320, and store the second protocol data and the second link data of the nth host 200 in the memory 320. In some embodiments, the switch 310 may record the data to the memory 320 in a single-layer cell (SLC) scheme. In some embodiments, the switch 310 may record the data to the memory 320 in a multi-layer cell (MLC) scheme. The MLC scheme may also include a triple-layer cell (TLC) scheme, a quad-layer cell (QLC) scheme, and the like.

[0035] The memory 320 may be implemented with a non-volatile memory. For example, the memory 320 may be implemented with a NAND flash memory, a vertical NAND (VNAND), a NOR flash memory, a resistive random access memory (RRAM), a phase change random access memory (PRAM), a conductive bridge RAM (CBRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), or a spin transfer torque random access memory (STT-RAM). The memory 320 may store protocol data and link data even when power is off.

[0036] When a plurality of hosts 50 are connected, the switch 310 may check whether protocol data is stored in the memory 320. For example, when the switch is powered on and a plurality of hosts 50 are connected, the switch 310 may check whether protocol data is stored in the memory 320. When protocol data is stored in the memory 320, the switch 310 may determine whether the protocol data in the memory 320 matches the protocol data of the plurality of hosts 50. In an embodiment, when connected to a plurality of hosts 50, the switch 310 may receive protocol data from the plurality of hosts 50. In an embodiment, when the switch 310 is connected to a plurality of hosts 50, the switch 310 may request protocol data from the plurality of hosts 50 and receive protocol data in response to the request.

[0037] When the protocol data in the memory 320 matches the protocol data of the plurality of hosts 50, the switch 310 can perform link connection processing with the plurality of hosts 50 by using the link data associated with the matching protocol data in the memory 320. By allowing the switch 310 to use the link data stored in the memory 320, the LTSSM can omit setting a recovery state, thereby allowing the plurality of hosts 50 and the storage device 300 to quickly establish a link. When the protocol data is not stored in the memory 320, or when the protocol data in the memory 320 does not match the protocol data of the plurality of hosts 50, the switch 310 can perform the link connection processing from the beginning (i.e., can set a recovery state).

[0038] Figure 2 is a schematic block diagram of an electronic system according to an embodiment.

[0039] refer to Figure 2 , the electronic system 20 according to the embodiment may include a host 110 and a storage device 400. Figure 2 In the figure, one host 110 is shown to illustrate a configuration in which the storage device 400 establishes a link with the host 110 in the electronic system 20, but the embodiment is not necessarily limited thereto, and the electronic system 20 may further include one or more additional hosts.

[0040] The host 110 may control the storage device 400 to store data in the storage device 400, or read data stored in the storage device 400. The host 110 may be one of a central processing unit (CPU), an application processor (AP), a system on chip (SoC), an electronic control unit (ECU), etc.

[0041] The host 110 may include a first interface (IF) 111A connected to the storage device 400, a second interface (IF) 111B connected to other components, a core 112 and a memory (MEM) 113 for performing calculations. According to an embodiment, the host 110 may include two or more cores 112, and the memory 113 may include a cache memory within the host 110, etc. According to one embodiment, the host 110 may also include an accelerator to perform calculations. For example, the accelerator may perform AI data calculations, etc. The host 110 may be further connected to other devices by using the second interface 111B. In some embodiments, the electronic system 20 may also include components such as sensors, graphics processing units, and network cards, and the host 110 may communicate with these components through the second interface 111B.

[0042] The storage device 400 may include an interface (IF) 401, a switch (switch) 410, a first memory (MEM1) 420, a controller (CTRL) 430, and a second memory (MEM2) 440. Figure 1 The description of the switch 310 and the memory 320 may also be applied to Figure 2 4 and the first memory 420. That is, the first memory 420 may store the first protocol data and link data of the host 110. When the host 110 is connected, the switch 410 may determine whether the data (i.e., the protocol data and the link data) is stored in the first memory 420. When the protocol data is not stored in the first memory 420, the switch 410 may perform a link connection process to establish a link with the host 110. When the switch 410 completes the link connection process and establishes a link with the host 110, the switch 410 may store the link data in the first memory 420.

[0043] When the host 110 is connected and the second protocol data and the link data are stored in the first memory 420, the switch 410 may determine whether the second protocol data in the first memory 420 matches the first protocol data in the host 110. When the first protocol data matches the second protocol data, the switch 410 may establish a link with the host 110 based on the link data in the first memory 420. When the first protocol data does not match the second protocol data, the switch 410 may perform a link connection process. The first memory 420 and the second memory 440 may be non-volatile memories. In some embodiments, the first memory 420 and the second memory 440 may be implemented as a single memory.

[0044] The switch 410 may periodically obtain protocol data from the host 110. In an embodiment, the switch 410 may periodically send an identification command to the host 110, and receive protocol data from the host 110 in response to the identification command. In an embodiment, the host 110 may periodically send protocol data to the switch 410.

[0045] The switch 410 may determine whether the protocol data of the host 110 has been updated. For example, the switch 410 may receive the third protocol data from the host 110, and the switch 410 may determine whether the second protocol data of the first memory 420 matches the third protocol data received from the host 110. When the second protocol data matches the third protocol data, the switch 410 may determine that the protocol data has not been updated. When the second protocol data does not match the third protocol data, the switch 410 may determine that the protocol data has been updated. When the protocol data has been updated, the switch 410 may reconfigure the link. At this point, the switch 410 may perform the link connection process again based on the third protocol data to obtain new link data. For example, the protocol data may change according to the number and type of devices connected to the host 110, the version of the host 110, etc. In some embodiments, when the external temperature of the electronic system 20, the temperature of the host 110, the temperature of the storage device 400, or the amount of power provided to the electronic system 20 changes, the switch 410 may reestablish the link. The switch 410 may store new link data based on the reconfigured link in the first memory 420.

[0046] The controller 430 operates by receiving a control command from the host 110 through the interface 401, and may receive data and store the received data in the second memory 440, or may retrieve data stored in the second memory 440 and output the data to the host 110. The control command may include address information, and the controller 430 may store data in at least one of the plurality of memory chips included in the second memory 440, or read data from at least one of the plurality of memory chips, by referring to the address information.

[0047] In an embodiment, the first interface 111A of the host 110 and the interface 401 of the storage device 400 can exchange data with each other through the PCIe interface protocol. In order to exchange data with each other, when the electronic system 20 is powered on and the host 110 and the storage device 400 are powered on, a link connection process can be performed to configure the link between the interfaces 111A and 401. In the link connection process, the data rate, the voltage level and conversion rate of the signal for transmitting data, the number and polarity of the data channels, the number of channels, etc. can be determined. The determined data rate, the determined voltage level and conversion rate of the signal for sending data, the determined number and polarity of the data channels, the determined number of channels, etc. can be used for communication between the host 110 and the storage device 400 via the link. Although the interfaces 111A and 401 are described as using the PCIe interface protocol, the embodiment is not necessarily limited thereto, and SATA, SATAe, SAS, NVMe, AHCI or MMC can be used. In an embodiment, the electronic system 20 may also include a host other than the host 110, and the storage device 400 may communicate with other hosts through the interface 401.

[0048] In an embodiment, when the electronic system 20 further includes other components connected via the second interface 111B of the host 110, the host 110 and the components may also be connected via the reference interface 111B. Figure 2 The link connection process described establishes a link.

[0049] Figure 3 is a block diagram illustrating the operation of an electronic system including a semiconductor device according to an embodiment.

[0050] refer to Figure 3 , the electronic system 30 according to the embodiment may include a first semiconductor device 500 and a second semiconductor device 600. The first semiconductor device 500 and the second semiconductor device 600 may exchange data according to the PCIe interface protocol. In an embodiment, the first semiconductor device 500 may be a storage device, and the second semiconductor device 600 may be a host, such as an electronic control unit (ECU), but the embodiment is not necessarily limited thereto. The electronic system 30 may include a plurality of hosts, and the first semiconductor device 500 may be connected to and communicate with the plurality of hosts.

[0051] like Figure 3 As shown, the PCIe architecture may include a plurality of logically distinct layers 510 to 540 and 610 to 640. For example, the PCIe architecture may include software layers 510 and 610, transaction layers 520 and 620, link layers 530 and 630, and physical layers 540 and 640.

[0052] Among the layers included in the PCIe architecture, the physical layers 540 and 640 may be the lowest layers, and packets generated by the link layers 530 and 630 may be serially transmitted between the first semiconductor device 500 and the second semiconductor device 600. The physical layers 540 and 640 provide a link formed by a transmitter TX and a receiver RX of the first semiconductor device 500 and the second semiconductor device 600, respectively, and packets may be transmitted between the first semiconductor device 500 and the second semiconductor device 600 through the link.

[0053] The link layers 530 and 630 correspond to a higher layer of the physical layers 540 and 640, and can provide functions of ensuring the reliability of packet transmission on the link and managing the link. For example, the link layers 530 and 630 can add sequence number information, link cyclic redundancy check (LCRC) information, etc. to the packets generated by the transaction layers 520 and 620.

[0054] The transaction layers 520 and 620 may receive a read or write request from the software layers 510 and 610, generate a request packet, and transmit the generated request packet to the link layers 530 and 630. In addition, the transaction layers 520 and 620 may receive a response packet from the link layers 530 and 630, and match the received response packet with the request received from the software layers 510 and 610. The transaction layers 520 and 620 may transmit a packet including header information and end-to-end cyclic redundancy check (ECRC) information to the link layers 530 and 630.

[0055] Software layers 510 and 610 are top layers that are not defined by the PCIe specification. For example, software layers 510 and 610 may include software that drives semiconductor devices 500 and 600 including a PCIe interface protocol, or software that receives data read or write requests from a user or host application and provides responses to the received requests to the user or host application.

[0056] More specific details regarding the physical layers 540 and 640, the link layers 530 and 630, and the transaction layers 520 and 620 may be understood with reference to the PCIe specification.

[0057] The physical layer 540 of the first semiconductor device 500 may include an LTSSM 550. Similarly, the physical layer 640 of the second semiconductor device 600 may also include an LTSSM 650. In an embodiment, the first semiconductor device 500 may include a switch that manages routing of packets of a plurality of hosts (including the second semiconductor device 600), and the switch may store the LTSSM. In an embodiment, the second semiconductor device 600 may store the LTSSM in a PCIe controller, but is not necessarily limited to this form.

[0058] Referring to the first semiconductor device 500 as an example, the LTSSM 550 may include a detection state, a polling state, a configuration state, a recovery state, an L0 state, an L0s state, an L1 state, an L2 state, a hot reset state, a loopback state, and a disabled state. The LTSSM 550 transitions through 11 states, and may perform a plurality of processes to send data according to the PCIe interface protocol. The definition of each of the 11 states included in the LTSSM 550 is also provided in the PCIe specification, and the LTSSM 550 may be implemented to comply with the definition of the LTSSM provided in the PCIe specification. Similarly, the description of the LTSSM 550 is also applicable to the LTSSM 650.

[0059] In an embodiment, at least one of the LTSSM 550 of the first semiconductor device 500 and the LTSSM 650 of the second semiconductor device 600 may perform a link connection process to establish a link for the first semiconductor device 500 and the second semiconductor device 600 to exchange data with each other. As described above, a path for data to be transmitted between the first semiconductor device 500 and the second semiconductor device 600 may be defined as a link LINK. The link LINK includes one or more pairs of a transmission path and a reception path, wherein a pair of the transmission path and the reception path may be defined as a "channel". In addition, the number of lanes constituting one link may be defined as a "link width".

[0060] In order to establish a link LINK between the first semiconductor device 500 and the second semiconductor device 600, at least one of the LTSSM 550 of the first semiconductor device 500 and the LTSSM 650 of the second semiconductor device 600 can perform link number negotiation and channel number negotiation to determine whether the channel is working normally, select a channel for data transmission to establish a link, and determine the link width.

[0061] When the connection is completed, the first semiconductor device 500 and the second semiconductor device 600 can exchange data with each other. As mentioned above, in addition to the actual data to be transmitted, the data packets exchanged between the physical layers 540 and 640 may also include header information, ECRC information, sequence number information, LCRC information, etc.

[0062] In addition, when the link connection is completed, the first semiconductor device 500 may store link data used in the link connection in the memory. For example, the first semiconductor device 500 may store link data associated with the protocol data of the second semiconductor device 500. When the first semiconductor device 500 is disconnected from the second semiconductor device 600 and then reconnected, the first semiconductor device 500 may be quickly connected to the second semiconductor device 600 by using the link data stored in the memory. When the protocol data of the second semiconductor device 600 has not changed, the first semiconductor device 500 may use the link data stored in the memory. Therefore, the electronic system 30 can achieve fast link establishment of the first semiconductor device 500 and the second semiconductor device 600.

[0063] Figure 4 and Figure 5 is a simplified diagram of a LTSSM included in a semiconductor device according to an embodiment.

[0064] exist Figure 4 and Figure 5 Prior to the operations shown, it may be determined whether the protocol data received from the host corresponds to the protocol data stored in the memory. If the protocol data received from the host does not match the protocol data stored in the memory, or if the protocol data is not stored in the memory, performing Figure 4 The operations shown in the figure can be performed to configure and initialize the link by performing a link connection process. If the protocol data received from the host matches the protocol data stored in the memory, the link connection process can be performed by using the link data stored in association with the matching protocol data. At this point, the link data stored in association with the matching protocol data can be reused to perform a link establishment process to configure and initialize the link.

[0065] Reference Figure 4 The semiconductor device may compare the first protocol data received from the host with the second protocol data stored in the memory. The determination that the first protocol data received from the host matches the second protocol data stored in the memory may be performed. Figure 5 The operations shown. LTSSM can provide link connection processing, which is the control process of configuring and initializing the link as mentioned above. In addition to configuring and initializing the link on the PCIe interface, LTSSM can also support data packet transmission, recovery from link errors, and restarting the PCIe interface in a low power state.

[0066] For example, the LTSSM may pass through 11 states (S100 to S110) and perform the above functions. The LTSSM may enter the detection state S100, in which the circuit of the physical layer is initialized, or in which the LTSSM detects the presence of another external device connected to the PCIe interface in response to a command received from the link layer. For example, the LTSSM may enter the detection state S100 according to the instruction of the switch in the semiconductor device. When the protocol data is not stored in the memory connected to the switch, or when the protocol data of the host does not match the protocol data of the memory, the switch may instruct the LTSSM to perform link connection processing. The LTSSM may move from the detection state S100 to the polling state S101, detect the receiver associated with the transmitter and set the bit lock, symbol lock, channel polarity, etc. For example, when the LTSSM switches from the detection state S100 to the polling state S101, the channel where the receiver is not detected may enter the electrical idle state.

[0067] When the LTSSM moves to the configuration state S102, the data rate, lane number, link width, etc. can be set. After the operation in the configuration state S102 is completed, the LTSSM can enter the L0 state S103, which is a normal operation state for exchanging data on the established link. Depending on the operation of the PCIe interface, the LTSSM can enter the L0s state S104 as an electrical idle / standby state, the L1 state S105 as a low power standby / sleep state, or the L2 state S106 as a shutdown state.

[0068] In addition, when an error occurs while operating in the L0 state S103, the LTSSM can enter the recovery state S107. In addition, in order to return to the L0 state S103 from the L1 state S105, the LTSSM can move to the recovery state S107. In the recovery state S107, the LTSSM can perform functions such as bit lock, symbol lock, and channel-to-channel deskew, or change the link rate based on data such as a training sequence exchanged by the transmitter and the receiver. For example, in the recovery state S107, the LTSSM has sub-states such as Recovery.RcvrLock, Recovery.Equalization, Recovery.Speed, Recovery.RcvrCfg, and Recovery.Idle, and can enter the detection state S100, the configuration state S102, the L0 state S103, the loopback state S108, the hot reset state S109, or the disabled state S110 depending on the results in the sub-states. The LTSSM can optimize equalization by exchanging training sequences with the receiver in the substate of Recovery.Equalization. In Recovery.Equalization, the LTSSM can set a preset and complete equalization while sequentially changing the phase from phase 0 to phase 3. Each stage from phase 0 to phase 3 can represent an equalization process. For example, the LTSSM can change the phase to increase the operating speed to the desired speed. The speed corresponding to phase 0 to phase 3 can be stored in the memory as link data.

[0069] Loopback state S108 is a state for testing, where the LTSSM can enter loopback state S108 based on the value of the loopback bit in a predetermined ordered symbol set exchanged by a device connected to the PCIe interface. In loopback state S108, the receiver can retransmit all received packets identically.

[0070] In the warm reset state S109, the LTSSM may perform the function of resetting the link. In the disabled state S110, when the receiver is in a low impedance state, the LTSSM may switch the transmitter to an electrical idle state.

[0071] In the link connection process of configuring the link, the LTSSM moves between 11 states (S100 to S110) in a predetermined order to perform the above functions. When the link connection is successful, the states actually executed by the LTSSM in states S100 to S110 are until the link connection is successful, and the execution order of the states can be stored in a memory or the like as a reference order. That is, the link data stored by the memory may include a reference order. When the switch reestablishes the link, the switch can verify the link connection process based on the stored reference order. For example, the switch can determine whether the state sequence (state sequence) executed by the LTSSM matches the reference sequence until the link connection is completed. When the state sequence executed by the LTSSM matches the reference sequence, the switch can determine that the verification is successful, and when the state sequence executed by the LTSSM does not match the reference sequence, the switch can determine that the verification fails. When the verification fails, the switch may change the link parameters and perform the link connection process again. When the link connection is successful, the switch can store the link parameters as link data in the memory.

[0072] Figure 5 is a simplified diagram of an LTSSM included in a semiconductor device according to an embodiment. The semiconductor device may compare first protocol data received from a host with second protocol data stored in a memory. The determination that the first protocol data received from the host matches the second protocol data stored in the memory may be performed. Figure 5 The operation shown.

[0073] Reference Figure 5 According to an embodiment, a semiconductor device (eg, a storage device) may include a switch and a memory connected to the switch. The switch may include an LTSSM. Figure 1 The description of the switch 310 and the memory 320 also applies to the description of the switch and the memory.

[0074] The semiconductor device may be connected to a host (e.g., an electronic control unit (ECU)). When the semiconductor device is connected to the host, the semiconductor device may receive first protocol data from the host. When the switch receives the first protocol data, the switch may determine whether to store the data in a memory. The memory may store second protocol data of the host and link data stored through a previous link connection process.

[0075] When the first protocol data matches the second protocol data, the switch can perform a link connection process by using the link data associated with the matched protocol data. For example, the switch can instruct the LTSSM to perform a link connection process, and the LTSSM can establish a link by moving between states in the order of the detection state S100, the polling state S101, the configuration state S102, and the L0 state S103 using the link data associated with the matched protocol data. The link data stored in the memory includes a preset value set in the recovery state S107 of the previous link connection process, and the LTSSM that performs the link connection process using the link data can complete the link connection without entering the recovery state S107. Therefore, compared with the related link connection process of establishing a link by going through the recovery state S107, the semiconductor device according to the embodiment can bypass the recovery state S107, thereby reducing the time consumed to establish a link.

[0076] When the memory does not store the protocol data, the switch can instruct the LTSSM to perform the link connection process. In addition, when the first protocol data does not match the second protocol data, the switch can instruct the LTSSM to perform the link connection process even if the memory has stored the data. Based on the instruction from the switch, the LTSSM can perform the following operations: Figure 4 At this point, the LTSSM performs the link connection process without link data, so the LTSSM can enter the recovery state S107.

[0077] Figure 6 and Figure 7 is a diagram for illustrating the operation of an electronic system including a semiconductor device according to an embodiment.

[0078] refer to Figure 6 and Figure 7 , the electronic system 40 according to the embodiment may include a first semiconductor device 710 and a second semiconductor device 720. The first semiconductor device 710 may include a first transmitter TX1 and a first receiver RX1, and the second semiconductor device 720 may include a second transmitter TX2 and a second receiver RX2. In an embodiment, the first semiconductor device 710 may be a storage device, and the second semiconductor device 720 may be a host such as an electronic control unit (ECU), but the embodiment is not necessarily limited thereto. The electronic system 40 may include a plurality of hosts, and the first semiconductor device 710 may be connected to and communicate with the plurality of hosts.

[0079] The first data signal DATA0 may be transmitted via a first transmission path between a first transmission port 711 connected to the first transmitter TX1 and a second reception port 721 connected to the second receiver RX2. The second data signal DATA1 may be transmitted via a second transmission path between a second transmission port 722 connected to the second transmitter TX2 and a first reception port 712 connected to the first receiver RX1. The first transmission path and the second transmission path are included in one channel and may provide a path for transmitting a pair of differential signals, such as Figure 6 and Figure 7 shown.

[0080] Each of the first data signal DATA0 and the second data signal DATA1 may have a value such as Figure 6 and Figure 7 For example, the amplitudes ΔV1 and ΔV2 determined by the maximum voltage level and the minimum voltage level of the first data signal DATA0 and the second data signal DATA1, the conversion rate indicating the voltage increase / decrease rate of the first data signal DATA0 and the second data signal DATA1, etc. are shown in FIG. Figure 6 and Figure 7 It can be different.

[0081] This may be because the link data established by the LTSSM of at least one of the first semiconductor device 710 and the second semiconductor device 720 when the link connection process is completed is Figure 6 and Figure 7 When another component of the electronic system 40 is newly connected, when the version of the driving system of at least one of the first semiconductor device 710 and the second semiconductor device 720 is updated, when the temperature is outside a predetermined range, when a predetermined amount of time has passed, or when power is blocked and newly applied, at least one of the first semiconductor device 710 and the second semiconductor device 720 may re-perform the link connection process to re-establish the link.

[0082] Therefore, at least one of the first semiconductor device 710 and the second semiconductor device 720 may store different link data at different time points through the reestablished link. In addition, due to the different link data, at least one of the data signals DATA0 and DATA1 transmitted on the same channel may have different waveforms (such as Figure 6 and Figure 7 shown).

[0083] Figure 8 is a block diagram of a storage device according to an embodiment, Fig. 9 is a flow chart of a link connection method of a switch according to an embodiment.

[0084] Reference Figure 8According to the embodiment, the storage device 800 may be connected to a plurality of hosts and perform link connection processing with each host. The storage device 800 may include a switch 810, a first non-volatile memory (NVM1) 820, a controller 830, a volatile memory (VM) 840, and a second non-volatile memory (NVM2) 850. Figure 1 The contents described for the switch 310 and the memory 320 are also applicable to the switch 810 and the first nonvolatile memory 820. That is, when the storage device 800 is connected to the host, the switch 810 can perform a link connection process based on the data in the first nonvolatile memory 820.

[0085] Reference Figure 8 and Fig. 9 , the switch 810 may receive the first protocol data PTCL_DATA1 from the host (S910). For example, when the storage device 800 is powered on and the storage device 800 and the host are connected, the host may send the first protocol data PTCL_DATA1 to the storage device 800. In an embodiment, the host may detect the connection and send the first protocol data PTCL_DATA1. In an embodiment, the storage device 800 may request the host for protocol data when connected to the host, and the host may send the first protocol data PTCL_DATA1 in response to the request.

[0086] When the switch 810 receives the first protocol data PTCL_DATA1, the switch 810 may determine whether the first nonvolatile memory 820 has stored data (S920). The first nonvolatile memory 820 may be a dedicated memory of the switch 810 connected to the switch 810. When the first nonvolatile memory 820 stores protocol data, the data may include protocol data of the host stored by the switch 810 and link data for linking to the host. The protocol data may include data for identifying the host. The link data may include parameters set in the link connection process.

[0087] When the first nonvolatile memory 820 has stored the data, the switch 810 may obtain the second protocol data PTCL_DATA2 from the first nonvolatile memory 820 (S930). The switch 810 may read the second protocol data PTCL_DATA2 from the first nonvolatile memory 820.

[0088] The switch 810 may determine whether the first protocol data PTCL_DATA1 matches the second protocol data PTCL_DATA2 (S940). When the state of the host has not changed, the first protocol data PTCL_DATA1 and the second protocol data PTCL_DATA2 may be the same. The state of the host may vary depending on the version, temperature, power size, etc. of the driving system. When the state changes, the switch 810 may output the changed protocol data.

[0089] When the first protocol data PTCL_DATA1 and the second protocol data PTCL_DATA2 match, the switch 810 may perform a link connection process (S950) by using the first link data LINK_DATA1 of the first nonvolatile memory 820. The first link data LINK_DATA1 may be data corresponding to the second protocol data PTCL_DATA2. The first link data LINK_DATA1 includes a preset value set in a recovery state in the link connection process, so that the switch 810 may establish a link between the storage device 800 and the host without going through a recovery state. Therefore, the storage device 800 may reduce the time consumed to establish a link.

[0090] When the first nonvolatile memory 820 does not store data, the switch 810 may perform a link connection process (S960). When the first protocol data PTCL_DATA1 and the second protocol data PTCL_DATA2 do not match, the switch 810 may perform a link connection process (S960) even if the first nonvolatile memory 820 stores data. The switch 810 may perform a link connection process (S960) by using a reference Figure 4 The switch 810 performs the link connection process without link data (e.g., preset value), so that the switch 810 can enter the recovery state even when the first nonvolatile memory 820 does not store data or when the first protocol data PTCL_DATA1 and the second protocol data PTCL_DATA2 do not match.

[0091] When the link is completed, the switch 810 may store the link parameters used in the link connection process in the first nonvolatile memory 820 as the second link data LINK_DATA2 (S970). When the host is reconnected, the switch 810 may then perform the link connection process by using the second link data LINK_DATA2. For example, when the storage device 800 is powered off and then powered on and connected to the host, the switch 810 may perform the link connection process. When the switch 810 completes the link with the host, the host may send a data-related request to the storage device 800.

[0092] Refer again Figure 8, the controller 830 may access the second non-volatile memory 850 in response to requests from a plurality of hosts. The controller 830 may be configured to provide an interface between the second non-volatile memory 850 and the plurality of hosts. In addition, the controller 830 may be configured to drive firmware for controlling the second non-volatile memory 850.

[0093] The controller 830 may control the operation of the second nonvolatile memory 850. Specifically, the controller 830 may provide at least one of an address, a command, data, a control signal, or power along an input / output line connected to the second nonvolatile memory 850. The controller 830 may record data into the second nonvolatile memory 850, erase data in the second nonvolatile memory 850, or read data from the second nonvolatile memory 850 by using at least one of the address, command, control signal, and power. The control signal may include a chip enable, a lamp enable, a pin enable, and the like.

[0094] The volatile memory 840 may act as a buffer memory to mitigate the speed difference between the second nonvolatile memory 850 as a data storage space and the host as an external device of the storage device 800. The volatile memory 840 included in the storage device 800 may also operate as a kind of cache memory and may also provide a space for temporarily storing data in a control operation on the second nonvolatile memory 850. The controller 830 may further include a memory controller for controlling the volatile memory 840.

[0095] The volatile memory 840 may be a dynamic random access memory (DRAM) or a static random access memory (SRAM). For example, the volatile memory 840 may be implemented using a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), etc.

[0096] The second nonvolatile memory 850 may include a plurality of memory chips 850_1 to 850_m (where m is an integer greater than 1). The second nonvolatile memory 850 may record, erase, or output data based on the control of the controller 830. The storage device 800 may transmit or receive data to or from the host through a link.

[0097] In some embodiments, the switch 810 and the controller 830 may include security logic (i.e., security circuit) to perform encryption. For example, the switch 810 may include a first security logic, and the controller 830 may include a second security logic. The first security logic of the switch 810 may perform encryption on the data of the host to generate first encrypted data. The switch 810 may output the first encrypted data to the controller 830. The second security logic of the controller 830 may perform encryption on the first encrypted data to generate second encrypted data. The controller 830 may output the second encrypted data to the second non-volatile memory 850. The second non-volatile memory 850 may store the second encrypted data.

[0098] In some embodiments, the switch 810 may include compression logic (ie, compression circuit) to compress data. The controller 830 may record the data compressed by the compression logic to the second non-volatile memory 850.

[0099] Fig.10 is a flow chart of a host monitoring method of a switch according to an embodiment.

[0100] Reference Figure 8 and Fig.10 According to an embodiment, the switch 810 may monitor the connected host (S1010). The switch 810 and the host may establish a link and exchange data through a link connection process. In an embodiment, the switch 810 may send an identification signal to the host. For example, the switch 810 may periodically send the identification signal.

[0101] The switch 810 may receive the protocol data PTCL_DATA from the host (S1020). In some embodiments, even when the host does not receive the identification signal, the host may periodically send the protocol data PTCL_DATA to the storage device 800. The protocol data PTCL_DATA may include data to identify the host.

[0102] When receiving the protocol data PTCL_DATA, the switch 810 may determine whether the protocol data PTCL_DATA is new data (S1030). For example, when the host connected to the storage device 800 is a new host that has never been connected before, or when the host has a changed state, the protocol data PTCL_DATA may include new data. The switch 810 may read the data stored in the first non-volatile memory 820. When none of the data stored in the first non-volatile memory 820 matches the protocol data PTCL_DATA, the switch 810 may determine that the protocol data PTCL_DATA is new data. When any data stored in the first non-volatile memory 820 matches the protocol data PTCL_DATA, the switch 810 may determine that the protocol data PTCL_DATA is not new data. When the protocol data PTCL_DATA is not new data, the switch 810 may continue to monitor the host (S1010).

[0103] When the protocol data PTCL_DATA is new data, the switch 810 may perform a link connection process (S1040). The switch 810 may perform a link connection process (S1040) by using Figure 4 Because the switch 810 performs the link connection process without link data (such as a preset value), the switch 810 can enter the recovery state.

[0104] When the link connection is completed, the switch 810 may store the link parameters used in the link connection process as the link data LINK_DATA in the first nonvolatile memory 820 (S1050). Subsequently, when the host is connected again, the switch 810 may perform the link connection process by using the link data LINK_DATA. For example, when the storage device 800 is powered off and then powered on and connected to the host, the switch 810 may perform the link connection process.

[0105] When the switch 810 completes the link connection with the host, the host may send a data-related request to the storage device 800 .

[0106] Fig.11 is a block diagram of a storage device according to an embodiment.

[0107] Reference Fig.11 The storage device 1100 according to the embodiment may be connected to a plurality of hosts and perform link connection processing with each host. The storage device 1100 may include a switch 1110, a first nonvolatile memory (NVM1) 1120, a controller 1130, a volatile memory (VM) 1140, and a second nonvolatile memory (NVM2) 1150. Figure 8The description of the switch 810, the first nonvolatile memory 820, the controller 830, the volatile memory 840, and the second nonvolatile memory 850 may also be applied to the description of the switch 1110, the first nonvolatile memory 1120, the controller 1130, the volatile memory 1140, and the second nonvolatile memory 1150. For this reason, redundant descriptions will be omitted.

[0108] The storage device 1100 can communicate with an external device through the first port 1101 and the second port 1102. For example, the first port 1101 can be a port that supports communication with multiple hosts. The first port 1101 can use an interface protocol, such as PCIe, SATA, SATAe, SAS (SA-SCSI), NVMe, AHCI, or MMC. The switch 1110 can receive protocol data from multiple hosts through the first port 1101. The switch 1110 can perform link connection processing through the first port 1101 based on the protocol data of the multiple hosts and the data in the first non-volatile memory 1120. In this case, when the first non-volatile memory 1120 does not store the protocol data of the host to which the link is to be established, the switch 1110 can perform the following steps: Figure 4 The link connection process shown.

[0109] When the link connection is completed, the switch 1110 can communicate with the plurality of hosts based on the established link width, data rate, etc. For example, the switch 1110 can transmit data received from the controller 1130 to any host among the plurality of hosts through the first port 1101. The switch 1110 can receive data of the plurality of hosts through the first port 1101 and transmit the received data to the controller 1130. The controller 1130 can process the data of the plurality of hosts.

[0110] The second port 1102 may be a port that supports communication with a debugging device. For example, the second port 1102 may be a port that supports a debugging interface. The debugging interface may use methods such as the Joint Test Action Group (JTAG) or Serial Wire Debug (SWD). The controller 1130 may receive debugging data through the second port 1102. The controller 1130 may perform debugging of the storage device 1100 based on the debugging data. In some embodiments, the storage device 1100 may further include an authentication device for authenticating the debugging device. The authentication device may receive authentication data of the debugging device through the second port 1102, and may verify the authentication data. When the authentication data is successfully verified, the authentication device may output the debugging data to the controller 1130.

[0111] In some embodiments, the authentication device may be integrated into the controller 1130 .

[0112] In some embodiments, in addition to the first port 1101 and the second port 1102 , the storage device 1100 may further include at least one port for communicating with another external device.

[0113] Fig.12 is a block diagram of a storage device according to an embodiment.

[0114] Reference Fig.12 , the storage device 1200 according to the embodiment may be connected to a plurality of hosts and perform a link connection process with each host. The storage device 1200 may include a switch 1210, a controller 1220, a volatile memory (VM) 1230, and a non-volatile memory (NVM) 1240. The non-volatile memory 1240 may include a plurality of memory chips 1240_1 to 1240_k (where k is an integer greater than 1). In the non-volatile memory 1240, the first memory chip 1240_1 may include a switch area 1241. The switch area 1241 may be a non-defective area formed by normal memory cells in the first memory chip 1240_1. The controller 1220 may determine the switch area 1241 in the non-volatile memory 1240 and allocate the switch area 1241 as a dedicated area of ​​the switch 1210. When establishing a link with the host, the switch 1210 may perform a link connection process and store the protocol data and link data of the host in the switch area 1241. In some embodiments, the switch 1210 may record data to the switch area 1241 in an SLC manner.

[0115] When the storage device 1200 is connected to the host, the switch 1210 may perform a link connection process based on the data in the switch area 1241. When the storage device 1200 is connected to the host, the switch 1210 may determine whether data (i.e., protocol data and link data) is stored in the switch area 1241. When no protocol data is stored in the switch area 1241, the switch 1210 may perform the following steps: Figure 4 The link connection process shown.

[0116] The switch 1210 may receive first protocol data from a connected host. The switch 1210 may determine whether the switch area 1241 stores data corresponding to the first protocol data. For example, the switch 1210 may read the second protocol data in the switch area 1241. When the first protocol data and the second protocol data match, the switch 1210 may perform link connection processing based on the link data in the switch area 1241. The switch area 1241 may store link data corresponding to the second protocol data. When the first protocol data and the second protocol data do not match, the switch 1210 may perform the following steps: Figure 4The switch 1210 can establish links between the storage device 1200 and multiple hosts through the link connection process.

[0117] When the link is established, the switch 1210 may send the host's request and data to the controller 1220. The controller 1220 may access the non-volatile memory 1240 in response to requests from a plurality of hosts. The controller 1220 may be configured to provide an interface between the non-volatile memory 1240 and a plurality of hosts. In addition, the controller 1220 may be configured to drive firmware for controlling the non-volatile memory 1240.

[0118] The controller 1220 may control the operation of the nonvolatile memory 1240. Specifically, the controller 1220 may provide at least one of an address, a command, data, a control signal, or power along an input / output line connected to the nonvolatile memory 1240. The controller 1220 may record data into the nonvolatile memory 1240, erase data from the nonvolatile memory 1240, or read data from the nonvolatile memory 1240 by using at least one of the address, command, control signal, and power. The control signal may include a chip enable, a lamp enable, a pin enable, and the like. In some embodiments, the controller 1220 may record data into a data area other than the switch area 1241 in the nonvolatile memory 1240. In some embodiments, the controller 1220 may record data into the data area in an MLC manner.

[0119] The volatile memory 1230 may act as a buffer memory to mitigate the speed difference between the nonvolatile memory 1240 as a data storage space and a host as an external device of the storage device 1200. The volatile memory 1230 included in the storage device 1200 may also operate as a kind of cache memory and may also provide a space for temporarily storing data in a control operation on the nonvolatile memory 1240. The controller 1220 may also include a memory controller for controlling the volatile memory 1230.

[0120] The volatile memory 1230 may be a dynamic random access memory (DRAM) or a static random access memory (SRAM). For example, the volatile memory 1230 may be implemented using DDR SDRAM, LPDDR SDRAM, GDDR SDRAM, RDRAM, etc.

[0121] The nonvolatile memory 1240 may record, erase, or output data based on the control of the switch 1210 or the controller 1220. The storage device 1200 may transmit or receive data to or from a host through a link.

[0122] Fig.13 is a schematic block diagram of an electronic system according to an embodiment.

[0123] refer to Fig.13 According to an embodiment, the electronic system 90 includes a plurality of hosts 910, a switch 913, a memory 914, and a storage device 915. The plurality of hosts 910 include a first host 911 to an nth host 912, where n may be an integer greater than 1. The plurality of hosts 910 may be connected to the storage device 915 through the switch 913. The plurality of hosts 910 may read data from the storage device 915, erase data from the storage device 915, or record data to the storage device 915. The plurality of hosts 910 may be implemented with a central processing unit (CPU), an application processor (AP), a system on chip (SoC), and the like. In some embodiments, the electronic system 90 may be provided in a vehicle to form an electronic system. For example, the plurality of hosts 910 may be an electronic control unit (ECU) that controls various functions related to vehicle operation.

[0124] The switch 913 may establish a link between a plurality of hosts 910 and a storage device 915. When a plurality of hosts 910 and a storage device 915 are connected, the switch 913 may establish a link by using data stored in the memory 914. The memory 914 may be implemented with a non-volatile memory. For example, the memory 914 may be implemented with a NAND flash memory, a vertical NAND flash memory (VNAND), a NOR flash memory, a resistive RAM (RRAM), a phase change RAM (PRAM), a conductive bridge RAM (CBRAM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FRAM), or a spin transfer magnetization reversal RAM (STT-RAM). In this regard, the memory 914 may retain data even when power is off.

[0125] The memory 914 may store protocol data and link data from the plurality of hosts 910. The protocol data is data for identifying the plurality of hosts 910, which may include identifiers (IDs), port numbers, version information, etc. of the plurality of hosts 910. The link data is a parameter set in the link connection process, which may include a preset value set by the LTSSM in the recovery state in the link connection process. The switch 913 includes the LTSSM, which indicates various states of the link when performing the link connection process, and may determine the link width, data rate, voltage level and conversion rate of a signal for transmitting data, the number of data channels, the number of channels, the polarity of channels, the boundary between consecutive bits, etc. according to the LTSSM.

[0126] In some embodiments, the memory 914 may store protocol data and link data of some hosts among the plurality of hosts 910. For example, the memory 914 may store first protocol data and first link data of the first host 911, but not protocol data and link data of the nth host 912.

[0127] When the switch 913 is connected to the first host 911, the switch 913 may receive the second protocol data from the first host 911. The switch 913 may determine whether the first protocol data and the second protocol data match. When the first protocol data and the second protocol data match, the switch 913 may establish a link with the first host 911 by using the first link data. By using the first link data, the switch 913 may omit the recovery state of the link connection process, which may allow a fast link to be established. When the first protocol data and the second protocol data do not match, the switch 913 may perform the link connection process without using the first link data. Because the switch 913 does not use the first link data, the switch 913 may enter the recovery state and perform an equalization operation, etc. When the switch 913 establishes a link by performing a new link connection process, the switch 913 may record the second protocol data of the first host 911 and the second link data of the established link in the memory 914.

[0128] When connected to the nth host 912, the switch 913 may receive the third protocol data from the nth host 912. The switch 913 may read the data stored in the memory 914 and determine that the memory 914 does not store data matching the third protocol data. The switch 913 may perform a new link connection process with the nth host 912. The switch 913 may establish a link with the nth host 912 and record the third protocol data and the third link data of the established link in the memory 914. In some embodiments, the switch 913 may record the data to the memory 914 in an SLC manner.

[0129] The storage device 915 may be implemented with various types of storage devices such as a solid state drive (SSD), an embedded multimedia card (eMMC), a universal flash memory (UFS), CF, SD, micro SD, mini SD, xD, or a memory stick.

[0130] In an embodiment, when the storage device 915 is an SSD, the storage device 915 may be a device that complies with the NVMe standard. When the storage device 915 is an embedded memory or an external memory, the storage device 915 may be a device that complies with the UFS standard or the eMMC standard. Multiple hosts 910 and storage devices 915 may each generate a packet according to the adopted standard protocol and send the generated packet.

[0131] In some embodiments, multiple hosts 910, switches 913, and storage devices 915 may use PCIe interface protocols. PCIe interface protocols provide bidirectional connections. In some embodiments, multiple hosts 910, switches 913, and storage devices 915 may use various interface protocols, such as SATA, SATAe, SA-SCSI (SAS), NVMe, AHCI, or MMC.

[0132] Fig.14 is a block diagram illustrating a computing system according to an embodiment.

[0133] Reference now Fig.14 , the computing system 2000 may be implemented by a PC, a data server, a laptop computer, an automotive electronic component, or a portable device. The portable device may be implemented by a mobile phone, a smart phone, a tablet PC, a wearable device, a PDA, an EDA, a digital camera, a digital video camera, a PMP, a PND, a handheld game console, or an e-book. In addition, the computing system 2000 may be implemented by a system on a chip (SoC).

[0134] The computing system 2000 may include a host 2100 and a storage device 2200. The host 2100 may communicate with the storage device 2200 through various interfaces. The host 2100 may request data processing operations, such as data read operations, data write (record, program) operations, and data erase operations, from the storage device 2200. For example, the host 2100 may be a CPU, a GPU, a microprocessor, an AP, an ECU, etc.

[0135] The host 2100 may include a host controller 2110 and a host memory 2120. The host memory 2120 may be used as a buffer memory for temporarily storing data to be transmitted to or from the storage device 2200.

[0136] The storage device 2200 may include a storage controller 2210 and a non-volatile memory (NVM) 2220. The storage device 2200 may include a storage medium for storing data in response to a request from the host 2100. For example, the storage device 2200 may be implemented in various types such as SSD, eMMC, UFS, CF, SD, micro SD, mini SD, xD, or a memory stick.

[0137] When the storage device 2200 is an SSD, the storage device 2200 may be a device that complies with the NVMe standard. When the storage device 2200 is an embedded memory or an external memory, the storage device 2200 may be a device that complies with the UFS standard or the eMMC standard. The host 2100 and the storage device 2200 may each generate a packet according to the adopted standard protocol and send the generated packet.

[0138] When the non-volatile memory 2220 of the storage device 2200 includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D NAND memory array. As another example, the storage device 2200 may include various other types of non-volatile memories. For example, various other types of memories, such as MRAM, STT-RAM, CBRAM, FRAM, PRAM, and RRAM, may be applied to the storage device 2200.

[0139] In some embodiments, the host controller 2110 and the host memory 2120 may be implemented on separate semiconductor chips. Alternatively, in some embodiments, the host controller 2110 and the host memory 2120 may be integrated on the same semiconductor chip. In one example, the host controller 2110 may be any one of a plurality of modules provided in the AP, and the AP may be implemented with a SoC. In addition, the host memory 2120 may be an embedded memory provided within the AP, or may be a non-volatile memory or memory module placed outside the AP.

[0140] The host controller 2110 may manage an operation of storing data of the buffer (eg, program data) in the nonvolatile memory 2220 or storing data of the nonvolatile memory 2220 (eg, read data) in the buffer.

[0141] The storage controller 2210 may include a switch (SW) 2201, a memory (MEM) 2202, a host interface 2211, a memory interface 2212, and a CPU 2213. The storage controller 2210 may also include a flash translation layer (FTL) 2214, a packet manager 2215, a buffer memory 2216, an error correction code (ECC) engine 2217, and an advanced encryption standard (AES) engine 2218.

[0142] The memory controller 2210 may further include a working memory into which the FTL 2214 is loaded, and execution of the FTL 2214 by the CPU 2213 may result in data programming operations and reading operations on the nonvolatile memory being controlled.

[0143] Reference Figure 1The contents of the described switch 310 and memory 320 are also applicable to the switch 2201 and memory 2202. That is, when the switch 2201 receives protocol data from the host 2100, the switch 2201 can determine whether the memory 2202 stores data matching the protocol data. When the memory 2202 stores data matching the protocol data, the switch 2201 can read link data corresponding to the protocol data from the memory 2202. The switch 2201 can perform a link connection process with the host 2100 by using the link data associated with the matching protocol data. When the memory 2202 does not store data matching the protocol data, the switch 2201 can perform a link connection process without the link data. When the switch 2201 establishes a link with the host 2100, the switch 2201 can record the link data in the memory 2202. In some embodiments, at least one of the switch 2201 and the memory 2202 can be implemented as being set outside the storage controller 2210.

[0144] The host interface 2211 may transmit and receive packets to and from the host 2100. The packet transmitted from the host 2100 to the host interface 2211 may include a command or data to be programmed into the nonvolatile memory 2220, and the packet transmitted from the host interface 2211 to the host 2100 may include a response to a command or data read from the nonvolatile memory 2220.

[0145] The memory interface 2212 may transmit data to be programmed into the nonvolatile memory 2220 or receive data read from the nonvolatile memory 2220. The memory interface 2212 may be implemented to comply with a standard protocol such as a switching or open NAND flash interface (ONFI).

[0146] The FTL 2214 may perform various functions such as address mapping, wear leveling, and garbage collection. The address mapping operation is an operation of changing a logical address received from a host into a physical address for actually storing data in the nonvolatile memory 2220. Wear leveling is a technique for ensuring that blocks within the nonvolatile memory 2220 are uniformly used to prevent excessive degradation of a particular block, which may be achieved, for example, by a firmware technique that balances the erase counts of physical blocks. Garbage collection is a technique for ensuring available capacity within the nonvolatile memory 2220 by copying valid data of a block into a new block and then erasing the old block.

[0147] The packet manager 2215 may generate a packet according to an interface protocol negotiated with the host 2100, or may parse various information in a packet received from the host 2100. In addition, the buffer memory 2216 may temporarily store data to be programmed into the nonvolatile memory 2220 or data to be read from the nonvolatile memory 2220. The buffer memory 2216 may be configured within the memory controller 2210, but may also be provided outside the memory controller 2210.

[0148] The ECC engine 2217 may perform an error detection and correction function on read data read from the nonvolatile memory 2220. More specifically, the ECC engine 2217 may generate parity bits for write data to be written to the nonvolatile memory 2220, and the generated parity bits may be stored in the nonvolatile memory 2220 together with the program data. When data is read from the nonvolatile memory 2220, the ECC engine 2217 may correct errors in the read data by using the parity bits read from the nonvolatile memory 2220 together with the read data, and output the error-corrected read data.

[0149] The AES engine 2218 may perform at least one of an encryption operation and a decryption operation on data input to the storage controller 2210 by using a symmetric key algorithm.

[0150] Fig.15 is a block diagram showing a vehicle system according to an embodiment.

[0151] refer to Fig.15 , the vehicle system 3000 according to the embodiment includes a server 3100 and a vehicle 3200. The server 3100 may communicate with the vehicle 3200. The vehicle 3200 may include a plurality of electronic control units (ECUs) 3210 and a storage device (ie, storage) 3220. The vehicle 3200 may also include a sensor 3230, a drive unit 3240, an input unit 3250, and a connection control unit (CCU) 3260.

[0152] The plurality of electronic control units 3210 may include first to fth electronic control units 3211 to 3213. Each of the plurality of electronic control units 3210 is electrically, mechanically, and communicatively connected to at least one of a plurality of devices provided in the vehicle 3200, and may control the operation of the at least one device based on any one function execution command.

[0153] Here, the plurality of devices may include a storage device 3220, a sensor 3230, a driving unit 3240, an input unit 3250, a connection control unit 3260, etc. The sensor 3230 may include an image sensor for acquiring an image required to perform at least one function, a temperature sensor for detecting the temperature inside or outside the vehicle, an environmental sensor for measuring air quality, etc. The image sensor may correspond to an automobile sensor including a unit pixel.

[0154] The drive unit 3240 may include fans and compressors in air conditioning equipment, fans in ventilation equipment, engines and motors in power units, motors in steering units, motors and valves in brake units, and opening and closing devices in doors or tailgates.

[0155] The plurality of electronic control units 3210 may communicate with the sensor 3230 and the driving unit 3240 by using at least one of, for example, Ethernet, low voltage differential signaling (LVDS) communication, local interconnect network (LIN) communication, and controller area network (CAN) communication.

[0156] Multiple electronic control units 3210 can determine whether it is necessary to perform a function based on information obtained through the storage device 3220, and when it is determined that it is necessary to perform the function, multiple electronic control units 3210 control the operation of the drive unit 3240 that performs the corresponding function, but control the operation amount based on the obtained information.

[0157] The storage device 3220 can be referenced Figures 1 to 12 . That is, the storage device 3220 may include a switch and a memory. The memory may store protocol data and link data. When the storage device 3220 is connected to multiple electronic control units 3210, the storage device 3220 may receive protocol data from the multiple electronic control units 3210. For example, the switch may receive first protocol data from the first electronic control unit 3211. When the memory stores the first protocol data, the switch may perform a link connection process with the first electronic control unit 3211 by using first link data corresponding to the first protocol data. When the memory does not store the first protocol data, the switch may perform a link connection process with the first electronic control unit 3211 and record the second link data of the established link to the memory. In some embodiments, the switch and the memory may be disposed outside the storage device 3220 (such as Fig.13 shown).

[0158] Multiple electronic control units 3210 can control the operation of the drive unit 3240 that performs the corresponding function based on the function execution command input through the input unit 3250, and can also check the setting quantity corresponding to the information input through the input unit 3250, and control the operation of the drive unit 3240 that performs the corresponding function based on the checked setting quantity.

[0159] Each of the plurality of electronic control units 3210 may independently control the function of any one device, or may control the function of any one device together with other electronic control units.

[0160] For example, when the distance to the obstacle detected by the distance detector is within a threshold distance, the electronic control unit of the collision avoidance device may cause the speaker to emit a warning sound of collision with the obstacle.

[0161] Combined with the electronic control unit of the terminal for the vehicle, the electronic control unit of the image acquisition unit and the electronic control unit of the anti-collision device, the electronic control unit of the automatic driving control unit can receive navigation information, road image information and distance information from obstacles, and control the power equipment, equipment and steering equipment to perform automatic driving by using the received information.

[0162] A connectivity control unit (CCU) 3260 is electrically, mechanically, and communicatively connected to each of the plurality of electronic control units 3210 , and communicates with each of the plurality of electronic control units 3210 .

[0163] In this regard, the connectivity control unit 3260 may directly communicate with a plurality of electronic control units 3210 disposed inside the vehicle, communicate with an external server, and communicate with an external terminal through an interface.

[0164] Here, the connectivity control unit 3260 may communicate with the plurality of electronic control units 3210 and may communicate with the server 3100 by using RF communication having one or more antennas.

[0165] In addition, the connection control unit 3260 may communicate with the server 3100 via wireless communication. In this case, the wireless communication between the connection control unit 3260 and the server 3100 may be implemented by various wireless communication methods, such as a wireless fidelity (WiFi) module and a wireless broadband module, as well as a global system for mobile communications (GSM), code division multiple access (CDMA), wideband code division multiple access (WCDMA), universal mobile telecommunications system (UMTS), time division multiple access (TDMA), and long term evolution (LTE).

[0166] In some embodiments, reference Figures 1 to 15Each component described or a combination of two or more components may be implemented as a digital circuit, a programmable or non-programmable logic device or array, an application specific integrated circuit (ASIC), and the like.

[0167] While various aspects of the embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device that supports multiple hosts and quickly establishes links, comprising: A memory configured to store first protocol data and first link data corresponding to the first host; as well as Switches, connected to storage, and configured as: reading the first protocol data from the memory based on the second protocol data received from the first host, and Based on the first protocol data matching the second protocol data, a link connection process with the first host is performed by using the first link data.

2. The storage device according to claim 1, wherein: The switch is further configured to determine whether the first protocol data is stored in the memory based on the second protocol data received from the first host, and compare the second protocol data with the first protocol data based on determining that the first protocol data is stored in the memory.

3. The storage device according to claim 1, wherein: The first link data indicates a preset value set in a previous link connection process, and The switch is further configured to perform link connection processing by using the preset value.

4. The storage device according to claim 3, wherein: The first link data indicates a reference order of states of link connection processing, and The switch is further configured to determine whether a state sequence performed in the link connection process matches a reference sequence.

5. The storage device according to claim 4, wherein: The switch is further configured to re-execute the link connection process when the link connection process is performed based on the state sequence not matching the reference sequence.

6. The storage device according to claim 1, wherein: The switch is also configured to: Sending an identification signal to the first host, determining whether the first protocol data and the third protocol data match based on the third protocol data received from the first host in response to the identification signal, and Based on a determination that the first protocol data and the third protocol data do not match, the link connection process is re-executed.

7. The storage device according to claim 6, wherein: The switch is further configured to obtain second link data based on the link reestablished with the first host and record the second link data in the memory.

8. The storage device according to claim 1, further comprising: a controller configured to control data operations based on a request from a first host; as well as A nonvolatile memory configured to store, erase, or output data based on the control of a controller.

9. The storage device according to claim 8, wherein: The switch is further configured to send a command of the first host to the controller when the link connection with the first host is completed, and The controller is further configured to control the non-volatile memory based on the command.

10. The storage device according to claim 1, wherein: The switch is also configured to: performing a link connection process without the first link data based on the first protocol data and the second protocol data not matching, and Upon completion of the link connection with the first host, second link data and second protocol data of the established link are stored in the memory.

11. The storage device according to claim 10, wherein: The switch is also configured to store the second link data and the second protocol data in the memory in a single layer unit (SLC) manner.

12. The storage device according to claim 1, wherein: The memory is further configured to store second link data and third protocol data corresponding to the second host, and The switch is further configured to perform link connection processing with the second host based on the third protocol data and the second link data.

13. The storage device according to claim 12, wherein: The switch is further configured to read third protocol data from the memory based on fourth protocol data received from the second host, and based on matching the third protocol data with the fourth protocol data, read second link data and perform link connection processing with the second host by using the second link data.

14. A storage device that supports multiple hosts and quickly establishes links, comprising: a non-volatile memory configured to store first protocol data and first link data corresponding to a first host in a switch region; a switch connected to the first host and configured to determine whether the first protocol data and the second protocol data match based on the second protocol data received from the first host, and to perform a link connection process to establish a link with the first host by using the first link data based on the determination that the first protocol data and the second protocol data match; as well as The controller is configured to receive a packet from a first host via a link and perform a data operation on a non-volatile memory based on the packet.

15. The storage device according to claim 14, wherein: The switch is further configured to perform a link connection process to obtain the second link data based on the determination that the first protocol data and the second protocol data do not match, and record the second protocol data and the second link data in the switch area.

16. The storage device according to claim 15, wherein: The second protocol data and the second link data correspond to the second host, The nonvolatile memory is further configured to store the second link data and the third protocol data corresponding to the second host in the switch area, and The switch is further configured to perform link connection processing with the second host based on the third protocol data and the second link data based on the second host being connected.

17. The storage device according to claim 14, wherein: The controller is further configured to perform data operations on a data region other than the switch region in the nonvolatile memory.

18. The storage device according to claim 17, wherein: The controller is also configured to store the first protocol data and the first link data in the switch region in a single-layer cell (SLC) manner, and perform a data operation in the data region in a multi-layer cell (MLC) manner.

19. An electronic system that supports multiple hosts and quickly establishes links, comprising: Multiple hosts; a memory configured to store link data corresponding to at least one host among the plurality of hosts; a switch configured to establish a link with the at least one host based on the link data, and to receive commands and data from the at least one host when the link is established; as well as The storage device is configured to perform a data operation based on the command and the data.

20. The electronic system according to claim 19, wherein: The switch is further configured to perform a link connection process with a first host among the plurality of hosts based on the link data not including link data of the first host, and based on the link with the first host being established, store first link data of the established link in the memory.

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