Method, device and electronic device for determining gate resistance of a hybrid device

Abstract

Embodiments of the present application disclose a method, apparatus, and electronic device for determining the gate resistance of a hybrid device. The method includes: obtaining a parasitic parameter circuit model of the hybrid device according to the design model of the hybrid device; simulating the parasitic parameter circuit model to obtain a plurality of switching parameters corresponding to different gate resistances; fitting the plurality of switching parameters to obtain a fitness function and a screening condition function; iteratively optimizing the fitness function according to the screening condition function to obtain the target gate resistance corresponding to each power device; The present application comprehensively considers the influence of different gate resistances on the switching behavior of the power device, so that the obtained gate resistance value can minimize the switching loss of the hybrid device on the premise of ensuring the safe operation of the hybrid device.

Description

Technical Field

[0001] The present application relates to the technical field of parameter regulation; specifically, it relates to a method, device, and electronic device for determining the gate resistance of a hybrid device. Background Art

[0002] As a core device in power electronic converters, power semiconductor devices have currently been widely used in fields such as new energy system inverters, battery management, electric drive systems, and frequency converters. The Si IGBT-SiC MOSFET hybrid device can combine the high current-carrying capacity of IGBT and the high-frequency and high-efficiency characteristics of SiC MOSFET to achieve the complementary advantages of the two devices. At the same time, compared with IGBT devices, it has lower switching losses, and compared with the all-SiC solution, it has lower costs, and can achieve a compromise between performance and cost.

[0003] The gate resistance regulates the charging and discharging rate of the gate capacitance by changing the magnitude of the gate drive current, thereby affecting the change rate of the gate voltage and the switching speed of the power device; a larger gate resistance will reduce the switching speed and increase the switching loss; an overly small gate resistance value will reduce the damping coefficient of the gate drive loop and easily cause gate voltage oscillation and overshoot; therefore, selecting an appropriate gate resistance is crucial for optimizing the switching characteristics of power devices, improving efficiency, and ensuring device reliability.

[0004] However, the hybrid device involves both IGBT and SiC MOSFET at the same time, and the gate resistances of both will affect the switching behavior of the hybrid device. When the traditional method of determining the gate resistance through physical testing is applied to the hybrid device, it is not only time-consuming, laborious, and costly, but also difficult to obtain the gate resistance value that can achieve the minimum switching loss while ensuring the safe operation of the hybrid device.

[0005] Therefore, how to optimize the gate resistance on the premise of the safe operation of the hybrid device is an urgent problem to be solved currently. Summary of the Invention

[0006] To solve the above technical problems, the embodiments of the present application provide a method, device, and electronic device for determining the gate resistance of a hybrid device. The present application comprehensively considers the influence of different gate resistances on the switching behavior of power devices, so that the obtained gate resistance value can ensure the minimization of the switching loss of the hybrid device on the premise of the safe operation of the hybrid device.

[0007] According to one aspect of the embodiments of the present application, a method for determining the gate resistance of a hybrid device, the hybrid device including at least one first power device and at least one second power device, the method comprising: obtaining a parasitic parameter circuit model of the hybrid device according to the design model of the hybrid device; simulating the parasitic parameter circuit model to obtain a plurality of switching parameters corresponding to different gate resistances; fitting the plurality of switching parameters to obtain a fitness function and a screening condition function; and iteratively optimizing the fitness function according to the screening condition function to obtain the target gate resistance corresponding to each power device.

[0008] Optionally, obtaining a parasitic parameter circuit model of the hybrid device according to the design model of the hybrid device includes: performing three-dimensional layout design according to the circuit topology diagram of the hybrid device to obtain a design model of the hybrid device; importing the design model into simulation software and setting the material properties corresponding to each device in the simulation software; performing mesh division according to the positions of the power terminals and signal terminals of the hybrid device and the electrode positions of each power device to obtain a plurality of meshes with different functions; setting the current flow direction in each mesh according to the actual current direction of the driving loop and the commutation loop; running the simulation software to obtain a parasitic parameter matrix; and generating a parasitic parameter circuit model of the hybrid device according to the parasitic parameter matrix.

[0009] Optionally, based on the parasitic parameter circuit model, performing simulation to obtain a plurality of switching parameters corresponding to different gate resistances includes: importing the parasitic parameter circuit model and the power device model into circuit simulation software to build a double-pulse simulation circuit; setting simulation parameters for the double-pulse simulation circuit according to actual test conditions, and simulating the switching process of the hybrid device at different gate resistances; and extracting a plurality of switching parameters corresponding to different gate resistances.

[0010] Optionally, fitting the plurality of switching parameters to obtain a fitness function and a screening condition function includes: fitting the plurality of switching parameters corresponding to different gate resistances to obtain a fitting function for each switching parameter, and the specific expression is:

[0011]

[0012] where represents the gate resistance of the first power device, represents the gate resistance of the second power device, represents the fitting function of the kth switching parameter, k = 1, 2, ……, K; K represents the total number of switching parameters; represents the coefficient of the polynomial, and respectively represent the highest values of i and j; use the fitting function corresponding to the total turn-on loss of the hybrid device, the total turn-off loss of the hybrid device, or the total switching loss of the hybrid device as the fitness function; use the fitting function corresponding to the peak turn-on current of the first power device, the peak turn-on current of the second power device, the peak turn-off current of the first power device, the peak turn-off current of the second power device, and the peak turn-off voltage of the hybrid device as the screening condition function.

[0013] Optionally, when different gate resistances are used in the turn-on process and the turn-off process of the power device, iteratively optimize the fitness function according to the screening condition function to obtain the target gate resistance corresponding to each power device, including: using the fitting function corresponding to the total turn-on loss of the hybrid device as the first fitness function, and iteratively optimizing the first fitness function according to the screening condition function to obtain the turn-on gate resistances corresponding to the first power device and the second power device respectively; using the fitting function corresponding to the total turn-off loss of the hybrid device as the second fitness function, and iteratively optimizing the second fitness function according to the screening condition function to obtain the turn-off gate resistances corresponding to the first power device and the second power device respectively.

[0014] Optionally, when the same gate resistance is used in the turn-on process and the turn-off process of the power device, iteratively optimize the fitness function according to the screening condition function to obtain the target gate resistance corresponding to each power device, including: using the fitting function corresponding to the total switching loss of the hybrid device as the third fitness function, and iteratively optimizing the third fitness function according to the screening condition function to obtain the target gate resistances corresponding to the first power device and the second power device respectively.

[0015] Optionally, iteratively optimize the fitness function according to the screening condition function to obtain the target gate resistance corresponding to each power device, including: generating an individual population according to the first gate resistance and the second gate resistance; wherein, the first gate resistance corresponds to the gate resistance of the first power device, and the second gate resistance corresponds to the gate resistance of the second power device; calculating the screening condition function value corresponding to each individual in the individual population according to the screening condition function; judging whether the screening condition function value corresponding to each individual satisfies the constraint condition; using the fitness function value corresponding to the individual that satisfies the constraint condition as the fitness value of the individual; when the current iteration meets the termination criterion, using the first gate resistance and the second gate resistance corresponding to the minimum fitness function value as the target gate resistance of the first power device and the target gate resistance of the second power device respectively; wherein, the termination criterion includes that the change value of the fitness value in continuous N iterations is less than the preset function tolerance, or the maximum number of iterations is reached.

[0016] Optionally, the method further includes: setting the fitness value of an individual that does not meet the constraint condition to a preset value; when the current iteration does not meet the termination criterion, selecting new individuals for the next iteration according to the fitness value corresponding to each individual; performing crossover and genetic mutation on the new individuals to generate a new population of individuals; and performing cyclic iteration on the new population of individuals until the termination criterion is met.

[0017] According to one aspect of the embodiments of the present application, there is provided a gate resistance determination device for a hybrid device, the device including: a circuit model acquisition module, configured to obtain a parasitic parameter circuit model of the hybrid device according to the design model of the hybrid device; a switch parameter acquisition module, configured to simulate the parasitic parameter circuit model to obtain a plurality of switch parameters corresponding to different gate resistances; a parameter fitting module, configured to fit the plurality of switch parameters to obtain a fitness function and a screening condition function; and an iterative optimization module, configured to iteratively optimize the fitness function according to the screening condition function to obtain the target gate resistance corresponding to each power device.

[0018] According to one aspect of the embodiments of the present application, there is provided a computer-readable medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the method for determining the gate resistance of a hybrid device as in the above technical solution.

[0019] According to one aspect of the embodiments of the present application, there is provided an electronic device, the electronic device including: a processor; and a memory, configured to store executable instructions of the processor; wherein, the processor is configured to execute the executable instructions to enable the electronic device to implement the method for determining the gate resistance of a hybrid device as in the above technical solution.

[0020] According to one aspect of the embodiments of the present application, there is provided a computer program product, including a computer program, and when the computer program is executed by a processor, it implements the method for determining the gate resistance of a hybrid device as in the above technical solution.

[0021] The technical solution provided by the present application has at least the following beneficial effects:

[0022] Based on the design model of the hybrid device, the parasitic parameter circuit model of the hybrid device is obtained; the parasitic parameter circuit model is simulated to obtain multiple switching parameters corresponding to different gate resistances; then the multiple switching parameters are fitted to obtain the fitness function for multi-objective optimization and the screening condition function to ensure the safe operation of the hybrid device; finally, the fitness function is iteratively optimized according to the screening condition function, so as to obtain the target gate resistance corresponding to each power device. Therefore, this application comprehensively considers the influence of different gate resistances on the switching behavior of the power device, so that the obtained gate resistance value can ensure the minimization of the switching loss of the hybrid device on the premise of ensuring the safe operation of the hybrid device. Description of the Drawings

[0023] The drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. In the drawings:

[0024] Figure 1 The figure shows a schematic flowchart of a method for determining the gate resistance of a hybrid device provided by an embodiment of the present application;

[0025] Figure 2 The figure shows a schematic circuit structure diagram of a hybrid device provided by an embodiment of the present application;

[0026] Figure 3 Shown as Figure 1 An exemplary flowchart of step S10 in

[0027] Figure 4 The figure shows a schematic design model diagram of a hybrid device provided by an embodiment of the present application;

[0028] Figure 5 The figure shows a schematic parasitic parameter circuit model diagram of a hybrid device provided by an embodiment of the present application;

[0029] Figure 6 Shown as Figure 1 An exemplary flowchart of step S20 in

[0030] Figure 7 The figure shows a schematic dual-pulse simulation circuit diagram of a hybrid device provided by an embodiment of the present application;

[0031] Figure 8 Shown as Figure 1 An exemplary flowchart of step S40 in

[0032] Figure 9The figure shows a schematic diagram of a multi-objective optimization process provided by an embodiment of the present application;

[0033] Figure 10 The figure shows another schematic diagram of a multi-objective optimization process provided by an embodiment of the present application;

[0034] Figure 11 The figure shows a schematic diagram of a circuit in which different gate resistors are used in the turn-on process and the turn-off process provided by an embodiment of the present application;

[0035] Figure 12 The figure shows a schematic diagram of the change of the fitness value with the number of iterations provided by an embodiment of the present application;

[0036] Figure 13 The figure shows a schematic diagram of the simulated switching waveform of a hybrid device under the target gate resistor provided by an embodiment of the present application;

[0037] Figure 14 The figure shows a schematic diagram of the measured switching waveform of a hybrid device under the target gate resistor provided by an embodiment of the present application;

[0038] Figure 15 The figure shows a schematic diagram of the structure of a device for determining the gate resistor of a hybrid device provided by an embodiment of the present application;

[0039] Figure 16 The figure shows a schematic diagram of the structure of a computer system of an electronic device suitable for implementing an embodiment of the present application. Detailed implementation manners

[0040] Here, an exemplary embodiment will be described in detail, and its examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0041] The block diagrams shown in the drawings are only functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0042] The flowcharts shown in the drawings are only exemplary descriptions and do not necessarily include all contents and operations / steps, nor do they necessarily execute in the described order. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined. Therefore, the actual execution order may be changed according to the actual situation.

[0043] It should also be noted that: "a plurality of" mentioned in this application means two or more. " / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0044] Figure 1 The figure shows a schematic flowchart of a method for determining the gate resistance of a hybrid device provided by an embodiment of the present application; as Figure 1 shown, the method specifically includes the following steps:

[0045] Step S10: Obtain the parasitic parameter circuit model of the hybrid device according to the design model of the hybrid device.

[0046] The hybrid device in this embodiment includes at least one first power device and at least one second power device. The first power device and the second power device have the same function but different characteristics. That is to say, both the first power device and the second power device have the same switching function, but their device types, process materials, process technologies, etc. are different. The first power device can be a SiC-MOSFET (SiC-Metal-Oxide-Semiconductor Field-Effect Transistor), and the second power device can be a Si-IGBT (Si-Insulated Gate Bipolar Transistor). Additionally, the first power device and the second power device can also be transistors of other materials. The specific types and quantities of the two power devices are not limited here, as long as the characteristics of the first power device and the second power device are different, they all belong to the scope of the hybrid device of the present application.

[0047] For example: Figure 2 The figure shows a schematic circuit structure diagram of a hybrid device provided by an embodiment of the present application, which is a half-bridge structure. Each bridge arm includes 1 Si IGBT chip, 1 SiC MOSFET chip, and 1 Si FRD chip. Among them, the SiC MOSFET has an anti-parallel parasitic diode due to its own structure; Figure 2The hybrid device therein includes four power devices, where T1 and T2 are Si-IGBTs, and M1 and M2 are SiC-MOSFETs. M1 and M2 can be used as the first power devices, and T1 and T2 can be used as the second power devices. Further, resistors R1, R2, R3, and R4 are the gate resistors of T1, T2, M1, and M2 respectively. The main purpose of this application is to determine the resistance values of resistors R1, R2, R3, and R4. It should be noted that the power devices in this application do not include diodes, that is, in Figure 2 the two diodes connected in parallel with T1 and T2 do not fall within the scope of the power devices of this application; in addition, Figure 2 the two diodes connected in parallel with M1 and M2 are integrated in M1 and M2,

[0048] In this embodiment, Figure 2 the circuit topology diagram therein includes two first power devices and two second power devices. The gate resistors of these 4 power devices can be determined by taking these 4 power devices as a hybrid device.

[0049] In addition, it should be noted that ideally, the characteristics of T1 and T2 chips are the same, and the characteristics of M1 and M2 chips are the same. However, due to the existence of parasitic parameters in the actual circuit, the influence of parasitic parameter differences may cause differences in the switching parameters of T1 and T2 and the switching parameters of M1 and M2. In order to optimize the performance of the upper bridge arm (T1 and M1) and the lower bridge arm (T2 and M2) respectively, the resistance values of R1 and R2 and the resistance values of R3 and R4 are not necessarily the same; since one of the devices in the upper bridge arm devices T1 and M1 and the lower bridge arm devices T2 and M2 is always in the off state during the double-pulse test, the gate resistor of the power device in this bridge arm will not affect the switching characteristics of the other bridge arm. In order to improve the evaluation efficiency of the gate resistor, the gate resistor of the power device in one of the bridge arms can be determined first, and then the gate resistor of the power device in the other bridge arm can be determined.

[0050] In the double-pulse test, one of the upper and lower bridge arms of the half-bridge circuit is always in the off state, which is called the accompanying device, and the other bridge arm performs switching actions, which is called the device under test. In one embodiment, if the upper bridge arm devices (T1 and M1) are the accompanying devices and the lower bridge arm devices are the devices under test (T2 and M2), that is, the gate resistors of T2 and M2 are determined in this test.

[0051] In one embodiment, as Figure 3 shown, according to the design model of the hybrid device, a parasitic parameter circuit model of the hybrid device is obtained, which specifically includes the following steps:

[0052] Step S11: Perform three-dimensional layout design according to the circuit topology diagram of the hybrid device to obtain the design model of the hybrid device.

[0053] It should be noted that Figure 2

[0053] is a circuit topology diagram of a hybrid device. In practical applications, a three-dimensional layout design needs to be carried out for the circuit topology diagram, that is, layout design is carried out according to the connection relationship between each component, and performance optimization is carried out from aspects such as electricity, heat, and force, to obtain a three-dimensional design model as Figure 4 shown.

[0054] Step S12: Import the design model into simulation software, and set the material properties corresponding to each device in the simulation software.

[0055] Specifically, import the three-dimensional design model into finite element simulation software, and set the material properties corresponding to each device. The material properties include but are not limited to conductivity, relative permittivity, etc.

[0056] Step S13: Perform mesh generation according to the positions of the power terminals and signal terminals of the hybrid device and the electrode positions of each power device to obtain multiple meshes with different functions.

[0057] It should be noted that the power terminals and signal terminals of this embodiment are different from the device electrodes. The power terminals and signal terminals refer to the input and output ends of the entire hybrid device; for example, the power terminals are Figure 2 P, U, N in Figure 4 which correspond to DC+, AC, DC- in

[0058] Specifically, performing mesh generation according to the positions of the power terminals and signal terminals of the hybrid device and the electrode positions of each power device is equivalent to performing mesh generation according to the connection relationship between conductors and between conductors and the chip, so as to form different meshes on the design model.

[0059] Step S14: Set the current flow direction in each mesh according to the actual current direction of the drive loop and commutation loop.

[0060] Specifically, set multiple current inflow points and outflow points according to the required circuit interface and the actual current direction in the module during double-pulse testing.

[0061] Step S15: Run the simulation software to obtain the parasitic parameter matrix.

[0062] Specifically, the parasitic parameter matrix includes parasitic parameter types and corresponding parasitic values. The parasitic parameter types include but are not limited to parasitic inductance, parasitic capacitance, and parasitic resistance; the parasitic parameter matrix can be solved by running the simulation software.

[0063] Step S16: Generate a parasitic parameter circuit model of the hybrid device according to the parasitic parameter matrix.

[0064] It should be noted that by outputting the parasitic parameter matrix as an equivalent circuit model and importing it into circuit simulation software, a parasitic parameter circuit model for circuit simulation can be obtained, as Figure 5 shown.

[0065] Step S20: Simulate the parasitic parameter circuit model to obtain multiple switching parameters corresponding to different gate resistances.

[0066] In one embodiment, as Figure 6 shown, simulating the parasitic parameter circuit model to obtain multiple switching parameters corresponding to different gate resistances specifically includes the following steps:

[0067] Step S21: Import the parasitic parameter circuit model and the power device model into circuit simulation software to build a double-pulse simulation circuit.

[0068] Specifically, import the parasitic parameter circuit model and the power device model into circuit simulation software to construct a double-pulse simulation circuit with a parasitic parameter model, as Figure 7 shown; in Figure 7 , HPD_HyS (i.e., U7) is the extracted parasitic parameter circuit model, U1 and U2 are the SPICE models of the SiC MOSFET chips, with junction temperature setting ports; U3 and U4 are the SPICE models of the IGBT chips, and U5 and U6 are the SPICE models of the FRD chips. In addition, Figure 7 also gives the drive circuits and bus models of the SiC MOSFET and IGBT, where is the external gate resistance of the MOSFET, is the external gate resistance of the IGBT, and L1, C1, and V1 are the load inductor, bus capacitor, and DC power supply respectively. During simulation, to control variables, the time TD_ON for the SiC MOSFET to turn on earlier than the IGBT and the time TD_OFF for it to turn off later are both set to 0.

[0069] The circuit simulation software in this embodiment includes but is not limited to LTSPICE software, Pspice software, and Simplorer software.

[0070] Step S22: Set the simulation parameters for the double-pulse simulation circuit according to the actual test conditions, and simulate the switching process of the hybrid device at different gate resistances.

[0071] Specifically, set appropriate simulation parameters according to the actual test conditions, and set the gate resistance of the IGBT and the gate resistance of the SiC MOSFET as variables and , then simulate to obtain different gate resistances and the switching waveforms of the hybrid device under different combinations.

[0072] Step S23: Extract multiple switching parameters corresponding to different gate resistances.

[0073] In this embodiment, the multiple switching parameters include the peak turn-on current of the first power device, the peak turn-on current of the second power device, the peak turn-off current of the first power device, the peak turn-off current of the second power device, the peak turn-off voltage of the hybrid device, the turn-on loss of the first power device, the turn-on loss of the second power device, the turn-off loss of the first power device, the turn-off loss of the second power device, the total turn-on loss of the hybrid device, the total turn-off loss of the hybrid device, and the total switching loss of the hybrid device.

[0074] Step S30: Fit the multiple switching parameters to obtain the fitness function and the screening condition function.

[0075] It should be noted that by extracting the peak voltage and current and key parameters such as switching loss during the switching process of the hybrid device, after obtaining a sufficient amount of data, the switching parameters are fitted into a binary polynomial function of the gate resistances Rt and Rm through non-linear fitting; specifically, the switching parameters of the hybrid device under different combinations of Rm and Rt are obtained through simulation, including the peak turn-on current of SiCMOSFET, the peak turn-on current of Si IGBT, the peak turn-off current of SiC MOSFET, the peak turn-off current of Si IGBT, the peak turn-off voltage of the module, the turn-on loss of SiC MOSFET, the turn-on loss of Si IGBT, the turn-off loss of SiC MOSFET, the turn-off loss of Si IGBT, and the total switching loss of the hybrid device, and these switching parameters are fitted into a binary polynomial function with the gate resistance Rt of IGBT and the gate resistance Rm of SiC MOSFET as variables through non-linear fitting.

[0076] In this embodiment, fitting the multiple switching parameters to obtain the fitness function and the screening condition function includes: fitting the multiple switching parameters corresponding to different gate resistances to obtain the fitting function of each switching parameter, and the specific expression is as shown in formula (1):

[0077] (1)

[0078] Among them, represents the gate resistance of the first power device, represents the gate resistance of the second power device, represents the fitting function of the k-th switching parameter, k = 1, 2, ……, K; K represents the total number of switching parameters; Denote the coefficients of the polynomial, where \(i\) and \(j\) represent and the powers respectively. The range of \(i\) is from 0 to and the range of \(j\) is from 0 to . For the \(k\)-th switching parameter, the number of coefficients of its corresponding binary polynomial fitting function is \(( + 1)( + 1)\), and The values of and are determined by evaluating the goodness of fit of the fitting function. Select the highest degree terms of and in the fitting function when the goodness of fit is the highest as the values of

[0079] In one embodiment, the goodness of fit can be evaluated by the following metrics:

[0080] (1) Sum of Squared Errors (SSE) or Mean Squared Error (MSE)

[0081]

[0082]

[0083] In the formula, is the value extracted by simulation, is the predicted value of the fitting function, and \(N\) is the number of data points. The smaller the values of SSE and MSE, the better the model fits the data.

[0084] (2) Root Mean Squared Error (RMSE)

[0085]

[0086] The unit of RMSE is the same as the original data. The smaller it is, the smaller the prediction error of the model and the better the fitting effect.

[0087] (3) R-squared

[0088]

[0089] Among them, is the mean of the values extracted by simulation. The value range of R-squared is from 0 to 1. The closer it is to 1, the better the fitting effect of the model.

[0090] (4) Adjusted R-squared

[0091]

[0092] p is the number of independent variables in the model. In the present invention, p = 2. The closer the adjusted R-squared value is to 1, the better the model fits the data, and the complexity of the model is considered.

[0093] In this embodiment, the fitting functions corresponding to each switching parameter are shown in Table 1:

[0094] Table 1. Fitting function relationship table

[0095]

[0096] For the fitting functions in Table 1, there are the following relationships:

[0097]

[0098]

[0099]

[0100] It can be seen therefrom that the fitting functions 、 and can be obtained by operating on other fitting functions. Therefore, in this application, only the ~ A total of 9 switching parameters in Table 1 need to be nonlinearly fitted.

[0101] In one embodiment, the fitting function corresponding to the total turn-on loss of the hybrid device, the total turn-off loss of the hybrid device, or the total switching loss of the hybrid device as the switching parameter can be used as the fitness function; wherein, the fitness function represents the target optimization function.

[0102] In another embodiment, the fitting functions corresponding to the peak turn-on current of the first power device, the peak turn-on current of the second power device, the peak turn-off current of the first power device, the peak turn-off current of the second power device, and the peak turn-off voltage of the hybrid device as the switching parameter can be used as the screening condition function.

[0103] Step S40. Iteratively optimize the fitness function according to the screening condition function to obtain the target gate resistance corresponding to each power device.

[0104] It should be noted that after obtaining the nonlinear fitting functions of each switching parameter with respect to the gate resistance and , this embodiment proposes a multi-objective optimization method to obtain the target gate resistance corresponding to each power device; the specific process of the multi-objective optimization method is as follows:

[0105] (1) Initialize the population: Randomly generate an initial population consisting of a series of individuals. Each individual in the population is usually represented by binary coding or other means, representing a possible solution in the problem solution space.

[0106] (2) Calculate the screening condition function: Evaluate the fitness of each individual to determine its ability to solve the problem.

[0107] (3) Selection operation: Select individuals according to fitness. Individuals with better fitness are more likely to be selected to participate in crossover and reproduction, thereby passing on their characteristics to the next generation. Among them, in this embodiment, the minimum value of the fitness function (i.e., loss) is sought, that is, individuals with smaller fitness values are selected.

[0108] (4) Crossover operation: The selected individuals exchange part of their coding through the crossover operation to generate new offspring.

[0109] (5) Mutation operation: Randomly change some genes of the individuals to enable a more diverse solution space to be generated during the iteration process.

[0110] (6) Generate a new population: Replace the individuals with poorer fitness in the original population with the new individuals generated by the selection, crossover, and mutation operations, thereby generating a new generation of population.

[0111] (7) Termination condition judgment: Repeat the above operations, continuously optimize the population through the iteration process until termination conditions such as reaching the maximum number of iterations, finding a solution that meets the requirements, or the change in fitness is less than the threshold.

[0112] Since the effectiveness of the multi-objective optimization method in this embodiment depends to a large extent on the definition of the fitness function, the design of the selection strategy, and the setting of the termination conditions, in this embodiment, the loss during the switching process of the hybrid device (i.e., and , or ) is defined as the fitness function, and the termination condition is set such that the change in the fitness function value in consecutive generations is less than the preset function tolerance to find the minimum value of the fitness function, that is, the minimum value of the switching loss of the hybrid device. In addition, for multi-objective optimization, the peak currents of the IGBT and SiC MOSFET during the switching process and the peak voltage during the turn-off process are added as screening conditions to the multi-objective optimization process to ensure the safe operation of the hybrid device, that is, before calculating the fitness of an individual, substitute it into the fitting functions in Table 1 ~ In it, it is judged whether the function value exceeds the Safe Operating Area (SOA) of the IGBT and SiC MOSFET. If any of the parameters exceeds the SOA of the device, the fitness value of this individual is set to infinity, and this individual is less likely to be selected and participate in the subsequent iteration process. If the function value is within the SOA of the device, the switching loss value of the hybrid device is calculated as the fitness value of this individual. Then, through selection, crossover, mutation, and multiple iteration processes, the gate resistance that can achieve the minimum switching loss is found on the premise of ensuring the safe operation of the IGBT and SiC MOSFET. and value.

[0113] In summary, according to the design model of the hybrid device of the present application, the parasitic parameter circuit model of the hybrid device is obtained; based on the parasitic parameter circuit model, simulation is carried out to obtain multiple switching parameters corresponding to different gate resistances; then, the multiple switching parameters are fitted to obtain the fitness function of multi-objective optimization and the screening condition function for ensuring the safe operation of the hybrid device; finally, the fitness function is iteratively optimized according to the screening condition function, so as to obtain the target gate resistance corresponding to each power device; therefore, the present application comprehensively considers the influence of different gate resistances on the switching behavior of power devices, so that the obtained gate resistance value can ensure the minimization of the switching loss of the hybrid device on the premise of safe operation.

[0114] In one embodiment, as Figure 8 shown, iteratively optimizing the fitness function according to the screening condition function to obtain the target gate resistance corresponding to each power device specifically includes the following steps:

[0115] (1) Generate an individual population according to the first gate resistance and the second gate resistance; wherein, the first gate resistance corresponds to the gate resistance of the first power device, and the second gate resistance corresponds to the gate resistance of the second power device; in addition, it should be noted that when generating the initial individual population, the individual population can be obtained by random generation.

[0116] (2) According to the screening condition function, calculate the screening condition function value corresponding to each individual in the individual population; wherein, the number of screening condition functions can be multiple, and then the screening condition function value corresponding to each individual can also be multiple. For example, in this embodiment, the fitting functions in Table 1 , , , and are all used as screening condition functions.

[0117] (3) Determine whether the screening condition function value corresponding to each individual meets the constraint condition; specifically, in this embodiment, each screening condition function value can be compared with the corresponding safety threshold range. If all screening condition function values are within the corresponding safety threshold range, it is determined that the individual meets the constraint condition; if any one screening condition function value is not within the corresponding safety threshold range, it is determined that the individual does not meet the constraint condition.

[0118] (4) Use the fitness function value corresponding to the individual that meets the constraint condition as the fitness value of the individual, and set the fitness value of the individual that does not meet the constraint condition to a preset value; where the preset value can be an infinite value or zero, which mainly serves a filtering purpose.

[0119] (5) Determine whether the current iteration meets the termination criterion; in this embodiment, meeting the termination criterion includes that the change value of the fitness value in N consecutive iterations is less than the preset function tolerance, or reaching the maximum number of iterations.

[0120] (6) If the current iteration meets the termination criterion, use the first gate resistance and the second gate resistance corresponding to the minimum fitness function value as the target gate resistance of the first power device and the target gate resistance of the second power device respectively, and perform simulation verification on the obtained target gate resistance.

[0121] (7) If the current iteration does not meet the termination criterion, select new individuals for the next iteration according to the fitness value corresponding to each individual.

[0122] (8) Perform crossover and genetic mutation on the new individuals to generate a new population of individuals.

[0123] (9) Perform cyclic iteration on the new population of individuals until the termination criterion is met.

[0124] In one embodiment, in the simulation experiment of the switching process of the hybrid device, the switching process is divided into cases of using the same gate resistance and different gate resistances according to actual needs; specifically, using the same gate resistance means using the same gate resistance in both the turn-on simulation process and the turn-off simulation process of the power device, and the case of using different gate resistances means using different gate resistances in the turn-on simulation process and the turn-off simulation process of the power device.

[0125] Optionally, if the process of iteratively optimizing the fitness function according to the screening condition function is regarded as a multi-objective optimization algorithm, when different gate resistances are used during the turn-on process and turn-off process of the power device, the multi-objective optimization algorithm needs to be run twice to obtain the target gate resistance corresponding to each power device. Specifically: taking the fitting function corresponding to the total turn-on loss of the hybrid device as the first fitness function, and iteratively optimizing the first fitness function according to the screening condition function to obtain the turn-on gate resistances corresponding to the first power device and the second power device respectively; taking the fitting function corresponding to the total turn-off loss of the hybrid device as the second fitness function, and iteratively optimizing the second fitness function according to the screening condition function to obtain the turn-off gate resistances corresponding to the first power device and the second power device respectively.

[0126] Optionally, when the same gate resistance is used during the turn-on process and turn-off process of the power device, the multi-objective optimization algorithm only needs to be run once to obtain the target gate resistance corresponding to each power device. Specifically: taking the fitting function corresponding to the total switching loss of the hybrid device as the third fitness function, and iteratively optimizing the third fitness function according to the screening condition function to obtain the target gate resistances corresponding to the first power device and the second power device respectively.

[0127] As Figure 9 shown, when the same driving resistance is used during the switching process, the multi-objective optimization algorithm shown only needs to be run once. At this time, the screening condition function includes the fitting function of the peak turn-on current of the SiC MOSFET Figure 8 shown, the fitting function of the peak turn-on current of the Si IGBT , the fitting function of the peak turn-off current of the SiC MOSFET , the fitting function of the peak turn-off current of the Si IGBT , and the fitting function of the peak turn-off voltage of the hybrid device . It is necessary to ensure that the values of the above 5 functions are all within the SOA of the Si IGBT or SiC MOSFET chip. At the same time, the fitness function is set to the total switching loss of the hybrid device . The optimization algorithm will continuously search for the minimum value of the fitness function until the change in the fitness function value in consecutive generations is less than the preset function tolerance. After selection, crossover, mutation, and multiple iteration processes, the optimized IGBT gate resistance value and the SiC MOSFET gate resistance value are output, as well as the total switching loss fitting value Eloss_tot of the hybrid device under the optimized gate resistance. This solution can simplify the gate drive circuit, but the obtained total switching loss fitting value Eloss_tot is a local optimal solution.

[0128] As Figure 10As shown, when different driving resistances are used in the switching process, it needs to be run twice. Figure 8 The gate resistance optimization algorithm shown in the figure. When the algorithm is run for the first time, the screening condition function includes the fitting function of the peak turn-on current of the SiC MOSFET and the fitting function of the peak turn-on current of the Si IGBT . It is necessary to ensure that the values of the above two functions are both within the SOA of the Si IGBT or SiC MOSFET chip. At the same time, the fitness function is set as the total turn-on loss f10(Rm, Rt) of the hybrid device. The optimization algorithm will continuously search for the minimum value of the fitness function until the change in the fitness function value in consecutive generations is less than the preset function tolerance. After selection, crossover, mutation, and multiple iteration processes, the optimized IGBT turn-on gate resistance value Rt_on and the SiC MOSFET turn-on gate resistance value Rm_on are output, as well as the total turn-on loss fitting value Eloss_on of the hybrid device under the optimized turn-on gate resistance. When the algorithm is run for the second time, the screening condition function includes the fitting function of the peak turn-off current of the SiC MOSFET , the fitting function of the peak turn-off current of the Si IGBT and the fitting function of the peak turn-off voltage of the hybrid device . It is necessary to ensure that the values of the above three functions are all within the SOA of the Si IGBT or SiC MOSFET chip. At the same time, the fitness function is set as the total turn-off loss f11(Rm, Rt) of the hybrid device. The optimization algorithm will continuously search for the minimum value of the fitness function until the change in the fitness function value in consecutive generations is less than the preset function tolerance. After selection, crossover, mutation, and multiple iteration processes, the optimized IGBT turn-off gate resistance value Rt_off and the SiC MOSFET turn-off gate resistance value Rm_off are output, as well as the total turn-off loss fitting value Eloss_off of the hybrid device under the optimized turn-off gate resistance. At the same time, the total switching loss fitting value Eloss_tot = Eloss_on + Eloss_off of the hybrid device can also be obtained. The total switching loss fitting value Eloss_tot obtained by this scheme is the global optimal solution, but the gate drive circuit is relatively complex.

[0129] Such as Figure 11As shown, taking an IGBT power device as an example, when different gate resistances are adopted during the turn-on process and the turn-off process, the target gate resistances obtained include the turn-on gate resistance Rt_on and the turn-off gate resistance Rt_off. In an actual drive circuit, a turn-on diode Dt_on and a turn-off diode Dt_off need to be connected in series with the turn-on gate resistance Rt_on and the turn-off gate resistance Rt_off respectively. Since the current flows into the gate of the device during the turn-on process, while the direction of the gate current during the turn-off process is opposite, that is, it flows out from the gate of the device. Assuming that the current flows from left to right during turn-on, due to the unidirectional conduction of the diode, the turn-on diode Dt_on conducts and the turn-off diode Dt_off turns off, thus connecting the turn-on gate resistance Rt_on to the gate of the power device. On the contrary, for the turn-off process, the current flows from right to left, then the turn-off diode Dt_off conducts and the turn-on diode Dt_on turns off, thus connecting the turn-off gate resistance Rt_off to the gate of the power device. The resistance values of the turn-on gate resistance Rt_on and the turn-off gate resistance Rt_off in this embodiment are obtained through Figure 10 the method shown.

[0130] To simplify the drive circuit, this embodiment adopts Figure 9 the method of using the same gate resistance during the switching process shown for experimental verification. Based on Figure 8 the multi-objective optimization results of the gate resistance are as Figure 12 shown. In Figure 12 , when the number of iterations reaches about 90 times, the change in the fitness function value in several consecutive generations is less than the preset function tolerance, and the determination of the multi-objective optimization algorithm reaches the termination condition and outputs the result: the optimized gate resistance value of the SiC MOSFET is 17.9586 Ω, the gate resistance value of the IGBT is 1.5 Ω, and the total switching loss of the hybrid device at this gate resistance is 16.414 mJ.

[0131] Furthermore, substituting the optimized target gate resistance value into the simulation circuit, the switching waveform is as Figure 13 shown; among them, Figure 13Among them, 13a is the simulation turn-on waveform, and 13b is the simulation turn-off waveform; key switching parameters are extracted. During the turn-on process, the peak values of the IGBT current IC and the SiC MOSFET current ID are 439.25591 A and 144.67885 A respectively. During the turn-off process, the peak values of IC and ID are 251.17457 A and 90.857289 A respectively, and the peak turn-off voltage is 737.07632 V. The above parameters are all within the safe operating area of the chip. The simulated value of the total loss during the switching process during the mixing period is 14.217 mJ, which is lower than the fitting value, attributed to the accuracy difference of the fitting model under different gate resistances. However, the proposed optimization strategy can obviously control the voltage and current during the switching process within the safe range and reduce the switching loss.

[0132] Furthermore, under the optimized target gate resistance, the measured results of the switching waveforms of the Si IGBT-SiC MOSFET hybrid device are as Figure 14 shown. Figure 14 Among them, 14a is the measured turn-on waveform, and 14b is the measured turn-off waveform. During the turn-on process, the peak values of the IGBT current IC and the SiC MOSFET current ID are 473 A and 191 A respectively. During the turn-off process, the peak values of IC and ID are 265 A and 101 A respectively, and the peak turn-off voltage is 761 V. The above parameters are all within the safe operating area of the chip. Under the optimized gate resistance, the total switching loss of the Si / SiC hybrid power device is 17.29 mJ. It can be seen that the measured results are similar to the simulation output results, with high consistency. Therefore, the gate resistance determination method proposed in this application can effectively achieve the multi-objective optimization of the gate resistance of the Si IGBT-SiC MOSFET hybrid device, shorten the development cycle, and save R & D costs.

[0133] Among them, Figure 13 and Figure 14 the V in F represents Figure 2 the voltage between point U and point N in HyS and I Figure 2 represents C the current that flows into from point U, passes through devices T2 and M2, and then flows out from point N in D , that is, the sum of current I C and current I D .

[0134] In summary, the technical solution provided by this application has at least the following beneficial effects:

[0135] 1. Multi-objective optimization of the gate resistance of Si IGBT-SiC MOSFET hybrid devices can be achieved: The Si IGBT-SiC MOSFET hybrid device involves both IGBT and SiC MOSFET. The gate resistance of both will affect the switching behavior of the hybrid device. An inappropriate gate resistance will not only increase the switching loss of the hybrid device and reduce its cost performance, but even cause the peak voltage and current of the device during the switching process to exceed the safe operating area of the IGBT and SiC MOSFET chips, resulting in device failure. The traditional method of selecting the gate resistance value through physical tests often obtains a local optimal solution and it is difficult to comprehensively consider the influence of the gate resistance on multiple parameters. However, the method for determining the gate resistance of the hybrid device proposed in this application comprehensively considers the influence of the IGBT gate resistance and the SiC MOSFET gate resistance on the device switching behavior. The obtained gate resistance value can minimize the switching loss of the hybrid device on the premise that the peak voltage and current of the hybrid device are both within the safe operating area of the IGBT and SiC MOSFET chips.

[0136] 2. Lower cost and shorter cycle: When the traditional physical test method is used to select the gate resistance, since two variables, namely the IGBT gate resistance and the SiC MOSFET gate resistance, need to be considered simultaneously, the test volume is large and it takes a long time. Moreover, in the actual dynamic test process, since the current overshoot that the power chip can withstand is certain, an unreasonable gate resistance value will cause overcurrent failure of the power chip, increasing the development cost. When the gate resistance needs to be integrated into the power module, once the physical test result is inappropriate, the power module needs to be re-prepared. For power modules with a longer production time and higher material costs, this method will cause a significant increase in the development cycle and cost. The method for determining the gate resistance proposed in this application obtains the fitting function of the switching parameters with respect to the gate resistance by building a simulation circuit considering the parasitic parameters of the hybrid device and performs multi-objective optimization through a genetic algorithm, thereby obtaining the optimized gate resistance value. Compared with physical tests, the method of this application mainly relies on simulation, reducing a large number of physical preparation and test links. Even in the design stage of the hybrid device, the evaluation of the gate resistance value can be realized, effectively shortening the development cycle and reducing the R & D cost.

[0137] 3. Wide range of applicability: The gate resistor selection method proposed in this application is applicable not only to Si IGBT-SiC MOSFET hybrid devices, but also to the parallel connection schemes of Si IGBT and SiC MOSFET discrete devices, all-Si IGBT schemes, and all-SiC MOSFET schemes. For example, for Si IGBT modules, their parasitic parameter matrices can also be extracted and exported as circuit models for electrical simulation, the physical switch parameters under different gate resistors can be extracted and non-linearly fitted, and finally multi-objective optimization can be carried out. Since there is only one variable, the simulation calculation amount is smaller, the time is shorter, at the same time the complexity of the fitting function is lower, and the calculation amount of the optimization algorithm is reduced, so it is easier to determine the gate resistor.

[0138] Figure 15 The following is a schematic structural diagram of a gate resistor determination device for a hybrid device provided by an embodiment of the present application; as Figure 15 shown, the device includes:

[0139] A circuit model acquisition module 111, configured to obtain a parasitic parameter circuit model of the hybrid device according to the design model of the hybrid device;

[0140] A switch parameter acquisition module 112, configured to simulate the multi-port circuit model and obtain a plurality of switch parameters corresponding to different gate resistors;

[0141] A parameter fitting module 113, which fits a plurality of switch parameters to obtain a fitness function and a screening condition function;

[0142] An iterative optimization module 114, configured to iteratively optimize the fitness function according to the screening condition function to obtain the target gate resistor corresponding to each power device.

[0143] In an embodiment, the gate resistor determination device further includes a verification module, configured to perform double-pulse simulation and testing on the target gate resistor value corresponding to each power device, and verify whether the peak values of voltage and current during the switching process of the hybrid device are within the safe operating area of the IGBT and SiC MOSFET chips, and whether the switching loss meets the design requirements.

[0144] In an embodiment, the hardware control system architecture of the gate resistor determination device for the hybrid device may include, but is not limited to:

[0145] (1) Core control unit (CPU): As the core control unit, it processes parasitic parameter extraction, multi-objective optimization algorithm calculation, and data transmission control.

[0146] (2) Storage unit (ROM + RAM): ROM: Stores fixed programs, such as optimization algorithms, control logic, and simulation verification models; RAM: Used to store dynamic data, including parasitics parameters collected in real time, intermediate optimization results, simulation data, etc.

[0147] (3) I / O interface: Interacts with external modules, used for inputting data (such as experimental measurement data) and outputting control signals.

[0148] (4) Input module: Includes a measurement device interface, used for collecting parasitics parameters and switching characteristics of the device.

[0149] (5) Output module: Used to control external experimental equipment or feedback optimization results, such as the gate resistance value after multi-objective optimization.

[0150] (6) Driver module: Used to control the working states of Si IGBT and SiC MOSFET.

[0151] Figure 16 The structural schematic diagram of a computer system of an electronic device suitable for implementing the embodiments of the present application is shown.

[0152] It should be noted that Figure 16 The shown computer system 1000 of the electronic device is only an example, and should not impose any limitation on the functions and usage scope of the embodiments of the present application.

[0153] As Figure 16 shown, the computer system 1000 includes a central processing unit (CPU) 1001, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1002 or the program loaded from the storage section 1008 into the random access memory (RAM) 1003, such as executing the method described in the above embodiments. In the RAM 1003, various programs and data required for system operation are also stored. The CPU 1001, ROM 1002, and RAM 1003 are connected to each other through a bus 1004. The input / output (I / O) interface 1005 is also connected to the bus 1004.

[0154] The following components are connected to the I / O interface 1005: an input section 1006 including a keyboard, a mouse, etc.; an output section 1007 including, for example, a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1008 including a hard disk, etc.; and a communication section 1009 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 1009 performs communication processing via a network such as the Internet. The drive 1010 is also connected to the I / O interface 1005 as needed. A removable medium 1011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is mounted on the drive 1010 as needed so that a computer program read therefrom is installed into the storage section 1008 as needed.

[0155] Specifically, according to an embodiment of the present application, the processes described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product that includes a computer program carried on a computer-readable medium, and the computer program includes a computer program for performing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 1009, and / or installed from the removable medium 1011. When the computer program is executed by a central processing unit (CPU) 1001, various functions defined in the system of the present application are executed.

[0156] It should be noted that the computer-readable medium shown in the embodiments of the present application can be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, the computer-readable storage medium can be any tangible medium that contains or stores a program, and this program can be used by or in combination with an instruction execution system, apparatus, or device. In the present application, a computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable computer program. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, and this computer-readable medium can send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device. The computer program contained on the computer-readable medium can be transmitted by any suitable medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0157] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present application. Among them, each block in the flowchart or block diagram can represent a module, a program segment, or a part of code, and the above module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order from that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, as well as the combination of blocks in the block diagram or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0158] The units involved in the embodiments described in this application can be implemented in software or in hardware, and the described units can also be provided in a processor. Among them, the names of these units do not constitute a limitation to the units themselves in some cases.

[0159] The above content is only a preferred exemplary embodiment of this application and is not used to limit the implementation of this application. Those of ordinary skill in the art can easily make corresponding adaptations or modifications according to the main concept and spirit of this application. Therefore, the protection scope of this application shall be subject to the protection scope required by the claims.

Claims

1. A method for determining the gate resistance of a hybrid device, characterized in that: The hybrid device includes at least one first power device and at least one second power device, and the method includes: Obtaining a parasitic parameter circuit model of the hybrid device according to the design model of the hybrid device; Simulating the parasitic parameter circuit model to obtain a plurality of switch parameters corresponding to different gate resistances; Fitting the multiple switch parameters to obtain a fitness function and a screening condition function; specifically including: fitting the multiple switch parameters corresponding to different gate resistances to obtain a fitting function of each switch parameter, the specific expression of which is: in, represents the gate resistance of the first power device, represents the gate resistance of the second power device, represents the fitting function of the kth switch parameter, k=1,2,…,K; K represents the total number of switch parameters; represents the coefficients of the polynomial, and Represent the highest values ​​of i and j respectively; The fitting function corresponding to the switch parameters of the total turn-on loss of the hybrid device, the total turn-off loss of the hybrid device, or the total switching loss of the hybrid device is used as the fitness function; the fitting function corresponding to the switch parameters of the turn-on current peak of the first power device, the turn-on current peak of the second power device, the turn-off current peak of the first power device, the turn-off current peak of the second power device, and the turn-off voltage peak of the hybrid device is used as the screening condition function; The fitness function is iteratively optimized according to the screening condition function to obtain a target gate resistance corresponding to each power device.

2. The method according to claim 1, characterized in that: According to the design model of the hybrid device, a parasitic parameter circuit model of the hybrid device is obtained, including: Perform three-dimensional layout design according to the circuit topology diagram of the hybrid device to obtain a design model of the hybrid device; Importing the design model into simulation software, and setting the material properties corresponding to each device in the simulation software; Grid division is performed according to the positions of the power terminals and signal terminals of the hybrid device and the electrode positions of each power device to obtain a plurality of grids with different functions; According to the actual current direction of the drive circuit and the commutation circuit, the current flow direction in each grid is set; Running the simulation software to obtain a parasitic parameter matrix; A parasitic parameter circuit model of the hybrid device is generated according to the parasitic parameter matrix.

3. The method according to claim 1, characterized in that The parasitic parameter circuit model is simulated to obtain a plurality of switch parameters corresponding to different gate resistances, including: Importing the parasitic parameter circuit model and the power device model into circuit simulation software to build a double pulse simulation circuit; Setting simulation parameters for the double pulse simulation circuit according to actual test conditions to simulate the switching process of the hybrid device under different gate resistances; Extract multiple switching parameters corresponding to different gate resistances.

4. The method according to claim 1, characterized in that: When different gate resistances are used in the turn-on process and the turn-off process of the power device, the fitness function is iteratively optimized according to the screening condition function to obtain the target gate resistance corresponding to each power device, including: Taking the fitting function corresponding to the total turn-on loss of the hybrid device as the first fitness function, iteratively optimizing the first fitness function according to the screening condition function, and obtaining the turn-on gate resistances corresponding to the first power device and the second power device respectively; The fitting function corresponding to the total turn-off loss of the hybrid device is used as the second fitness function, and the second fitness function is iteratively optimized according to the screening condition function to obtain the turn-off gate resistances corresponding to the first power device and the second power device respectively.

5. The method according to claim 1, characterized in that When the same gate resistance is used in the turn-on process and the turn-off process of the power device, the fitness function is iteratively optimized according to the screening condition function to obtain the target gate resistance corresponding to each power device, including: The fitting function corresponding to the total switching loss of the hybrid device is used as the third fitness function, and the third fitness function is iteratively optimized according to the screening condition function to obtain the target gate resistances corresponding to the first power device and the second power device respectively.

6. The method according to claim 4 or 5, characterized in that: Iteratively optimizing the fitness function according to the screening condition function to obtain a target gate resistance corresponding to each power device includes: Generate an individual population according to a first gate resistor and a second gate resistor, wherein the first gate resistor corresponds to the gate resistor of the first power device, and the second gate resistor corresponds to the gate resistor of the second power device; According to the screening condition function, calculating the screening condition function value corresponding to each individual in the individual population; The screening condition function value corresponding to each individual is used to determine whether it satisfies the constraint condition; The fitness function value corresponding to the individual that meets the constraint conditions is taken as the fitness value of the individual; If the current iteration meets the termination criteria, the first gate resistance and the second gate resistance corresponding to the minimum fitness function value are respectively used as the target gate resistance of the first power device and the target gate resistance of the second power device; wherein the termination criteria include that the change value of the fitness value in N consecutive iterations is less than the preset function tolerance, or the maximum number of iterations is reached.

7. The method according to claim 4, characterized in that The method further comprises: Set the fitness values ​​of individuals that do not meet the constraints to the preset values; If the current iteration does not meet the termination criteria, a new individual for the next iteration is selected based on the fitness value corresponding to each individual; Performing crossover and genetic mutation on the new individuals to generate a new individual population; The new individual population is iterated in a loop until a termination criterion is met.

8. A device for determining gate resistance of a hybrid device, characterized in that: The device comprises: A circuit model acquisition module, used to obtain a parasitic parameter circuit model of the hybrid device according to the design model of the hybrid device; A switch parameter acquisition module, used to simulate the parasitic parameter circuit model to obtain a plurality of switch parameters corresponding to different gate resistances; The parameter fitting module is used to fit the multiple switch parameters to obtain a fitness function and a screening condition function; specifically, it is used to fit the multiple switch parameters corresponding to different gate resistances to obtain a fitting function of each switch parameter, and the specific expression is: in, represents the gate resistance of the first power device, represents the gate resistance of the second power device, represents the fitting function of the kth switch parameter, k=1,2,…,K; K represents the total number of switch parameters; represents the coefficients of the polynomial, and Respectively represent the highest values ​​of i and j; also used to use the fitting function corresponding to the switch parameter being the total turn-on loss of the hybrid device, the total turn-off loss of the hybrid device, or the total switching loss of the hybrid device as the fitness function; also used to use the fitting function corresponding to the switch parameter being the turn-on current peak of the first power device, the turn-on current peak of the second power device, the turn-off current peak of the first power device, the turn-off current peak of the second power device, and the turn-off voltage peak of the hybrid device as the screening condition function; The iterative optimization module is used to iteratively optimize the fitness function according to the screening condition function to obtain a target gate resistance corresponding to each power device.

9. An electronic device, characterized in that: include: processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute the executable instructions to enable the electronic device to implement the gate resistance determination method of the hybrid device as described in any one of claims 1 to 7.

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