Position Optimization-Based Encapsulation Reliability Optimization Method, System and Related Devices

Abstract

The present invention relates to a method, system and related device for optimizing package reliability based on position optimization. The method designs a package scheme by randomly arranging the positions of chip packages on a substrate, and optimizes the package scheme by calculating the variance of solder ball stress through modeling of the chip, substrate and solder balls. In this way, the solder ball stress during chip packaging can be made as average as possible, thereby improving the reliability of chip packaging; moreover, this method is easy to implement automated processing, which is beneficial to improving the working efficiency of the chip packaging design and manufacturing process.

Description

Technical Field

[0001] The present invention is applicable to the field of semiconductor packaging technology, and particularly relates to a packaging reliability optimization method, system and related equipment based on position optimization. Background Art

[0002] In the chip packaging process, FPG (Fine Pitch BGA) packaging and BGA (Ball Grid Array) packaging have become important chip packaging forms due to their excellent efficiency and performance. FPG packaging is mainly applied to fields such as high-frequency communication equipment, computer motherboards, high-performance graphics cards, mobile devices, and consumer electronics, and is suitable for scenarios that require high signal integrity and miniaturized designs; BGA is widely used in processors, microcontrollers, FPGAs, network devices, and consumer electronic products, and is suitable for occasions that require high-power processing, stable performance, and high-density pin connections. With the progress of manufacturing technology, the solder ball pitch of FPG and BGA packaging has been continuously reduced, promoting the development of chip miniaturization and high performance. With the rapid development of the Internet of Things (IoT), artificial intelligence (AI), and 5G technologies, the demand for high-performance and high-density chip packaging continues to increase. The respective advantages of FPG packaging and BGA packaging make them suitable for different application scenarios. When selecting a packaging form, design engineers need to comprehensively consider factors such as performance, cost, heat dissipation, and production process to achieve the best design effect.

[0003] During the chip packaging process, the solder ball stress problem is a key consideration factor. Problems related to solder ball stress include the following:

[0004] Thermal expansion mismatch: The thermal expansion coefficients of the chip and the substrate (such as a PCB) are usually different when the temperature changes. This difference will cause stress in the solder balls during heating and cooling, which may affect the reliability of the solder joints.

[0005] Solder joint fatigue: The solder balls will experience periodic thermal cycles during long-term use, which will cause solder joint fatigue and possible failure. Excessive stress may accelerate the crack formation of the solder joints.

[0006] Insufficient signal integrity: Excessive solder ball stress may cause poor connection between the chip and the substrate, thereby affecting the integrity of signal transmission and causing a decline in electrical performance.

[0007] Reliability and lifespan are difficult to guarantee: The stress level of the solder balls directly affects the overall reliability of the package. Excessive stress may cause solder joint failure, thereby shortening the service life of the product.

[0008] Problems in the manufacturing process: During the packaging process, the stress of the solder balls may cause the generation of defects such as bubbles and cracks, and these defects may cause problems in subsequent tests and use.

[0009] In summary, during the chip packaging design and manufacturing process, the positions between chips on the packaging substrate and the positions between solder balls are different, which will result in a large difference in the stress received between solder balls, causing some solder balls to bear excessive stress and fail in advance. This situation will greatly affect the manifestation of the reliability of the packaging process in terms of consistency. Summary of the Invention

[0010] The present invention provides an optimization method, system and related equipment for packaging reliability based on position optimization, aiming to solve the technical problem of insufficient packaging reliability caused by a large difference in stress between solder balls during the existing chip packaging process.

[0011] To solve the above technical problem, in a first aspect, the present invention provides an optimization method for packaging reliability based on position optimization, including the following steps:

[0012] S101. Obtain the first shape of the packaging substrate and the second shape of the chip to be packaged, where the first shape and the second shape include length and width;

[0013] S102. Mesh the packaging substrate according to the first shape and the second shape to obtain a meshed packaging substrate. At the same time, determine the number of iterations according to the meshing degree of the packaging substrate;

[0014] S103. Arrange the chips on the meshed packaging substrate in a random layout to obtain a packaging scheme;

[0015] S104. Determine whether the packaging scheme meets the preset chip arrangement rules. If so, execute step S105; if not, return to step S103;

[0016] S105. Based on the packaging scheme, model the chips and the packaging substrate, and at the same time model the solder balls for welding the chips to the packaging substrate to obtain a packaging model;

[0017] S106. Obtain the average equivalent stress of each solder ball in the packaging model, and obtain the stress variance value according to the average equivalent stress;

[0018] S107. Repeat steps S103 - S106 until the number of repetitions is equal to the number of iterations to obtain multiple packaging schemes and the corresponding stress variance values;

[0019] S108. Select one packaging scheme corresponding to the stress variance value with the smallest value as the optimized packaging scheme, and output the packaging position of the chip corresponding to the optimized packaging scheme packaged on the packaging substrate.

[0020] Further, in step S102, the grid size for meshing the encapsulation substrate is determined according to the second shapes of the multiple chips. Define the length and width of the multiple chips as ( a 1 , b 1 ), ( a 2 , b 2 ), … ( a n , b n ). The greatest common divisor of the lengths and widths of the multiple chips is k . The grid size is equal to the greatest common divisor k . The length and width of the encapsulation substrate are ( A , B ). The number of chips is n . The number of iterations is N . The following relationship is satisfied:

[0021] .

[0022] Further, in step S106, define the number of solder balls in the encapsulation model as n . The average equivalent stress of each solder ball is respectively F 1 , F 2 , …, F n . The stress variance value is St 2 . The following relationship is satisfied:

[0023] ;

[0024] .

[0025] Further, the preset chip layout rule is: different chips are arranged on the meshed encapsulation substrate without overlapping each other;

[0026] Construct a plane coordinate system with the top corner of the meshed encapsulation substrate as the origin. Define any first chip R1 and second chip R2 arranged on the meshed encapsulation substrate. The sequences formed by the lower left corner coordinates and upper right corner coordinates in the plane coordinate system are respectively R1 = [x11, y11, x12, y12] , R2 = [x21, y21, x22, y22] . When any one of the following relationships is satisfied, the encapsulation scheme meets the preset chip layout rule:

[0027] R1[2] ≤ R2[0] ;

[0028] R1[0] ≥ R2[2] ;

[0029] R1[3] ≤ R2[1] ;

[0030] R1[1] ≥ R2[3] 。

[0031] Furthermore, the preset chip layout rule is as follows:

[0032] When different chips are arranged on the grid-shaped packaging substrate, the distance between each other is not less than the preset packaging distance;

[0033] Taking the vertex angle of the grid-shaped packaging substrate as the origin to construct a plane coordinate system, defining any first chip arranged on the grid-shaped packaging substrate R1 , and a second chip R2 The sequences formed by the lower left corner coordinates and the upper right corner coordinates in the plane coordinate system are respectively R1 = [x11, y11, x12, y12] , R2 = [x21, y21, x22, y22] , the preset packaging distance is GP , when any one of the following relationships is satisfied, the packaging scheme meets the preset chip layout rule:

[0034] R1[2] ≤ R2[0], GP ≤ R2[0] - R1[2] ;

[0035] R2[2] ≤ R1[0], GP ≤ R1[0] - R2[2] ;

[0036] R1[3] ≤ R2[1], GP ≤ R2[1] - R1[3] ;

[0037] R2[3] ≤ R1[1], GP ≤ R1[1] - R2[3] 。

[0038] In a second aspect, the present invention further provides a packaging reliability optimization system based on position optimization, including:

[0039] An initialization module, configured to obtain the first shape of the packaging substrate and the second shape of the chip to be packaged, where the first shape and the second shape include length and width;

[0040] A gridification module, configured to gridify the packaging substrate according to the first shape and the second shape to obtain a grid-shaped packaging substrate, and at the same time, determine the number of iterations according to the degree of gridification of the packaging substrate;

[0041] A random layout module, configured to arrange the chips on the grid-shaped packaging substrate in a random arrangement manner to obtain a packaging scheme;

[0042] A judgment module, configured to judge whether the encapsulation scheme meets a preset chip layout rule. If so, execute the modeling module; if not, return to the random layout module;

[0043] A modeling module, configured to perform modeling on the chip and the encapsulation substrate based on the encapsulation scheme, and simultaneously perform modeling on the solder balls for soldering the chip to the encapsulation substrate, to obtain an encapsulation model;

[0044] A stress simulation module, configured to obtain the average equivalent stress of each solder ball in the encapsulation model, and obtain a stress variance value according to the average equivalent stress;

[0045] An iteration control module, configured to repeatedly execute the random layout module, the judgment module, the modeling module, and the stress simulation module in sequence until the number of repetitions is equal to the number of iterations, to obtain multiple encapsulation schemes and the corresponding stress variance values;

[0046] An output module, configured to select, according to the stress variance value with the smallest numerical value, a corresponding encapsulation scheme as the optimized encapsulation scheme, and output the encapsulation position where the chip corresponding to the optimized encapsulation scheme is encapsulated on the encapsulation substrate.

[0047] Furthermore, the random layout module is further configured to determine the grid size for meshing the encapsulation substrate according to the second shapes of multiple chips, define the lengths and widths of the multiple chips as ( a 1 , b 1 ), ( a 2 , b 2 ),..., ( a n , b n ), the greatest common divisor of the lengths and widths of the multiple chips is k , the grid size is equal to the greatest common divisor k , the length and width of the encapsulation substrate are ( A , B ), the number of chips is n , the number of iterations is N , and the following relationship is satisfied:

[0048] .

[0049] Furthermore, the stress simulation module is further configured to define the number of solder balls in the encapsulation model as n , and the average equivalent stress of each solder ball is respectively F1 , F 2 , …, F n , the stress variance value is St 2 , and satisfies the following relationship:

[0050] ;

[0051] .

[0052] In a third aspect, the present invention further provides a computer device, including: a memory, a processor, and an optimization program for package reliability based on position optimization stored on the memory and executable on the processor. When the processor executes the optimization program for package reliability based on position optimization, the steps in the method for optimizing package reliability based on position optimization as described in any one of the above embodiments are implemented.

[0053] In a fourth aspect, the present invention further provides a computer-readable storage medium, on which an optimization program for package reliability based on position optimization is stored. When the optimization program for package reliability based on position optimization is executed by a processor, the steps in the method for optimizing package reliability based on position optimization as described in any one of the above embodiments are implemented.

[0054] The beneficial effects achieved by the present invention are as follows: A method for optimizing package reliability based on position optimization is proposed. This method designs the package scheme by randomly arranging the chip packages on the substrate, and optimizes the package scheme by calculating the variance of the solder ball stress through the modeling of the chip, substrate, and solder balls. In this way, the solder ball stress during chip packaging can be made as average as possible, thereby improving the reliability of chip packaging; moreover, this method is easy to implement automated processing, which is beneficial to improving the work efficiency of the chip packaging design and manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 is a flowchart of the steps of the method for optimizing package reliability based on position optimization provided by an embodiment of the present invention;

[0056] Figure 2 is a schematic diagram of the chip layout position in the method for optimizing package reliability based on position optimization provided by an embodiment of the present invention;

[0057] Figure 3 is a schematic diagram of the package model structure in the method for optimizing package reliability based on position optimization provided by an embodiment of the present invention;

[0058] Figure 4It is a schematic structural diagram of an encapsulation reliability optimization system based on position optimization provided by an embodiment of the present invention;

[0059] Figure 5 It is a schematic structural diagram of a computer device provided by an embodiment of the present invention. Detailed implementation manners

[0060] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0061] Please refer to Figure 1 , Figure 1 It is a step flowchart of an encapsulation reliability optimization method based on position optimization provided by an embodiment of the present invention. The encapsulation reliability optimization method based on position optimization includes the following steps:

[0062] S101. Obtain the first shape of the encapsulation substrate and the second shape of the chip to be encapsulated. The first shape and the second shape include length and width.

[0063] S102. Mesh the encapsulation substrate according to the first shape and the second shape to obtain a meshed encapsulation substrate. At the same time, determine the number of iterations according to the meshing degree of the encapsulation substrate.

[0064] In step S102, determine the mesh size for meshing the encapsulation substrate according to the second shapes of multiple chips. Define the length and width of multiple chips as ( a 1 , b 1 ), ( a 2 , b 2 ), … ( a n , b n ). The greatest common divisor of the length and width of multiple chips is k . The mesh size is equal to the greatest common divisor k . The length and width of the encapsulation substrate are ( A , B ). The number of chips is n . The number of iterations is N , satisfying the following relationship:

[0065] .

[0066] In an embodiment of the present invention, the greatest common divisor kIt can be determined according to the size of the encapsulation substrate. From the above relationship, it can be seen that the grid size determines the scale of iteration. The higher the degree of gridification, the more positions where the chips can be arranged, and the more iterations there will be; conversely, the smaller the degree of gridification, the fewer positions where the chips can be arranged, and the fewer iterations there will be. During the implementation process, since the scale of the chips is generally between 10μm - 100μm, in order to achieve miniaturization of the chips, the greatest common divisor k The least common divisor can be used, which can ensure that the positions for arranging the chips are rich enough.

[0067] S103. Arrange the chips on the gridified encapsulation substrate in a random arrangement manner to obtain an encapsulation scheme.

[0068] Specifically, when arranging the chips on the gridified encapsulation substrate, align the top corners of the chips with the top corners of the grids in the gridified encapsulation substrate.

[0069] S104. Determine whether the encapsulation scheme meets the preset chip arrangement rules. If so, execute step S105; if not, return to step S103.

[0070] Specifically, please refer to Figure 2 , Figure 2 which is a schematic diagram of the chip arrangement positions in the encapsulation reliability optimization method based on position optimization provided by an embodiment of the present invention. The preset chip arrangement rules are as follows: When different chips are arranged on the gridified encapsulation substrate, they do not overlap with each other;

[0071] Construct a plane coordinate system with the top corner of the gridified encapsulation substrate as the origin, and define any first chip arranged on the gridified encapsulation substrate R1 , second chip R2 . The sequences formed by the lower left corner coordinates and the upper right corner coordinates of the two chips in the plane coordinate system are respectively R1 = [x11, y11, x12, y12] , R2 = [x21, y21, x22, y22] . When any of the following relationships is satisfied, the encapsulation scheme meets the preset chip arrangement rules:

[0072] R1[2] ≤ R2[0] ;

[0073] R1[0] ≥ R2[2] ;

[0074] R1[3] ≤ R2[1] ;

[0075] R1[1] ≥ R2[3] .

[0076] The above relationships determine the positional relationships between any chips by comparing the sequence index values. Corresponding to the positional relationships shown in Figure 2 , the above relationships actually respectively correspond to:

[0077] The first chip R1 The right side is on the second chip R2 The left side;

[0078] The first chip R1 The left side is on the second chip R2 The right side;

[0079] The first chip R1 The upper side is on the second chip R2 The lower side;

[0080] The first chip R1 The lower side is on the second chip R2 The upper side.

[0081] Alternatively, since in cases with specific requirements, due to packaging or performance needs, the spacing between chips shall not be less than a certain value, the preset chip layout rule can also be:

[0082] When different chips are arranged on the grid-shaped packaging substrate, the spacing between them is not less than the preset packaging spacing;

[0083] The preset packaging spacing is GP , when any one of the following relationships is satisfied, the packaging scheme meets the preset chip layout rule:

[0084] R1[2] ≤ R2[0], GP ≤ R2[0] - R1[2] ;

[0085] R2[2] ≤ R1[0], GP ≤ R1[0] - R2[2] ;

[0086] R1[3] ≤ R2[1], GP ≤ R2[1] - R1[3] ;

[0087] R2[3] ≤ R1[1], GP ≤ R1[1] - R2[3] .

[0088] It can be understood that the spacing between different chips is a situation based on the non-overlap of chips. Therefore, the positional relationship reflected by the above relationships is similar to that in the previous text, that is:

[0089] The first chip R1 The right side is on the second chip R2 The left side, and the spacing is greater than the preset packaging spacing;

[0090] The first chip R1 The left side is on the second chip R2 The right side, and the spacing is greater than the preset packaging spacing;

[0091] The first chip R1 The upper side is on the second chip R2 The lower side, and the spacing is greater than the preset packaging spacing;

[0092] The first chip R1 The lower side is on the second chip R2 On the upper side, and the spacing is greater than the preset packaging spacing.

[0093] Figure 2 The chip R3 is also included. It can be understood that when arranging multiple chips on the grid-shaped packaging substrate, the preset chip arrangement rules must be satisfied between any two of the chips. During the implementation process, the specific type of the preset chip arrangement rules can be determined according to actual needs, and since the position data (coordinate sequence) of the chips is known and does not involve complex mathematical calculations, the judgment process of step S104 can be easily implemented through an automated process.

[0094] S105. Based on the packaging scheme, model the chip and the packaging substrate, and at the same time model the solder balls for welding the chip to the packaging substrate to obtain a packaging model.

[0095] Specifically, please refer to Figure 3 , Figure 3 It is a schematic diagram of the packaging model structure in the packaging reliability optimization method based on position optimization provided by the embodiment of the present invention. Generally, pads are designed corresponding to the positions where the chips are welded to the packaging substrate. In fact, the solder balls are in contact with the pads, and their final form is not a complete sphere.

[0096] S106. Based on the packaging model, obtain the average equivalent stress of each solder ball therein, and obtain the stress variance value according to the average equivalent stress.

[0097] Specifically, in the embodiment of the present invention, for the convenience of finite element analysis, the modeling of the solder balls in the packaging model is evenly divided into 4 equal parts in height. Among them, the upper contact area and the lower contact area are the most sensitive areas when the stress of the packaging substrate changes. Therefore, when calculating the stress, only the volume average equivalent (mises) stress of the upper contact area and the lower contact area needs to be concerned. During the implementation process, the average equivalent stress can be obtained through the force analysis of the packaging model.

[0098] In step S106, define the number of solder balls in the packaging model as n , and the average equivalent stress of each solder ball is respectively F 1 , F 2 , …, F n , and the stress variance value is St 2 , satisfying the following relationship:

[0099] ;

[0100] 。

[0101] S107. Repeat steps S103 - S106 until the number of repetitions is equal to the number of iterations, obtaining multiple said encapsulation schemes and the corresponding stress variance values.

[0102] S108. Select one said encapsulation scheme corresponding to the stress variance value with the smallest numerical value as the optimized encapsulation scheme, and output the encapsulation position of the chip encapsulated in the encapsulation substrate corresponding to the optimized encapsulation scheme.

[0103] The stress variance value measures the stress dispersion degree of all the solder balls in the encapsulation model. One encapsulation scheme with the smallest variance value not only meets the requirements of chip layout but also makes the chip products in actual assembly have relatively average solder ball stress, thus realizing the optimization of chip encapsulation reliability.

[0104] The beneficial effect achieved by the present invention lies in providing an optimization method for encapsulation reliability based on position optimization. This method designs the encapsulation scheme by randomly arranging the positions of chip encapsulation on the substrate, and optimizes the encapsulation scheme by calculating the variance of the solder ball stress through the modeling of the chip, substrate, and solder balls. In this way, the solder ball stress during chip encapsulation can be made as average as possible, thereby improving the reliability of chip encapsulation; moreover, this method is easy to implement automated processing, which is beneficial to improving the work efficiency in the chip encapsulation design and manufacturing process.

[0105] The embodiment of the present invention also provides an optimization system 200 for encapsulation reliability based on position optimization. Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of the optimization system for encapsulation reliability based on position optimization provided by the embodiment of the present invention. The optimization system 200 for encapsulation reliability based on position optimization includes:

[0106] An initialization module 201, configured to obtain the first shape of the encapsulation substrate and the second shape of the chip to be encapsulated, where the first shape and the second shape include length and width;

[0107] A meshing module 202, configured to mesh the encapsulation substrate according to the first shape and the second shape to obtain a meshed encapsulation substrate, and at the same time, determine the number of iterations according to the meshing degree of the encapsulation substrate;

[0108] A random arrangement module 203, configured to arrange the chip on the meshed encapsulation substrate in a random arrangement manner to obtain an encapsulation scheme;

[0109] A judgment module 204, configured to judge whether the encapsulation scheme meets a preset chip layout rule. If so, execute a modeling module 205; if not, return to the random layout module 203;

[0110] A modeling module 205, configured to perform modeling on the chip and the encapsulation substrate based on the encapsulation scheme, and simultaneously perform modeling on solder balls for soldering the chip to the encapsulation substrate, to obtain an encapsulation model;

[0111] A stress simulation module 206, configured to obtain the average equivalent stress of each solder ball in the encapsulation model based on the encapsulation model, and obtain a stress variance value according to the average equivalent stress;

[0112] An iteration control module 207, configured to repeatedly execute the random layout module 203, the judgment module 204, the modeling module 205, and the stress simulation module 206 in sequence until the number of repetitions is equal to the number of iterations, to obtain multiple encapsulation schemes and corresponding stress variance values;

[0113] An output module 208, configured to select, according to the stress variance value with the smallest numerical value, a corresponding encapsulation scheme as an optimized encapsulation scheme, and output the encapsulation position where the chip corresponding to the optimized encapsulation scheme is encapsulated on the encapsulation substrate.

[0114] The random layout module 203 is further configured to determine the grid size for meshing the encapsulation substrate according to the second shapes of multiple chips, and define the lengths and widths of multiple chips as ( a 1 , b 1 ), ( a 2 , b 2 ),..., ( a n , b n ). The greatest common divisor of the lengths and widths of multiple chips is k , and the grid size is equal to the greatest common divisor k . The length and width of the encapsulation substrate are ( A , B ), the number of chips is n , the number of iterations is N , and the following relationship is satisfied:

[0115] .

[0116] The stress simulation module 206 is further configured to define the number of solder balls in the encapsulation model as n, the average equivalent stress of each of the solder balls is respectively F 1 、 F 2 、…、 F n , and the stress variance value is St 2 , satisfying the following relationship:

[0117] ;

[0118] .

[0119] The packaging reliability optimization system 200 based on position optimization can implement the steps in the packaging reliability optimization method based on position optimization in the above embodiments, and can achieve the same technical effects. Refer to the description in the above embodiments, and details are not described herein again.

[0120] An embodiment of the present invention further provides a computer device. Please refer to Figure 5 , Figure 5 which is a schematic structural diagram of the computer device provided by the embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and a packaging reliability optimization program stored on the memory 302 and executable on the processor 301.

[0121] The processor 301 calls the packaging reliability optimization program stored in the memory 302 and executes the steps in the packaging reliability optimization method provided by the embodiment of the present invention. Please refer to Figure 1 , which specifically includes the following steps:

[0122] S101. Obtain the first shape of the packaging substrate and the second shape of the chip to be packaged, where the first shape and the second shape include length and width.

[0123] S102. Mesh the packaging substrate according to the first shape and the second shape to obtain a meshed packaging substrate. At the same time, determine the number of iterations according to the meshing degree of the packaging substrate.

[0124] In step S102, determine the mesh size for meshing the packaging substrate according to the second shapes of multiple chips. Define the lengths and widths of multiple chips as ( a 1 , b 1 ), ( a 2 , b 2 ), … (a n , b n ), the greatest common divisor of the length and width of multiple said chips is k , the grid size is equal to said greatest common divisor k , the length and width of the packaging substrate are ( A , B ), the number of said chips is n , the number of iterations is N , satisfying the following relationship:

[0125] .

[0126] S103. Arrange the said chips on the grid-shaped packaging substrate in a random layout manner to obtain a packaging scheme.

[0127] S104. Determine whether the said packaging scheme meets the preset chip arrangement rules. If so, execute step S105; if not, return to step S103.

[0128] The said preset chip arrangement rules are: When different said chips are arranged on the grid-shaped packaging substrate, they do not overlap with each other;

[0129] Taking the vertex angle of the grid-shaped packaging substrate as the origin to construct a plane coordinate system, define any first chip R1 , second chip R2 arranged on the grid-shaped packaging substrate. The sequences formed by the lower left corner coordinates and the upper right corner coordinates in the plane coordinate system are respectively R1 = [x11, y11, x12, y12] , R2 = [x21, y21, x22, y22] . When any one of the following relationships is satisfied, the said packaging scheme meets the said preset chip arrangement rules:

[0130] R1[2] ≤ R2[0] ;

[0131] R1[0] ≥ R2[2] ;

[0132] R1[3] ≤ R2[1] ;

[0133] R1[1] ≥ R2[3] .

[0134] Or, the said preset chip arrangement rules are:

[0135] When different said chips are arranged on the grid-shaped packaging substrate, the distance between each other is not less than the preset packaging distance;

[0136] The said preset packaging distance is GP . When any one of the following relationships is satisfied, the said packaging scheme meets the said preset chip arrangement rules:

[0137] R1[2] ≤ R2[0], GP ≤ R2[0] - R1[2] ;

[0138] R2[2] ≤ R1[0], GP ≤ R1[0] - R2[2] ;

[0139] R1[3] ≤ R2[1], GP ≤ R2[1] - R1[3] ;

[0140] R2[3] ≤ R1[1], GP ≤ R1[1] - R2[3] 。

[0141] S105. Based on the encapsulation scheme, model the chip and the encapsulation substrate, and at the same time model the solder balls for soldering the chip to the encapsulation substrate, to obtain an encapsulation model.

[0142] S106. Obtain the average equivalent stress of each solder ball in the encapsulation model, and obtain the stress variance value according to the average equivalent stress.

[0143] In step S106, define the number of solder balls in the encapsulation model as n , and the average equivalent stress of each solder ball is respectively F 1 , F 2 ,..., F n , and the stress variance value is St 2 , satisfying the following relationship:

[0144] ;

[0145] 。

[0146] S107. Repeat steps S103 - S106 until the number of repetitions is equal to the number of iterations, to obtain multiple encapsulation schemes and the corresponding stress variance values.

[0147] S108. Select one encapsulation scheme corresponding to the minimum stress variance value as the optimized encapsulation scheme, and output the encapsulation position of the chip encapsulated on the encapsulation substrate corresponding to the optimized encapsulation scheme.

[0148] The computer device 300 provided by the embodiment of the present invention can implement the steps in the method in the above - mentioned embodiment, and can achieve the same technical effects. Refer to the description in the above - mentioned embodiment, and details are not described herein again.

[0149] An embodiment of the present invention further provides a computer-readable storage medium, on which an encapsulation reliability optimization program based on position optimization is stored. When the encapsulation reliability optimization program based on position optimization is executed by a processor, it implements each process and step in the method provided by the embodiment of the present invention, and can achieve the same technical effects. To avoid repetition, it will not be elaborated here.

[0150] Those of ordinary skill in the art can understand that all or part of the processes of implementing the above embodiment methods can be completed by instructing relevant hardware (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) through an encapsulation reliability optimization program based on position optimization. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the above-mentioned method embodiments. Among them, the storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM, for short), etc.

[0151] It should be noted that in this article, the terms "include", "comprise", or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article, or device. Without more limitations, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article, or device including the element.

[0152] The embodiments of the present invention have been described above with reference to the accompanying drawings. What is disclosed is only the preferred embodiments of the present invention. However, the present invention is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present invention, those of ordinary skill in the art can still make many equivalent changes in form without departing from the purpose of the present invention and the scope protected by the claims, and all belong to the protection scope of the present invention.

Claims

1. A packaging reliability optimization method based on position optimization, characterized in that: The following steps are involved: S101, obtaining a first shape of a packaging substrate and a second shape of a chip to be packaged, wherein the first shape and the second shape include a length and a width; S102, gridding the packaging substrate according to the first shape and the second shape to obtain a gridded packaging substrate, and determining the number of iterations according to the gridding degree of the packaging substrate; S103, arranging the chips on the grid packaging substrate in a random arrangement manner to obtain a packaging solution; S104, determining whether the packaging solution meets the preset chip layout rule, if so, executing step S105; If not, return to step S103; S105, based on the packaging solution, modeling the chip and the packaging substrate, and simultaneously modeling the solder balls for soldering the chip to the packaging substrate, to obtain a packaging model; S106, obtaining an average equivalent stress of each solder ball based on the packaging model, and obtaining a stress variance value according to the average equivalent stress; S107, repeating steps S103-S106 until the number of repetitions is equal to the number of iterations, to obtain a plurality of the packaging solutions and the corresponding stress variance values; S108, selecting a corresponding packaging solution as an optimized packaging solution according to the stress variance value with the smallest value, and outputting a packaging position of the chip corresponding to the optimized packaging solution on the packaging substrate; Wherein, in step S102, the grid size for gridding the packaging substrate is determined according to the second shapes of the plurality of chips, and the length and width of the plurality of chips are defined as ( a 1, b 1) ( a 2, b 2) … a n , b n ), the common divisor of the length and width of the plurality of said chips is k , the grid size and the common divisor k The length and width of the packaging substrate are equal to ( A , B ), the number of chips is n , the number of iterations is N , satisfying the following relationship: ； The preset chip arrangement rule is: different chips are arranged on the grid packaging substrate without overlapping each other; A plane coordinate system is constructed with the top corner of the grid packaging substrate as the origin to define any first chip arranged on the grid packaging substrate. R1 , Second chip R2 The series of coordinates of the lower left corner and the upper right corner in the plane coordinate system are R1=[x11,y11,x12,y12] , R2=[x21,y21,x22,y22] When any one of the following relations is satisfied, the packaging solution satisfies the preset chip layout rule: R1[2] ≤ R2[0] ； R1[0] ≥ R2[2] ； R1[3] ≤ R2[1] ； R1[1] ≥ R2[3] ； Or: when different chips are arranged on the grid packaging substrate, the spacing between them is not less than the preset packaging spacing; A plane coordinate system is constructed with the top corner of the grid packaging substrate as the origin to define any first chip arranged on the grid packaging substrate. R1 , Second chip R2 The series of coordinates of the lower left corner and the upper right corner in the plane coordinate system are R1=[x11,y11,x12,y12] , R2=[x21,y21,x22,y22] , the preset package spacing is GP When any one of the following relations is satisfied, the packaging solution satisfies the preset chip layout rule: R1[2] ≤ R2[0], GP ≤ R2[0] - R1[2] ； R2[2] ≤ R1[0], GP ≤ R1[0] - R2[2] ； R1[3] ≤ R2[1], GP ≤ R2[1] - R1[3] ； R2[3] ≤ R1[1], GP ≤ R1[1] - R2[3] 。 2. The packaging reliability optimization method based on position optimization according to claim 1, characterized in that: In step S106, the number of solder balls in the package model is defined as n , the average equivalent stress of each solder ball is F 1. F 2. … F n , the stress variance value is St 2 , satisfying the following relationship: ； 。 3. A packaging reliability optimization system based on position optimization, characterized in that: include: An initialization module, used to obtain a first shape of a packaging substrate and a second shape of a chip to be packaged, wherein the first shape and the second shape include a length and a width; A gridding module, used for gridding the packaging substrate according to the first shape and the second shape to obtain a gridded packaging substrate, and determining the number of iterations according to the gridding degree of the packaging substrate; A random arrangement module, used to arrange the chips on the grid packaging substrate in a random arrangement manner to obtain a packaging solution; A judging module, used to judge whether the packaging solution meets the preset chip arrangement rule, and if so, execute the modeling module; If not, return to the random arrangement module; A modeling module, used to model the chip and the packaging substrate based on the packaging solution, and simultaneously model the solder balls used to solder the chip to the packaging substrate, to obtain a packaging model; A stress simulation module, used for obtaining an average equivalent stress of each solder ball based on the packaging model, and obtaining a stress variance value according to the average equivalent stress; An iterative control module, used for repeatedly executing the random arrangement module, the judgment module, the modeling module and the stress simulation module in sequence until the number of repetitions is equal to the number of iterations, so as to obtain a plurality of the packaging schemes and the corresponding stress variance values; An output module, used for selecting a corresponding packaging scheme as an optimized packaging scheme according to the stress variance value with the smallest numerical value, and outputting a packaging position of the chip packaged on the packaging substrate corresponding to the optimized packaging scheme; The random arrangement module is also used to determine the grid size for gridding the packaging substrate according to the second shapes of the plurality of chips, and define the length and width of the plurality of chips as ( a 1, b 1) ( a 2, b 2) … a n , b n ), the common divisor of the length and width of the plurality of said chips is k , the grid size and the common divisor k The length and width of the packaging substrate are equal to ( A , B ), the number of chips is n , the number of iterations is N , satisfying the following relationship: ； The preset chip arrangement rule is: different chips are arranged on the grid packaging substrate without overlapping each other; A plane coordinate system is constructed with the top corner of the grid packaging substrate as the origin to define any first chip arranged on the grid packaging substrate. R1 , Second chip R2 The series of coordinates of the lower left corner and the upper right corner in the plane coordinate system are R1=[x11,y11,x12,y12] , R2=[x21,y21,x22,y22] When any one of the following relations is satisfied, the packaging solution satisfies the preset chip layout rule: R1[2] ≤ R2[0] ； R1[0] ≥ R2[2] ； R1[3] ≤ R2[1] ； R1[1] ≥ R2[3] ； Or: when different chips are arranged on the grid packaging substrate, the spacing between them is not less than the preset packaging spacing; A plane coordinate system is constructed with the top corner of the grid packaging substrate as the origin to define any first chip arranged on the grid packaging substrate. R1 , Second chip R2 The series of coordinates of the lower left corner and the upper right corner in the plane coordinate system are R1=[x11,y11,x12,y12] , R2=[x21,y21,x22,y22] , the preset package spacing is GP When any one of the following relations is satisfied, the packaging solution satisfies the preset chip layout rule: R1[2] ≤ R2[0], GP ≤ R2[0] - R1[2] ； R2[2] ≤ R1[0], GP ≤ R1[0] - R2[2] ； R1[3] ≤ R2[1], GP ≤ R2[1] - R1[3] ； R2[3] ≤ R1[1], GP ≤ R1[1] - R2[3] 。 4. The packaging reliability optimization system based on position optimization according to claim 3 is characterized in that: The stress simulation module is also used to define the number of solder balls in the packaging model as n , the average equivalent stress of each solder ball is F 1. F 2. … F n , the stress variance value is St 2 , satisfying the following relationship: ； 。 5. A computer device, characterized in that: include: A memory, a processor, and a packaging reliability optimization program based on position optimization stored in the memory and executable on the processor, wherein the processor implements the steps of the packaging reliability optimization method based on position optimization as described in any one of claims 1 to 2 when executing the packaging reliability optimization program based on position optimization.

6. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a packaging reliability optimization program based on position optimization, and when the packaging reliability optimization program based on position optimization is executed by a processor, the steps in the packaging reliability optimization method based on position optimization as described in any one of claims 1-2 are implemented.

Images