Display panel

Abstract

The present invention provides a display panel, comprising a plurality of sub-pixels, a plurality of storage modules, and a plurality of grayscale control modules. Each storage module is electrically connected to the pixel drive circuits of the plurality of sub-pixels, each grayscale control module is electrically connected to a storage module, and each grayscale control module comprises a plurality of grayscale control groups, each grayscale control group being electrically connected between a corresponding storage module and the pixel drive circuit of a sub-pixel. By causing each storage module to store or output an image data signal upon receiving a corresponding scan signal and a bit signal, and each grayscale control group to generate a grayscale control signal upon receiving a plurality of corresponding clock signals and image data signals and output it to the pixel drive circuit of the corresponding sub-pixel, time-sharing control of the light emission durations of different sub-pixels is achieved, enabling multiple sub-pixels to share a single storage module and a single grayscale control module, thereby reducing the number of transistors included in the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel. Background Art

[0002] Existing silicon-based microdisplays typically include driver circuits and light-emitting devices. The luminescent materials of micro-LEDs, organic light-emitting diodes, and other types of light-emitting devices can be grown on a silicon substrate to create a silicon-based microdisplay. Digital subfield scanning technology is often used to drive displays for micro-LEDs or sub-millimeter LEDs. However, this technology requires more peripheral storage space, high power consumption due to read and write caching, and high clock speed requirements.

[0003] Existing sub-pixels use embedded pixel storage units to store data related to the driving of light-emitting elements. This improves the sub-field scanning technology's need for more peripheral storage space, power consumption due to read / write buffering, and higher clock rate requirements. However, the size of the embedded pixel storage unit is determined by the number of bits of image data. Each static random access memory (SRAM) cell in the embedded pixel storage unit uses at least four transistors to store one bit of data. Therefore, the more bits of image data there are, the larger the number of transistors used in the embedded pixel storage unit.

[0004] However, to meet the demand for high pixel density in micro-displays, each sub-pixel needs to integrate multi-bit storage units and functional modules, which requires the wafer fab to have very high process preparation precision. The process is difficult and the preparation cost is also high, which poses a great challenge to achieving the goal of high pixel density specifications. Summary of the Invention

[0005] An embodiment of the present invention provides a display panel that can improve the problem that under high pixel density requirements, each sub-pixel needs to integrate multiple-bit storage units and functional modules, resulting in a large number of transistors included in the display panel and high requirements for wafer fab process.

[0006] An embodiment of the present invention provides a display panel, comprising a display panel, wherein the display panel includes a plurality of sub-pixels, a plurality of storage modules, and a plurality of grayscale control modules. Each of the sub-pixels includes a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light; each of the storage modules is electrically connected to the pixel driving circuits of the plurality of sub-pixels, and each of the storage modules is configured to receive corresponding scan signals and bit signals to store or output image data signals. Each of the grayscale control modules is electrically connected to a storage module, and each of the grayscale control modules includes a plurality of grayscale control groups, each of the grayscale control groups is electrically connected between a corresponding storage module and the pixel driving circuit of a sub-pixel, and each of the grayscale control groups is configured to receive corresponding multiple clock signals and the image data signals to generate grayscale control signals and output them to the corresponding pixel driving circuit.

[0007] An embodiment of the present invention provides a display panel comprising a plurality of sub-pixels, a plurality of storage modules, and a plurality of grayscale control modules. Each storage module is electrically connected to the pixel driving circuits of the plurality of sub-pixels, each grayscale control module is electrically connected to a storage module, and each grayscale control module includes a plurality of grayscale control groups, each grayscale control group being electrically connected between a corresponding storage module and the pixel driving circuit of a sub-pixel. By causing each storage module to store or output an image data signal upon receiving a corresponding scan signal and a bit signal, and each grayscale control group to generate a grayscale control signal upon receiving a plurality of corresponding clock signals and image data signals and output it to the pixel driving circuit of the corresponding sub-pixel, time-sharing control of the light-emitting durations of different sub-pixels is achieved. Multiple sub-pixels can share a single storage module and a single grayscale control module, thereby reducing the number of transistors included in the display panel and improving the problem that, under high pixel density requirements, each sub-pixel must integrate multiple-bit storage units and functional modules, resulting in a large number of transistors included in the display panel and high wafer fab process requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0009] Figure 1 This is a schematic diagram of the micro display panel driving backplane structure in the prior art;

[0010] Figure 2 This is a schematic diagram of sub-field segmentation corresponding to 256 gray levels in the prior art;

[0011] Figure 3It is a schematic diagram of the structure of a pixel driving circuit in the prior art;

[0012] Figure 4 This is a schematic diagram of the structure of a pixel internal storage module in the prior art;

[0013] Figure 5 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0014] Figures 6A to 6C Schematic diagram of the corresponding relationship between the storage module and the sub-pixel provided by an embodiment of the present invention;

[0015] Figures 7A to 7C Schematic diagram of the connection structure of sub-pixels, storage modules and grayscale control modules provided by an embodiment of the present invention;

[0016] Figure 8 is a schematic structural diagram of a storage unit provided by an embodiment of the present invention;

[0017] Figure 9 1 is a schematic structural diagram of an inverting unit provided in an embodiment of the present invention;

[0018] Figure 10 This is a timing diagram provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In the present invention, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.

[0020] Specifically, Figure 1 This is a schematic diagram of a conventional micro-display panel driver backplane structure. A frame buffer 101 is designed around the display area 10a to store bit-plane data (e.g., n-bit byte data, such as Bit 0, Bit 1, ..., Bit n). The display unit includes sub-pixels Pi, each of which includes a light-emitting device (LED). Optionally, a power management chip 102, a source driver chip 103, a gate driver chip 104, and a timing controller 105 are also located around the display area 10a.

[0021] In the prior art, after video source data is input, it needs to be processed in a certain manner (such as image scaling, image mirroring / flipping, etc.). Therefore, a compression algorithm is generally used to first store the image data, then process the image data, and then decompress the data and transmit it to the bit plane data storage module (i.e., frame buffer 101) to achieve image data storage. The size of the frame buffer 101 is at least the number of pixels × color depth, and the image data is stored in a bit plane manner. After that, at least 8 subfields are required to read the data in the frame buffer 101 and write it to each pixel circuit in the display area 10a. The data flow processing is relatively cumbersome, and the power consumption of data reading and writing is also relatively high. In addition, the frame buffer 101 needs to occupy a certain area, which makes the border of the display screen larger, thereby affecting the overall module size and weight of the micro display device.

[0022] Figure 2 This is a schematic diagram of the subfield segmentation corresponding to 256 grayscales in the prior art. In the existing digital subfield scanning method, a frame of display data 1F includes multiple subframes, each with a different weighting value, so that the duration of the light-emitting device LED (i.e., the light-emitting phase t1) within each subframe is different. Each subframe includes a data writing phase ta and a light-emitting phase t1.

[0023] The weight value of each subframe can be set in a standard binary weight value increment or a non-standard binary weight value increment. For example, a frame 1F display data includes 8 subframes, namely subframe F1, subframe F2, subframe F3, subframe F4, subframe F5, subframe F6, subframe F7 and subframe F8. The standard binary weight value increment method is used, and the weight value ratio of each subframe is 1=2 0 、2=2 1 、4=2 2 、8=2 3 、16=2 4 、32=2 5 、64=2 6 、128=2 7 The display data of one frame 1F is the grayscale superposition of each subframe to achieve 256 grayscale display.

[0024] In order to improve the luminance of the display unit at the L255 grayscale, when the scanning signal scans each row of display units, the display units in each row can emit light immediately after the addressing scanning time, and each display unit can continue to emit light during the driving time of the entire frame display image.

[0025] like Figure 3 FIG. 1 is a schematic diagram of a pixel driving circuit structure in the prior art. Figure 4This is a schematic diagram of the internal pixel storage module structure in the prior art. The pixel drive circuit includes a one-byte static random access memory (1-bit SRAM) structure. Specifically, the pixel drive circuit includes a signal receiving module 8, a signal storage module 9, a light-emitting switch module 10, and a current regulation module 11. The two inverters formed by transistors T7, T8, T9, and T10 are cross-coupled to form a bistable flip-flop circuit (i.e., a one-byte static random access memory structure). When the scan driver module in the row scan circuit addresses the pixel drive circuit row by row via the scan signal Scan, transistors T2 and T2' store the column drive signal Data or Data' from the data driver in the bistable flip-flop. Transistor T1 switches the electrical connection between the anode of the light-emitting device LED and the drain electrode of transistor T3 based on the data level on the bistable flip-flop. The cathode of the light-emitting device LED is connected to the drive power supply ground VSS to control the light-emitting device LED's on and off state. The column drive signal Data, combined with the Iref signal that regulates the gate electrode potential of transistor T3, controls the state of the light-emitting device LED. By adjusting the voltage of the signal Iref, VDDIref is controlled to be larger, so that the current flowing through the light-emitting device LED is larger, and then the brightness of the light-emitting device LED is larger. Therefore, the brightness of the light-emitting device LED can be adjusted by adjusting the signal Iref.

[0026] Using embedded pixel storage units (such as Figure 4 M1~M8) in the memory and each sub-pixel Pi (such as Figure 4 Although the sub-field scanning technology can improve the problem of more peripheral storage space and power consumption caused by read and write cache and higher clock rate requirements due to the need for sub-field scanning technology, the design of using embedded pixel storage units to store data related to the driving of light-emitting element LEDs (Pi1 to Pi8) is not suitable for display devices with high pixel density requirements due to the high requirements of process accuracy, frame size, pixel density, etc. for display devices with high pixel density requirements (such as the high PPI specifications required by AR / VR micro-display devices).

[0027] In order to improve the demand for high pixel density, each sub-pixel Pi needs to integrate multiple-bit storage units and functional modules, resulting in a large number of transistors included in the sub-pixel Pi and higher requirements for wafer factory process. The present application provides a display panel that can use an embedded pixel storage unit to store data related to the light-emitting element LED drive, which is suitable for display devices with high pixel density requirements of micro-displays.

[0028] Figure 5 is a schematic structural diagram of a display panel provided by an embodiment of the present invention, Figures 6A to 6C is a schematic diagram of the corresponding relationship between the storage module and the sub-pixel provided in an embodiment of the present invention, Figures 7A to 7CSchematic diagram of the connection structure of the sub-pixel, storage module and grayscale control module provided by the embodiment of the present invention. Figure 7A The n*m ​​in the figure indicates that the storage unit outputs n-bit image data signals m times, and Pi1, Pi2, ..., Pim indicate m sub-pixels.

[0029] The present invention provides a display panel, which includes a plurality of sub-pixels Pi, a plurality of storage modules 2 and a plurality of grayscale control modules 3.

[0030] Optionally, each of the sub-pixels Pi includes a light-emitting device LED and a pixel driving circuit 40 for driving the light-emitting device LED to emit light.

[0031] Optionally, the light emitting device LED includes an organic light emitting diode, a micro light emitting diode or a sub-millimeter light emitting diode, etc.

[0032] Optionally, the pixel driving circuit 40 includes a driving transistor Tdr, wherein an input terminal and an output terminal of the driving transistor Tdr are electrically connected between a first power supply terminal VDD and the light-emitting device LED. Optionally, the input terminal of the driving transistor Tdr is electrically connected to the first power supply terminal VDD, the output terminal of the driving transistor Tdr is electrically connected to an anode of the light-emitting device LED, and a cathode of the light-emitting device LED is electrically connected to a second power supply terminal VSS, wherein a first voltage corresponding to the first power supply terminal VDD is greater than a second voltage corresponding to the second power supply terminal VSS.

[0033] Optionally, the pixel driving circuit 40 includes a current source CS, and the current source CS is electrically connected to the input terminal of the driving transistor Tdr.

[0034] Please continue reading Figure 5 、 Figures 6A to 6C and Figures 7A to 7C Each of the storage modules 2 is electrically connected to the pixel driving circuits 40 of the plurality of sub-pixels Pi, so that the plurality of sub-pixels Pi can share one storage module 2, thereby reducing the number of storage modules 2 used in the display panel and, in turn, reducing the average number of transistors included in each storage module 2 in the display panel. Each of the storage modules 2 is configured to receive a corresponding scan signal Scan and a bit signal to store or output an image data signal.

[0035] Optionally, in order to enable the image data signal stored or output by the storage module 2 to correspond to multiple sub-pixels Pi, so that multiple sub-pixels Pi can realize the display function according to the corresponding image data signal, the storage module 2 stores or outputs the image data signal corresponding to different sub-pixels Pi at different times.

[0036] If the first sub-pixel Pi1 and the second sub-pixel Pi2 included in the multiple sub-pixels Pi share the storage module 2, the moment when the storage module 2 stores or outputs the image data signal corresponding to the first sub-pixel Pi1 and the moment when the storage module 2 stores or outputs the image data signal corresponding to the second sub-pixel Pi2 can be different, so that the first sub-pixel Pi1 and the second sub-pixel Pi2 can match the corresponding image data signals to achieve the display function.

[0037] Please continue reading Figure 5 、 Figures 6A to 6C and Figures 7A to 7C Each of the grayscale control modules 3 is electrically connected to a storage module 2, and each of the grayscale control modules 3 includes a plurality of grayscale control groups (such as Figures 6A to 6C and Figures 7A to 7C 301, 302, 303, 304, ..., 30m), each of the grayscale control groups is electrically connected between the corresponding storage module 2 and the pixel driving circuit 40 of a sub-pixel Pi, and each of the grayscale control groups is configured to receive the corresponding multiple clock signals and the image data signal to generate a grayscale control signal and output it to the corresponding pixel driving circuit 40, so that multiple sub-pixels Pi can share the same grayscale control module 3, and each sub-pixel Pi corresponds to a grayscale control group of the grayscale control module 3, so that the grayscale control group cooperates with the corresponding storage module 2 to generate the grayscale control signal required by the sub-pixel Pi, so that the sub-pixel Pi can realize the display function according to the grayscale control signal.

[0038] By making multiple sub-pixels Pi share a storage module 2 and a grayscale control module 3, the number of storage modules 2 included in the display panel is reduced, and then the number of transistors included in the display panel is reduced, thereby improving the problem that under high pixel density requirements, each sub-pixel Pi needs to integrate multiple-bit storage units and functional modules, resulting in a large number of transistors included in the display panel and higher requirements for wafer factory processes.

[0039] Optionally, see Figure 6A Each storage module 2 is electrically connected to the pixel driving circuits 40 of the m sub-pixels Pi in the same row, and each grayscale control module 3 includes m grayscale control groups. This allows the m sub-pixels Pi in the same row to share the same storage module 2 and the same grayscale control module 3. Furthermore, the m sub-pixels Pi in the same row correspond to m grayscale control groups, thereby reducing the number of storage modules 2 and grayscale control modules 3. Here, m>1.

[0040] Optionally, each of the storage modules 2 is electrically connected to the pixel driving circuits 40 of the three sub-pixels Pi located in the same row, and each of the grayscale control modules 3 includes three grayscale control groups. For example, the multiple storage modules 2 include a first storage module 21 to a fourth storage module 24, the multiple grayscale control modules 3 include a first grayscale control module 31 to a fourth grayscale control module 34, and the multiple sub-pixels Pi include a first sub-pixel Pi1 to a twelfth sub-pixel Pi12; wherein the first sub-pixel Pi1 to the sixth sub-pixel Pi6 are located in the same row, and the seventh sub-pixel Pi7 to the twelfth sub-pixel Pi12 are located in the same row. Then, the first sub-pixel Pi1 to the third sub-pixel Pi3 can share the first storage module 21 and the first grayscale control module 31, and the first grayscale control group 301 of the three grayscale control groups included in the first grayscale control module 31 is electrically connected between the first storage module 21 and the pixel driving circuit 401 of the first sub-pixel Pi1, and the first grayscale control group 301 included in the first grayscale control module 31 is configured to receive the corresponding clock signal and the image data signal output by the first storage module 21 to generate a first grayscale control signal and output it to the pixel driving circuit 401 of the first sub-pixel Pi1; the second grayscale control group 302 of the three grayscale control groups included in the first grayscale control module 31 is electrically connected between the first storage module 21 and the second sub-pixel Pi2 Between the pixel driving circuit 402, the second grayscale control group 302 included in the first grayscale control module 31 is configured to receive the corresponding clock signal and the image data signal output by the first storage module 21 to generate a second grayscale control signal and output it to the pixel driving circuit 402 of the second sub-pixel Pi2; the third grayscale control group 303 among the three grayscale control groups included in the first grayscale control module 31 is electrically connected between the first storage module 21 and the pixel driving circuit 403 of the third sub-pixel Pi3, and the third grayscale control group 303 included in the first grayscale control module 31 is configured to receive the corresponding clock signal and the image data signal output by the first storage module 21 to generate a third grayscale control signal and output it to the pixel driving circuit 403 of the third sub-pixel Pi3.

[0041] Similarly, the fourth sub-pixel Pi4 to the sixth sub-pixel Pi6 can share the second storage module 22 and the second grayscale control module 32, and the first grayscale control group 301 of the three grayscale control groups included in the second grayscale control module 32 is electrically connected between the second storage module 22 and the pixel driving circuit 404 of the fourth sub-pixel Pi4, the second grayscale control group 302 of the three grayscale control groups included in the second grayscale control module 32 is electrically connected between the second storage module 22 and the pixel driving circuit 405 of the fifth sub-pixel Pi5, and the third grayscale control group 303 of the three grayscale control groups included in the second grayscale control module 32 is electrically connected between the second storage module 22 and the pixel driving circuit 406 of the sixth sub-pixel Pi6. Similarly, the seventh sub-pixel Pi7 to the ninth sub-pixel Pi9 can share the third storage module 23 and the third grayscale control module 33, and the first grayscale control group 301 of the three grayscale control groups included in the third grayscale control module 33 is electrically connected between the third storage module 23 and the pixel driving circuit 407 of the seventh sub-pixel Pi7, the second grayscale control group 302 of the three grayscale control groups included in the third grayscale control module 33 is electrically connected between the third storage module 23 and the pixel driving circuit 408 of the eighth sub-pixel Pi8, and the third grayscale control group 303 of the three grayscale control groups included in the third grayscale control module 33 is electrically connected between the third storage module 23 and the pixel driving circuit 409 of the ninth sub-pixel Pi9. Similarly, the tenth sub-pixel Pi10 to the twelfth sub-pixel Pi12 can share the fourth storage module 24 and the fourth grayscale control module 34, and the first grayscale control group 301 of the three grayscale control groups included in the fourth grayscale control module 34 is electrically connected between the fourth storage module 24 and the pixel driving circuit 4010 of the tenth sub-pixel Pi10, the second grayscale control group 302 of the three grayscale control groups included in the fourth grayscale control module 34 is electrically connected between the fourth storage module 24 and the pixel driving circuit 4011 of the eleventh sub-pixel Pi11, and the third grayscale control group 303 of the three grayscale control groups included in the fourth grayscale control module 34 is electrically connected between the fourth storage module 24 and the pixel driving circuit 4012 of the twelfth sub-pixel Pi12.

[0042] Optionally, the plurality of sub-pixels Pi electrically connected to the same storage module 2 and the grayscale control module 3 may be located in the same pixel, so as to cooperate with the demultiplexing circuit to decompose the data signal and synchronously generate clock signals corresponding to each grayscale control group, thereby realizing the coordinated work of the demultiplexing circuit with the storage module 2 and the grayscale control module 3.

[0043] Optionally, the plurality of sub-pixels Pi electrically connected to the same storage module 2 and the grayscale control module 3 may also be located in different pixels to be applicable to various application scenarios.

[0044] Please continue reading Figures 6B to 6C Each storage module 2 is electrically connected to the pixel driving circuits 40 of the m sub-pixels Pi located in adjacent rows, and each grayscale control module 3 includes m grayscale control groups. This allows the m sub-pixels Pi located in adjacent rows to share the same storage module 2 and the same grayscale control module 3, and the m sub-pixels Pi located in adjacent rows correspond to m grayscale control groups, thereby reducing the number of storage modules 2 and grayscale control modules 3. Here, m>1.

[0045] Optionally, the plurality of sub-pixels Pi located in two adjacent rows share the same storage module 2 and the same grayscale control module 3 .

[0046] Optionally, two sub-pixels Pi located in two adjacent rows share the same storage module 2 and the same grayscale control module 3. Figure 6BAs shown, take the example of a plurality of storage modules 2 including a first storage module 21 to a fourth storage module 24, a plurality of grayscale control modules 3 including a first grayscale control module 31 to a fourth grayscale control module 34, and a plurality of sub-pixels Pi including a first sub-pixel Pi1 to an eighth sub-pixel Pi8. The first sub-pixels Pi1 to the fourth sub-pixel Pi4 are located in the same row, and the fifth sub-pixels Pi5 to the eighth sub-pixel Pi8 are located in the same row. Therefore, the first sub-pixel Pi1 and the fifth sub-pixel Pi5 can share the first storage module 21 and the first grayscale control module 31. The first grayscale control group 301 of the two grayscale control groups included in the first grayscale control module 31 is electrically connected between the first storage module 21 and the pixel driving circuit 401 of the first sub-pixel Pi1, and the second grayscale control group 302 of the two grayscale control groups included in the first grayscale control module 31 is electrically connected between the first storage module 21 and the pixel driving circuit 405 of the fifth sub-pixel Pi5. Similarly, the second sub-pixel Pi2 and the sixth sub-pixel Pi6 share the second storage module 22 and the second grayscale control module 32, and the first grayscale control group 301 of the two grayscale control groups included in the second grayscale control module 32 is electrically connected between the second storage module 22 and the pixel driving circuit 402 of the second sub-pixel Pi2, and the second grayscale control group 302 of the two grayscale control groups included in the second grayscale control module 32 is electrically connected between the second storage module 22 and the pixel driving circuit 406 of the sixth sub-pixel Pi6. Similarly, the third sub-pixel Pi3 and the seventh sub-pixel Pi7 share the third storage module 23 and the third grayscale control module 33. The first grayscale control group 301 of the two grayscale control groups included in the third grayscale control module 33 is electrically connected between the third storage module 23 and the pixel driving circuit 403 of the third sub-pixel Pi3, and the second grayscale control group 302 of the two grayscale control groups included in the third grayscale control module 33 is electrically connected between the third storage module 23 and the pixel driving circuit 407 of the seventh sub-pixel Pi7. Similarly, the fourth sub-pixel Pi4 and the eighth sub-pixel Pi8 share the fourth storage module 24 and the fourth grayscale control module 34. The first grayscale control group 301 of the two grayscale control groups included in the fourth grayscale control module 34 is electrically connected between the fourth storage module 24 and the pixel driving circuit 404 of the fourth sub-pixel Pi4, and the second grayscale control group 302 of the two grayscale control groups included in the fourth grayscale control module 34 is electrically connected between the fourth storage module 24 and the pixel driving circuit 408 of the eighth sub-pixel Pi8.

[0047] Optionally, the four sub-pixels Pi located in two adjacent rows share the same storage module 2 and the same grayscale control module 3. Figure 6CAs shown, taking the example of the multiple storage modules 2 including the first storage module 21 and the second storage module 22, the multiple grayscale control modules 3 including the first grayscale control module 31 and the second grayscale control module 32, and the multiple sub-pixels Pi including the first sub-pixel Pi1 to the eighth sub-pixel Pi8, the first sub-pixel Pi1 to the fourth sub-pixel Pi4 are located in the same row, and the fifth sub-pixel Pi5 to the eighth sub-pixel Pi8 are located in the same row. Then, the first sub-pixel Pi1, the second sub-pixel Pi2, the fifth sub-pixel Pi5 and the sixth sub-pixel Pi6 can share the first storage module 21 and the first grayscale control module 31, and the first grayscale control group 301 of the four grayscale control groups included in the first grayscale control module 31 is electrically connected between the first storage module 21 and the pixel driving circuit 401 of the first sub-pixel Pi1, the second grayscale control group 302 of the four grayscale control groups included in the first grayscale control module 31 is electrically connected between the first storage module 21 and the pixel driving circuit 402 of the second sub-pixel Pi2, the third grayscale control group 303 of the four grayscale control groups included in the first grayscale control module 31 is electrically connected between the first storage module 21 and the pixel driving circuit 405 of the fifth sub-pixel Pi5, and the fourth grayscale control group 304 of the four grayscale control groups included in the first grayscale control module 31 is electrically connected between the first storage module 21 and the pixel driving circuit 406 of the sixth sub-pixel Pi6. Similarly, the third sub-pixel Pi3, the fourth sub-pixel Pi4, the seventh sub-pixel Pi7 and the eighth sub-pixel Pi8 share the second storage module 22 and the second grayscale control module 32, the first grayscale control group 301 of the four grayscale control groups included in the second grayscale control module 32 is electrically connected between the second storage module 22 and the pixel driving circuit 403 of the third sub-pixel Pi3, the second grayscale control group 302 of the four grayscale control groups included in the second grayscale control module 32 is electrically connected between the second storage module 22 and the pixel driving circuit 404 of the fourth sub-pixel Pi4, the third grayscale control group 303 of the four grayscale control groups included in the second grayscale control module 32 is electrically connected between the second storage module 22 and the pixel driving circuit 407 of the seventh sub-pixel Pi7, and the fourth grayscale control group 304 of the four grayscale control groups included in the second grayscale control module 32 is electrically connected between the second storage module 22 and the pixel driving circuit 408 of the eighth sub-pixel Pi8.

[0048] Understandably, Figures 6A to 6CThis is merely an example of multiple sub-pixels Pi sharing the same storage module 2 and the same grayscale control module 3. In some embodiments, the multiple sub-pixels Pi sharing the same storage module 2 and the same grayscale control module 3 are distributed in the same row or in different rows, and / or in the same column or in different columns. When the multiple sub-pixels Pi sharing the same storage module 2 and the same grayscale control module 3 are distributed in different rows and / or columns, the multiple sub-pixels Pi may be adjacent or non-adjacent.

[0049] Please continue reading Figures 7A to 7C Each of the storage modules 2 includes a plurality of storage units 20 (such as Figure 7C , 201, 202, ..., 20n in the figure), a plurality of the storage units 20 are electrically connected to a scan line SL, each of the storage units 20 is electrically connected to a corresponding first bit line l1 and second bit line l2, and each of the storage units 20 is configured to output a bit data signal according to a scan signal Scan transmitted by the scan line SL, a first bit signal transmitted by the first bit line l1, and a second bit signal transmitted by the second bit line l2; wherein the image data signal includes the bit data signals output by a plurality of the storage units.

[0050] Optionally, the first bit signal transmitted by the first bit line and the second bit signal transmitted by the second bit line are in opposite phases. The bit data signal corresponds to a state of 0 or 1.

[0051] like Figure 7C Each of the storage modules 2 includes n storage cells, each of which is electrically connected to a scan line SL. The first storage cell 201 among the n storage cells is electrically connected to a first bit line 111, and the first storage cell 201 among the n storage cells is electrically connected to a second bit line 121. The second storage cell 202 among the n storage cells is electrically connected to a first bit line 112, and the second storage cell 202 among the n storage cells is electrically connected to a second bit line 122, ..., the nth storage cell 20n is electrically connected to a first bit line 11n, and the nth storage cell 20n is electrically connected to a second bit line 12n. The image data signal includes the bit data signals output by the n storage cells 20.

[0052] Optionally, each of the storage units 20 may include a 1-byte static random access memory. Accordingly, when the storage module 2 includes n storage units 20, the storage module 2 is an n-byte static random access memory.

[0053] Optionally, see Figure 82 is a schematic structural diagram of a memory cell 20 provided in an embodiment of the present invention. The memory cell 20 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6.

[0054] The control terminal of the first transistor M1 is electrically connected to the corresponding scan line SL, the input terminal of the first transistor M1 is electrically connected to the corresponding first bit line l1, and the output terminal of the first transistor M1 is electrically connected to the grayscale control unit included in the corresponding grayscale control module 3.

[0055] Optionally, the output terminal of the first transistor M1 (ie Figure 8 The Q point in the grayscale control unit is electrically connected to the input end of the switching transistor Ts included in the corresponding grayscale control unit.

[0056] A control terminal of the second transistor M2 is electrically connected to the corresponding scan line SL, and an input terminal of the second transistor M2 is electrically connected to the corresponding second bit line I2.

[0057] The control end of the third transistor M3 is electrically connected to the output end of the first transistor M1 , the input end of the third transistor M3 is electrically connected to the first power supply end VDD, and the output end of the third transistor M3 is electrically connected to the output end of the second transistor M2 .

[0058] The control terminal of the fourth transistor M4 is electrically connected to the output terminal of the first transistor M1 , the input terminal of the fourth transistor M4 is electrically connected to the second power supply terminal VSS, and the output terminal of the fourth transistor M4 is electrically connected to the output terminal of the second transistor M2 .

[0059] The control end of the fifth transistor M5 is electrically connected to the output end of the second transistor M2 , the input end of the fifth transistor M5 is electrically connected to the first power supply end VDD, and the output end of the fifth transistor M5 is electrically connected to the output end of the first transistor M1 .

[0060] The control end of the sixth transistor M6 is electrically connected to the output end of the second transistor M2 , the input end of the sixth transistor M6 is electrically connected to the second power supply end VSS, and the output end of the sixth transistor M6 is electrically connected to the output end of the first transistor M1 .

[0061] Please continue reading Figure 5 、 Figures 6A to 6C and Figures 7A to 7C Each of the grayscale control groups includes a plurality of grayscale control units (such as Figure 7CThe first grayscale control group 301 includes grayscale control units 3011, 3012, ..., 301n; the second grayscale control group 302 includes grayscale control units 3021, 3022, ..., 302n) and an inverting unit (such as Figure 7C The first grayscale control group 301 includes an inverting unit 3031; the second grayscale control group 302 includes an inverting unit 3032).

[0062] Each of the grayscale control units is electrically connected to a storage unit 20 and a corresponding clock signal line. Each of the grayscale control units is configured to electrically connect the inverting unit and the corresponding storage unit 20 according to the clock signal transmitted by the clock signal line.

[0063] Optionally, each of the grayscale control units includes a switch transistor Ts, a control end of the switch transistor Ts is electrically connected to the corresponding clock signal line, and an input end of the switch transistor Ts is electrically connected to the corresponding storage unit 20 .

[0064] The inverting unit is electrically connected between the plurality of grayscale control units and the pixel driving circuit 40 of the corresponding sub-pixel Pi. The inverting unit is configured to receive the bit data signal PWM outputted by the corresponding storage unit 20 and output the grayscale control signal.

[0065] like Figure 9 1 is a structural schematic diagram of an inverting unit provided in an embodiment of the present invention, wherein the inverting unit includes a first inverting transistor M7 and a second inverting transistor M8, wherein the control ends of the first inverting transistor M7 and the second inverting transistor M8 are electrically connected to the output ends of the corresponding switching transistor Ts, and the output ends of the first inverting transistor M7 and the second inverting transistor M8 are electrically connected to the pixel driving circuit 40 of the corresponding sub-pixel Pi.

[0066] Optionally, the control terminal of the driving transistor Tdr is connected to the output terminal of the first inverting transistor M7 and the second inverting transistor M8 included in the corresponding inverting unit (ie Figure 9 Point O in the diagram is electrically connected.

[0067] Optionally, x sub-pixels Pi share one storage module 2 and one grayscale control module 3, each storage module 2 includes n storage units 20, each grayscale control module 3 includes x grayscale control groups, and each grayscale control group includes n grayscale control units. Accordingly, the display panel includes multiple clock signal transmission modules, each clock signal transmission module includes x clock signal transmission groups, each clock signal transmission group includes n clock signal lines, and the n clock signal lines are electrically connected to the n grayscale control units, so that each grayscale control unit is electrically connected to a corresponding clock signal line and then receives a corresponding clock signal. Wherein, n ≥ 1, x > 1.

[0068] like Figure 7CAs shown, it is taken as an example that two sub-pixels Pi share one storage module 2 and one grayscale control module 3, the storage module 2 includes n storage units 20, each grayscale control module 3 includes two grayscale control groups, and each grayscale control group includes n grayscale control units. The grayscale control module 3 includes a first grayscale control group 301 and a second grayscale control group 302. The clock signal transmission module includes a first clock signal transmission group and a second clock signal transmission group. The first clock signal transmission group includes n clock signal lines CKL11, CKL12, ..., CKL1n, and the second clock signal transmission group includes n clock signal lines CKL21, CKL22, ..., CKL2n. The first clock signal line CKL11 included in the first clock signal transmission group is electrically connected to the control end of the switch transistor Ts included in the first grayscale control unit 3011 in the first grayscale control group 301. The second clock signal line CKL12 included in the first clock signal transmission group is electrically connected to the control end of the switch transistor Ts included in the second grayscale control unit 3012 in the first grayscale control group 301. ..., the nth clock signal line CKL1n included in the first clock signal transmission group is electrically connected to the nth grayscale control unit 301 in the first grayscale control group 301. 1n included in the switching transistor Ts; the first clock signal line CKL21 included in the second clock signal transmission group is electrically connected to the control end of the switching transistor Ts included in the first grayscale control unit 3021 in the second grayscale control group 302, the second clock signal line CKL22 included in the second clock signal transmission group is electrically connected to the control end of the switching transistor Ts included in the second grayscale control unit 3022 in the second grayscale control group 302, ..., the n-th clock signal line CKL2n included in the second clock signal transmission group is electrically connected to the control end of the switching transistor Ts included in the n-th grayscale control unit 302n in the second grayscale control group 302, so that the multiple grayscale control units included in the first grayscale control group 301 are electrically connected to the multiple clock signal lines included in the first clock signal transmission group, and the multiple grayscale control units included in the second grayscale control group 302 are electrically connected to the multiple clock signal lines included in the second clock signal transmission group, and then receive corresponding clock signals.

[0069] Optionally, by controlling the effective pulse output sequence and pulse width of the effective pulses of the clock signals received by the multiple grayscale control groups included in each grayscale control module 3, time-sharing drive control of the luminous duration of each sub-pixel Pi corresponding to multiple sub-fields can be achieved, so that each pixel in the display panel can independently achieve multi-grayscale display.

[0070] Taking the example of two sub-pixels Pi sharing one storage module 2 and one grayscale control module 3, the multiple sub-pixels Pi include a first sub-pixel Pi1 and a second sub-pixel Pi2, the multiple storage modules 2 include a first storage module 21, the multiple clock signals include a plurality of first clock signals CK1 and a plurality of second clock signals CK2, and the multiple grayscale control groups included in the grayscale control module 3 include a first grayscale control group 301 and a second grayscale control group 302. The first sub-pixel Pi1 and the second sub-pixel Pi2 share the first storage module 21; the first clock signal transmission group includes n clock signal lines CKL11, CKL12, ..., CKL1n for transmitting the multiple first clock signals CK1, and the second clock signal transmission group includes n clock signal lines CKL21, CKL22, ..., CKL2n for transmitting the multiple second clock signals CK2.

[0071] The first grayscale control group 301 is electrically connected between the first storage module 21 and the pixel driving circuit 401 of the first sub-pixel Pi1. The first grayscale control group 301 is configured to receive a plurality of the first clock signals CK1 and the corresponding image data signals to generate a first grayscale control signal and output it to the corresponding first sub-pixel Pi1. The second grayscale control group 302 is electrically connected between the first storage module 21 and the pixel driving circuit 402 of the second sub-pixel Pi2. The second grayscale control group 302 is configured to receive a plurality of the second clock signals CK2 and the corresponding image data signals to generate a second grayscale control signal and output it to the corresponding second sub-pixel Pi2.

[0072] Among them, the valid pulses of multiple second clock signals CK2 lag behind the valid pulses of multiple first clock signals CK1, so that the switching transistors Ts included in the multiple first grayscale control units 3011, 3012, ..., 301n included in the first grayscale control group 301 and the switching transistors Ts included in the multiple second grayscale control units 3021, 3022, ..., 302n included in the second grayscale control group 302 are turned on in a time-sharing manner, so that the image data signal output by the first storage module 21 matches the first sub-pixel Pi1 and the second sub-pixel Pi2, so that the first sub-pixel Pi1 and the second sub-pixel Pi2 can be displayed according to the corresponding image data signal, thereby realizing the time-sharing drive control of the first sub-pixel Pi1 and the second sub-pixel Pi2.

[0073] Optionally, the plurality of grayscale control units included in at least one of the grayscale control modules 3 include at least a first grayscale control unit (eg Figure 7C 3011 in) and the second grayscale control unit (such as Figure 7C3012); wherein, the effective pulse of the clock signal received by the second grayscale control unit lags behind the effective pulse of the clock signal received by the first grayscale control unit, and the pulse width of the effective pulse of the clock signal received by the second grayscale control unit is smaller than the pulse width of the effective pulse of the clock signal received by the first grayscale control unit, so that the display panel can control the light-emitting duration of multiple sub-fields corresponding to the sub-pixel Pi.

[0074] Taking the first grayscale control group 301 including multiple grayscale control units corresponding to receiving multiple first clock signals CK1 as an example, the pulse width of the effective pulses of the multiple first clock signals CK1 will be described. The multiple grayscale control units included in the first grayscale control module 31 include at least a first grayscale control unit 3011 and a second grayscale control unit 3012. The first clock signal received by the first grayscale control unit 3011 is CK11, and the first clock signal received by the second grayscale control unit 3012 is CK12. Therefore, the effective pulse of the first clock signal CK12 received by the second grayscale control unit 3012 lags behind the effective pulse of the first clock signal CK11 received by the first grayscale control unit 3011, and the pulse width of the effective pulse of the first clock signal CK12 received by the second grayscale control unit 3012 is smaller than the pulse width of the effective pulse of the first clock signal CK11 received by the first grayscale control unit 3011.

[0075] Specifically, if Figure 10 FIG2 is a timing diagram of two sub-pixels Pi provided by an embodiment of the present invention sharing a storage module 2 and a grayscale control module 3. In this diagram, T represents a period, SF1 to SFn represent sub-fields, n corresponds to the number of grayscale control units included in the grayscale control module 3, and 1F represents a frame.

[0076] Please continue reading Figure 7C and Figure 10 Still taking the case where the first sub-pixel Pi1 and the second sub-pixel Pi2 share the storage module 2, the first grayscale control group 301 is electrically connected between the storage module 2 and the pixel driving circuit 401 of the first sub-pixel Pi1, and the first grayscale control group 301 receives a plurality of the first clock signals CK1 and the corresponding image data signals; the second grayscale control group 302 is electrically connected between the storage module 2 and the pixel driving circuit 402 of the second sub-pixel Pi2, and the second grayscale control group 302 receives a plurality of the second clock signals CK2 and the corresponding image data signals as an example, the working principle of driving the first sub-pixel Pi1 and the second sub-pixel Pi2 in this application is explained.

[0077] A frame duration of 1F includes a first portion for driving the first sub-pixel Pi1 and a second portion for driving the second sub-pixel Pi2, wherein both the first portion and the second portion include a data writing period t1 and a light-emitting period t2. The storage module 2 shared by the first sub-pixel Pi1 and the second sub-pixel Pi2 writes image data signals twice within a frame duration of 1F to respectively determine the bit data signals corresponding to the light-emitting durations of the first sub-pixel Pi1 and the second sub-pixel Pi2. After the bit data signal corresponding to the first sub-pixel Pi1 is transmitted to the storage module 2, the corresponding bit data signals (such as Figure 10 1 in the image data signal), then the multiple grayscale control units included in the first grayscale control group 301 receive the multiple first clock signals CK11~CK1n in response, and turn on the storage units 20 at different bits in the storage module 2 in turn, and determine the turn-on time of each bit according to different byte bits, to generate a first inverted grayscale control signal PWM1 for controlling the light-emitting time of the first sub-pixel Pi1. The first inverted grayscale control signal PWM1 is inverted by the first inverting unit 3031 included in the first grayscale control group 301 to generate a first grayscale control signal for controlling the light-emitting time of the first sub-pixel Pi1. The first grayscale control signal is output to the control end of the driving transistor Tdr1 of the first sub-pixel Pi1, directly controlling the switching time of the driving transistor Tdr1 of the first sub-pixel Pi1. The current source CS controls the current flowing through the driving transistor Tdr1, thereby determining the brightness (i.e., grayscale) that can be finally achieved by the light-emitting device LED1 in the first sub-pixel Pi1.

[0078] After the first sub-pixel Pi1 finishes emitting light, the bit data signal that determines the emitting time of the second sub-pixel Pi2 is written into the multiple storage units 20 of the storage module 2. Similarly, the bit data signal (such as Figure 101 in the storage module 2), the plurality of grayscale control units included in the second grayscale control group 302 receive the plurality of second clock signals CK21~CK2n in response to the image data signal formed by the n-bit data 101…1 in the storage module 2, and turn on the storage units 20 located at different bits in the storage module 2 in turn, and determine the turn-on duration of each bit according to the different bits, and generate a second inverted grayscale control signal PWM2 for controlling the light-emitting duration of the second sub-pixel Pi2. The second inverted grayscale control signal PWM2 is inverted by the second inverting unit 3032 included in the second grayscale control group 302 to generate a second grayscale control signal for controlling the light-emitting duration of the second sub-pixel Pi2. The second grayscale control signal is output to the control end of the driving transistor Tdr2 of the second sub-pixel Pi2, directly controlling the switching time of the driving transistor Tdr2 of the second sub-pixel Pi2, and the current source CS controls the current flowing through the driving transistor Tdr2, thereby determining the brightness (i.e., grayscale) that can be finally achieved by the light-emitting device LED2 in the second sub-pixel Pi2.

[0079] Similarly, the working principle that more than two sub-pixels Pi share one storage module 2 and one grayscale control module 3 can also be obtained.

[0080] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A display panel, characterized in that: include: A plurality of sub-pixels, each of the sub-pixels comprising a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light; a plurality of storage modules, each of the storage modules being electrically connected to the pixel driving circuits of a plurality of the sub-pixels, and each of the storage modules being configured to receive a corresponding scanning signal and a bit signal to store or output an image data signal; Multiple grayscale control modules, each of the grayscale control modules is electrically connected to a storage module, each of the grayscale control modules includes multiple grayscale control groups, each of the grayscale control groups is electrically connected between the corresponding storage module and the pixel driving circuit of a sub-pixel, and each of the grayscale control groups is configured to receive corresponding multiple clock signals and the image data signal to generate a grayscale control signal and output it to the corresponding pixel driving circuit.

2. The display panel according to claim 1, wherein: Each of the storage modules comprises: A plurality of storage units, wherein the plurality of storage units are electrically connected to a scan line, each of the storage units is electrically connected to a corresponding first bit line and a second bit line, and each of the storage units is configured to store or output a bit data signal based on the scan signal transmitted by the scan line, the first bit signal transmitted by the first bit line, and the second bit signal transmitted by the second bit line; wherein the image data signal includes the bit data signals output by the plurality of storage units.

3. The display panel according to claim 2, wherein: Each of the grayscale control groups includes: A plurality of grayscale control units, each of the grayscale control units being electrically connected to one of the storage units and a corresponding clock signal line; an inverting unit electrically connected between the plurality of grayscale control units and the pixel driving circuits of the corresponding sub-pixels; Among them, each grayscale control unit is configured to electrically connect the inverting unit and the corresponding storage unit according to the clock signal transmitted by the clock signal line, and the inverting unit is configured to receive the bit data signal output by the corresponding storage unit and output the grayscale control signal.

4. The display panel according to any one of claims 1 to 3, wherein: Each of the storage modules is electrically connected to the pixel driving circuits of the m sub-pixels in the same row, and each of the grayscale control modules includes m grayscale control groups, wherein m>1.

5. The display panel according to any one of claims 1 to 3, wherein: Each of the storage modules is electrically connected to the pixel driving circuits of m sub-pixels located in adjacent rows, and each of the grayscale control modules includes m grayscale control groups; wherein m>1.

6. The display panel according to claim 3, wherein: Each of the grayscale control units includes a switching transistor, a control terminal of the switching transistor is electrically connected to the corresponding clock signal line, and an input terminal of the switching transistor is electrically connected to the corresponding storage unit; The inverting unit includes a first inverting transistor and a second inverting transistor, the control ends of the first inverting transistor and the second inverting transistor are electrically connected to the output end of the switching transistor, and the output ends of the first inverting transistor and the second inverting transistor are electrically connected to the pixel driving circuit of the corresponding sub-pixel.

7. The display panel according to claim 6, wherein: The pixel driving circuit includes a driving transistor, an input terminal of the driving transistor is electrically connected to the first power supply terminal, and an output terminal of the driving transistor is electrically connected to the light emitting device; The control terminal of the driving transistor is electrically connected to the output terminals of the first inverting transistor and the second inverting transistor included in the corresponding inverting unit.

8. The display panel according to claim 6, wherein: The storage unit includes: a first transistor, wherein a control terminal of the first transistor is electrically connected to the corresponding scan line, an input terminal of the first transistor is electrically connected to the corresponding first bit line, and an output terminal of the first transistor is electrically connected to the input terminal of the switching transistor included in the corresponding grayscale control unit; a second transistor, wherein a control terminal of the second transistor is electrically connected to the corresponding scan line, and an input terminal of the second transistor is electrically connected to the corresponding second bit line; a third transistor, wherein a control terminal of the third transistor is electrically connected to the output terminal of the first transistor, an input terminal of the third transistor is electrically connected to the first power supply terminal, and an output terminal of the third transistor is electrically connected to the output terminal of the second transistor; a fourth transistor, wherein a control terminal of the fourth transistor is electrically connected to the output terminal of the first transistor, an input terminal of the fourth transistor is electrically connected to the second power supply terminal, and an output terminal of the fourth transistor is electrically connected to the output terminal of the second transistor; a fifth transistor, wherein a control terminal of the fifth transistor is electrically connected to the output terminal of the second transistor, an input terminal of the fifth transistor is electrically connected to the first power terminal, and an output terminal of the fifth transistor is electrically connected to the output terminal of the first transistor; and a sixth transistor, wherein the control end of the sixth transistor is electrically connected to the output end of the second transistor, the input end of the sixth transistor is electrically connected to the second power supply end, and the output end of the sixth transistor is electrically connected to the output end of the first transistor.

9. The display panel according to claim 3, wherein: The multiple grayscale control units included in at least one of the grayscale control modules include at least a first grayscale control unit and a second grayscale control unit; wherein, the valid pulse of the clock signal received by the second grayscale control unit lags behind the valid pulse of the clock signal received by the first grayscale control unit, and the pulse width of the valid pulse of the clock signal received by the second grayscale control unit is smaller than the pulse width of the valid pulse of the clock signal received by the first grayscale control unit.

10. The display panel according to claim 1, wherein The plurality of storage modules include a first storage module, the plurality of sub-pixels include a first sub-pixel and a second sub-pixel, and the plurality of clock signals include a plurality of first clock signals and a plurality of second clock signals; Multiple grayscale control groups include: a first grayscale control group, the first grayscale control group being electrically connected between the first storage module and the pixel driving circuit of the first sub-pixel, the first grayscale control group being configured to receive a plurality of the first clock signals and the corresponding image data signals to generate a first grayscale control signal and output it to the corresponding first sub-pixel; a second grayscale control group, the second grayscale control group being electrically connected between the first storage module and the pixel driving circuit of the second sub-pixel, the second grayscale control group being configured to receive a plurality of the second clock signals and the corresponding image data signals to generate a second grayscale control signal and output it to the corresponding second sub-pixel; The valid pulses of the plurality of second clock signals lag behind the valid pulses of the plurality of first clock signals.

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