Semiconductor device and semiconductor package

Abstract

A semiconductor device and a semiconductor package are provided. The semiconductor device includes: a first transmission pad configured to output a data signal; a second transmission pad configured to output a clock signal; a data transmission circuit connected to the first transmission pad and including a data driver configured to generate a data signal; a clock transmission circuit connected to the second transmission pad and including a clock driver configured to generate a clock signal; a core circuit configured to control the data driver and the clock driver; and at least one buffer, in which each of the at least one buffer includes an input terminal connected to at least one of the output terminal of the data driver and the output terminal of the clock driver, and an output terminal connected to the core circuit.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2023-0122321 filed on September 14, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety for all purposes by reference. Technical Field

[0002] The present disclosure relates to a semiconductor device and a semiconductor package. Background Art

[0003] Instead of implementing a plurality of integrated circuits (ICs) performing different functions in one semiconductor device, a method of implementing a high-performance computing device by including a plurality of semiconductor devices in one semiconductor package has been proposed. A plurality of corresponding semiconductor devices included in the semiconductor package are mounted on one substrate and connected to each other through a redistribution pattern included in the substrate, and can operate by exchanging data signals and clock signals. However, as the size of the bumps connecting the semiconductor device to the substrate decreases, the semiconductor device may not be fully tested at the wafer level. As a result, problems such as a decrease in the yield of the semiconductor package and an increase in the manufacturing cost may occur. Summary of the invention

[0004] The present disclosure provides a semiconductor device and a semiconductor package, in which a built-in self-test can be effectively performed at a wafer level by connecting a buffer between a pad (or referred to as a "pad" or "bonding pad") and an output terminal of a transmitting circuit that outputs a data signal and / or a clock signal, and by forcibly setting the output of a sense amplifier to a specific value using an offset cancellation function of a sense amplifier included in a receiving circuit.

[0005] According to one aspect of the disclosure, a semiconductor device includes: a first transmitting pad configured to output a data signal; a second transmitting pad configured to output a clock signal; a data transmitting circuit connected to the first transmitting pad and including a data driver configured to generate a data signal; a clock transmitting circuit connected to the second transmitting pad and including a clock driver configured to generate a clock signal; a core circuit configured to control the data driver and the clock driver; and at least one buffer, wherein each of the at least one buffer includes an input terminal connected to an output terminal of the data driver and at least one of an output terminal of the clock driver, and an output terminal connected to the core circuit.

[0006] According to one aspect of the disclosure, a semiconductor package includes: a first semiconductor device including a first transmitting pad configured to output a data signal and a second transmitting pad configured to output a clock signal; a second semiconductor device including a first receiving pad configured to receive a data signal and a second receiving pad configured to receive a clock signal; an intermediate substrate on which the first semiconductor device and the second semiconductor device are mounted, wherein the intermediate substrate includes a redistribution pattern connecting the first transmitting pad with the first receiving pad and connecting the second transmitting pad with the second receiving pad; and a packaging substrate on which the intermediate substrate is mounted, wherein the first semiconductor device includes a first switching element and a first buffer, the first switching element being connected between an output terminal of a data driver configured to output a data signal and the first transmitting pad, and the first buffer being connected to the first switching element.

[0007] According to one aspect of the disclosure, a semiconductor device includes: a receiving pad configured to receive a data signal; a sense amplifier including a first input terminal, a second input terminal, an offset cancellation switch and an offset cancellation circuit, the first input terminal being connected to the receiving pad, the second input terminal being configured to receive a predetermined reference voltage, the offset cancellation switch being connected between the first input terminal and the second input terminal, and the offset cancellation circuit being connected to at least one of the first input terminal and the second input terminal; and a core circuit configured to control the offset cancellation switch, control the offset cancellation circuit to output a first offset cancellation code and a second offset cancellation code, turn on the offset cancellation switch when the receiving pad is in a floating state, set one of the first offset cancellation code and the second offset cancellation code to a maximum value and set the other of the first offset cancellation code and the second offset cancellation code to a minimum value, and confirm whether the sense amplifier is defective. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 and Figure 2 is a schematic diagram of a semiconductor package according to example embodiments.

[0010] Figure 3 2 is a diagram illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0011] Figure 4 is a block diagram schematically illustrating a semiconductor package according to example embodiments.

[0012] Figure 5 , Figure 6 and Figure 7 is a diagram illustrating a method of testing a semiconductor package according to example embodiments.

[0013] Figure 8 is a schematic block diagram of a semiconductor device according to example embodiments.

[0014] Fig. 9 and Fig.10 is a diagram illustrating an operation of a semiconductor device according to example embodiments.

[0015] Fig.11 is a diagram schematically illustrating a semiconductor device according to example embodiments.

[0016] Fig.12 and Fig.13 is a diagram illustrating a method of testing a semiconductor device according to example embodiments.

[0017] Fig.14 is a diagram schematically illustrating a semiconductor device according to example embodiments.

[0018] Fig.15 is a flowchart illustrating a method of testing a semiconductor device according to example embodiments.

[0019] Fig.16 and Fig.17 is a schematic diagram of a semiconductor device according to example embodiments.

[0020] Fig.18 is a diagram illustrating an operation of a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0021] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0022] In the following description, throughout the specification, the same reference numerals represent the same elements. Because the known functions or structures will make one or more example embodiments obscure with unnecessary details, they are not described in detail. Terms such as "unit", "module", "component" and "block" can be implemented as hardware or software. According to an embodiment, multiple "units", "modules", "components" and "blocks" can be implemented as single components, or single "unit", "module", "component" and "block" can include multiple components.

[0023] It will be understood that when an element is referred to as being “connected to” or “connected to” another element, the element may be directly connected to the other element or indirectly connected to the other element.

[0024] Furthermore, when a component “includes” or “comprises” an element, unless there is a specific description contrary thereto, the component may further include other elements without excluding the other elements.

[0025] Throughout the specification, when a member is “on” another member, this includes not only when the member is in contact with the other member but also when another member exists between the two members.

[0026] Here, the expressions "at least one of a, b or c" and "at least one of a, b and c" mean "only a", "only b", "only c", "both a and b", "both a and c", "both b and c" and "all of a, b and c".

[0027] It will be understood that, although the terms “first”, “second”, “third”, etc. may be used herein to describe various elements, the disclosure should not be limited by these terms. These terms are only used to distinguish one element from another.

[0028] As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0029] Figure 1 and Figure 2 is a schematic diagram of a semiconductor package according to example embodiments.

[0030] Reference Figure 1 and Figure 2 , a semiconductor package 1 according to example embodiments may include a plurality of semiconductor devices 10 , a silicon interposer 20 , a package substrate 30 , etc. The plurality of semiconductor devices 10 are mounted on the silicon interposer 20 , and the number of semiconductor devices 10 included in the semiconductor package 1 may vary according to example embodiments.

[0031] The first semiconductor device 11 and the second semiconductor device 12 may each be a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), an application specific integrated circuit (ASIC), etc. According to example embodiments, the semiconductor package 1 may include at least one memory device mounted on a silicon interposer 20, and the memory device may include a plurality of memory chips stacked in a direction perpendicular to an upper surface of the silicon interposer 20. The plurality of memory chips stacked together may be connected to each other through through silicon vias (or referred to as "Through Silicon Vias"), etc.

[0032] Reference Figure 2 The first semiconductor device 11 and the second semiconductor device 12 may be electrically connected to each other through the redistribution pattern 25 disposed in the silicon interposer 20. The first semiconductor device 11 and the second semiconductor device 12 may operate by exchanging data signals, command signals, clock signals, etc. with each other through the redistribution pattern 25.

[0033] Each of the first semiconductor device 11 and the second semiconductor device 12 may be mounted on the silicon interposer 20 through a plurality of microbumps 40. Alternatively, the silicon interposer 20 may be mounted on the package substrate 30 through a plurality of bumps 50. Solder balls 60 are formed on the bottom of the package substrate 30 for connection with other semiconductor packages and the like, and the semiconductor package 1 may exchange signals with other semiconductor packages or receive a power supply voltage required for operation via the solder balls 60.

[0034] The size of each of the plurality of micro bumps 40 that combine each of the first semiconductor device 11 and the second semiconductor device 12 with the silicon interposer 20 may be smaller than the size of each of the plurality of bumps 50 and the solder ball 60. For example, the diameter of each of the plurality of micro bumps 40 may be several tens of micrometers, and according to an exemplary embodiment, the diameter of each of the plurality of micro bumps 40 may be 50 micrometers or less. Therefore, the integration degree of the redistribution pattern 25 included in the silicon interposer 20 may be increased, and a high-performance semiconductor package 1 may be implemented.

[0035] However, since microbumps 40 having a relatively small diameter are formed in each of the semiconductor devices 10, wafer-level testing performed by contacting each of the microbumps 40 with a probe device may not be feasible. For example, in each of the semiconductor devices 10, a transmission circuit and a reception circuit that exchange signals with other external devices have not been tested at the wafer level. The semiconductor devices 10 may be mounted on the silicon interposer 20. Therefore, if a defect occurs in one of the semiconductor devices 10 after the semiconductor device 10 is mounted on the silicon interposer 20, the entire semiconductor package 1 may need to be discarded, or the packaging process may need to be performed again.

[0036] In one example embodiment, a method for testing each of the semiconductor devices 10 in which micro bumps 40 having a diameter of several tens of micrometers are formed at a wafer level is proposed. For example, each of the semiconductor devices 10 may connect a switching element and a buffer between a driver of a transmission circuit and a transmission pad, and an output terminal of the buffer may be connected to a core circuit.

[0037] Before performing a scribing process of separating the semiconductor devices 10 from a wafer, a power supply voltage and a command signal instructing to perform a test operation may be input through a test pad provided on each of the semiconductor devices 10. The test pad is combined with a plurality of micro bumps 40 and has a relatively large size compared to a pad involved in an actual operation of each of the semiconductor devices 10, and thus may be contacted by a probe device.

[0038] Each of the semiconductor devices 10 can perform self-tests at the wafer level using a power supply voltage and a command signal input through a test pad. For example, a driver that outputs a data signal is set to continuously output a voltage corresponding to "0" (i.e., digital "0") or a voltage corresponding to "1" (i.e., digital "1"), and a core circuit can detect the output of a buffer whose input terminal is connected between the output terminal of the driver and the sending pad to check whether the driver is defective. Therefore, each of the semiconductor devices 10 can be tested before the packaging process, thereby improving the yield of the semiconductor package 1 and reducing manufacturing costs.

[0039] Figure 3 2 is a diagram illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0040] Reference Figure 3 , a plurality of semiconductor dies are manufactured by applying a semiconductor process to the wafer W, and the wafer W may be manufactured to completion. In an example embodiment, the plurality of semiconductor dies included in the wafer W may be according to the previous reference Figure 1 and Figure 2 At least one of the first semiconductor device 11 and the second semiconductor device 12 included in the semiconductor package 1 of the described example embodiment.

[0041] When the wafer W is manufactured, a first test 71 for each of the plurality of semiconductor dies may be performed at the wafer level. Each of the plurality of semiconductor dies may include a plurality of pads and a plurality of test pads, and a plurality of microbumps may be connected to the plurality of pads. The test pad has a relatively large area compared to the pad, and therefore, a power supply voltage and a command signal may be applied to the semiconductor die by contacting the probe device with the test pad.

[0042] The semiconductor die may perform a first test 71 in a self-testing manner in response to a command signal. For example, while the self-test is in progress, the core circuit of the semiconductor die may generate data of a specific pattern and use the data to perform the test. Once the first test 71 is completed, a dicing process 72 for separating the semiconductor die from each other and a packaging process 73 may be performed.

[0043] In an example embodiment, the semiconductor die may be configured to test the sending circuit and receiving circuit of the input and output signals in the first test 71. For example, the input terminal of the buffer may be connected between the pad and the output terminal of the driver that outputs the data signal and / or the clock signal. The buffer may provide a feedback path for sending the signal output by the driver back to the core circuit. The core circuit of the semiconductor die may set the driver to output data of a predetermined pattern in response to a command signal received from a probe device in contact with the test pad, and compare the signal output by the driver with the data fed back by the buffer, thereby performing the first test 71.

[0044] In addition, in the first test 71, the core circuit can test the receiving circuit. For example, the core circuit can activate the offset cancellation function of the sense amplifier included in the receiving circuit in response to a command signal received from a probe device in contact with the test pad. In the case where the offset cancellation function is activated, the core circuit can set one of the first offset cancellation code and the second offset cancellation code input to the sense amplifier to a maximum value and set the other to a minimum value, and can detect whether the output voltage of the sense amplifier is maintained at a level corresponding to a specific logic value. Therefore, in the first test 71, even a circuit that sends a signal to the outside of the semiconductor die or receives a signal from the outside can be verified.

[0045] In the packaging process 73, a plurality of semiconductor dies are mounted on an intermediate substrate (such as a silicon interposer), and the intermediate substrate may be mounted on a packaging substrate. According to an example embodiment, the intermediate substrate may be inserted into a groove formed on an upper surface of the packaging substrate. In this case, some of the pads formed on each of the plurality of semiconductor dies may be bonded to the intermediate substrate, and the remaining pads may be directly bonded to the packaging substrate. Once the packaging process 73 is completed, a second test 74 may be performed. The second test 74 may be a test process performed at the packaging level, and may be performed by applying a power supply voltage and a command signal via solder balls formed on the packaging substrate and exposed to the outside.

[0046] Figure 4 is a block diagram schematically illustrating a semiconductor package according to example embodiments.

[0047] Reference Figure 4 , a semiconductor package 100 according to an example embodiment may include a first semiconductor device 110 and a second semiconductor device 120. Each of the first semiconductor device 110 and the second semiconductor device 120 may include at least one of various devices such as a central processing unit, a graphics processor, an application processor, a dedicated semiconductor, a modem, and a memory device. Figure 4In one example embodiment shown in FIG. 1 , it is assumed that the first semiconductor device 110 and the second semiconductor device 120 are devices having similar structures. Alternatively, the first semiconductor device 110 and the second semiconductor device 120 may have different structures.

[0048] In the semiconductor package 100, the first semiconductor device 110 and the second semiconductor device 120 may operate by exchanging signals with each other. A receiving path may be provided by a wiring pattern in a substrate on which the first semiconductor device 110 and the second semiconductor device 120 are mounted. For example, the first semiconductor device 110 and the second semiconductor device 120 may be mounted on a silicon interposer.

[0049] The first semiconductor device 110 may include a transmitting circuit 111, a receiving circuit 112, a core circuit 113, etc. The transmitting circuit 111 may output a signal to the outside through a first transmitting pad TP1, and the receiving circuit 112 may receive a signal from the outside through a first receiving pad RP1. Figure 4 In one example embodiment shown in , the first transmitting pad TP1 may be connected to the second receiving pad RP2 of the second semiconductor device 120 , and the first receiving pad RP1 may be connected to the second transmitting pad TP2 of the second semiconductor device 120 .

[0050] The second semiconductor device 120 may include a transmitting circuit 121, a receiving circuit 122, a core circuit 123, etc. The transmitting circuit 121 may transmit a data signal, a clock signal, etc. to the first semiconductor device 110 through a second transmitting pad TP2, and the receiving circuit 122 may receive a data signal, a clock signal, etc. transmitted from the first semiconductor device 110 through a second receiving pad RP2.

[0051] The first semiconductor device 110 may include a buffer 115 connected to the transmission pad TP1 through a switching element 114, and the second semiconductor device 120 may include a buffer 125 connected to the transmission pad TP2 through a switching element 124. The buffers 115 and 125 may provide a feedback path through which signals output to the transmission pads TP1 and TP2 are re-input to the core circuits 113 and 123.

[0052] When a test is performed in a state where the first semiconductor device 110 and the second semiconductor device 120 are not connected to each other (for example, in a wafer level state), the switch elements 114 and 124 may be turned on. For example, when the first semiconductor device 110 is in a state before being separated from a wafer, a power supply voltage and a command signal for performing a test are input through a test pad different from the first transmission pad TP1 and the first reception pad RP1. When the power supply voltage and the command signal are input, the core circuit 113 may turn on the switch element 114 in response to the command signal.

[0053] Therefore, the signal output by the transmission circuit 111 can be fed back to the core circuit 113 through the switch element 114 and the buffer 115, instead of being output to the first transmission pad TP1 in a floating state. Since the signal output by the transmission circuit 111 is also determined by the core circuit 113, the core circuit 113 compares the signal to be output to the transmission circuit 111 with the signal fed back through the buffer 115. Whether the transmission circuit 111 operates normally can be verified. The second semiconductor device 120 can also test the transmission circuit 121 in a similar manner.

[0054] The receiving circuits 112 and 122 may include sense amplifiers according to the type of received signals and the transmission speed of the signals. The core circuits 113 and 123 of the first and second semiconductor devices 110 and 120 may perform self-tests on a wafer level for the receiving circuits 112 and 122 including the sense amplifiers.

[0055] For example, the core circuits 113 and 123 may activate the offset cancellation function of the sense amplifier and set the offset cancellation code input to the sense amplifier to a maximum value or a minimum value. When the offset cancellation code is set to a maximum value or a minimum value, the sense amplifier continuously outputs a voltage corresponding to a digital "0" or a voltage corresponding to a digital "1" while the receiving pads RP1 and RP2 are floating. The core circuits 113 and 123 may verify the receiving circuits 112 and 122 including the sense amplifier by comparing the output predicted according to the setting of the offset cancellation code with the actual output of the sense amplifier.

[0056] Thus, in an example embodiment, even when the transmission pads TP1 and TP2 and the reception pads RP1 and RP2 are floated, the operation of the driver that outputs the signal and the sense amplifier that operates as a receiver that receives the signal can be tested. Therefore, by including only the semiconductor devices 110 and 120 that are judged to be good products in the manufacture of the semiconductor package 100, the yield of the semiconductor package 100 can be improved, and the manufacturing cost can be reduced.

[0057] Figures 5 to 7 is a diagram illustrating a method of testing a semiconductor package according to example embodiments.

[0058] Reference Figure 5, a semiconductor package 200 according to example embodiments may include a first semiconductor device 210 and a second semiconductor device 220. A first transmission pad 201 of the first semiconductor device 210 is connected to a first reception pad 203 of the second semiconductor device 220, and a second transmission pad 202 of the first semiconductor device 210 may be connected to a second reception pad 204 of the second semiconductor device 220. A data signal may be transmitted between the first transmission pad 201 and the first reception pad 203, and a clock signal may be transmitted between the second transmission pad 202 and the second reception pad 204.

[0059] The first semiconductor device 210 may include a data transmission circuit 211, a serializer 212, a clock divider 213, clock buffers 214 and 215, a duty cycle correction (DCC) circuit 216, a phase-locked loop (PLL) circuit 217, a clock transmission circuit 218, etc. The second semiconductor device 220 may include a data reception circuit 221, a deserializer 222, a clock divider 223, clock buffers 224 and 225, a DCC circuit 226, a PLL circuit 227, a selection circuit 228, etc. However, the configuration of each of the first semiconductor device 210 and the second semiconductor device 220 may be modified in various ways according to example embodiments.

[0060] The serializer 212 may serialize data processed in the first semiconductor device 210 to generate a data signal. For example, the serializer 212 may serialize the data in synchronization with a clock signal output by the clock divider 213. According to example embodiments, the serializer 212 may include a 16:8 serializer, an 8:4 serializer, etc., in which case clock signals having different frequencies may be input to the 16:8 serializer and the 8:4 serializer, respectively.

[0061] The data transmission circuit 211 may include a retimer, a serializer, and a driver that perform final processing on the data signal. For example, assuming that the serializer 212 includes a 16:8 serializer and an 8:4 serializer as described above, the data transmission circuit 211 may include a 4:1 serializer. The serializer, the retimer, etc. included in the data transmission circuit 211 may operate in synchronization with the clock signal output from the clock buffer 214.

[0062] The clock divider 213 may change the frequency of the clock signal received from the clock buffer 214 and input the clock signal with its frequency changed to the serializer 212. According to the frequency of the clock signal output by the clock divider 213, the transmission speed of the data signal input to the data transmitting circuit 211 may vary.

[0063] An internal clock signal for operating the first semiconductor device 210 may be generated in the PLL circuit 217. When the PLL circuit 217 generates the internal clock signal, the DCC circuit 216 may adjust the duty ratio of the internal clock signal and transmit the internal clock signal whose duty ratio is adjusted to the clock buffer 215. The clock buffer 215 may transmit the clock signal to the clock buffer 214 on the circuit side that transmits the data signal, or may transmit the clock signal to the clock transmission circuit 218. The clock transmission circuit 218 includes a driver, and the clock signal output by the clock transmission circuit 218 may be provided to the second semiconductor device 220 as an external clock signal.

[0064] The second semiconductor device 220 may receive the data signal through the first receiving pad 203, and receive the external clock signal through the second receiving pad 204. However, the second semiconductor device 220 may also generate an internal clock signal in the PLL circuit 227, and the selection circuit 228 connected to the second receiving pad 204 may select one of the internal clock signal and the external clock signal, and send the signal to the DCC circuit 226. The DCC circuit 226 may adjust the duty ratio of the clock signal selected by the selection circuit 228, and output the clock signal whose duty ratio is adjusted to the clock buffer 225. The clock buffer 225 may send the clock signal to the clock buffer 224 on the circuit side that receives the data signal.

[0065] The clock divider 223 may change the frequency of the clock signal output by the clock buffer 224 and input the clock signal whose frequency is changed to the deserializer 222, and the clock buffer 224 may also output the clock signal to the data receiving circuit 221. The data receiving circuit 221 may include a sense amplifier, a retimer, etc. that receive the data signal from the first semiconductor device 210 through the first receiving pad 203. According to example embodiments, a plurality of sense amplifiers may be connected in parallel to one first receiving pad 203. The deserializer 222 may be synchronized with the clock signal output from the clock divider 223, and may process the data signals output from the data receiving circuit 221 in parallel.

[0066] In accordance with Figure 5 In the semiconductor package 200 of the example embodiment shown in FIG. 1 , in a process of testing each of the first semiconductor device 210 and the second semiconductor device 220 at a wafer level, the transmitting pads 201 and 202 and the receiving pads 203 and 204 may be floated. This may be because, as described above, the size of each of the plurality of micro bumps included in each of the first semiconductor device 210 and the second semiconductor device 220 is small, and thus, contacting a probe device may be difficult.

[0067] Therefore, it may be difficult to test the data transmission circuit 211 , the clock transmission circuit 218 , and the data reception circuit 221 at a wafer level where the transmission pads 201 and 202 and the reception pads 203 and 204 are not connected to each other. Figure 6 2 is a diagram showing a test operation of the first semiconductor device 210 performed at the wafer level. At the wafer level, the first semiconductor device 210 and the second semiconductor device 220 may not be connected to each other. Figure 6 As shown in , even if the data transmission circuit 211 actually outputs a data signal or the clock transmission circuit 218 actually outputs a clock signal, testing the data transmission circuit 211 and the clock transmission circuit 218 may be difficult because there is no circuit to receive the data signal or the clock signal.

[0068] Figure 7 2 is a diagram showing a test operation of the second semiconductor device 220 performed at the wafer level. At the wafer level, the first semiconductor device 210 and the second semiconductor device 220 are not connected to each other, and the probe device cannot contact the receiving pads 203 and 204. Figure 7 As shown in , the data receiving circuit 221 cannot actually receive the data signal. Therefore, it may not be feasible to test the sense amplifier included in the data receiving circuit 221. However, by setting the selection circuit 228 to select the internal clock signal output by the PLL circuit 227, the circuit connected to the second receiving pad 204 and receiving the clock signal can be tested at the wafer level.

[0069] Figure 8 is a schematic block diagram of a semiconductor device according to example embodiments.

[0070] Reference Figure 8 , a semiconductor device 300 according to example embodiments may include a transmission pad 301 , a data transmission circuit 310 , a core circuit 320 , and the like. Figure 8 It may be a diagram selectively showing some of the components included in the semiconductor device 300 .

[0071] Reference Figure 8 , the data transmission circuit 310 may include a pre-driver 311 and a main driver 312, and the output terminal of the main driver 312 may be directly connected to the transmission pad 301. The output terminal of the main driver 312 and the transmission pad 301 are also connected to the switching element 330, and the switching element 330 may be connected to the input terminal of the buffer 340. The output terminal of the buffer 340 may be connected to the core circuit 320.

[0072] The core circuit 320 may include a clock divider 322 that adjusts the frequency of the clock signal CLK and a serializer 321 . The serializer 321 may serially process data processed in parallel within the core circuit 320 in synchronization with rising and / or falling edges of the clock signal output by the clock divider 322 .

[0073] Before the semiconductor device 300 is separated from the wafer (for example, before the dicing process is performed), the transmission pad 301 may be maintained in a floating state. Therefore, when a command for performing a self-test is received through the test pad of the semiconductor device 300, the core circuit 320 turns on the switch element 330 to verify the operation of the data transmission circuit 310. Fig. 9 and Fig.10 The operation of the semiconductor device is described in more detail.

[0074] Fig. 9 and Fig.10 is a diagram illustrating an operation of a semiconductor device according to example embodiments.

[0075] first, Fig. 9 is a diagram showing the operation of the semiconductor device 300 while testing is being performed on a wafer level. Fig. 9 , while the test is being performed at the wafer level, the core circuit 320 may set the serializer 321 to be input with only data “0” or data “1” and turn on the switch element 330 .

[0076] The data signal output from the data transmission circuit 310 to the transmission pad 301 may be a signal swinging between a first voltage level and a second voltage level. When only data "0" is set as input to the serializer 321, the data signal may be maintained at the first voltage level. On the other hand, if only data "1" is set as input to the serializer 321, the data signal may be maintained at the second voltage level.

[0077] The core circuit 320 can test the operation of the data transmission circuit 310 by comparing the signal output by the buffer 340 with the data input to the serializer 321. In a state where only data "0" is set as input to the serializer 321 and the buffer 340 continuously outputs a signal of a first voltage level, and when the buffer 340 continuously outputs a signal of a second voltage level while only data "1" is set as input to the serializer 321, the core circuit 320 can determine that there is no defect in the data transmission circuit 310. The result determined by the core circuit 320 can be output by a probe device contacting a test pad having an area larger than that of the transmission pad 301.

[0078] On the other hand, when only data "0" is set as input to the serializer 321 and the buffer 340 outputs a signal of the second voltage level, or when only data "1" is set as input to the serializer 321 and the buffer 340 outputs a signal of the first voltage level, the core circuit 320 may determine that there is a defect in the data transmission circuit 310. In this case, the semiconductor device 300 may not be input to a packaging process for manufacturing a semiconductor package, and thus, the yield and manufacturing cost of the semiconductor package may be improved.

[0079] Fig.10 3 is a diagram showing a test performed at a package level after a semiconductor device 300 is determined as a good product in a wafer level test and mounted on a silicon interposer or the like in a semiconductor package. At the package level, a transmission pad of the semiconductor device 300 may be connected to a reception pad of another semiconductor device through a redistribution pattern such as a redistribution pattern of a silicon interposer.

[0080] When the test on the package level starts, the core circuit 320 may control the serializer 321 to output the test data of a predetermined pattern. At this time, the data output by the serializer 321 may not be selected as "0" or "1", and the test data of the predetermined pattern may be input through a package board or the like, for example. The data transmission circuit 310 may output a data signal to another semiconductor device included in the semiconductor package through the transmission pad 301, and determine whether the data restored by the other semiconductor device receiving the data signal matches the test data. The semiconductor device 300 may be verified. Therefore, as Fig.10 As shown in , the switch element 330 is turned off, and the buffer 340 may not be involved in the operation of the semiconductor device 300 .

[0081] Fig.11 is a diagram schematically illustrating a semiconductor device according to an embodiment.

[0082] Reference Fig.11 , the semiconductor device 400 according to an example embodiment may include a first clock transmission circuit 410, a second clock transmission circuit 420, and a PLL circuit 430. The first clock transmission circuit 410 may output a first clock signal to a first transmission pad 401, and the second clock transmission circuit 420 may output a second clock signal to a second transmission pad 402. For example, the first clock signal and the second clock signal are complementary signals and may have a phase difference of 180 degrees. However, according to an example embodiment, the first clock signal and the second clock signal may have a phase difference of 90 degrees.

[0083] The clock signal output by the PLL circuit 430 may be input to the first clock transmission circuit 410 and the second clock transmission circuit 420 respectively through the DCC circuit. For example, the DCC circuit may include a plurality of elements NM1, NM2, PM1, PM2, R1 and C1 connected to the first clock transmission circuit 410 and a plurality of elements NM3, NM4, PM3, PM4, R2 and C2 connected to the second clock transmission circuit 420. Fig.11 , a source of each of the NMOS elements NM1 to NM4 may be connected to a first power node supplying a first power voltage VSS, and a source of each of the PMOS elements PM1 to PM4 may be connected to a second power node supplying a second power voltage VDD.

[0084] More specifically, the gate of the first PMOS element PM1 may receive the first control signal CTL1, and the gate of the first NMOS element NM1 may receive the second control signal CTL2. The gate of the third PMOS element PM3 may receive the third control signal CTL3, and the gate of the third NMOS element NM3 may receive the fourth control signal CTL4. The first control signal CTL1 to the fourth control signal CTL4 may be signals output from the core circuit of the semiconductor device 400. The gate of the second PMOS element PM2 may be connected to the drain of the first PMOS element PM1, and the gate of the second NMOS element NM2 may be connected to the drain of the first NMOS element NM1. On the other hand, the gate of the fourth PMOS element PM4 may be connected to the drain of the third PMOS element PM3, and the gate of the fourth NMOS element NM4 may be connected to the drain of the third NMOS element NM3.

[0085] The first clock transmission circuit 410 may include an inverter 411, a pre-driver 412, and a main driver 413, and the second clock transmission circuit 420 may include an inverter 421, a pre-driver 422, and a main driver 423. The first clock transmission circuit 410 may include an inverter chain consisting of two or more inverters 411 connected in series, and the second clock transmission circuit 420 may include an inverter chain consisting of two or more inverters 421 connected in series.

[0086] A first terminal (e.g., input terminal) of the first switch element SW1 is connected between the first transmission pad 401 and the output terminal of the main driver 413, and a first terminal (e.g., input terminal) of the second switch element SW2 is connected between the second transmission pad 402 and the output terminal of the main driver 423. A second terminal (e.g., output terminal) of the first switch element SW1 may be connected to the first buffer BF1, and a second terminal (e.g., output terminal) of the second switch element SW2 may be connected to the second buffer BF2. The first switch element SW1 may be turned on / off by the first selection signal SEL1, and the second switch element SW2 may be turned on / off by the second selection signal SEL2. The first buffer BF1 may output a first comparison signal CMP1, and the second buffer BF2 may output a second comparison signal CMP2. The core circuit of the semiconductor device 400 may output the first selection signal SEL1 and the second selection signal SEL2, and receive the first comparison signal CMP1 and the second comparison signal CMP2.

[0087] The core circuit of the semiconductor device 400 uses the first control signal CTL1 to the fourth control signal CTL4 so that each of the first transmission pad 401 and the second transmission pad 402 can be set to output only a signal having a voltage level corresponding to a digital "0" or a digital "1". In this state, the first selection signal SEL1 and the second selection signal SEL2 are used to turn on the switch elements SW1 and SW2, and by receiving the first comparison signal CMP1 and the second comparison signal CMP2, it can be determined whether the first clock transmission circuit 410 and the second clock transmission circuit 420 are defective. Hereinafter, reference will be made to Fig.12 and Fig.13 The operation of the semiconductor device 400 is described in more detail.

[0088] Fig.12 and Fig.13 is a diagram illustrating a method of testing a semiconductor device according to example embodiments.

[0089] First, refer to Fig.12 , the core circuit may set the first control signal CTL1 and the second control signal CTL2 to "0", and set the third control signal CTL3 and the fourth control signal CTL4 to "1", and stop the operation of the PLL circuit 430. Fig.12 As shown in FIG, the first PMOS element PM1, the fourth PMOS element PM4, the second NMOS element NM2, and the third NMOS element NM3 may be turned on, and the second PMOS element PM2, the third PMOS element PM3, the first NMOS element NM1, and the fourth NMOS element NM4 may be turned off.

[0090] At the input terminal side of the first clock transmission circuit 410, a current path including the first PMOS element PM1, the second NMOS element NM2, and the first resistor element R1 is formed, thereby providing "0" to the inverter 411. "0" is input, and the voltage level of the signal output to the first transmission pad 401 can be determined according to the number of inverters 411. Fig.12 In one example embodiment shown in , the number of inverters 411 may be an even number, and a signal having a voltage level corresponding to “0” (eg, the first power supply voltage VSS) may be output to the first transmission pad 401 .

[0091] On the other hand, on the input terminal side of the second clock transmission circuit 420, a current path including the fourth PMOS element PM4, the third NMOS element NM3, and the second resistor element R2 is formed, thereby providing "1" to the inverter 421. "1" is input, and the voltage level of the signal output to the second transmission pad 402 can be determined according to the number of inverters 421. Fig.12 In one example embodiment shown in , a signal having a voltage level corresponding to “1” (eg, the second power supply voltage VDD) may be output to the second transmission pad 402 .

[0092] The core circuit may turn on each of the first switching element SW1 and the second switching element SW2. Therefore, the signal output to the first transmission pad 401 is fed back to the core circuit through the first buffer BF1 as the first comparison signal CMP1, and the signal output to the second transmission pad 402 may be fed back to the core circuit through the second buffer BF2 as the second comparison signal CMP2. When the voltage level of the first comparison signal CMP1 is the first power supply voltage VSS and the voltage level of the second comparison signal CMP2 is the second power supply voltage VDD, the core circuit may determine that the first clock transmission circuit 410 and the second clock transmission circuit 420 are normal.

[0093] Next, refer to Fig.13 , the core circuit may set the first control signal CTL1 and the second control signal CTL2 to "1", and set the third control signal CTL3 and the fourth control signal CTL4 to "0", and stop the operation of the PLL circuit 430. Fig.13 As shown in FIG. 1 , the first PMOS element PM1 , the fourth PMOS element PM4 , the second NMOS element NM2 , and the third NMOS element NM3 are turned off, and the second PMOS element PM2 , the third PMOS element PM3 , the first NMOS element NM1 , and the fourth NMOS element NM4 may be turned on.

[0094] At the input terminal side of the first clock transmission circuit 410, a current path including the second PMOS element PM2, the first NMOS element NM1, and the first resistor element R1 is formed, thereby providing "1" to the inverter 411. The second power supply voltage VDD corresponding to "1" may be input. Fig.13 In one example embodiment shown in , a signal having the second power supply voltage VDD as a voltage level corresponding to “1” may be output to the first transmission pad 401 .

[0095] On the other hand, on the input terminal side of the second clock transmission circuit 420, a current path including the third PMOS element PM3, the fourth NMOS element NM4, and the second resistor element R2 is formed. The first power supply voltage VSS corresponding to the digital "0" may be applied to the inverter 421. Fig.13 In one example embodiment shown in , the first power supply voltage VSS having a voltage level corresponding to digital “0” may be output to the second transmission pad 402 .

[0096] The core circuit may turn on each of the first switching element SW1 and the second switching element SW2. Therefore, the signal output to the first transmission pad 401 is fed back to the core circuit through the first buffer BF1 as the first comparison signal CMP1, and the signal output to the second transmission pad 402 may be fed back to the core circuit through the second buffer BF2 as the second comparison signal CMP2. When the voltage level of the first comparison signal CMP1 is the second power supply voltage VDD and the voltage level of the second comparison signal CMP2 is the first power supply voltage VSS, the core circuit may determine that the first clock transmission circuit 410 and the second clock transmission circuit 420 are normal.

[0097] As reference Fig.12 and Fig.13 As described above, even when the first transmission pad 401 and the second transmission pad 402 are floated, the semiconductor device 400 can test the first clock transmission circuit 410 and the second clock transmission circuit 420. The core circuit sets the PLL circuit 430 to be non-operating, and sets the voltage of each of the first transmission pad 401 and the second transmission pad 402 to a specific level using the control signals CTL1 to CTL4 input to the DCC circuit. Therefore, even at the wafer level where the first transmission pad 401 and the second transmission pad 402 are not connected to a probe device, other semiconductor devices, etc., the semiconductor device 400 can perform a self-test to verify whether the first clock transmission circuit 410 and the second clock transmission circuit 420 are defective.

[0098] On the other hand, in normal operation except for the self-test, the core circuit sets the first control signal CTL1 and the third control signal CTL3 to "1", and may set the second control signal CTL2 and the fourth control signal CTL4 to "0". Therefore, the first PMOS element PM1, the first NMOS element NM1, the third PMOS element PM3, and the third NMOS element NM3 may all be turned off.

[0099] Fig.14 is a diagram schematically illustrating a semiconductor device according to an embodiment.

[0100] Reference Fig.14 , a semiconductor device 500 according to an example embodiment may include a first clock transmission circuit 510, a second clock transmission circuit 520, and a PLL circuit 530. The first clock transmission circuit 510 and the second clock transmission circuit 520 may receive a clock signal from the PLL circuit 530 through a DCC circuit, and the configuration and operation of the DCC circuit may be the same as previously described with reference to Figures 11 to 13 The configuration and operation described are similar.

[0101] exist Fig.14 In one example embodiment shown in FIG. 5 , a first switching element SW1 connected to a first transmission pad 501 and a second switching element SW2 connected to a second transmission pad 502 may be commonly connected to one buffer BF. Therefore, the number of switching elements SW1 and SW2 may be different from the number of buffers BF. While testing at the wafer level, the core circuit of the semiconductor device 500 turns on the first switching element SW1 and the second switching element SW2 alternately, thereby verifying whether each of the first clock transmission circuit 510 and the second clock transmission circuit 520 is defective.

[0102] For example, with Fig.12 Refer to Fig.14 , when the first control signal CTL1 is set to "0" and the second control signal CTL2 is set to "1", a signal having the first power supply voltage VSS may be output to the first transmission pad 501, and a signal having the second power supply voltage VDD may be output to the second transmission pad 502. The core circuit determines whether the comparison signal CMP is the first power supply voltage VSS when the first switch element SW1 is turned on and the second switch element SW2 is turned off, and the first clock transmission circuit 510 may be verified. In addition, the core circuit determines whether the comparison signal CMP is the second power supply voltage VDD when the first switch element SW1 is turned off and the second switch element SW2 is turned on. The second clock transmission circuit 520 may be verified accordingly.

[0103] Fig.15 is a flowchart illustrating a testing method of a semiconductor device according to example embodiments.

[0104] Fig.15 1 is a flow chart schematically illustrating a test method for verifying whether a receiving circuit included in a semiconductor device and receiving a signal from another external device operates normally. Fig.15 , the testing method according to example embodiments may start with a core circuit of a semiconductor device activating an offset cancellation function of a sense amplifier included in a receiving circuit ( S10 ).

[0105] When the offset cancellation function is activated, the core circuit can set the output of the sense amplifier to remain at a specific logic value using the first offset cancellation code and the second offset cancellation code. For example, first, the core circuit can set the first offset cancellation code to a minimum value and the second offset cancellation code to a maximum value (S20). In this state, the core circuit can determine whether the output of the sense amplifier remains at the first logic value (S30).

[0106] When one of the offset cancellation codes input to the sense amplifier is set to a minimum value and the other is set to a maximum value, the output voltage of the sense amplifier without a defect may be maintained at a level corresponding to "0" or a level corresponding to "1." Therefore, after the first offset cancellation code and the second offset cancellation code are set as in step S20, if the output voltage of the sense amplifier is not maintained at a level corresponding to the first logic value, the core circuit determines that the sense amplifier is defective (S70).

[0107] If the output voltage of the sense amplifier remains at a level corresponding to the first logic value in step S30, the core circuit may set the first offset elimination code to a maximum value and the second offset elimination code to a minimum value (S40). Compared to step S20, the first offset elimination code and the second offset elimination code are set oppositely, so if there is no defect in the sense amplifier, the output voltage of the sense amplifier may be changed to a level corresponding to the second logic value. Therefore, the core circuit may determine whether the output of the sense amplifier remains at the second logic value (S50), and verify whether the sense amplifier is defective based on the result.

[0108] If the output of the sense amplifier remains at the second logic value in step S50, the core circuit may determine that the sense amplifier is normal (S60). On the other hand, if the output voltage of the sense amplifier does not remain at a level corresponding to the second logic value in step S50, the core circuit may determine that the sense amplifier is defective (S70).

[0109] Fig.16 and Fig.17 is a schematic diagram of a semiconductor device according to example embodiments.

[0110] Fig.16 is a circuit diagram schematically illustrating a sense amplifier connected to a receiving pad 601 receiving a data signal in a semiconductor device 600 according to an example embodiment. Fig.16 , the sense amplifier includes first to third PMOS elements PM1 to PM3, first and second NMOS elements NM1 and NM2, an offset cancellation switch 605, a first offset cancellation circuit 610, a second offset cancellation circuit 620, etc. However, the structure of the sense amplifier may be modified in various ways according to example embodiments.

[0111] The gate of the first PMOS element PM1 is connected to the receiving pad 601, and the gate of the second PMOS element PM2 can receive the reference voltage VREF. The gate of the first PMOS element PM1 can provide a first input terminal of the sense amplifier, and the gate of the second PMOS element PM2 can provide a second input terminal of the sense amplifier. On the other hand, the gate of each of the first NMOS element NM1 and the second NMOS element NM2 can receive the clock signal CLK. In normal operation of receiving a data signal, the sense amplifier can output an output signal determined as a result of a comparison between the data signal input to the receiving pad 601 and the reference voltage VREF for each rising edge and / or falling edge of the clock signal CLK.

[0112] The first offset cancellation circuit 610 may be connected to the first output node DP, and the second offset cancellation circuit 620 may be connected to the second output node DN. However, according to example embodiments, the offset cancellation circuit may be connected to only one of the output nodes DP and DN of the sense amplifier. The first offset cancellation circuit 610 may receive the first offset cancellation code and operate, and the second offset cancellation circuit 620 may receive the second offset cancellation code and operate. Before the offset cancellation operation, the offset cancellation switch 605 may be turned on. Each of the first offset cancellation code and the second offset cancellation code may be N-bit data (where N is a natural number of 2 or more), and the number of bits of the first offset cancellation code may be the same as the number of bits of the second offset cancellation code.

[0113] In one example embodiment, a determination of whether the sense amplifier is defective can be obtained using an offset cancellation operation of the sense amplifier. At the wafer level before the semiconductor device 600 is connected to another semiconductor device or mounted on a substrate, the receiving pad 601 remains floating. However, since the receiving pad 601 is small in size and cannot be in contact with the probe device, it may not be possible to obtain a determination of whether the sense amplifier is operating normally at the wafer level. In one example embodiment, a defect in the sense amplifier can be verified by forcing the output of the sense amplifier to "0" or "1" using the offset cancellation operation of the sense amplifier.

[0114] At the wafer level, the core circuit of the semiconductor device 600 turns on the offset elimination switch 605, and in response, the reference voltage VREF can be input to the receiving pad 601. In this state, the first offset elimination code can be set to a maximum value, and the second offset elimination code can be set to a minimum value. For example, if each of the first offset elimination code and the second offset elimination code is 3-bit data, the first offset elimination code can be set to "111" and the second offset elimination code can be set to "000". By setting the offset elimination code like this, the output of the sense amplifier can be fixed to "1". The core circuit turns on the offset elimination switch 605, and in the case where the first offset elimination code is set to "111" and the second offset elimination code is set to "000", the sense amplifier can be tested by determining whether the output of the sense amplifier is "1".

[0115] On the other hand, the core circuit may set the first offset elimination code to a minimum value, and the second offset elimination code to a maximum value, and turn on the offset elimination switch 605. For example, when each of the first offset elimination code and the second offset elimination code is 3-bit data, the first offset elimination code may be set to "000", and the second offset elimination code may be set to "111". By setting the offset elimination code like this, the output of the sense amplifier is fixed to "0", and the core circuit can test the sense amplifier by determining whether the output of the sense amplifier is "0".

[0116] Fig.17 2 may be a circuit diagram schematically showing a second offset cancellation circuit 620 included in a sense amplifier. Fig.17 , the second offset cancellation circuit 620 may include first to third switching elements SW0 to SW2 connected in parallel to each other and a fourth switching element SW3 receiving the second power supply voltage VDD. The fourth switching element SW3 is turned on / off by the clock signal CLK, and the first to third switching elements SW0 to SW2 may be turned on / off by bits D0 to D2 included in the second offset cancellation code, respectively. Fig.16 It may be an example embodiment assuming that the second offset elimination code is 3-bit data.

[0117] When the second offset cancellation code is "000", the first to third switching elements SW0 to SW2 are all turned on, and current can be supplied to the second output node DN. In this state, when the first offset cancellation code is set to "111" and the offset cancellation switch 605 is turned on, the second power supply voltage VDD corresponding to "1" can be output to the second output node DN of the sense amplifier. On the other hand, when the second offset cancellation code is "111", the first to third switching elements SW0 to SW2 are all turned off, and the first power supply voltage VSS corresponding to "0" can be output to the second output node DN.

[0118] Fig.18 is a diagram illustrating an operation of a semiconductor device according to example embodiments.

[0119] exist Fig.18 As previously referenced Fig.16 As described above, the first offset cancellation (OC) code is a code input to the first offset cancellation circuit 610, and the second OC code may be a code input to the second offset cancellation circuit 620. Fig.18 In an exemplary embodiment shown in FIG. 1 , it is assumed that each of the first offset elimination code and the second offset elimination code is a 3-bit code, but it is not necessarily limited to this form. For example, each of the first offset elimination code and the second offset elimination code as a 3-bit code can be input bit by bit to three switch elements connected in parallel (such as in FIG. Fig.17 The respective gates of the switching elements SW0 to SW2 in one example embodiment shown in FIG.

[0120] First, when the first offset cancellation code is set to "000" and the second offset cancellation code is set to "111", the switch element in the first offset cancellation circuit 610 may be turned on, and the switch element in the second offset cancellation circuit 620 may be turned off. Therefore, the voltage of the second output node DN, which is the output of the sense amplifier, may be maintained at a voltage corresponding to "0". In this state, the core circuit of the semiconductor device 600 may verify whether the sense amplifier is defective by determining whether the output of the sense amplifier is a voltage corresponding to "0".

[0121] Next, when the first offset cancellation code is set to "111" and the second offset cancellation code is set to "000", the switch element in the first offset cancellation circuit 610 may be turned off, and the switch element in the second offset cancellation circuit 620 may be turned on. Therefore, the voltage of the second output node DN, which is the output of the sense amplifier, may increase to a voltage corresponding to "1". While the first offset cancellation code remains at "111" and the second offset cancellation code remains at "000", the core circuit of the semiconductor device 600 may verify whether the sense amplifier is defective by determining whether the output of the sense amplifier remains at a voltage corresponding to "1".

[0122] As explained above, according to the example embodiments, by connecting a buffer between a transmission pad and an output terminal of a transmission circuit that outputs a data signal and / or a clock signal, a circuit that outputs a signal to the outside can be tested at a wafer level by inputting power and a command to a test pad without separate probing. Therefore, defects in a semiconductor device can be determined in advance before packaging work, and the yield of a semiconductor package can be improved, and the manufacturing cost of a semiconductor package can be reduced.

[0123] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: a first transmission pad configured to output a data signal; a second transmission pad configured to output a clock signal; a data transmission circuit connected to the first transmission pad and including a data driver configured to generate a data signal; a clock transmission circuit connected to the second transmission pad and including a clock driver configured to generate a clock signal; a core circuit configured to control a data driver and a clock driver; as well as At least one buffer, wherein each of the at least one buffer comprises: an input terminal connected to at least one of an output terminal of a data driver and an output terminal of a clock driver; and an output terminal connected to a core circuit.

2. The semiconductor device according to claim 1, further comprising: The switch element is connected between the input terminal of the buffer and at least one of the output terminal of the data driver and the output terminal of the clock driver.

3. The semiconductor device according to claim 2, further comprising: A plurality of switch elements, including the switch element, wherein the number of the plurality of switch elements is equal to the number of the at least one buffer.

4. The semiconductor device according to claim 2, further comprising: A plurality of switching elements including the switching element, wherein the number of the plurality of switching elements is different from the number of the at least one buffer.

5. The semiconductor device according to claim 1, wherein The at least one buffer includes: a first buffer connected to an output terminal of the data driver; and a second buffer connected to an output terminal of the clock driver.

6. The semiconductor device according to claim 5, further comprising: a first switch element connected between an input terminal of the first buffer and an output terminal of the data driver; as well as The second switch element is connected between the input terminal of the second buffer and the output terminal of the clock driver.

7. The semiconductor device according to claim 5, wherein: The core circuit is also configured as: During a predetermined first test time, controlling the data driver to continuously output a voltage corresponding to a digital 0 or a voltage corresponding to a digital 1; and During a predetermined first test time, the data transmission circuit is verified using the output of the first buffer.

8. The semiconductor device according to claim 5, wherein: The core circuit is also configured as: During a predetermined second test time, controlling the clock driver to continuously output a voltage corresponding to a digital 0 or a voltage corresponding to a digital 1; and During a predetermined second test time, the clock transmission circuit is verified using the output of the second buffer.

9. The semiconductor device according to claim 8, in, The clock transmission circuit further includes a duty cycle correction circuit connected between the clock driver and the phase-locked loop circuit, wherein the phase-locked loop circuit is configured to generate an internal clock signal corresponding to the clock signal, wherein the duty cycle correction circuit is configured to adjust the duty cycle of the internal clock signal, and The core circuit is further configured to stop the operation of the phase-locked loop circuit during a predetermined second test time, and use the duty cycle correction circuit to control the clock driver to continuously output a voltage corresponding to a digital 0 or a voltage corresponding to a digital 1.

10. The semiconductor device according to any one of claims 1 to 9, further comprising: a receiving pad, exposed to the outside and configured to receive an external signal; as well as a sense amplifier including a first input terminal connected to the receiving pad and a second input terminal configured to receive a predetermined reference voltage, The core circuit is further configured to verify the sense amplifier by adjusting an offset cancellation code input to the sense amplifier while activating an offset cancellation function of the sense amplifier.

11. The semiconductor device according to claim 10, wherein The core circuit is also configured as: The sense amplifier is verified by inputting the first offset compensation code and the second offset compensation code to the sense amplifier, setting the first offset compensation code to a minimum value and the second offset compensation code to a maximum value, and setting the first offset compensation code to a maximum value and the second offset compensation code to a minimum value.

12. The semiconductor device according to claim 11, wherein The core circuit is also configured as: verifying that the sense amplifier is defective based on confirming that the output of the sense amplifier is not fixed to a voltage corresponding to a digital 0 while the first offset cancellation code is set to a minimum value and the second offset cancellation code is set to a maximum value; as well as The sense amplifier is verified as defective based on confirmation that the output of the sense amplifier is not fixed to a voltage corresponding to digital 1 while the first offset cancellation code is set to a maximum value and the second offset cancellation code is set to a minimum value.

13. The semiconductor device according to claim 11, wherein Each of the first offset elimination code and the second offset elimination code includes an N-bit code, where N is a natural number greater than or equal to two.

14. A semiconductor package, comprising: A first semiconductor device including a first transmission pad configured to output a data signal and a second transmission pad configured to output a clock signal; a second semiconductor device including a first receiving pad configured to receive a data signal and a second receiving pad configured to receive a clock signal; an intermediate substrate on which the first semiconductor device and the second semiconductor device are mounted, wherein the intermediate substrate includes a redistribution pattern connecting the first transmitting pad with the first receiving pad and connecting the second transmitting pad with the second receiving pad; and A packaging substrate, an intermediate substrate is mounted on the packaging substrate, The first semiconductor device further includes: a first switching element having a first terminal connected between an output terminal of a data driver configured to output a data signal and the first transmitting pad; and a first buffer connected to a second terminal of the first switching element.

15. The semiconductor package according to claim 14, wherein: The first semiconductor device further includes: a second switching element having a first terminal connected between an output terminal of a clock driver configured to output a clock signal and a second transmission pad; and The second buffer is connected to the second terminal of the second switching element and is implemented separately from the first buffer.

16. The semiconductor package according to claim 14, in, The first semiconductor device further includes: a second switch element having a first terminal connected between an output terminal of a clock driver configured to output a clock signal and the second transmission pad, and The second terminal of the second switch element is connected to the first buffer.

17. The semiconductor package according to any one of claims 14 to 16, further comprising: a plurality of micro bumps in contact with the upper surface of the intermediate substrate, the first semiconductor device, and the second semiconductor device, wherein the first semiconductor device and the second semiconductor device are mounted on the upper surface of the intermediate substrate via the plurality of micro bumps; and a plurality of bumps in contact with the upper surface of the package substrate and the intermediate substrate, wherein the intermediate substrate is mounted on the upper surface of the package substrate via the plurality of bumps, Wherein, each of the plurality of microbumps has a diameter of 50 micrometers or less.

18. A semiconductor device, comprising: a receiving pad configured to receive a data signal; A sense amplifier including a first input terminal, a second input terminal, an offset cancellation switch, and an offset cancellation circuit, wherein the first input terminal is connected to a receiving pad, the second input terminal is configured to receive a predetermined reference voltage, the offset cancellation switch is connected between the first input terminal and the second input terminal, and the offset cancellation circuit is connected to at least one of the first input terminal and the second input terminal; as well as The core circuit is configured to: control the offset elimination switch; control the offset elimination circuit to output a first offset elimination code and a second offset elimination code; turn on the offset elimination switch when the receiving pad is in a floating state; One of the first offset elimination code and the second offset elimination code is set to a maximum value, and the other of the first offset elimination code and the second offset elimination code is set to a minimum value; And confirm whether the sense amplifier is defective.

19. The semiconductor device according to claim 18, wherein: The core circuit is also configured as: Based on the output voltage of the sense amplifier being maintained at a first level while the first offset elimination code is set to a minimum value and the second offset elimination code is set to a maximum value, and the output voltage of the sense amplifier being maintained at a second level different from the first level while the first offset elimination code is set to a maximum value and the second offset elimination code is set to a minimum value, it is confirmed that the sense amplifier is not defective.

20. The semiconductor device according to claim 19, wherein The first level is a level of a first power supply voltage input to the sense amplifier, and the second level is a level of a second power supply voltage input to the sense amplifier, wherein the second level is greater than the first level.

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