Power device and method of forming the same

Abstract

The embodiment of the present application provides a power device and a forming method thereof, and the forming method of the power device comprises the following steps: providing a substrate, wherein the substrate has an epitaxial layer; forming a dielectric layer on the epitaxial layer; forming a first alignment structure in the dielectric layer, and the first alignment structure is in contact with the top of the epitaxial layer; forming a metal contact layer on the dielectric layer; forming a first opening in the metal contact layer, and the first opening exposes the first alignment structure; and forming an etch-resistant layer which fills the first opening and covers the top of the metal contact layer, wherein the light transmittance of the etch-resistant layer to a detection light is greater than the light transmittance of the metal contact layer to the detection light. By using the technical scheme, the detection accuracy of the alignment structure can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a power device and a method for forming the same. Background Technology

[0002] In the semiconductor field, power devices have high drive voltage, low resistance and good switching characteristics, and are widely used in high voltage integrated circuits and power integrated circuits.

[0003] In the process of forming power devices, alignment structures are usually formed. The position of the alignment structures is detected to ensure the accuracy of overlay between different process layers.

[0004] However, in the power devices currently available, the alignment structure cannot be detected or the detection effect is poor when using probe light to detect the alignment structure, resulting in a weak alignment signal. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a power device and a method for forming the same, which can improve the detection accuracy of the alignment structure.

[0006] This invention provides a method for forming a power device, comprising: providing a substrate having an epitaxial layer thereon; forming a dielectric layer on the epitaxial layer; forming a first alignment structure in the dielectric layer that contacts the top of the epitaxial layer; forming a metal contact layer on the dielectric layer; forming a first opening in the metal contact layer that exposes the first alignment structure; and forming an etch-resistant layer that fills the first opening and covers the top of the metal contact layer, wherein the transmittance of the etch-resistant layer to probe light is greater than the transmittance of the metal contact layer to the probe light.

[0007] Optionally, the width of the first alignment structure is 1 μm to 8.8 μm and the height is 0.5 μm to 0.7 μm.

[0008] Optionally, the material of the first alignment structure includes one or more of Ni, W, Ti, TiN, Ta, Pt, and Co.

[0009] Optionally, the thickness of the metal contact layer is 3 μm to 5 μm.

[0010] Optionally, forming a first opening within the metal contact layer to expose the first alignment structure includes:

[0011] A mask structure with a first patterned opening is formed on the metal contact layer, and the first patterned opening is disposed opposite to the first alignment structure along the normal direction of the substrate surface.

[0012] Along the first pattern opening, remove the metal contact layer exposed by the first pattern opening, and form a first opening in the metal contact layer that exposes the first alignment structure.

[0013] After the first opening is formed, the mask structure is removed.

[0014] Optionally, the process for removing the exposed metal contact layer from the first patterned opening includes: a dry etching process;

[0015] The parameters of the dry etching process include: pressure of 7 mTorr to 9 mTorr, power of 1000 watts to 1200 watts, radio frequency energy of 335 watts to 410 watts, and etching gases of CL2 and BCL3, wherein the flow rate of CL2 is 220 sccm to 270 sccm and the flow rate of BCL3 is 125 sccm to 150 sccm.

[0016] Optionally, the step of forming a first opening in the metal contact layer to expose the first alignment structure further includes: forming a second opening in the metal contact layer on one side of the first opening to expose the top of the dielectric layer;

[0017] In the step of forming an anti-etching layer that fills the first opening and covers the top of the metal contact layer, the anti-etching layer also fills the second opening, wherein the anti-etching layer located within the second opening serves as a second alignment structure.

[0018] Optionally, the material of the anti-etching layer is one of photoresist, Si-ARC material, DARC material, BARC material, DUO material or ODL material.

[0019] Optionally, before forming the anti-etching layer that fills the first opening and covers the top of the metal contact layer, the method further includes:

[0020] A protective layer is formed on the metal contact layer and inside the first opening, and the top height of the protective layer inside the first opening is lower than the top height of the first opening;

[0021] In the step of forming an anti-etching layer that fills the first opening and covers the metal contact layer, the anti-etching layer also covers the top and part of the sidewalls of the protective layer.

[0022] This invention also provides a power device, comprising: a substrate having an epitaxial layer thereon; a dielectric layer located on the epitaxial layer; a first alignment structure located within the dielectric layer and in contact with the top of the epitaxial layer; a metal contact layer located on the dielectric layer; and an etch-resistant layer including a first portion located on the metal contact layer and a second portion located within the metal contact layer and in contact with the top of the first alignment structure.

[0023] Optionally, the power device further includes a protective layer located between the first portion and the metal contact layer, and between the second portion and the first alignment structure.

[0024] Optionally, the anti-etching layer further includes a third portion located within the metal contact layer and in contact with the top of the dielectric layer, the third portion serving as a second alignment mark.

[0025] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0026] In the method for forming a power device provided in this embodiment of the invention, after forming a first alignment structure in the dielectric layer that contacts the top of the epitaxial layer, an anti-etching layer can be formed in the first opening in the metal contact layer to expose the first alignment structure. Since the transmittance of the anti-etching layer to the probe light is greater than that of the metal contact layer to the probe light, the obstruction of the probe light by the metal contact layer can be reduced, allowing most of the probe light to be transmitted to the first alignment structure. Thus, with most of the probe light irradiating the first alignment structure, the strength of the alignment signal can be increased, thereby improving the detection accuracy of the alignment structure.

[0027] In the power device provided in this embodiment of the invention, the anti-etching layer includes a second portion within the metal contact layer that contacts the top of the first alignment structure. Since the transmittance of the anti-etching layer to the probe light is greater than that of the metal contact layer to the probe light, the obstruction of the metal contact layer to the probe light can be reduced, allowing most of the probe light to be transmitted to the first alignment structure. Thus, when most of the probe light is irradiated to the first alignment structure, the strength of the alignment signal can be increased, thereby improving the detection accuracy of the alignment structure. Attached Figure Description

[0028] Figures 1 to 8 This invention is a schematic diagram of the structure corresponding to each step of a power device;

[0029] Figure 9 This is a schematic diagram of the structure of one embodiment of the power device of the present invention. Detailed Implementation

[0030] As described in the background section, in currently developed power devices, the alignment structure cannot be detected or the detection effect is poor when using probe light to detect the alignment structure. This is because:

[0031] During the formation of power devices, a thicker metal layer needs to be grown to meet the electrical parameter requirements of the power devices (for example, in some application scenarios, power devices need to have high withstand voltage and current values); and in subsequent processing, a thicker photoresist needs to be spin-coated on the metal layer to ensure that the surface of the metal layer is not etched and to improve the integrity of the metal layer surface.

[0032] Thus, with the double obstruction of the thicker metal and the thicker photoresist, only a small portion of the probe light can be transmitted to the alignment structure (or alignment mark), which adversely affects the alignment process and may even prevent the alignment operation from being performed effectively.

[0033] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate having an epitaxial layer thereon; forming a dielectric layer on the epitaxial layer; forming a first alignment structure within the dielectric layer that contacts the top of the epitaxial layer; forming a metal contact layer on the dielectric layer; forming a first opening within the metal contact layer that exposes the first alignment structure; and forming an etch-resistant layer that fills the first opening and covers the metal contact layer, wherein the transmittance of the etch-resistant layer to probe light is greater than the transmittance of the metal contact layer to the probe light.

[0034] In the formation method provided by the present invention, since the transmittance of the anti-etching layer to the probe light is greater than that of the metal contact layer to the probe light, the obstruction of the metal contact layer to the probe light can be reduced, so that most of the probe light can be transmitted to the first alignment structure. In this way, when most of the probe light is irradiated to the first alignment structure, the strength of the alignment signal can be improved, thereby improving the detection accuracy of the alignment structure.

[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described below with reference to the accompanying drawings.

[0036] Figures 1 to 8 This invention is a schematic diagram of the structure corresponding to each step of a power device.

[0037] See Figure 1 A substrate 100 is provided, on which an epitaxial layer 102 is provided.

[0038] In this embodiment, the substrate 100 can provide the basis for the fabrication process of the power device. The power device may include a vertically double-diffused metal-oxide-semiconductor (LDMOS) structure and / or a vertically double-diffused metal-oxide-semiconductor (VDMOS) structure. In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate (IHD), etc., and the substrate may also be a silicon-on-insulator (SiI) substrate or a germanium-on-insulator (CHI) substrate, etc. The substrate material can be a material suitable for process requirements or easy to integrate.

[0039] In some embodiments, the substrate may further include a substrate, a plurality of discrete fins located above the substrate, and an isolation structure located on the substrate exposed by the fins, the isolation structure covering a portion of the sidewalls of the fins, and the top of the isolation structure being lower than the top of the fins.

[0040] In this embodiment, the isolation structure serves to electrically isolate adjacent fins.

[0041] In some embodiments, the material of the isolation structure can be an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride.

[0042] In this embodiment, the material of the isolation structure can be silicon oxide.

[0043] The epitaxial layer 102 serves to improve the withstand voltage of the power device. The thicker the epitaxial layer 102, the greater the withstand voltage of the power device.

[0044] In this embodiment, an epitaxial layer 102 is formed on the substrate 100 by an epitaxial process, wherein the thickness of the epitaxial layer 102 can be 4 μm.

[0045] In this embodiment, the epitaxial layer 102 can be made of single-crystal silicon. See also Figure 2 A dielectric layer 104 is formed on the epitaxial layer 102.

[0046] The dielectric layer 104 provides a spatial location for forming the first alignment structure and enables electrical isolation between adjacent devices.

[0047] In this embodiment, atomic layer deposition (ALD) can be used to form a dielectric layer 104 on the epitaxial layer 102. By performing multiple atomic layer deposition cycles, the thickness uniformity of the dielectric layer 104 can be improved.

[0048] In some other embodiments, other deposition processes (such as chemical vapor deposition) may be used to form a dielectric layer on the epitaxial layer.

[0049] In this embodiment, the thickness of the dielectric layer 104 should not be too large or too small. If the thickness of the dielectric layer 104 is too large, the area of ​​the power device will increase, thereby increasing power consumption; if the thickness of the dielectric layer 104 is too small, the optical path of the probe light will be longer when the probe light is used to detect the first alignment structure, which may easily lead to the inability to detect the first alignment structure or a weak detection signal when the first alignment structure is detected. Based on this, in this embodiment, the thickness of the dielectric layer 104 is 0.5 μm to 0.7 μm.

[0050] In one specific embodiment, the dielectric layer 104 has a thickness of 0.6 μm.

[0051] In this embodiment, the dielectric layer 104 can be made of B / P doped silicon. In some other examples, the dielectric layer 104 can be made of other insulating materials such as silicon nitride and silicon oxide.

[0052] See Figure 3 and Figure 4 A first alignment structure 106 is formed within the dielectric layer 104 to contact the top of the epitaxial layer 102.

[0053] The first alignment structure 106 can serve as an alignment mark to determine the overlay accuracy between different film layers.

[0054] In this embodiment, the step of forming a first alignment structure 106 in the dielectric layer 104 that contacts the top of the epitaxial layer 102 includes:

[0055] See Figure 3 A trench G1 is formed within the dielectric layer 104 to expose the epitaxial layer 102.

[0056] In this embodiment, an etching process (dry etching process and / or wet etching process) is used to remove part of the dielectric layer 104 until the top of the epitaxial layer 102 is exposed, and a trench G1 is formed in the dielectric layer 104.

[0057] See Figure 4 A first alignment structure 106 is formed in the trench G1 to contact the top of the epitaxial layer 102.

[0058] Specifically, the step of forming a first alignment structure 106 in the trench G1 that contacts the top of the epitaxial layer 102 includes: forming an alignment mark material layer (not shown) that fills the trench G1 on the top of the dielectric layer 104; performing planarization to remove the alignment mark material layer above the top of the dielectric layer 104, and retaining the alignment mark material layer in the trench G1 as the first alignment structure 106.

[0059] In this embodiment, after planarization, the top of the first alignment structure 106 can be trimmed by means of ion beam etching to reduce the roughness of the top of the first alignment structure 106.

[0060] In this embodiment, the width w of the first alignment structure 106 should not be too large or too small. If the width w of the first alignment structure 106 is too large, it will increase the power consumption of the device; if the width w of the first alignment structure 106 is too small, it means that the alignment area is too small, and when the first alignment structure 106 is detected by the probe light, it is difficult to detect the first alignment structure 106 or the detection signal is weak. Based on this, in this embodiment, the width w of the first alignment structure 106 is 1μm to 8.8μm.

[0061] In one specific embodiment, the width w of the first alignment structure 106 can be 8 μm. In this embodiment, the height of the first alignment structure 106 is the same as the height of the dielectric layer 104, and the height of the first alignment structure 106 is 0.5 μm to 0.7 μm.

[0062] In one specific embodiment, the height of the first alignment structure 106 is 0.6 μm.

[0063] In this embodiment, the material of the first alignment structure 106 includes one or more of Ni, W, Ti, TiN, Ta, Pt, and Co.

[0064] In one specific embodiment, the material of the first alignment structure 106 may include W.

[0065] It should be noted that this embodiment uses the formation of two first alignment structures 106 within the dielectric layer 104 as an example for illustrative purposes. In some other embodiments, only one first alignment structure 106 may be formed within the dielectric layer 104. This embodiment does not limit the number of first alignment structures 106.

[0066] See Figure 5 A metal contact layer 108 is formed on the dielectric layer 104.

[0067] The metal contact layer 108 determines the withstand voltage of the power device. The thicker the metal contact layer 108, the greater the withstand voltage of the power device.

[0068] In this embodiment, a physical vapor deposition process can be used to form a metal contact layer 108 on the dielectric layer 104.

[0069] In this embodiment, the thickness of the metal contact layer 108 should not be too large or too small. If the thickness of the metal contact layer 108 is too large, the thickness of the subsequently formed anti-etching layer will be too large, which will increase the optical path of the probe light, making it difficult to detect the first alignment structure or resulting in a weak detection signal when the first alignment structure is detected using the probe light. If the thickness of the metal contact layer 108 is too small, the withstand voltage of the power device will be reduced. Therefore, the thickness of the metal contact layer 108 is 3μm to 5μm.

[0070] In one specific embodiment, the thickness of the metal contact layer 108 is 4 μm.

[0071] In this embodiment, the material of the metal contact layer 108 may include one or more of Ni, W, Ti, TiN, Ta, Pt, Al, Cu, Ag, Au and Co.

[0072] In one specific embodiment, the metal contact layer 108 is made of an alloy of Al and Cu.

[0073] See Figure 6 and Figure 7 A first opening K1 is formed within the metal contact layer 108 to expose the first alignment structure 106.

[0074] The first opening K1 provides process space for forming the etch stop layer.

[0075] In this embodiment, the step of forming a first opening K1 exposing the first alignment structure 106 within the metal contact layer 108 includes:

[0076] See Figure 6 A mask structure 110 with a first patterned opening P1 is formed on the metal contact layer 108, and the first patterned opening P1 is disposed opposite to the first alignment structure 106 along the normal direction of the surface of the substrate 100.

[0077] In this embodiment, the material of the mask structure 110 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, and boron carbide.

[0078] In this embodiment, the mask structure 110 is a single-layer structure. In some other examples, the mask structure 110 may also be a multi-layer structure.

[0079] See Figure 7 Along the first pattern opening P1, the exposed metal contact layer 108 of the first pattern opening P1 is removed, and a first opening K1 is formed in the metal contact layer 108 to expose the first alignment structure 106.

[0080] Specifically, using the mask structure 110 as a mask, photolithography and etching processes are performed to remove the metal contact layer 108 exposed by the first pattern opening P1 until the first alignment structure 106 is exposed to form the first opening K1.

[0081] The width of the first opening K1 is related to the width of the first alignment structure 106. For example, the larger the width of the first alignment structure 106, the larger the width of the first opening K1 will be.

[0082] In this embodiment, the process of removing the exposed metal contact layer 108 from the first pattern opening P1 includes: a dry etching process.

[0083] More specifically, the parameters of the dry etching process include: pressure of 7 mTorr to 9 mTorr, power of 1000 WT to 1200 WT, radio frequency energy of 335 WB to 410 WB, and etching gases of CL2 and BCL3, wherein the flow rate of CL2 is 220 sccm to 270 sccm and the flow rate of BCL3 is 125 sccm to 150 sccm.

[0084] In this embodiment, the parameters of the dry etching process may also include the processing time, for example, the processing time may be 8 min to 12 min.

[0085] In this embodiment, during the step of forming the first patterned opening P1, the first patterned opening P1 may also expose a portion of the top of the dielectric layer 104. That is, the width of the first patterned opening P1 is greater than the width of the first alignment structure 106.

[0086] In this embodiment, see Figure 7 After the first opening K1 is formed, the mask structure 110 is removed.

[0087] In one specific implementation, an ashing process is used to remove the mask structure 110.

[0088] See Figure 8 This forms an anti-etching layer 120 that fills the first opening K1 and covers the top of the metal contact layer.

[0089] The anti-etching layer 120 is used to protect the surface of the channel structure layer 108. The transmittance of the anti-etching layer 120 to the probe light is greater than that of the metal contact layer 108 to the probe light. This reduces the obstruction of the probe light by the metal contact layer 108, allowing most of the probe light to be transmitted to the first alignment structure 106. In this way, when most of the probe light is irradiated to the first alignment structure 106, the strength of the alignment signal can be improved, thereby improving the detection accuracy of the alignment structure.

[0090] In this embodiment, an anti-etching layer 120 that fills the first opening K1 and covers the top of the metal contact layer is formed by a deposition process (e.g., chemical vapor deposition).

[0091] In this embodiment, the thickness Th of the resist layer 120 should not be too large or too small. If the thickness Th of the resist layer 120 is too large, the time required to open the resist layer 120 during subsequent photolithography processes will be too long. If the thickness Th of the resist layer 120 is too small, the resist layer 120 located on top of the metal contact layer 108 may be completely consumed during etching processes in other areas above the substrate 100, thereby etching a portion of the metal contact layer 108 and reducing the electrical performance of the power device. Therefore, in this embodiment, the thickness Th of the resist layer 120 is 4 μm to 6 μm.

[0092] In one specific embodiment, the thickness Th of the anti-etching layer 120 is 5 μm. In this embodiment, the anti-etching layer 120 includes: a first portion 121 covering the top of the metal contact layer, and a second portion 122 filling the first opening K1 and contacting the first alignment structure 106.

[0093] In this embodiment, the material of the anti-etching layer 120 is one of photoresist, Si-ARC material, DARC material, BARC material, DUO material or ODL material.

[0094] In one specific embodiment, the etch-resistant layer 120 is a photoresist.

[0095] In the actual alignment process, the inventors further discovered that the more alignment structures set up and distributed in different film layers, the better the alignment effect.

[0096] Based on this, see further. Figure 6 and Figure 7 In the step of forming a first opening K1 in the metal contact layer 108 to expose the first alignment structure 106, the method of forming the power device further includes forming a second opening K2 in the metal contact layer 108 on one side of the first opening K1 to expose the top of the dielectric layer 104.

[0097] The second opening K2 provides process space for forming the second alignment mark.

[0098] In this embodiment, the formation process of the second opening K2 can be referred to the description of the first opening K1, except that the width of the second opening K2 is smaller than the width of the first opening K1, that is, the width of the second graphic opening P2 is smaller than the width of the first graphic opening P1.

[0099] In this embodiment, see Figure 8In the step of forming an anti-etching layer 120 that fills the first opening K1 and covers the top of the metal contact layer 108, the anti-etching layer 120 also fills the second opening K2.

[0100] The method of forming the anti-etching layer 120 in the second opening K2 can be found in the aforementioned example.

[0101] In this embodiment, the anti-etching layer 120 located within the second opening K2 serves as the second alignment structure, that is... Figure 8 The third portion 123, located within the metal contact layer 108 and in contact with the top of the dielectric layer 104, can serve as a second alignment structure.

[0102] It should be noted that, firstly, when the second opening K2 is formed, there are multiple second openings K2 (e.g., Figure 7 The two second openings K2 shown in the diagram allow for the formation of a dense pattern of alternating light and dark areas within the metal contact layer 108, facilitating precise location of the alignment mark. Secondly, due to the relatively thick metal contact layer 108, the sidewalls of the formed second openings K2 have poor smoothness after etching, resulting in a poor morphology of the formed second alignment structure and unsatisfactory detection performance. Therefore, directly relying on the detection signal formed by the second alignment structure could easily lead to extensive wafer rework. Thus, in this embodiment of the invention, the first alignment structure is preferentially used as the alignment mark.

[0103] In this embodiment, before the anti-etching layer 120 that fills the first opening K1 and covers the top of the metal contact layer 108 is formed, the top of the metal contact layer 108 is exposed to air. When the metal contact layer 108 is in a humid environment or an environment full of corrosive gases, the flatness of the top surface of the metal contact layer 108 is easily damaged, thereby reducing the performance of the power device.

[0104] Based on this, see Figure 8 Before forming the anti-etching layer 120 that fills the first opening K1 and covers the top of the metal contact layer 108, the method for forming the power device further includes:

[0105] A protective layer 112 is formed on the metal contact layer 108 and inside the first opening K1, and the top height of the protective layer 112 inside the first opening K1 is lower than the top height of the first opening K1.

[0106] In this embodiment, a chemical vapor deposition process is used to form a protective layer 112 on the metal contact layer 108 and inside the first opening K1.

[0107] In this embodiment, the thickness of the protective layer 112 should not be too large or too small. If the thickness of the protective layer 112 is too large, it will increase the power consumption of the power device; if the thickness of the protective layer 112 is too small, there is a risk that the surface of the metal contact layer 108 will be exposed to the air again due to the protective layer 112 being completely consumed in subsequent processes. Based on this, in this embodiment, the thickness of the protective layer 112 is 0.8 μm to 1 μm.

[0108] In one specific embodiment, the protective layer 112 has a thickness of 0.9 μm.

[0109] In this embodiment, the material of the protective layer 112 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate, silicon carbonitride, boron nitride, and boron carbonitride.

[0110] In one specific embodiment, the material of the protective layer 112 is silicon nitride.

[0111] See next Figure 8 In the step of forming an anti-etching layer 120 that fills the first opening K1 and covers the metal contact layer 108, the anti-etching layer 120 also covers the top and part of the sidewalls of the protective layer 112.

[0112] For example, the first portion 121 and the third portion 123 of the anti-etching layer 120 cover the top of the protective layer 112, while the second portion 122 of the anti-etching layer 120 covers the sidewalls of the protective layer 112.

[0113] Therefore, by employing the power device formation method described in the above example, the corrected residual value (ROPI) of the power device can be reduced. For example, the ROPI value in this embodiment is less than 40 nm, while the ROPI value in the prior art is close to 150 nm. Thus, it can be seen that the method in this embodiment can significantly improve alignment accuracy.

[0114] The present invention also provides a power device, see below. Figure 9 The schematic diagram shown is a structural diagram corresponding to an embodiment of the power device of the present invention, as follows: Figure 9 As shown, the power device includes: a substrate 200 having an epitaxial layer 202 thereon; a dielectric layer 204 located on the epitaxial layer 202; a first alignment structure 206 located within the dielectric layer 204 and in contact with the top of the epitaxial layer 202; a metal contact layer 208 located on the dielectric layer 204; and an etch resist layer 220 including a first portion 221 located on the metal contact layer 208 and a second portion 222 located within the metal contact layer 208 and in contact with the top of the first alignment structure 206.

[0115] In this embodiment, the substrate 200 can provide the basis for the fabrication process of the power device. The power device may include a vertically double-diffused metal-oxide-semiconductor (LDMOS) structure and / or a vertically double-diffused metal-oxide-semiconductor (VDMOS) structure.

[0116] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0117] In some embodiments, the substrate may further include a substrate, a plurality of discrete fins located above the substrate, and an isolation structure located on the substrate exposed by the fins, the isolation structure covering a portion of the sidewalls of the fins, and the top of the isolation structure being lower than the top of the fins.

[0118] In this embodiment, the isolation structure serves to electrically isolate adjacent fins.

[0119] In some embodiments, the material of the isolation structure can be an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride.

[0120] In this embodiment, the material of the isolation structure can be silicon oxide.

[0121] The epitaxial layer 202 serves to improve the withstand voltage of the power device. The thicker the epitaxial layer 202, the higher the withstand voltage of the power device. For example, the thickness of the epitaxial layer 202 can be 4μm.

[0122] In this embodiment, the material of the epitaxial layer 202 can be monocrystalline silicon.

[0123] The dielectric layer 204 provides location space for forming the first alignment structure and enables electrical isolation between adjacent devices.

[0124] In this embodiment, the thickness of the dielectric layer 204 should not be too large or too small. If the thickness of the dielectric layer 204 is too large, the area of ​​the power device will increase, thereby increasing power consumption; if the thickness of the dielectric layer 204 is too small, the optical path of the probe light will be longer when the probe light is used to detect the first alignment structure 206, which may lead to the inability to detect the first alignment structure 206 or a weak detection signal when the first alignment structure 206 is detected. Based on this, in this embodiment, the thickness of the dielectric layer 204 is 0.5 μm to 0.7 μm.

[0125] In one specific embodiment, the dielectric layer 204 has a thickness of 0.6 μm.

[0126] In this embodiment, the dielectric layer 204 can be made of B / P doped silicon. In some other examples, the dielectric layer 204 can be made of other insulating materials such as silicon nitride and silicon oxide.

[0127] The first alignment structure 206 can serve as an alignment mark to determine the overlay accuracy between different film layers.

[0128] In this embodiment, the width w of the first alignment structure 206 should not be too large or too small. If the width w of the first alignment structure 206 is too large, it will increase the power consumption of the device; if the width w of the first alignment structure 206 is too small, it means that the alignment area is too small, and when the first alignment structure 206 is detected by the probe light, it will be difficult to detect the first alignment structure 206 or the detection signal will be weak. Based on this, in this embodiment, the width w of the first alignment structure 206 is 1μm to 8.8μm.

[0129] In one specific embodiment, the width w of the first alignment structure 206 can be 8 μm.

[0130] In this embodiment, the height of the first alignment structure 206 is the same as the height of the dielectric layer 204, and the height of the first alignment structure 206 is 0.5μm to 0.7μm.

[0131] In one specific embodiment, the height of the first alignment structure 206 is 0.6 μm.

[0132] In this embodiment, the material of the first alignment structure 206 includes one or more of Ni, W, Ti, TiN, Ta, Pt and Co.

[0133] In one specific embodiment, the material of the first alignment structure 206 may include W.

[0134] It should be noted that this embodiment uses the formation of two first alignment structures 206 within the dielectric layer 204 as an example for illustrative purposes. In some other embodiments, only one first alignment structure 206 may be formed within the dielectric layer 204. This embodiment does not limit the number of first alignment structures 206.

[0135] The metal contact layer 208 determines the withstand voltage of the power device. The thicker the metal contact layer 208, the higher the withstand voltage of the power device.

[0136] In this embodiment, the thickness of the metal contact layer 208 should not be too large or too small. If the thickness of the metal contact layer 208 is too large, it will result in an excessively large thickness of the resist layer 220, which will increase the optical path of the probe light. This will make it difficult to detect the first alignment structure 206 when using the probe light, or if the first alignment structure 206 is detected, the detection signal will be weak. If the thickness of the metal contact layer 208 is too small, it will reduce the withstand voltage of the power device. Therefore, the thickness of the metal contact layer 208 is 3 μm to 5 μm.

[0137] In one specific embodiment, the thickness of the metal contact layer 208 is 4 μm.

[0138] In this embodiment, the material of the metal contact layer 208 may include one or more of Ni, W, Ti, TiN, Ta, Pt, Al, Cu, Ag, Au and Co.

[0139] In one specific embodiment, the metal contact layer 208 is made of an alloy of Al and Cu.

[0140] The anti-etching layer 220 is used to protect the surface of the channel structure layer 208. The transmittance of the anti-etching layer 220 to the probe light is greater than that of the metal contact layer 208 to the probe light. This reduces the obstruction of the probe light by the metal contact layer 208, allowing most of the probe light to be transmitted to the first alignment structure 206. In this way, when most of the probe light is irradiated to the first alignment structure, the strength of the alignment signal can be improved, thereby improving the detection accuracy of the alignment structure.

[0141] In this embodiment, the thickness Th of the anti-etching layer 220 is 4 μm to 6 μm. In a specific embodiment, the thickness Th of the anti-etching layer 220 is 5 μm.

[0142] In this embodiment, the material of the anti-etching layer 220 is one of photoresist, Si-ARC material, DARC material, BARC material, DUO material or ODL material.

[0143] In one specific embodiment, the etch-resistant layer 220 is a photoresist.

[0144] In the actual alignment process, the inventors further discovered that the more alignment structures set up and distributed in different film layers, the better the alignment effect.

[0145] Based on this, see further. Figure 9 The etch-resistant layer 220 also includes a third portion 222 located within the metal contact layer 208 and in contact with the top of the dielectric layer 207.

[0146] In this embodiment, the third part 222 can serve as a second alignment structure.

[0147] In this embodiment, see next. Figure 9 The power device also includes a protective layer 212 located between the first portion 221 and the metal contact layer 208, and between the second portion 222 and the first alignment structure 206.

[0148] The protective layer 212 is used to protect the metal contact layer 208 and avoid or reduce the probability of damage to the top of the metal contact layer 208 when the power device is in a humid environment or an environment full of corrosive gases.

[0149] In this embodiment, the thickness of the protective layer 212 should not be too large or too small. If the thickness of the metal contact layer 212 is too large, it will increase the power consumption of the power device; if the thickness of the protective layer 212 is too small, it may not be able to protect the surface of the metal contact layer 208. Based on this, in this embodiment, the thickness of the protective layer 212 is 0.8 μm to 1 μm.

[0150] In one specific embodiment, the protective layer 212 has a thickness of 0.9 μm.

[0151] In this embodiment, the material of the protective layer 212 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate, silicon carbonitride, boron nitride, and boron carbonitride.

[0152] In one specific embodiment, the material of the protective layer 212 is silicon nitride.

[0153] In this embodiment, when the power device includes a second alignment mark, the protective layer 212 is also located between the second alignment mark and the dielectric layer 204.

[0154] It should be noted that the power device described in this embodiment can be formed using the forming method described in the foregoing embodiments, or it can be formed using other forming methods. For a detailed description of the power device described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0155] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a power device, comprising: The method comprises: providing a substrate with an epitaxial layer on the substrate; forming a dielectric layer on the epitaxial layer; forming a first alignment structure in the dielectric layer and in contact with a top of the epitaxial layer; forming a metal contact layer on the dielectric layer; forming a first opening in the metal contact layer and exposing the first alignment structure; forming an etch-resistant layer filling the first opening and covering a top of the metal contact layer, wherein a light transmittance of the etch-resistant layer to a probe light is greater than a light transmittance of the metal contact layer to the probe light.

2. The method of claim 1, wherein The first alignment structure has a width of 1 μm to 8.8 μm and a height of 0.5 μm to 0.7 μm.

3. The method of forming a power device according to claim 1 or 2, wherein The first alignment structure is made of one or more of Ni, W, Ti, TiN, Ta, Pt and Co.

4. The method of claim 1, wherein The metal contact layer has a thickness of 3 μm to 5 μm.

5. The method of claim 1, wherein The forming of the first opening in the metal contact layer and exposing the first alignment structure comprises: forming a mask structure with a first pattern opening on the metal contact layer, wherein the first pattern opening is disposed opposite to the first alignment structure along a normal direction of a surface of the substrate; removing the metal contact layer exposed by the first pattern opening along the first pattern opening to form the first opening in the metal contact layer and exposing the first alignment structure; and removing the mask structure after the forming of the first opening.

6. The method of claim 5, wherein The process of removing the metal contact layer exposed by the first pattern opening comprises a dry etching process. The dry etching process has parameters including a pressure of 7 mTorr to 9 mTorr, a power of 1000 wT to 1200 wT, a radio frequency energy of 335 wB to 410 wB, and an etching gas of CL2 and BCL3, wherein the flow rate of CL2 is 220 sccm to 270 sccm and the flow rate of BCL3 is 125 sccm to 150 sccm.

7. The method of forming a power device according to claim 1 or 5, wherein The forming of the first opening in the metal contact layer and exposing the first alignment structure further comprises forming a second opening in the metal contact layer on a side of the first opening and exposing a top of the dielectric layer. The etch-resistant layer also fills the second opening in the step of forming the etch-resistant layer filling the first opening and covering the top of the metal contact layer, wherein the etch-resistant layer in the second opening serves as a second alignment structure.

8. The method of claim 1, wherein The etch-resistant layer is made of one of a photoresist, a Si-ARC material, a DARC material, a BARC material, a DUO material or an ODL material.

9. The method of claim 1, wherein The method further comprises, before the forming of the etch-resistant layer filling the first opening and covering the top of the metal contact layer: forming a protection layer on the metal contact layer and in the first opening, wherein a top of the protection layer in the first opening is lower than a top of the first opening; and the etch-resistant layer also covers the top and part of the sidewall of the protection layer in the step of forming the etch-resistant layer filling the first opening and covering the metal contact layer.

10. A power device, characterized by The method comprises: providing a substrate with an epitaxial layer on the substrate; forming a dielectric layer on the epitaxial layer; a first alignment structure within the dielectric layer and in contact with a top of the epitaxial layer; a metal contact layer on the dielectric layer; an etch-resistant layer including a first portion on the metal contact layer and a second portion within the metal contact layer and in contact with a top of the first alignment structure.

11. The power device of claim 10, wherein, Further comprising: a protective layer between the first portion and the metal contact layer and between the second portion and the first alignment structure.

12. The power device of claim 10, wherein, the etch-resistant layer further including a third portion within the metal contact layer and in contact with a top of the dielectric layer, the third portion as a second alignment mark.

Images