Formation method of semiconductor structure

Abstract

The embodiment of the invention provides a method for forming a semiconductor structure, which comprises the following steps of: providing a substrate on which a dielectric layer is formed; forming an initial groove in the dielectric layer; performing at least one time of etching treatment on the dielectric layer exposed out of the initial groove until a target groove with a set depth is formed in the dielectric layer; wherein any time of etching treatment comprises the steps that a planarization coating with a mask opening is formed on the dielectric layer, and the initial groove is exposed out of the mask opening; and removing the dielectric layer exposed in the depth direction of the initial groove by taking the planarization coating as a mask and adopting a directional etching process. By adopting the technical scheme, the electrical performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the rapid development of semiconductor technology, the performance requirements of semiconductor devices are getting higher and higher, the integration of semiconductor devices is getting higher and higher, and accordingly, the size of a single device is getting smaller and smaller.

[0003] Since the deep trench structure has the characteristic of expanding the chip area in the vertical direction, the deep trench structure is widely used in various semiconductor devices to improve the integration of the semiconductor devices.

[0004] However, the electrical performance of semiconductor devices formed so far still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure to improve the electrical performance of the semiconductor structure.

[0006] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, on which a dielectric layer is formed; forming an initial groove in the dielectric layer; performing at least one etching process on the dielectric layer exposed by the initial groove until a target groove with a set depth is formed in the dielectric layer; wherein any etching process comprises: forming a planarization coating having a mask opening on the dielectric layer, the mask opening exposing the initial groove; using the planarization coating as a mask, adopting a directional etching process, and removing the dielectric layer exposed by the initial groove along the depth direction.

[0007] Optionally, the directional etching process includes a gas etching process;

[0008] In the process of removing the dielectric layer exposed in the initial trench along the depth direction by using the gas etching process, the polymer remaining on the sidewall of the initial trench serves as an etching stop layer.

[0009] Optionally, the etching gas of the gas etching process includes C4F8, CHF3, Ar and O2; the etching power is 2200 to 2600W; the etching time is 700s to 900s; and the pressure is 200mT to 250mT.

[0010] Optionally, the step of forming a planarization coating having a mask opening on the dielectric layer includes:

[0011] forming a planarization coating on the dielectric layer, wherein the planarization coating completely fills the initial groove;

[0012] forming a first barrier layer having a first opening on the planarization coating layer, wherein the first opening exposes a top portion of the planarization coating layer, and a position of the first opening is opposite to a position of the initial groove;

[0013] The planarization coating layer exposed by the first opening is removed along the sidewall of the first barrier layer, and the mask opening is formed in the planarization coating layer.

[0014] Optionally, the material of the planarization coating includes at least one of SiON, Si3N4, SiC, SOC and TiO2;

[0015] The material of the first barrier layer includes at least one of photoresist and titanium nitride.

[0016] Optionally, the method for forming the semiconductor structure further includes:

[0017] Before forming a first barrier layer having a first opening on the planarization coating layer, forming a protective layer on the planarization coating layer; wherein the first barrier layer is located above the protective layer, and the first opening exposes the top of the protective layer;

[0018] In the step of removing the planarization coating layer exposed by the first opening along the sidewall of the first barrier layer, the protection layer exposed by the first opening is also removed.

[0019] Optionally, a low temperature oxidation process is used to form the protective layer on the planarization coating.

[0020] Optionally, a dry etching process is used to remove the protective layer exposed by the first opening and the planarization coating layer under the protective layer.

[0021] Optionally, the material of the protective layer includes: silicon oxide.

[0022] Optionally, any etching process further includes:

[0023] After removing the dielectric layer exposed in the initial trench along the depth direction by adopting a directional etching process, the planarization coating on the dielectric layer is removed.

[0024] Optionally, an ashing process is used to remove the planarization coating on the dielectric layer.

[0025] Optionally, the step of forming an initial trench in the dielectric layer includes:

[0026] forming a second barrier layer having a second opening on the dielectric layer, wherein the second opening exposes a top of the dielectric layer;

[0027] A portion of the dielectric layer exposed by the second opening is removed along the sidewall of the second barrier layer to form the initial trench in the dielectric layer.

[0028] Optionally, the set depth is greater than 10 microns.

[0029] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0030] In the method for forming a semiconductor structure provided by an embodiment of the present invention, an initial groove is formed in a dielectric layer, and a target groove with a set depth can be formed in the dielectric layer by performing at least one etching process on the dielectric layer exposed by the initial groove. For any etching process, when a planarization coating is used as a mask and a directional etching process is adopted, the dielectric layer exposed in the initial groove along the depth direction can be removed, the damage to the side wall of the initial groove is reduced, the flatness of the side wall of the target groove is improved, and the probability of subsequent generation of holes is reduced or avoided, thereby improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figures 1 to 8 It is a structural schematic diagram corresponding to each step of a semiconductor structure. DETAILED DESCRIPTION

[0032] The performance of current semiconductor structures needs to be improved. This is because an isotropic etching process is used when forming a deep trench structure. When etching the dielectric layer along the depth direction, the sidewalls of the dielectric layer are also etched, which causes a scalping effect on the sidewalls of the dielectric layer, forming sidewall ripples on the sidewalls of the dielectric layer. At present, the sidewall ripples can form a surface roughness of more than 100nm, which will produce holes when the deep trench structure is subsequently filled, thereby reducing the electrical performance of the semiconductor structure.

[0033] In order to solve the above technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, on which a dielectric layer is formed; forming an initial groove in the dielectric layer; performing at least one etching process on the dielectric layer exposed by the initial groove until a target groove with a set depth is formed in the dielectric layer; wherein any etching process comprises: forming a planarization coating having a mask opening on the dielectric layer, the mask opening exposing the initial groove; using the planarization coating as a mask, adopting a directional etching process to remove the dielectric layer exposed by the initial groove along the depth direction.

[0034] By adopting the above scheme, for any etching treatment, when the planarization coating is used as a mask and a directional etching process is adopted, the dielectric layer exposed in the initial groove along the depth direction can be removed, the damage to the side wall of the initial groove can be reduced, the flatness of the side wall of the target groove can be improved, and the probability of subsequent generation of holes can be reduced or avoided, thereby improving the electrical performance of the semiconductor structure.

[0035] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are exemplarily described below in conjunction with the accompanying drawings.

[0036] See also Figure 1 , a substrate 100 is provided, and a dielectric layer 102 is formed on the substrate 100.

[0037] In this embodiment, the substrate 100 can provide a process operation basis for the formation process of the semiconductor structure, wherein the semiconductor structure can include a complementary metal oxide semiconductor (CMOS), an integrated circuit (IC), a micro-electromechanical system (MEMS), any other electronic component or a combination of electronic components.

[0038] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0039] In some embodiments, the base may further include a substrate, a plurality of discrete fins located above the substrate, and an isolation structure located on the substrate where the fins are exposed. The isolation structure may cover a portion of the sidewalls of the fins, and the top of the isolation structure is lower than the top of the fins.

[0040] In this embodiment, the isolation structure serves to electrically isolate adjacent fins.

[0041] In some embodiments, the material of the isolation structure may be an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbon oxynitride.

[0042] In this embodiment, the material of the isolation structure may be silicon oxide.

[0043] The dielectric layer 102 may provide a spatial position for an initial trench and a target trench to be formed subsequently.

[0044] In this embodiment, a chemical vapor deposition process may be used to form a dielectric layer 102 on the substrate 100 .

[0045] In this embodiment, the material of the dielectric layer 102 may include low-k dielectric material (low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6), silicon oxide, silicon nitride or silicon oxynitride and other dielectric materials.

[0046] In a specific embodiment, the material of the dielectric layer 102 may include silicon oxide.

[0047] See also Figure 2 and Figure 3 , an initial trench 106 is formed in the dielectric layer 102 .

[0048] The initial trench 106 is used to provide a process window for forming a target trench.

[0049] In this embodiment, the step of forming the initial trench 106 in the dielectric layer 102 includes:

[0050] See also Figure 2 , a second barrier layer 104 having a second opening K1 is formed on the dielectric layer 102 , and the second opening K1 exposes the top of the dielectric layer 102 .

[0051] The second barrier layer 104 can protect the dielectric layer 102 to prevent other parts of the dielectric layer 102 from being damaged during the process of forming the second opening K1 .

[0052] In this embodiment, a photolithography process is used to form the second barrier layer 104 having the second opening K1 .

[0053] Specifically, a second barrier material layer (not shown) is formed on the dielectric layer 102 , a photoresist (not shown) having a pattern opening is formed on the second barrier material layer, and the second barrier material layer is patterned to form the second barrier layer 104 .

[0054] In this embodiment, chemical vapor deposition (for example, plasma enhanced PECVD, ion beam deposition IBD, sputtering and other deposition methods) is used to deposit and form the second barrier material layer.

[0055] In this embodiment, the material of the second barrier layer 104 may include at least one of photoresist, silicon nitride, titanium nitride and titanium oxide.

[0056] In a specific embodiment, the material of the second barrier layer 104 includes photoresist. The photoresist may include positive photoresist or negative photoresist, which is not specifically limited in the present invention.

[0057] See also Figure 3, along the sidewalls of the second barrier layer 104 , a portion of the dielectric layer 102 exposed by the second opening K1 is removed to form an initial trench 106 in the dielectric layer 102 , wherein the initial trench 106 is formed by the bottom and sidewalls of the dielectric layer 102 .

[0058] In this embodiment, a dry etching method is used to remove a portion of the dielectric layer 102 exposed by the second opening K1 .

[0059] In this embodiment, the depth of the initial groove 106 should not be too large, otherwise it is easy to affect the formation quality of the target groove. For example, if the depth of the initial groove 106 is too large, it means that the thickness of the removed dielectric layer 102 is relatively thick, which may cause damage to the side wall of the dielectric layer 102, and easily lead to the side wall of the target groove formed finally having poor smoothness; the depth of the initial groove 106 should not be too small, otherwise it takes too long to form the target groove. For this reason, in this embodiment, the depth of the initial groove 106 is 5 microns to 8 microns.

[0060] It should be noted that after the initial groove 106 is formed, the second barrier layer 104 is also removed; or, in the process of forming the initial groove 106, the second barrier layer 104 is also consumed (for example, when the material of the second barrier layer 104 is photoresist), when the initial groove 106 is formed, the second barrier layer 104 is completely consumed.

[0061] See also Figures 4 to 8 , performing at least one etching process on the dielectric layer 102 exposed by the initial groove 106 until a target groove 120 with a set depth is formed in the dielectric layer 102; wherein any etching process includes: forming a planarization coating 108 with a mask opening K2 on the dielectric layer 102, and the mask opening K2 exposes the initial groove 106; using the planarization coating 108 as a mask, adopting a directional etching process to remove the dielectric layer 102 exposed in the initial groove 106 along the depth direction.

[0062] The embodiment of the present invention performs at least one etching process on the dielectric layer 102 exposed by the initial groove 106, and adopts a directional etching process during the etching process, so as to remove the dielectric layer 102 exposed in the depth direction of the initial groove 106, thereby reducing damage to the side wall of the dielectric layer 102, improving the flatness of the side wall of the target groove, reducing or avoiding the probability of subsequent generation of holes, and thus improving the electrical performance of the semiconductor structure.

[0063] The steps of forming the target groove 120 in this embodiment are described in detail below with reference to the accompanying drawings.

[0064] See also Figures 4 to 6 The step of forming a planarization coating 108 having a mask opening K2 on the dielectric layer 102 includes:

[0065] See also Figure 4 , a planarization coating 108 is formed on the dielectric layer 102 , and the planarization coating 108 completely fills the initial trench 106 .

[0066] The planarization coating 108 can be used as a mask to remove the dielectric layer 102 exposed by the initial trench 106 to form a trench with a deeper depth.

[0067] In this embodiment, a chemical vapor deposition process is used to form a planarization coating 108 on the dielectric layer 102 to fill the initial trench 106 .

[0068] In this embodiment, the planarization coating 108 may include a bottom anti-reflection layer Barc, and the material of the bottom anti-reflection layer may include at least one of SiON, Si3N4, SiC, SOC and TiO2.

[0069] See also Figure 5 A first barrier layer 112 having a first opening K3 is formed on the planarization coating layer 108 . The first opening K3 exposes the top of the planarization coating layer 108 , and the position of the first opening K3 is opposite to the position of the initial trench 106 .

[0070] The first barrier layer 112 can protect the planarization coating layer 108 to prevent other parts of the planarization coating layer 108 from being damaged during the process of forming the first opening K3 .

[0071] In this embodiment, a photolithography process is used to form the first barrier layer 112 having the first opening K3.

[0072] Specifically, a first barrier material layer (not shown) is formed on the planarization coating layer 108 , a photoresist (not shown) is formed on the first barrier material layer, and the first barrier material layer is patterned to form a first barrier layer 112 having a first opening K3 .

[0073] In this embodiment, chemical vapor deposition (for example, deposition methods such as plasma enhanced PECVD, ion beam deposition IBD, sputtering, etc.) is used to form the first barrier material layer.

[0074] In this embodiment, the material of the first barrier layer 112 includes at least one of photoresist, silicon nitride, titanium nitride and titanium oxide.

[0075] In a specific embodiment, the material of the first barrier layer 112 includes photoresist. The photoresist may include positive photoresist or negative photoresist, which is not specifically limited in the present invention.

[0076] In this embodiment, the width of the first opening K3 parallel to the surface of the substrate 100 is the same as the width of the initial groove 106 parallel to the surface of the substrate 100, and the sidewall of the first opening K3 is collinear with the sidewall of the initial groove 106 in the normal direction of the surface of the substrate 100.

[0077] See also Figure 6 , the planarization coating layer 108 exposed by the first opening K3 is removed along the sidewall of the first barrier layer 112 , and a mask opening K2 is formed in the planarization coating layer 108 .

[0078] The mask opening K2 provides a process window for removing the dielectric layer 102 .

[0079] In this embodiment, a dry etching method is used to remove the planarization coating 108 exposed by the first opening K3. The etching gas used in the dry etching method includes CF4, CHF3, Ar and O2; the etching power is 2200 to 2600 W; the etching time is 250s to 350s; and the pressure is 200mT to 250mT.

[0080] It should be noted that after the mask opening K2 is formed, the first barrier layer 112 can be removed; or, in the process of forming the mask opening K2, the first barrier layer 112 is also consumed (for example, when the material of the first barrier layer 112 is photoresist), and when the mask opening K2 is formed, the first barrier layer 112 is completely consumed.

[0081] See next Figure 5 and Figure 6 Before forming the first barrier layer 112 having the first opening K3 on the planarization coating layer 108 , a protection layer 110 is formed on the planarization coating layer 108 .

[0082] The protection layer 110 is used to protect the planarization coating layer 108 to prevent the surface of the planarization coating layer 108 from being damaged due to the consumption of the first barrier layer 112 during the process of forming the mask opening K2 .

[0083] In this case, the first barrier layer 112 may be located above the protection layer 110 , and the first opening K3 exposes the protection layer 110 .

[0084] In this embodiment, a low temperature oxidation process may be used to form the protection layer 110 on the planarization coating layer 108 .

[0085] Accordingly, the material of the protective layer 110 may include silicon oxide. By selecting silicon oxide as the material of the protective layer 110, process compatibility can be improved and process risks can be reduced; moreover, compared with organic materials, silicon oxide materials have greater hardness and density, which is conducive to improving the protective effect of the protective layer 110 on the surface of the planarization coating 108.

[0086] In a specific embodiment, the material of the protective layer 110 may include silicon oxide. The silicon oxide material has good adhesion to the substrate 100, which is conducive to improving the stability of subsequent processes and process treatment effects; moreover, silicon oxide is a silicon oxide commonly used in semiconductor processes, which can reduce the difficulty and process cost of forming the protective layer 110 and improve process compatibility.

[0087] In the step of removing the planarization coating layer 108 exposed by the first opening K3 along the sidewall of the first barrier layer 112 , the protection layer 110 exposed by the first opening K3 is also removed.

[0088] That is, the protective layer 110 exposed by the first opening K3 is removed first, and then the planarization coating 108 under the protective layer 110 is removed. Accordingly, the sidewalls of the mask opening K2 may include the sidewalls of the protective layer 110 and the planarization coating 108 .

[0089] In this embodiment, a dry etching process is used to remove the protective layer 110 exposed by the first opening K3 and the planarization coating layer 108 under the protective layer 110 .

[0090] See also Figure 7 After a planarization coating 108 having a mask opening K2 is formed on the dielectric layer 102 , the planarization coating 108 is used as a mask and a directional etching process is adopted to remove the dielectric layer 102 exposed in the depth direction of the initial trench 106 to form a trench 114 .

[0091] In this embodiment, the directional etching process includes a gas etching process; in the process of removing the dielectric layer 102 exposed along the depth direction of the initial groove 106 by the gas etching process, a polymer will also be produced, and the polymer remaining on the side wall of the initial groove 106 can serve as an etching barrier layer to protect the side wall of the initial groove 106.

[0092] Specifically, in the process of removing the dielectric layer 102 exposed in the depth direction of the initial groove 106 by using the gas etching process, the sidewall of the initial groove 106 may also be etched. Since the polymer located in the initial groove 106 serves as a protective layer, and the present solution uses multiple etching processes to form the target groove, the thickness of the dielectric layer 102 removed in one gas etching process is small, the etching time is short, the damage to the sidewall of the dielectric layer 102 is small, and the sidewall of the dielectric layer 102 still has good smoothness.

[0093] In this embodiment, the etching gas of the gas etching process includes C4F8, CHF3, Ar and O2; the etching power is 2200 to 2600W; the etching time is 700s to 900s; and the pressure is 200mT to 250mT.

[0094] See next Figure 7 Any etching process further includes: after removing the dielectric layer 102 exposed along the depth direction of the initial trench 106 by using a directional etching process, removing the planarization coating 108 on the dielectric layer 102 .

[0095] In this embodiment, an ashing process is used to remove the planarization coating 108 on the dielectric layer 102. The ashing process can remove the planarization coating 108 in time, so that the organic material of the planarization coating 108 is not easy to contaminate the machine.

[0096] See also Figures 3 to 7 In this embodiment, the dielectric layer 102 exposed by the initial groove 106 is removed by the first etching process. The thickness of the removed dielectric layer 102 is small, and the depth of the formed groove 114 does not reach the set depth. Therefore, the first etching process can also be used. Figures 3 to 7 In the method step shown, the dielectric layer 102 is further removed.

[0097] For example, see Figure 8 , the dielectric layer 102 exposed by the trench 114 is continuously etched until a target trench 120 having a set depth is formed in the dielectric layer 102 .

[0098] It should be noted that as the depth of the groove gradually increases, the depth of the etching gradually decreases during the etching process, which is conducive to reducing the difficulty of operation and improving the smoothness of the sidewall. In this embodiment, the depth is set to be greater than 10 microns, that is, the above method can form a target groove 120 with a depth greater than 10 microns.

[0099] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, on which a dielectric layer is formed; forming an initial trench in the dielectric layer; Perform at least one etching process on the dielectric layer exposed by the initial groove until a target groove with a set depth is formed in the dielectric layer; wherein any etching process includes: forming a planarization coating with a mask opening on the dielectric layer, the mask opening exposing the initial groove; using the planarization coating as a mask, adopting a directional etching process to remove the dielectric layer exposed by the initial groove along the depth direction.

2. The method for forming a semiconductor structure according to claim 1, wherein: The directional etching process includes a gas etching process; In the process of removing the dielectric layer exposed in the initial trench along the depth direction by using the gas etching process, the polymer remaining on the sidewall of the initial trench serves as an etching stop layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The etching gas of the gas etching process includes C4F8, CHF3, Ar and O2; the etching power is 2200 to 2600W; the etching time is 700s to 900s; and the pressure is 200mT to 250mT.

4. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a planarization coating having a mask opening on the dielectric layer comprises: forming a planarization coating on the dielectric layer, wherein the planarization coating completely fills the initial groove; forming a first barrier layer having a first opening on the planarization coating layer, wherein the first opening exposes a top portion of the planarization coating layer, and a position of the first opening is opposite to a position of the initial groove; The planarization coating layer exposed by the first opening is removed along the sidewall of the first barrier layer, and the mask opening is formed in the planarization coating layer.

5. The method for forming a semiconductor structure according to claim 4, characterized in that: The material of the planarization coating includes at least one of SiON, Si3N4, SiC, SOC and TiO2; The material of the first barrier layer includes at least one of photoresist and titanium nitride.

6. The method for forming a semiconductor structure according to claim 4, characterized in that: Also includes: Before forming a first barrier layer having a first opening on the planarization coating layer, forming a protective layer on the planarization coating layer; wherein the first barrier layer is located above the protective layer, and the first opening exposes the top of the protective layer; In the step of removing the planarization coating layer exposed by the first opening along the sidewall of the first barrier layer, the protection layer exposed by the first opening is also removed.

7. The method for forming a semiconductor structure according to claim 6, wherein: The protection layer is formed on the planarization coating layer by a low temperature oxidation process.

8. The method for forming a semiconductor structure according to claim 6, wherein: The protective layer exposed by the first opening and the planarization coating layer under the protective layer are removed by a dry etching process.

9. The method for forming a semiconductor structure according to claim 6, wherein: The material of the protection layer includes silicon oxide.

10. The method for forming a semiconductor structure according to claim 1, wherein: Any etching process further comprises: After removing the dielectric layer exposed in the initial trench along the depth direction by adopting a directional etching process, the planarization coating on the dielectric layer is removed.

11. The method for forming a semiconductor structure according to claim 10, characterized in that: The planarization coating on the dielectric layer is removed by an ashing process.

12. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming an initial trench in the dielectric layer comprises: forming a second barrier layer having a second opening on the dielectric layer, wherein the second opening exposes a top of the dielectric layer; A portion of the dielectric layer exposed by the second opening is removed along the sidewall of the second barrier layer to form the initial trench in the dielectric layer.

13. The method for forming a semiconductor structure according to claim 1, wherein: The set depth is greater than 10 microns.

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