Fabrication method of package substrate

Abstract

A manufacturing method of a package substrate includes stacking a bonding layer and a release layer and bonding a first substrate body and a second substrate body to increase the overall thickness, thereby overcoming the limitation of general processing equipment on the thickness of the substrate.

Description

Technical Field

[0001] The invention relates to a semiconductor packaging process, and in particular to a method for manufacturing a packaging substrate that can meet thinning requirements. Background Art

[0002] With the vigorous development of the electronics industry, many high-end electronic products are gradually developing towards high integration such as light, thin, short and small. With the evolution of packaging technology, the packaging technology of semiconductor chips is becoming more and more diversified, and the size or volume of the packaging substrate is also continuously reduced, so that the semiconductor package can achieve the purpose of being light, thin and short.

[0003] Figure 1 FIG. 1 is a cross-sectional schematic diagram of an existing packaging substrate 1. Figure 1 As shown, the packaging substrate 1 includes a core layer 10, a circuit structure 11 arranged on both sides of the core layer 10, and a solder mask 12 arranged on the circuit structure 11, wherein the core layer 10 has a penetrating conductive column 100 to electrically connect the circuit layer 110 of the circuit structure 11, and the circuit structure 11 also includes at least one dielectric layer 111 covering multiple circuit layers 110, and the solder mask 12 exposes the outermost circuit layer 110 of the circuit structure 11 to serve as a contact (i.e., I / O) 112 for connecting a semiconductor chip.

[0004] In the production of the existing packaging substrate 1, for the package-on-package (POP) structure, a thinner packaging substrate is required as an intermediate layer, and coupled with the substrate through solder balls, thereby achieving thinner (<100μm), low warpage (<0.1mm), high-density pattern (L / S=15 / 15μm) and laser through-hole (≤50μm).

[0005] However, since the thin packaging substrate manufactured by general processing equipment (limited to board thickness ≥ 0.1mm) will have a risk of damage, its machinability will be limited, resulting in the need to use unique and expensive processing equipment in the entire processing process to manufacture the thin packaging substrate, which greatly increases the manufacturing cost.

[0006] Therefore, how to overcome the above-mentioned problems of the prior art has become a topic that needs to be solved urgently. Summary of the invention

[0007] In view of the various defects of the above-mentioned prior art, the present invention provides a method for preparing a packaging substrate, including: providing a bonding layer and a first substrate body and a second substrate body each having a first surface and a second surface opposite to each other; allowing the first substrate body and the second substrate body to be respectively disposed on both sides of the bonding layer by their second surfaces; forming a plurality of conductors in the first substrate body and the second substrate body; forming a first patterned circuit layer on the first surfaces of the first substrate body and the second substrate body respectively to electrically connect the plurality of conductors; separating the first substrate body, the second substrate body and the bonding layer; providing a release layer, and allowing the separated first substrate body and the second substrate body to be respectively bonded to both sides of the release layer by their first surfaces; forming a second patterned circuit layer on the second surfaces of the first substrate body and the second substrate body respectively to electrically connect the plurality of conductors; and separating the first substrate body, the second substrate body and the release layer to obtain two packaging substrates.

[0008] In a specific embodiment of the present invention, the first substrate body and the second substrate body each include a core layer, a first metal layer formed on both sides of the core layer, and a second metal layer formed on the first metal layer.

[0009] In a specific embodiment of the present invention, the first metal layer, the second metal layer and a portion of the core layer are burned around the second surfaces of the first substrate body and the second substrate body to form a sealed channel.

[0010] In a specific embodiment of the present invention, the method for manufacturing the packaging substrate also includes forming a plurality of first through holes around the first substrate body and the second substrate body, and forming a plurality of second through holes around the bonding layer corresponding to the positions of the first through holes, so that a pin of a pin fixture can penetrate the plurality of first through holes and the second through holes, so that the first substrate body and the second substrate body are respectively arranged on both sides of the bonding layer from their second surfaces.

[0011] In a specific embodiment of the present invention, when a sealing channel is formed around the second surfaces of the first substrate body and the second substrate body, the method for manufacturing the packaging substrate also includes forming a plurality of first through holes around the first substrate body and the second substrate body outside the sealing channel, and forming a plurality of second through holes around the bonding layer corresponding to the positions of the first through holes, so that a pin of a pin clamp can penetrate the plurality of first through holes and the second through holes, so that the first substrate body and the second substrate body are respectively arranged on both sides of the bonding layer from their second surfaces.

[0012] In a specific embodiment of the present invention, the step of making the separated first substrate body and the second substrate body respectively bonded to the two sides of the release layer by their first surfaces includes forming a plurality of third through holes around the first substrate body and the second substrate body, and forming a plurality of fourth through holes around the release layer corresponding to the positions of the third through holes, so that a pin of a pin clamp can pass through the plurality of third through holes and the fourth through holes to bond the separated first substrate body, the second substrate body and the release layer.

[0013] In a specific embodiment of the present invention, the method further includes laminating the separated first substrate body, the second substrate body and the release layer. In a specific embodiment of the present invention, the laminating method includes laminating the separated first substrate body, the second substrate body and the release layer with a roller.

[0014] In a specific embodiment of the present invention, a plurality of first alignment marks are formed around the second surfaces of the first substrate body and the second substrate body, so that the first substrate body and the second substrate body are respectively disposed on both sides of the bonding layer from their second surfaces.

[0015] In a specific embodiment of the present invention, when a sealing channel is formed around the second surfaces of the first substrate body and the second substrate body, the method for manufacturing the packaging substrate also includes forming a plurality of first alignment marks around the second surfaces of the first substrate body and the second substrate body outside the sealing channel, so that the first substrate body and the second substrate body are respectively arranged on both sides of the bonding layer by their second surfaces.

[0016] In a specific embodiment of the present invention, the plurality of first alignment marks are used as alignment references for combining the first substrate body and the second substrate body.

[0017] In a specific embodiment of the present invention, after forming a first patterned circuit layer on the first surfaces of the first substrate body and the second substrate body respectively, a plurality of second alignment marks are formed around the first surfaces of the first substrate body and the second substrate body, so that the separated first substrate body and the second substrate body can be respectively combined with the two sides of the release layer from their first surfaces.

[0018] In a specific embodiment of the present invention, the plurality of second alignment marks are used as alignment references for combining the first substrate body and the second substrate body, so as to overlap the first surface on both sides of the release layer respectively, and then press the separated first substrate body, the second substrate body and the release layer together.

[0019] In a specific embodiment of the present invention, the method further includes forming a first insulating layer having a plurality of openings on the first patterned circuit layer, and exposing a portion of the first patterned circuit layer.

[0020] In a specific embodiment of the present invention, the method further includes forming a surface treatment layer on the first patterned circuit layer having a plurality of openings in the first insulating layer.

[0021] The aforementioned method for manufacturing the package substrate further includes forming a second insulating layer having a plurality of openings on the second patterned circuit layer, and exposing a portion of the second patterned circuit layer.

[0022] As can be seen from the above, the method for manufacturing the packaging substrate of the present invention increases the overall thickness by stacking the bonding layer and the release layer and combining two thin first substrate bodies and the second substrate body, thereby overcoming the processing limitations of general processing equipment and providing general processing equipment for processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a cross-sectional schematic diagram of a conventional semiconductor package.

[0024] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H , Fig.2I and Figure 2J It is a cross-sectional schematic diagram of a method for manufacturing a packaging substrate according to a first embodiment of the present invention.

[0025] Figure 2H-1 It is a cross-sectional schematic diagram of the roller lamination method of the present invention.

[0026] FIG. 3A to FIG. 3K It is a cross-sectional schematic diagram of a manufacturing method of a second embodiment of a packaging substrate of the present invention.

[0027] Main component symbols

[0028] 1 Package substrate

[0029] 10 Core Layer

[0030] 100 Conductive Column

[0031] 11 Line structure

[0032] 110 Circuit layer

[0033] 111 Dielectric layer

[0034] 112 contacts

[0035] 12 Solder mask

[0036] 20,30The first substrate body

[0037] 20',30' packaging substrate

[0038] 21,31 Second substrate body

[0039] 20a, 30a first surface

[0040] 20b, 30b second surface

[0041] 200,300 core layer

[0042] 200a, 300a first side

[0043] 200b,300b Second side

[0044] 201,301 first metal layer

[0045] 201a, 301a first patterned circuit layer

[0046] 201b, 301b second patterned circuit layer

[0047] 202,302 Second metal layer

[0048] 203 first through hole

[0049] 204,304 sealed channel

[0050] 205,305 blind holes

[0051] 206,306 Conductors

[0052] 207,307 first insulation layer

[0053] 207a, 307a first opening

[0054] 208,308 surface treatment layer

[0055] 209 third through hole

[0056] 2010,3010 Second insulation layer

[0057] 2010a,3010a second opening

[0058] 303 First alignment mark

[0059] 309 Second alignment mark

[0060] 70 Roller

[0061] 80 First Pin Clamp

[0062] 81 Second pin fixture

[0063] 80a,81a pin

[0064] 90 Bonding layer

[0065] 91 Release layer

[0066] 90a, 91a first side

[0067] 90b, 91b Second side

[0068] 900 Second through hole

[0069] 910 Fourth through hole

[0070] D1,D2 width

[0071] T1, T2, T3, T4 thickness DETAILED DESCRIPTION

[0072] The following describes the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0073] It should be noted that the structures, proportions, sizes, etc. shown in the attached drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects and purposes that can be produced by the present invention, should still fall within the scope of the technical contents disclosed in the present invention. At the same time, the terms such as "on", "first", "second", "one", etc. quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0074] FIG. 2A to FIG. 2J It is a cross-sectional schematic diagram of a method for manufacturing a packaging substrate according to a first embodiment of the present invention.

[0075] like Figure 2A As shown, a first substrate body 20 and a second substrate body 21 having a plurality of first through holes 203 and a sealing channel 204 are provided.

[0076] In this specific embodiment, the first substrate body 20 and the second substrate body 21 have a first surface 20a and a second surface 20b opposite to each other, and include a core layer 200 having a first side surface 200a and a second side surface 200b opposite to each other, a first metal layer 201 formed on the first side surface 200a and the second side surface 200b, and a second metal layer 202 formed on the first metal layer 201, wherein the core layer 200 is a substrate composed of, for example, glass fiber and epoxy resin, such as dielectric materials such as BT (Bismaleimide Triazine) or FR5, and the material of the first metal layer 201 and the second metal layer 202 is, for example, copper (Cu).

[0077] In a specific embodiment, the first surface 20a and the second surface 20b of the first substrate body 20 and the second substrate body 21 are penetrated by a technique such as laser or mechanical drilling to form the plurality of first through holes 203 around the first substrate body 20 and the second substrate body 21. Specifically, the plurality of first through holes 203 penetrate the core layer 200, the first metal layer 201 and the second metal layer 202.

[0078] In one embodiment, an annular sealing channel 204 is formed around the second surface 20b of the first substrate body 20 and the second substrate body 21, and the sealing channel 204 is located inside the plurality of first through holes 203. For example, the first metal layer 201, the second metal layer 202 and a portion of the core layer 200 (i.e., a portion of the core layer 200 contacting the first metal layer 201) are sealed on the second surface 20b by laser burning to form the sealing channel 204, so that the sealing properties of the first metal layer 201, the second metal layer 202 and the core layer 200 are enhanced through the sealing channel 204 to prevent liquid from penetrating and causing a short circuit in subsequent processes.

[0079] In a specific embodiment, the thickness T1 of the first metal layer 20 is smaller than the thickness T2 of the second metal layer 202 . For example, the thickness T1 of the first metal layer 20 is about 3 μm; and the thickness T2 of the second metal layer 202 is about 18 μm.

[0080] like Figure 2B As shown, a bonding layer 90 having a first side 90 a and a second side 90 b opposite to each other is provided, and the first substrate body 20 and the second substrate body 21 are respectively disposed on the first side 90 a and the second side 90 b of the bonding layer 90 by a first pin fixture 80 .

[0081] Specifically, the bonding layer 90 has a plurality of second through holes 900 formed at positions corresponding to the first through holes 203, and the first substrate body 20 is disposed on the first side 90a of the bonding layer 90 through its second surface 20b, and the second substrate body 21 is disposed on the second side 90b of the bonding layer 90 through its second surface 20b, wherein the plurality of first through holes 203 of the first substrate body 20 and the second substrate body 21 correspond to the plurality of second through holes 900 of the bonding layer 90, so that the pin 80a of the first pin clamp 80 penetrates the plurality of first through holes 203 of the first substrate body 20 and the second substrate body 21, and the plurality of second through holes 900 of the bonding layer 90, so as to stack the first substrate body 20, the second substrate body 21 and the bonding layer 90.

[0082] In a specific embodiment, the width D1 of the first through holes 203 of the first substrate body 20 and the second substrate body 21 and the second through holes 900 of the bonding layer 90 is slightly larger than the width D2 of the pin 80 a of the first pin fixture 80 .

[0083] In a specific embodiment, the material of the bonding layer 90 can be selected from dielectric materials such as prepreg (PP), ABF film (Ajinomoto Build-up Film), photoimageable dielectric (PID) or polyimide (PI), but is not limited to the above-mentioned material types.

[0084] like Figure 2C As shown, after the pin 80a of the first pin fixture 80 is withdrawn, the first substrate body 20, the second substrate body 21 and the bonding layer 90 are pressed together so that the first substrate body 20 and the second substrate body 21 are respectively arranged on both sides of the bonding layer 90 by their second surfaces 20b, and then the second metal layer 202 on the first surfaces 20a of the first substrate body 20 and the second substrate body 21 are removed.

[0085] In this embodiment, a lamination method is used to make the material of the bonding layer 90 fill the first through holes 203 of the first substrate body 20 and the second substrate body 21 , and even fill the sealing channel 204 .

[0086] like Figure 2D As shown, a plurality of blind holes 205 are formed in the first substrate body 20 and the second substrate body 21 .

[0087] In this embodiment, on the first surfaces 20 a of the first substrate body 20 and the second substrate body 21 , portions of the first metal layer 201 and the core layer 200 are removed by mechanical, laser, etching or other appropriate methods to form the plurality of blind holes 205 .

[0088] like Figure 2E As shown, a plurality of conductors 206 are formed in the plurality of blind holes 205 , and a first patterned circuit layer 201 a is formed on the first side surface 200 a of the core layer 200 of the first substrate body 20 and the second substrate body 21 , and the first patterned circuit layer 201 a is electrically connected to the plurality of conductors 206 .

[0089] In this embodiment, the multiple conductors 206 are formed in the multiple blind holes 205 by electroplating until they are flush with the second metal layer 201, and then the first metal layer 201 is etched by a patterning process, thereby forming the first patterned circuit layer 201a on the first side 200a of the core layer 200 of the first substrate body 20 and the second substrate body 21.

[0090] like Figure 2F As shown, a first insulating layer 207 having a plurality of first openings 207a is formed on the first patterned circuit layer 201a, and a portion of the first patterned circuit layer 201a is exposed through the plurality of first openings 207a, and then a surface treatment layer 208 is formed in the plurality of first openings 207a and electrically connected to the first patterned circuit layer 201a.

[0091] In this embodiment, the surface treatment layer 208 is plated in the multiple first openings 207a of the first insulating layer 207 by electroless nickel immersion gold (ENIG), wherein the material forming the surface treatment layer 208 is such as nickel-phosphorus alloy (Ni / Au), and the material forming the first insulating layer 207 is such as green paint epoxy resin.

[0092] In one embodiment, the first substrate body 20 , the second substrate body 21 , and the periphery of the bonding layer 90 are cut by cutting, thereby removing the first through holes 203 and the second through holes 900 .

[0093] like Figure 2G As shown, the first substrate body 20, the second substrate body 21 and the bonding layer 90 are separated. Specifically, the second metal layer 202 on the bonding layer 90, the first substrate body 20 and the second surface 20b of the second substrate body 21 is removed, and a thermal released film (TRF) 91 is disposed on the first surface 20a of the first substrate body 20.

[0094] In this embodiment, the first surface 20a and the second surface 20b of the first substrate body 20 and the second substrate body 21 are penetrated to form the plurality of third through holes 209 around the first substrate body 20 and the second substrate body 21. For example, the core layer 200, the first metal layer 201, the first patterned circuit layer 201a and the first insulating layer 207 are penetrated by laser or mechanical drilling techniques to form the plurality of third through holes 209.

[0095] In one embodiment, the release layer 91 has a first side 91a and a second side 91b opposite to each other, and penetrates the first side 91a and the second side 91b of the release layer 91 to form the plurality of fourth through holes 910 at positions corresponding to the third through holes 209. Furthermore, the release layer 91 is disposed on the first surface 20a of the first substrate body 20 through the second side 91b thereof.

[0096] like Figure 2H As shown, the second substrate body 21 is disposed on the release layer 91 , and the separated first substrate body 20 and the second substrate body 21 are disposed on the first side 91 a and the second side 91 b of the release layer 91 respectively through a second pin fixture 81 .

[0097] In this embodiment, the second substrate body 21 is disposed on the first side 91a of the release layer 91 through its first surface 20a, wherein the multiple third through holes 209 of the first substrate body 20 and the second substrate body 21 correspond to the multiple fourth through holes 910 of the release layer 91, so that the pin 81a of the second pin clamp 81 can pass through the multiple third through holes 209 of the separated first substrate body 20 and the second substrate body 21, and the multiple fourth through holes 910 of the release layer 91, thereby aligning and stacking the first substrate body 20, the second substrate body 21 and the release layer 91 through the second pin clamp 81.

[0098] Furthermore, after removing the second pin fixture 81 , the first substrate body 20 , the second substrate body 21 and the release layer 91 are combined by lamination.

[0099] In another embodiment, if Figure 2H-1 As shown, after removing the second pin fixture 81, the first substrate body 20, the second substrate body 21 and the release layer 91 can be pressed together by rolling the roller 70 through roller lamination. Therefore, by pressing the first substrate body 20 and the second substrate body 21 through rolling lamination, more manufacturing cycle time can be saved.

[0100] like Fig.2IAs shown, a second patterned circuit layer 201b is formed on the second side surface 200b of the core layer 200 of the first substrate body 20 and the second substrate body 21, and the second patterned circuit layer 201b is electrically connected to the multiple conductors 206, and then a second insulating layer 2010 having a plurality of second openings 2010a is formed on the second patterned circuit layer 201b, and a portion of the second patterned circuit layer 201b is exposed through the multiple second openings 2010a.

[0101] In this embodiment, the first metal layer 201 is etched by a patterning process, thereby forming the second patterned circuit layer 201 b on the second side surface 200 b of the core layer 200 of the first substrate body 20 and the second substrate body 21 .

[0102] In a specific embodiment, the material forming the second insulating layer 2010 is an epoxy resin such as green paint.

[0103] like Figure 2J As shown, the first substrate body 20, the second substrate body 21 and the periphery of the release layer 91 are cut to remove the third through holes 209 and the fourth through holes 910, and then the first substrate body 20, the second substrate body 21 and the release layer 91 are separated to obtain two packaging substrates 20'.

[0104] FIG. 3A to FIG. 3K FIG. 1 is a cross-sectional view of a manufacturing method of a second embodiment of a packaging substrate 30 ′ of the present invention.

[0105] like Figure 3A As shown, a first substrate body 30 and a second substrate body 31 having a first alignment mark 303 and a sealing channel 304 are provided.

[0106] In this embodiment, the first substrate body 30 and the second substrate body 31 have a first surface 30a and a second surface 30b opposite to each other, and include a core layer 300 having a first side surface 300a and a second side surface 300b opposite to each other, a first metal layer 301 formed on the first side surface 300a and the second side surface 300b, and a second metal layer 302 formed on the first metal layer 301, wherein the core layer 300 is a substrate composed of glass fiber and epoxy resin, such as dielectric materials such as BT (Bismaleimide Triazine) or FR5, and the material of the first metal layer 301 and the second metal layer 302 is copper (Cu).

[0107] In one embodiment, the second metal layer 302 of the second surface 30b is etched around the first substrate body 30 and the second substrate body 31 by etching to form the first alignment mark 303. The structure of the first alignment mark 303 may be, for example, a concave portion or a groove, and may form a plurality of alignment structures or an annular groove, but is not limited thereto.

[0108] Furthermore, the annular sealing channel 304 is formed around the second surface 30b of the first substrate body 30 and the second substrate body 31, and the sealing channel 304 is located inside the first alignment mark 303. For example, the first metal layer 301, the second metal layer 302 and a part of the core layer 300 are penetrated on the second surface 30b by laser technology to burn and form the sealing channel 304, so as to strengthen the sealing of the first metal layer 301, the second metal layer 302 and the core layer 300 through the sealing channel 304.

[0109] In one embodiment, the thickness T3 of the first metal layer 301 is smaller than the thickness T4 of the second metal layer 302 . For example, the thickness T3 of the first metal layer 301 is approximately 3 μm; and the thickness T4 of the second metal layer 302 is approximately 18 μm.

[0110] like Figure 3B As shown, a bonding layer 90 having a first side 90 a and a second side 90 b opposite to each other is provided, so that the first substrate body 30 and the second substrate body 31 are disposed on the first side 90 a and the second side 90 b of the bonding layer 90 , respectively.

[0111] In this embodiment, the first substrate body 30 is disposed on the first side 90a of the bonding layer 90 through its second surface 30b, and the second substrate body 31 is disposed on the second side 90b of the bonding layer 90 through its second surface 30b, and the plurality of first alignment marks 303 are used as alignment references or reference marks (Fiducial marks) for the combination of the first substrate body 30 and the second substrate body 31, wherein the material of the bonding layer 90 can be selected from dielectric materials such as prepreg (Prepreg, abbreviated as PP), ABF film (Ajinomoto Build-up Film), photoimageable dielectric material (photoimageable dielectric, abbreviated as PID) or polyimide (polyimide, abbreviated as PI), and is not limited to the above-mentioned material types.

[0112] like Figure 3C As shown, the first substrate body 30 , the second substrate body 31 and the bonding layer 90 are combined, and the second metal layer 302 on the first surfaces 30 a of the first substrate body 30 and the second substrate body 31 are removed.

[0113] In this embodiment, a lamination method is used to combine the first substrate body 30 , the second substrate body 31 and the bonding layer 90 . In addition, the bonding layer 90 fills the sealing channels 304 of the first substrate body 30 and the second substrate body 31 .

[0114] like Figure 3D As shown, a plurality of blind holes 305 are formed on the first surface 30 a of the first substrate body 30 and the second substrate body 31 .

[0115] In this embodiment, on the first surfaces 30 a of the first substrate body 30 and the second substrate body 31 , a portion of the first metal layer 301 and the core layer 300 are removed by mechanical, laser, etching or other appropriate methods to form the plurality of blind holes 305 .

[0116] like Figure 3E As shown, a plurality of conductors 306 are formed in the plurality of blind holes 305 , and a first patterned circuit layer 301 a is formed on the first side surface 300 a of the core layer 300 of the first substrate body 30 and the second substrate body 31 , and the first patterned circuit layer 301 a is electrically connected to the plurality of conductors 306 .

[0117] In this embodiment, the multiple conductors 306 are formed in the multiple blind holes 305 by electroplating until they are flush with the first metal layer 301, and then the first metal layer 301 is etched by a patterning process, thereby forming the first patterned circuit layer 301a on the first side surface 300a of the core layer 300 of the first substrate body 30 and the second substrate body 31.

[0118] In one embodiment, the first metal layer 301 around the first side surface 300 a of the core layer 300 of the first substrate body 30 and the second substrate body 31 is etched to form a second alignment mark 309 such as a ring-shaped metal protrusion.

[0119] like Figure 3F As shown, a first insulating layer 307 having a plurality of first openings 307a is formed on the first patterned circuit layer 301a, and a portion of the first patterned circuit layer 301a is exposed through the plurality of first openings 307a, and then a surface treatment layer 308 is formed in the plurality of first openings 307a and electrically connected to the first patterned circuit layer 301a.

[0120] In this embodiment, the surface treatment layer 308 is plated in the multiple first openings 307a of the first insulating layer 307 by electroless nickel immersion gold (ENIG), wherein the material forming the surface treatment layer 308 is such as nickel-phosphorus alloy (Ni / Au), and the material forming the first insulating layer 307 is such as green paint epoxy resin.

[0121] In one embodiment, the first substrate body 20 , the second substrate body 21 , and the periphery of the bonding layer 90 are cut by a cutting method, and the second alignment mark 309 is retained.

[0122] like Figure 3G As shown, the second metal layer 302 on the second surface 30 b of the first substrate body 30 and the second substrate body 31 is removed, and a thermal released film (TRF) 91 is disposed on the second surface 30 a of the first substrate body 30 .

[0123] like Figure 3H As shown, the second substrate body 31 is disposed on the release layer 91 , thereby the first substrate body 30 and the second substrate body 31 are respectively disposed on the second side 91 b and the first side 91 a of the release layer 91 .

[0124] In this embodiment, the second substrate body 31 is disposed on the first side 91 a of the release layer 91 through the first surface 30 a thereof, so that the first substrate body 30 , the second substrate body 31 and the release layer 91 are stacked through the second alignment mark 309 .

[0125] like Fig. 3I As shown, the first substrate body 30, the second substrate body 31 and the release layer 91 are combined. In this embodiment, after the first substrate body 30, the second substrate body 31 and the release layer 91 are combined by lamination, the periphery of the first substrate body 30 and the second substrate body 31 are cut by cutting to remove the second alignment mark 309.

[0126] like Figure 3J As shown, a second patterned circuit layer 301b is formed on the second side surface 300b of the core layer 300 of the first substrate body 30 and the second substrate body 31, and the second patterned circuit layer 301b is electrically connected to the multiple conductors 306, and then a second insulating layer 3010 having a plurality of second openings 3010a is formed on the second patterned circuit layer 301b, and a portion of the second patterned circuit layer 301b is exposed through the multiple second openings 3010a.

[0127] In this embodiment, the first metal layer 301 is etched by a patterning process, thereby forming the second patterned circuit layer 301 b on the second side surface 300 b of the core layer 300 of the first substrate body 30 and the second substrate body 31 .

[0128] In one embodiment, the material forming the second insulating layer 3010 is an epoxy resin such as green paint.

[0129] like Figure 3K As shown, the first substrate body 30 , the second substrate body 31 and the release layer 91 are separated to obtain two package substrates 30 ′.

[0130] Therefore, in this embodiment, by providing the alignment marks 303 , 309 , there is no need to configure the through holes 203 , 209 , 900 , 910 .

[0131] In summary, the method for manufacturing the package substrate of the present invention mainly increases the overall thickness by stacking the bonding layer and the release layer and combining two thin first substrate bodies and the second substrate body, thereby overcoming the processing limitations of general processing equipment and providing general processing equipment for processing. Furthermore, by laser-forming the first metal layer and the second metal layer to form a sealed channel, the sealing of the board edge can prevent the substrate from being penetrated by chemicals in subsequent processes, thereby preventing short circuits and substrate reliability risks.

[0132] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Those skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. A method for manufacturing a packaging substrate, comprising: Providing a bonding layer and a first substrate body and a second substrate body each having a first surface and a second surface opposite to each other; The first substrate body and the second substrate body are respectively disposed on two sides of the bonding layer through the second surfaces thereof; forming a plurality of conductors in the first substrate body and the second substrate body; Forming a first patterned circuit layer on the first surface of the first substrate body and the first surface of the second substrate body respectively to electrically connect the plurality of conductors; Separating the first substrate body, the second substrate body and the bonding layer; Providing a release layer, and bonding the separated first substrate body and the second substrate body to two sides of the release layer through their first surfaces respectively; Forming a second patterned circuit layer on the second surface of the first substrate body and the second substrate body respectively to electrically connect the plurality of conductors; as well as The first substrate body, the second substrate body and the release layer are separated to obtain two packaging substrates.

2. The method for manufacturing a packaging substrate according to claim 1, wherein: The first substrate body and the second substrate body each include a core layer, a first metal layer formed on both sides of the core layer, and a second metal layer formed on the first metal layer.

3. The method for manufacturing a packaging substrate according to claim 2, wherein: The manufacturing method further comprises burning the first metal layer, the second metal layer and a part of the core layer around the second surfaces of the first substrate body and the second substrate body to form a sealed channel.

4. The method for manufacturing a packaging substrate according to claim 1, wherein: The manufacturing method also includes forming a plurality of first through holes around the first substrate body and the second substrate body, and forming a plurality of second through holes around the bonding layer corresponding to the positions of the first through holes, so that a pin of a pin fixture penetrates the plurality of first through holes and second through holes, so that the first substrate body and the second substrate body are respectively arranged on both sides of the bonding layer from their second surfaces.

5. The method for manufacturing a packaging substrate according to claim 3, wherein: The manufacturing method also includes forming a plurality of first through holes around the first substrate body and the second substrate body outside the sealing channel, and forming a plurality of second through holes around the bonding layer corresponding to the positions of the first through holes, so that a pin of a pin clamp penetrates the plurality of first through holes and second through holes, so that the first substrate body and the second substrate body are respectively arranged on both sides of the bonding layer from their second surfaces.

6. The method for manufacturing a packaging substrate according to claim 1, wherein: The step of making the separated first substrate body and the second substrate body respectively bonded to the two sides of the release layer by their first surfaces includes forming a plurality of third through holes around the first substrate body and the second substrate body, and forming a plurality of fourth through holes around the release layer corresponding to the positions of the third through holes, so that a pin of a pin clamp can pass through the plurality of third through holes and the fourth through holes to bond the separated first substrate body, the second substrate body and the release layer.

7. The method for manufacturing a packaging substrate according to claim 6, wherein: The manufacturing method further comprises pressing the separated first substrate body, the second substrate body and the release layer.

8. The method for manufacturing a packaging substrate according to claim 7, wherein: The pressing is performed by laminating the separated first substrate body, the second substrate body and the release layer with a roller.

9. The method for manufacturing a packaging substrate according to claim 1, wherein: The manufacturing method further comprises forming a plurality of first alignment marks around the second surfaces of the first substrate body and the second substrate body, so that the first substrate body and the second substrate body are respectively arranged on both sides of the bonding layer from their second surfaces.

10. The method for manufacturing a packaging substrate according to claim 3, wherein: The manufacturing method also includes forming a plurality of first alignment marks around the second surfaces of the first substrate body and the second substrate body outside the sealing channel, so that the first substrate body and the second substrate body are respectively arranged on both sides of the bonding layer from their second surfaces.

11. The method for manufacturing a packaging substrate according to claim 9 or 10, wherein: The plurality of first alignment marks are used as alignment references for combining the first substrate body and the second substrate body.

12. The method for manufacturing a packaging substrate according to claim 1, wherein: The manufacturing method also includes forming a plurality of second alignment marks around the first surfaces of the first substrate body and the second substrate body after forming a first patterned circuit layer on the first surfaces of the first substrate body and the second substrate body, so that the separated first substrate body and the second substrate body can be respectively bonded to the two sides of the release layer from their first surfaces.

13. The method for manufacturing a packaging substrate according to claim 12, wherein: The plurality of second alignment marks are used as alignment references for combining the first substrate body and the second substrate body, so as to overlap the first surface on both sides of the release layer respectively, and then press the separated first substrate body, the second substrate body and the release layer.

14. The method for manufacturing a packaging substrate according to claim 1, wherein: The manufacturing method also includes forming a first insulating layer with a plurality of openings on the first patterned circuit layer, and exposing a portion of the first patterned circuit layer.

15. The method for manufacturing a packaging substrate according to claim 14, wherein: The manufacturing method further comprises forming a surface treatment layer on the first patterned circuit layer of the plurality of openings of the first insulating layer.

16. The method for manufacturing a packaging substrate according to claim 1, wherein: The manufacturing method also includes forming a second insulating layer with a plurality of openings on the second patterned circuit layer, and exposing a portion of the second patterned circuit layer.

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