Package substrate and manufacturing method thereof

Abstract

The invention provides a package substrate and a manufacturing method thereof. The packaging substrate comprises a dielectric layer, an insulating layer, a first circuit layer, a second circuit layer and a plurality of conductive columns. The dielectric layer is provided with a first surface and a second surface which are opposite; the insulating layer is formed on the first surface of the dielectric layer and is provided with a plurality of grooves; the first circuit layer is formed in the plurality of grooves and is flush with the insulating layer; the second circuit layer is formed on the second surface of the dielectric layer; a plurality of conductive pillars are formed in the dielectric layer and electrically connected with the first circuit layer and the second circuit layer.

Description

Technical Field

[0001] The invention relates to a packaging substrate and a manufacturing method thereof, and in particular to a packaging substrate and a manufacturing method thereof which can avoid inconsistent side erosion and concave depth. Background Art

[0002] With the rapid development of the electronics industry, electronic products tend to be thinner, lighter, shorter and smaller in shape, and their functions are developing in the direction of high performance, high functionality and high speed. Therefore, in order to meet the needs of high integration and miniaturization of semiconductor devices, packaging substrates with high-density and fine-pitch circuits are often used in the packaging process.

[0003] Figures 1A to 1F It is a cross-sectional schematic diagram of a conventional method for manufacturing a packaging substrate 1 .

[0004] like Figure 1A As shown, a carrier 9 is provided, and a release layer 91 is provided on the surface of the plate 90, and a metal layer 92 is formed on the release layer 91. Next, a resist layer 10 having an opening area 100 is symmetrically formed on opposite sides of the carrier 9, so that a portion of the surface of the carrier 9 is exposed in the opening area 100.

[0005] like Figure 1B As shown, a first circuit layer 11 is formed on the metal layer 92 in the opening area 100. Next, the resist layer 10 is removed.

[0006] like Figure 1C As shown, a dielectric layer 12 is formed on the metal layer 92 of the carrier 9 , and a plurality of blind holes 120 are formed on the dielectric layer 12 .

[0007] like Figure 1D As shown, copper is electroplated on the dielectric layer 12 and in the blind hole 120 to form a second circuit layer 13 on the dielectric layer 12, and a plurality of conductive pillars 14 electrically connecting the first circuit layer 11 and the second circuit layer 13 are formed in the blind hole 120 to form a coreless circuit structure 1a.

[0008] like Figure 1E As shown, the plate body 90 of the carrier 9 and the circuit structure 1 a are separated by the release layer 91 to retain the metal layer 92 on the dielectric layer 12 and the first circuit layer 11 .

[0009] like Figure 1F As shown, the metal layer 92 is removed by etching, and part of the material of the first circuit layer 11 is removed by microetching at the same time, so as to form a plurality of grooves 15 on the dielectric layer 12 .

[0010] However, in the existing packaging substrate 1, when etching and removing the metal layer 92, the first circuit layer 11, 11a will be micro-etched at the same time, resulting in inconsistent depths D1, D2, D3, D4, D5, and D6 of the multiple grooves 15. It is difficult to effectively combine solder balls in the grooves 15 in subsequent processes, so the reliability of the packaging substrate 1 is poor.

[0011] Furthermore, since the first circuit layers 11, 11a are also microetched when the metal layer 92 is removed by etching, part of the first circuit layer 11a will be undercut, causing the first circuit layer 11a to be damaged or even disconnected, thereby causing poor signal transmission between the first circuit layer 11a and the solder ball.

[0012] In addition, since the first circuit layer 11a has the problem of being damaged by side corrosion, when the line width / line spacing (L / S) of the first circuit layer 11a is designed towards miniaturization, the first circuit layer 11a is more likely to be disconnected, resulting in the interruption of signal transmission between the first circuit layer 11a and the solder ball, and thus it is impossible to mass-produce the packaging substrate 1 that requires the miniaturized first circuit layer 11, 11a.

[0013] Therefore, how to overcome the various problems of the above-mentioned prior art has become a topic that needs to be solved urgently. Summary of the invention

[0014] An object of the present invention is to provide a packaging substrate and a manufacturing method thereof to solve at least one of the above problems.

[0015] In view of the various defects of the above-mentioned prior art, the present invention provides a packaging substrate, including: a dielectric layer, having a first surface and a second surface opposite to each other; an insulating layer, formed on the first surface of the dielectric layer and having a plurality of grooves; a first circuit layer, formed in the plurality of grooves and flush with the insulating layer; a second circuit layer, formed on the second surface of the dielectric layer; and a plurality of conductive pillars, formed in the dielectric layer and electrically connecting the first circuit layer and the second circuit layer.

[0016] As in the aforementioned packaging substrate, the insulating layer is photosensitive polyimide.

[0017] As in the aforementioned packaging substrate, the first circuit layer fills up the plurality of grooves.

[0018] As in the aforementioned packaging substrate, the first circuit layer partially fills the plurality of grooves, so that the dielectric layer partially fills the plurality of grooves.

[0019] The present invention also provides a method for manufacturing a packaging substrate, comprising: providing a carrier having a metal layer, and forming an insulating layer having a plurality of grooves on the metal layer, wherein the plurality of grooves expose the metal layer, and the metal layer has a plurality of recessed holes corresponding to the plurality of grooves; forming a barrier layer in the plurality of recessed holes; forming a first circuit layer on the barrier layer and in the plurality of recessed holes; forming a dielectric layer on the insulating layer and the first circuit layer, wherein the dielectric layer has a first surface and a second surface relative to each other so that the first surface of the dielectric layer is bonded to the insulating layer; forming a second circuit layer on the second surface of the dielectric layer, and forming a plurality of conductive pillars in the dielectric layer that electrically connect the first circuit layer and the second circuit layer; and removing the carrier, the metal layer and the barrier layer to expose the first circuit layer and make the first circuit layer flush with the insulating layer.

[0020] As in the aforementioned method for manufacturing a package substrate, after forming the insulating layer, a portion of the metal layer in the plurality of grooves is etched away to form the plurality of concave holes.

[0021] As in the aforementioned method for manufacturing a packaging substrate, the barrier layer fills up the plurality of recessed holes and is flush with the metal layer.

[0022] As in the aforementioned method for manufacturing the packaging substrate, the barrier layer is a photosensitive material, and the insulating layer is a photosensitive polyimide.

[0023] As in the aforementioned method for manufacturing the packaging substrate, the first circuit layer fills up the plurality of grooves.

[0024] As in the aforementioned method for manufacturing the package substrate, the first circuit layer partially fills the plurality of grooves, so that the dielectric layer partially fills the plurality of grooves.

[0025] In summary, the packaging substrate and the manufacturing method thereof of the present invention mainly form an insulating layer with a plurality of grooves on a metal layer, form a plurality of concave holes corresponding to the plurality of grooves in the metal layer, form a barrier layer in the plurality of concave holes, and form a first circuit layer on the barrier layer, so that when the metal layer is removed, the first circuit layer will not be micro-etched due to the protection of the barrier layer, and the lateral etching of the first circuit layer will be effectively prevented, thereby avoiding the problem of damage (such as disconnection) of the first circuit layer.

[0026] Furthermore, by making the barrier layer flush with the metal layer surface, the first circuit layer can be flush with the insulating layer without a recessed depth, thereby avoiding inconsistent recessed depths in subsequent processes, which makes it difficult to effectively combine solder balls and thus leads to poor reliability of the package substrate.

[0027] In addition, when the line width / line spacing (L / S) of the first circuit layer is designed towards miniaturization, the first circuit layer will not be damaged (such as disconnected) due to side corrosion, so as to ensure normal signal transmission between the first circuit layer and the solder balls. Therefore, the packaging substrate and its manufacturing method of the present invention are conducive to mass production of packaging substrates that need to be equipped with a miniaturized first circuit layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1A to 1F It is a cross-sectional schematic diagram of a conventional method for manufacturing a packaging substrate.

[0029] FIG. 2A to FIG. 2I It is a cross-sectional schematic diagram of a method for manufacturing a packaging substrate of the present invention.

[0030] The reference numerals are as follows:

[0031] 1,2 Package substrate

[0032] 1a, 2a line structure

[0033] 10. Barrier layer

[0034] 100 Opening Area

[0035] 11,11a,22 first circuit layer

[0036] 12,23 Dielectric layer

[0037] 120,230 blind holes

[0038] 13,24 Second circuit layer

[0039] 14,25 conductive pillars

[0040] 15,200 grooves

[0041] 20 Insulation layer

[0042] 21 Barrier layer

[0043] 23a First surface

[0044] 23b Second surface

[0045] 9 Bearing

[0046] 90 plate body

[0047] 91 Release layer

[0048] 92 Metal Layer

[0049] 920 Concave hole

[0050] D,D1,D2,D3,D4,D5,D6 Depth DETAILED DESCRIPTION

[0051] The following describes the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0052] It should be noted that the structures, proportions, sizes, etc. shown in the attached drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects and purposes that can be produced by the present invention, should still fall within the scope of the technical contents disclosed in the present invention. At the same time, the terms such as "upper", "first", "second", etc. quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0053] FIG. 2A to FIG. 2I It is a cross-sectional schematic diagram of a method for manufacturing a package substrate 2 of the present invention.

[0054] like Figure 2A As shown, a carrier 9 is provided, and an insulating layer 20 having a plurality of grooves 200 is symmetrically formed on two opposite sides of the carrier 9 , so that a portion of the surface of the carrier 9 is exposed to the plurality of grooves 200 .

[0055] In this embodiment, the carrier 9 is a temporary carrier, and the board body 90 thereof can be, for example, an organic polymer board including Bismaleimide triazine (BT), a prepreg (PP) with glass fiber, or other boards. The board body 90 has a release layer 91 such as copper on its surface, and a metal layer 92 such as a copper layer is formed on the release layer 91, so that the insulating layer 20 is formed on the metal layer 92.

[0056] Furthermore, the insulating layer 20 is a photosensitive polyimide (PSPI) with high resolution, which can form a high-density pattern, which is conducive to the subsequent miniaturization of the line width / line spacing (L / S) of the first circuit layer 22. Therefore, a plurality of grooves 200 can be formed by exposure and development, so that the plurality of grooves 200 expose a portion of the metal layer 92.

[0057] In one embodiment, the thickness of the metal layer 92 is 18 μm, and the thickness of the release layer 91 is 3 μm, but the invention is not limited thereto.

[0058] like Figure 2BAs shown, a portion of the metal layer 92 in the plurality of grooves 200 is removed by etching to form a plurality of recessed holes 920 corresponding to the plurality of grooves 200. In one embodiment, the depth of the recessed holes 920 after etching is less than the predetermined thickness of the metal layer 92. In some embodiments, the depth of the recessed holes 920 is 6 to 12 um, but is not limited thereto.

[0059] like Figure 2C As shown, a barrier layer 21 is formed in a plurality of recessed holes 920 .

[0060] In this embodiment, the barrier layer 21 may be formed in the concave hole 920 by roller coating or spraying, and the barrier layer 21 may fill the concave hole 920 and be flush with the surface of the metal layer 92 .

[0061] Furthermore, in this embodiment, the barrier layer 21 is a liquid type solder mask, but the present invention is not limited thereto, and other materials such as dry film solder mask or any photosensitive material may also be used as the material of the barrier layer 21 .

[0062] like Figure 2D As shown, a metal material (such as copper) is formed in the plurality of grooves 200 by plating or sputtering to serve as the first circuit layer 22 .

[0063] In this embodiment, the first circuit layer 22 partially fills the groove 200, so that the first circuit layer 22 is recessed in the surface of the insulating layer 20, that is, the thickness of the first circuit layer 22 is less than the thickness of the insulating layer 20. In other embodiments, the first circuit layer 22 can also fill the groove 200, so that the thickness of the first circuit layer 22 is equal to the thickness of the insulating layer 20, and the first circuit layer 22 is flush with the surface of the insulating layer 20. In addition, the first circuit layer 22 adopts the circuit redistribution layer (RDL) specification.

[0064] like Figure 2E As shown, a dielectric layer 23 is formed on the insulating layer 20 and the first circuit layer 22, and the dielectric layer 23 is defined with a first surface 23a and a second surface 23b opposite to each other, so that the first surface 23a of the dielectric layer 23 is bonded to the insulating layer 20, and a plurality of blind holes 230 exposing the first circuit layer 22 are formed on the second surface 23b of the dielectric layer 23 by laser.

[0065] In this embodiment, the dielectric layer 23 is ABF film (Ajinomoto build-up film, referred to as ABF), polybenzoxazole (Polybenzoxazole, referred to as PBO), polyimide (Polyimide, referred to as PI), glass fiber prepreg (Prepreg, referred to as PP) or other dielectric materials.

[0066] Furthermore, if the first circuit layer 22 is partially filled into the groove 200 , the dielectric layer 23 may be partially filled into the groove 200 , so that the first surface 23 a of the dielectric layer 23 has a step at the edge of the groove 200 ; if the first circuit layer 22 fills the groove 200 , the dielectric layer 23 is not filled into the groove 200 .

[0067] like Figure 2F As shown, a second circuit layer 24 is formed on the second surface 23b of the dielectric layer 23, and a plurality of conductive pillars 25 electrically connecting the first circuit layer 22 and the second circuit layer 24 are formed in the blind hole 230 to form a coreless circuit structure 2a.

[0068] In this embodiment, the second circuit layer 24 is fabricated by a build-up process by electroplating metal (such as copper) or other methods. For example, copper is electroplated on the dielectric layer 23 and in the blind hole 230 to form the second circuit layer 24 and the conductive pillar 25 as a whole.

[0069] Furthermore, the second circuit layer 24 is made of copper. For example, the second circuit layer 24 adopts a redistribution layer (RDL) specification.

[0070] It should be understood that, by using the build-up method, the number of dielectric layers 23 of the circuit structure 2a can be designed according to requirements to manufacture the required number of second circuit layers 24.

[0071] like Figure 2G As shown, the plate body 90 of the carrier 9 and the circuit structure 2 a are separated by the release layer 91 to retain the metal layer 92 on the insulating layer 20 .

[0072] In this embodiment, the release layer 91 is removed by peeling or other methods to separate the plate 90 from the metal layer 92 .

[0073] like Figure 2H As shown, the metal layer 92 is removed by etching to expose the barrier layer 21 .

[0074] like Fig.2I As shown, the barrier layer 21 is removed, so that the first circuit layer 22 is exposed from the insulating layer 20 and is flush with the surface of the insulating layer 20 .

[0075] In this embodiment, 1% sodium carbonate (NaCO 3 ) may be used to remove the barrier layer 21 .

[0076] It should be understood that in subsequent processes, multiple solder balls combined and electrically connected to the first circuit layer 22 can be set on the insulating layer 20, so that the packaging substrate 2 is connected to an electronic device such as a semiconductor chip, a passive component, a silicon interposer, a circuit board or other components through the multiple solder balls to form an electronic package.

[0077] The present invention also provides a package substrate 2 including an insulating layer 20 , a first circuit layer 22 , a dielectric layer 23 , a second circuit layer 24 and a plurality of conductive pillars 25 .

[0078] The insulating layer 20 has a plurality of grooves 200, and the first circuit layer 22 is formed in the plurality of grooves 200. Fig.2I In the illustrated embodiment, the plurality of grooves 200 are openings penetrating the insulating layer 20 , and the first circuit layer 22 is formed in the plurality of openings and flush with the insulating layer 20 , that is, flush with the surface of the insulating layer 20 corresponding to the outer surface of the packaging substrate 2 .

[0079] In this embodiment, the insulating layer 20 is a photosensitive polyimide (PSPI) with high resolution, and the first circuit layer 22 is formed by plating or sputtering a metal material (such as copper) in a plurality of grooves 200 .

[0080] Furthermore, the first circuit layer 22 is partially filled into the groove 200, so that the first circuit layer 22 is recessed in one surface of the insulating layer 20, but flush with the other surface of the insulating layer 20, that is, the thickness of the first circuit layer 22 is less than the thickness of the insulating layer 20. In other embodiments, the first circuit layer 22 can also fill the groove 200, so that the thickness of the first circuit layer 22 is equal to the thickness of the insulating layer 20, and the first circuit layer 22 is flush with the two surfaces of the insulating layer 20 respectively.

[0081] The dielectric layer 23 has a first surface 23a and a second surface 23b opposite to each other and a plurality of blind holes 230. The first surface 23a is connected to the insulating layer 20 and the first circuit layer 22. The plurality of blind holes 230 penetrate the first surface 23a and the second surface 23b and expose the first circuit layer 22.

[0082] The second circuit layer 24 is formed on the second surface 23 b of the dielectric layer 23 . A plurality of conductive pillars 25 are formed in the plurality of blind holes 230 to electrically connect the first circuit layer 22 and the second circuit layer 24 .

[0083] In this embodiment, the first circuit layer 22 and the second circuit layer 24 adopt the circuit redistribution layer (RDL) specification. It should be understood that the second circuit layer 24 and the conductive pillar 25 can be formed integrally or separately.

[0084] It should be understood that by using the build-up method, the number of dielectric layers 23 can be designed according to requirements to manufacture the required number of second circuit layers 24 .

[0085] In summary, the packaging substrate and the manufacturing method thereof of the present invention mainly form an insulating layer with a plurality of grooves on a metal layer, form a plurality of concave holes corresponding to the plurality of grooves in the metal layer, form a barrier layer in the plurality of concave holes, and form a first circuit layer on the barrier layer, so that when the metal layer is removed, the first circuit layer will not be micro-etched due to the protection of the barrier layer, and the lateral etching of the first circuit layer will be effectively prevented, thereby avoiding the problem of damage (such as disconnection) of the first circuit layer.

[0086] Furthermore, by making the barrier layer flush with the metal layer surface, the first circuit layer can be flush with the insulating layer without a recessed depth, thereby avoiding inconsistent recessed depths in subsequent processes, which makes it difficult to effectively combine solder balls and thus leads to poor reliability of the package substrate.

[0087] In addition, when the line width / line spacing (L / S) of the first circuit layer is designed towards miniaturization, the first circuit layer will not be damaged (such as disconnected) due to side corrosion, so as to ensure normal signal transmission between the first circuit layer and the solder balls. Therefore, the packaging substrate and its manufacturing method of the present invention are conducive to mass production of packaging substrates that need to be equipped with a miniaturized first circuit layer.

[0088] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Those skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. A packaging substrate, comprising: A dielectric layer having a first surface and a second surface opposite to each other; An insulating layer, formed on the first surface of the dielectric layer and having a plurality of grooves; A first circuit layer is formed in the plurality of grooves and is flush with the insulating layer; A second circuit layer is formed on the second surface of the dielectric layer; as well as A plurality of conductive pillars are formed in the dielectric layer and electrically connected to the first circuit layer and the second circuit layer.

2. The packaging substrate according to claim 1, wherein: The insulating layer is photosensitive polyimide.

3. The packaging substrate according to claim 1, wherein: The first circuit layer fills up the plurality of grooves.

4. The packaging substrate according to claim 1, wherein: The first circuit layer partially fills the plurality of grooves, so that the dielectric layer partially fills the plurality of grooves.

5. A method for manufacturing a packaging substrate, comprising: Providing a carrier having a metal layer, and forming an insulating layer having a plurality of grooves on the metal layer, wherein the plurality of grooves expose the metal layer, and the metal layer has a plurality of concave holes corresponding to the plurality of grooves; forming a barrier layer in the plurality of recessed holes; forming a first circuit layer on the barrier layer and in the plurality of grooves; Forming a dielectric layer on the insulating layer and the first circuit layer, wherein the dielectric layer has a first surface and a second surface opposite to each other, so that the first surface of the dielectric layer is bonded to the insulating layer; forming a second circuit layer on the second surface of the dielectric layer, and forming a plurality of conductive pillars in the dielectric layer that electrically connect the first circuit layer and the second circuit layer; and The carrier, the metal layer and the barrier layer are removed to expose the first circuit layer, and the first circuit layer is made flush with the insulating layer.

6. The method for manufacturing a packaging substrate according to claim 5, wherein: After forming the insulating layer, a portion of the metal layer in the plurality of grooves is removed by etching to form the plurality of concave holes.

7. The method for manufacturing a packaging substrate according to claim 5, wherein: The barrier layer fills the plurality of concave holes and is flush with the metal layer.

8. The method for manufacturing a packaging substrate according to claim 5, wherein: The barrier layer is a photosensitive material, and the insulating layer is a photosensitive polyimide.

9. The method for manufacturing a packaging substrate according to claim 5, wherein: The first circuit layer fills up the plurality of grooves.

10. The method for manufacturing a packaging substrate according to claim 5, wherein: The first circuit layer partially fills the plurality of grooves, so that the dielectric layer partially fills the plurality of grooves.

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