Interconnection structure of multi-chip interposer and manufacturing method thereof

Abstract

An interconnect structure (for a multi-chip interposer) includes: a via stack at a first position of defined positions respectively with respect to first and second vertical directions, the via stack including vias stacked on each other in a third direction perpendicular to the first and third directions; a transition section in the transition layer overlapping and coupled with an uppermost via in the stack of vias at a first location, the transition section being electrically conductive and extending in at least a first direction or a second direction to overlap with a second location offset from the first location; and a first contact bump located at the second position and over and coupled to the via stack.

Description

Technical Field

[0001] Embodiments of the present application relate to an interconnect structure of a multi-chip interposer and a method for manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry produces a variety of analog and digital devices to solve problems in many different fields. The development of semiconductor process technology nodes has gradually reduced component size and tightened spacing, resulting in a gradual increase in transistor density. ICs have become smaller and smaller. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, an interconnect structure for a multi-chip interposer is provided, the interconnect structure comprising: a first through-hole stack, located at a first position in a position, the position being defined correspondingly relative to a first direction and a second direction perpendicular to each other, the first through-hole stack comprising through-holes stacked on each other in a third direction perpendicular to each of the first direction and the second direction; and a transition section, located in a transition layer, overlapping and coupled with the topmost through-hole in the first through-hole stack, the transition section being conductive and extending in at least the first direction or the second direction to overlap with a second position in a position offset from the first position; and a first contact bump, located at a second position, located above the first through-hole stack and coupled to the first through-hole stack.

[0004] According to another aspect of an embodiment of the present application, an interconnect structure for a multi-chip interposer is provided, the interconnect structure comprising: an offset bump tower, each offset bump tower comprising: a through-hole stack located at a corresponding first position in a position, the position being correspondingly defined relative to a first direction and a second direction perpendicular to each other, the through-hole stack comprising through-holes stacked on each other in a third direction perpendicular to each of the first direction and the second direction; and a contact bump located at a corresponding second position offset from the first position in at least the first direction or the second direction, the contact bump being coupled to the through-hole stack.

[0005] According to another aspect of an embodiment of the present application, a method for forming an interconnect structure for a multi-chip interposer is provided, the method comprising: forming an offset bump tower, comprising: forming a through-hole stack at a corresponding first position among positions, the positions being correspondingly defined relative to first and second directions perpendicular to each other, each through-hole stack comprising corresponding through-holes stacked on each other in a third direction perpendicular to each of the first and second directions; and forming a contact bump at a corresponding second position correspondingly offset from the first position in at least the first direction or the second direction, the contact bump being correspondingly coupled to the through-hole stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, wherein elements having like reference numerals refer to like elements throughout. Unless otherwise disclosed, the drawings are not drawn to scale.

[0007] Figure 1A-1B is a cross-sectional view of a corresponding multi-chip system according to some embodiments.

[0008] Figure 1C-1H are corresponding simplified three-quarter perspective views collectively illustrating an interconnect structure in accordance with some embodiments.

[0009] Figure 2A-2D is a layout diagram of a corresponding interconnect structure according to some embodiments.

[0010] Figure 3A-3E is a cross-sectional view of a corresponding interconnect structure according to some embodiments.

[0011] Figure 4 and Figure 5 is a flow chart of a corresponding method of fabricating an interconnect structure according to some embodiments.

[0012] Figure 6 is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0013] Figure 7 is a block diagram of an integrated circuit (IC) manufacturing system and its associated IC manufacturing flow, according to some embodiments. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing the different features of the present disclosure. Specific embodiments or examples of components, materials, numerical values, steps, operations, arrangements, etc. are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. Other components, materials, numerical values, steps, operations, arrangements, etc. may also be considered. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted to form, and may also include an embodiment in which an additional component may be formed between the first component and the second component, so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] In addition, for ease of description, spacing relationship terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figure. In addition to the orientation shown in the figure, the spacing relationship terms are intended to include different orientations of the device in use or operating processes. The device can be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relationship descriptors used in the text can be interpreted accordingly. And in some embodiments, the term standard cell structure refers to a standardized building block included in a library of various standard cell structures. In some embodiments, various standard cell structures are selected from their library and used as components in a layout diagram representing a circuit.

[0016] In some embodiments, an interconnect structure (for a multi-chip interposer) includes an offset bump tower, each offset bump tower including: a stack of through holes at corresponding first positions among positions, which positions are correspondingly defined relative to perpendicular first and second directions, the through hole stack including through holes stacked on each other in a third direction perpendicular to each of the first and second directions; a transition section in the transition layer and overlapping and coupled with the topmost through hole in the through hole stack at the first position, the transition section is conductive and extends in at least the first direction or the second direction to overlap with a second position offset from the first position; and a contact bump at a corresponding second position offset from the first position in at least the first direction or the second direction, the contact bump being coupled to the transition section.

[0017] In some embodiments, the interconnect structure is used for a multi-chip interposer compatible with the High Bandwidth Interconnect (HBI) standard. In some embodiments, the interconnect structure is used for a multi-chip interposer compatible with the High Bandwidth Memory (HBM) standard.

[0018] In some embodiments, the interconnect structure is arranged as an array that is organized to include columns, rows, and slices. The interconnect structure includes non-offset bump towers and offset bump towers. Using offset bump towers and non-offset bump towers results in line segments (e.g. Figure 2A and Figure 2C-Figure 2D 216) is basically straight.

[0019] Another approach provides an interconnect structure that is compatible with a given HBM standard. In addition, the interconnect structure according to another approach has lines corresponding to substantially straight line segments of the present embodiment. According to another approach, only non-offset bump towers are used. Therefore, the line counterpart according to another approach is a segmented continuous line formed by short segments that intersect each other at approximately 45 degree angles, resulting in staggered or wavy line counterparts, which increases the length of the line counterparts and reduces the routability. In contrast, compared to other approaches, the use of offset bump towers according to some embodiments helps the line segments to be substantially straight, which shortens the length of the line segment instances and improves the routability of the interconnect structure.

[0020] Figure 1A is a cross-sectional view of a multi-chip system 100 ( 1 ) according to some embodiments.

[0021] The multi-chip system 100 (1) includes multiple chips (or dies), namely, die 1 and die 2, which are disposed on a multi-chip interposer. The multi-chip system 100 (1) facilitates high-bandwidth communication between die 1 and die 2. The interposer is disposed on a package substrate. Contact bumps of different sizes are formed as follows: between the interposer and each of the corresponding die 1 and die 2; between the interposer and the first and second package substrates; and on a second side of the package substrate opposite to the first side (i.e., opposite to the interposer). The multi-chip system 100 (1) communicates with an external device (not shown) through the contact bumps on the second side of the package substrate. For the sake of simplicity of illustration, Figure 1A A double tilde 137 is included to indicate Figure 1A Portions of the multi-chip system 100(1) shown in FIG.

[0022] At least one of die 1 and die 2 communicates with the package substrate via first and second wiring arrangements in the interposer, wiring arrangements (not shown) in the package substrate, and corresponding contact bumps. Die 1 and die 2 also communicate with each other via a third wiring arrangement in the interposer and corresponding contact bumps. More specifically, the third wiring arrangement includes an interconnect structure 102 (1) (see Figure 2A-2D , Figure 3A-3E etc.) Figure 1A , interconnect structure 102(1) is shown in an exploded view.

[0023] about Figure 1AIn some embodiments, the third wiring arrangement at least partially represents a physical layer PHY defined by a high-bandwidth interconnect (HBI) standard, such as a physical connection PHY, such as the HBI standard promulgated by the Joint Electron Device Engineering Council (JEDEC) Solid State Technology Association (SSTA), etc. In some embodiments, the third wiring arrangement at least partially represents a physical interface PHY defined by an HBI standard (such as the HBI standard promulgated by JEDEC SSTA, etc.), such as a low-level PHY. In some embodiments, the third wiring arrangement at least partially represents a physical connection interface PHY defined by an HBI standard (such as the HBI standard promulgated by JEDEC SSTA, etc.), such as a low-level PHY. In some embodiments, the HBI standard adopts the high-bandwidth memory (HBM) standard (see Figure 1B ) (such as the HBM standard issued by JEDEC SSTA, etc.), or the like.

[0024] Figure 1B is a multi-chip system 100 ( 2 ) according to some embodiments.

[0025] Figure 1B The multi-chip system 100 (2) is similar to Figure 1A For the sake of brevity, the discussion will focus on the differences between system 100(2) and system 100(1) rather than the similarities.

[0026] In the multi-chip system 100 (2), Figure 1A Die 1 and Die 2 are more specific devices. Die 1 is a logic die. Die 2 is a general purpose processing unit (GPU) die, a central processing unit (CPU), a system on a chip (SOC), etc. The third wiring arrangement of the interposer includes an interconnect structure 102 (2). Figure 1B , interconnect structure 102(2) is shown in an exploded view. In some embodiments, interconnect structure 102(2) is the same as interconnect structure 102(1).

[0027] The multi-chip system 100 ( 1 ) also includes a memory stack disposed on the logic die.

[0028] A memory stack includes memory dies, such as HBM dynamic random access memory (DRAM) dies, stacked on top of each other.

[0029] Contact bumps of different sizes are formed as follows: between the logic die and the bottommost memory die; and between adjacent memory dies. The memory dies of the memory stack communicate with the third wiring arrangement (including interconnect structure 102(2)) and thereby with die 2 through a fourth wiring arrangement of corresponding contact bumps.

[0030] about Figure 1B In some embodiments, the third wiring arrangement at least partially represents a physical layer PHY defined by a high bandwidth memory (HBM) standard (e.g., the HBM standard promulgated by JEDEC SSTA, etc.), such as a physical connection PHY. In some embodiments, the third wiring arrangement at least partially represents a physical interface PHY defined by an HBM standard (e.g., the HBM standard promulgated by JEDEC SSTA, etc.), such as a low-level PHY. In some embodiments, the third wiring arrangement at least partially represents a physical connection interface PHY defined by an HBM standard (e.g., the HBM standard promulgated by JEDEC SSTA, etc.), such as a low-level PHY.

[0031] Figure 1C-1H 1 are respective simplified three-quarter perspective views 102 ( 5 )C, 102 ( 5 )E, and 102 ( 5 )G that collectively represent interconnect structure 102 ( 5 ) in accordance with some embodiments.

[0032] Figure 1D , Figure 1F and Figure 1H is corresponding Figure 1C , Figure 1E and Figure 1G A more detailed version of . Interconnect structure 102(5) is an example of interconnect structure 102(1) or 102(2), etc. Similarly, Figure 2A-2D and Figure 3A-3E Accordingly, examples of interconnect structures 102(1) or 102(2), etc. are shown. Among other reasons, providing Figure 1C-1H To help Figure 2A-2D and Figure 3A-3E The orientation and Figure 1A-1B etc. and connect accordingly.

[0033] Interconnect structure 102(5) is a three-dimensional array organized into columns, rows, and slices. Figure 1C-Figure 1D View 102(5)C shows how the columns are arranged in the interconnect structure 102(5). Each column extends in the Y-axis and Z-axis directions. Thus, Figure 1D Each column in is labeled as column(YZ).

[0034] Figure 1E-1F View 102(5)E of FIG. 1 shows how the rows are arranged in the interconnect structure 102(5). Each row extends in the X-axis and Y-axis directions. Thus, Figure 1F Each row in is labeled Row(XY).

[0035] Figure 1G-1H View 102(5)G of FIG. 1 shows how the slices are arranged in the interconnect structure 102(5). Each slice extends along the X-axis and the Z-axis. Thus, Figure 1H Each slice in is labeled as Slice(XZ).

[0036] Figure 2A is a layout diagram of interconnect structure 202A( 1 ) according to some embodiments.

[0037] Figure 2A A layout diagram of a device (e.g., a semiconductor device) represents a portion of the device. The structures in the device are represented by patterns (also called shapes) in the layout diagram. To simplify the discussion, Figure 2A The elements in the layout diagram of (and other layout diagrams disclosed herein) will be referred to as structures rather than patterns themselves. For example, Figure 2A The instances of pattern 214 in represent instances of routing segments in the corresponding metallization layer. In the following discussion, instances of element 214 are referred to as instances of stacked segments 214 rather than instances of stacked segment patterns 214.

[0038] exist Figure 2A In other layout diagrams disclosed herein, an orthogonal Cartesian coordinate system is assumed, in which the first direction is parallel to the X-axis, the second direction is parallel to the Y-axis, and the third direction is parallel to the Z-axis. The layout diagram itself is a top view. The shapes in the layout diagram are two-dimensional relative to the X-axis and the Y-axis, while the devices represented are three-dimensional. In some embodiments, the first to third directions correspond to directions other than the X-axis, the Y-axis, and the Z-axis.

[0039] Typically, with respect to the Z-axis, the device is organized as a stack of layers in which there are corresponding structures, i.e., belonging to the corresponding structures. More specifically, each shape in the layout diagram represents a component in a corresponding layer of the corresponding device. In addition, typically, the layout diagram represents the relative depth of the shape and the corresponding layer, i.e., the position along the Z-axis, by superimposing a second shape on a first shape so that the second shape at least partially overlaps the first shape. Some structures are stacked along the Z-axis in the layout diagram; however, to simplify the description, the stacking order along the Z-axis is distorted in some aspects relative to the corresponding device. For example, in Figure 2A-2D , stacked segments 214 are shown on corresponding vias (eg, via 208 ( 1 )) or VT structures (eg, VT structure 210 ( 7 )).

[0040] exist Figure 2A In the embodiment, each of the section line IIIA-IIIA' and the section line IIIB-IIIB' is an offset section line, wherein the cutting plane of the offset section is stepped or offset at one or more right-angle bends. In some embodiments, the cutting plane that produces the offset section is called a piecewise continuous cutting plane. The section line IIIA-IIIA' corresponds to Figure 3A The cross-sectional view 330A of FIG. The cross-sectional line IIIB-IIIB' corresponds to Figure 3B Cross-sectional view 330B.

[0041] Layout drawings vary in the amount of detail represented. In some cases, for example, for simplicity, selected layers of the layout drawings are combined / abstracted into a single layer. Alternatively and / or additionally, in some cases, for example, for simplicity of illustration, not all layers of the corresponding semiconductor device are represented, selected layers of the layout drawings are omitted. Alternatively and / or additionally, in some cases, for example, for simplicity of illustration, not all elements of a given depicted layer of the corresponding semiconductor device are represented, i.e., selected elements of a given depicted layer of the layout drawings are omitted. For simplicity of illustration, not Figure 2A-2B All components in each of the figures in the drawings (and other layout figures disclosed herein) are represented by corresponding reference numerals. Figure 2A and other layout diagrams disclosed herein are examples of layout diagrams in which selected layers and / or selected elements of a given layer shown are omitted. In some embodiments, Figure 2A The layout diagram is part of a larger layout diagram.

[0042] exist Figure 2A , interconnect structure 202A(1) is an example of interconnect structure 102(1) or 102(2), etc. Figure 2A The organization of interconnect structure 202A( 1 ) is shown to include columns CP1 , CS1 - CS7 , and CP2 , and slices SCL1 - SLC4 .

[0043] Interconnect structure 202A(1) includes: offset bump towers 204(1)-204(4); non-offset bump towers 206(1)-206(4); uppermost vias 208(1)-208(4) in the corresponding via stack (for via 208, see Figure 3A For via stack 322(2) in FIG. 208(3), see Figure 3B ; stacked section 214; line section 216; offset transition section 218(1)-218(4); non-offset transition section (326, Figure 3A-3B ); through-via to transition element (VT) structures 210 ( 1 )- 210 ( 8 ); and contact bump 211 .

[0044] The vias and VT structures are located in the corresponding interconnect layers. The stacking segments, line segments, and transition segments are located in the corresponding metallization layers. The metallization layer with the transition segment is called a transition layer. Figure 2A , line segments 216 in columns CS1-CS7 correspond to Figure 3A-3B Line segment 316 in row RW3 of .

[0045] The offset bump tower 204 ( 1 ) includes: an instance of a stacking section 214 ; a through-via 208 ( 1 ); an offset transition section 218 ( 1 ); a VT structure 210 ( 3 ); and an instance of a contact bump 211 .

[0046] Segment 218(1) extends parallel to the X-axis from a first position (YX position) at the intersection of column CS1 and slice SLC1 on the Y-axis and the X-axis (i.e., YX position loc(CS1, SLC1)) to a second YX position loc(CS2, SLC1). At the first YX position loc(CS1, SLC1), segment 218(1) overlaps via 208(1). At the second YX position loc(CS2, SLC1), segment 218(1) protrudes under VT structure 210(3), which protrudes under an instance of contact bump 211. Due to transition segment 218(1), VT structure 210(3) and corresponding instances of contact bump 211 are offset from via 208(1).

[0047] The offset bump tower 204 ( 2 ) includes: an instance of a stacking section 214 ; a via 208 ( 2 ); an offset transition section 218 ( 2 ); a VT structure 210 ( 5 ); and an instance of a contact bump 211 .

[0048] Segment 218(2) extends parallel to the X-axis from a first YX position loc(CS1, SLC2) to a second YX position loc(CS5 / 6, SLC2), where CS5 / 6 represents the gap between columns CS5 and CS6. At the first YX position loc(CS1, SLC2), segment 218(2) overlaps via 208(2). At the second YX position loc(CS5 / 6, SLC2), segment 218(2) protrudes under VT structure 210(5), which protrudes under an instance of contact bump 211. Due to transition segment 218(2), VT structure 210(5) and corresponding instances of contact bump 211 are offset from via 208(2).

[0049] The offset bump tower 204 ( 3 ) includes: an instance of a stacking section 214 ; a through-via 208 ( 3 ); an offset transition section 218 ( 3 ); a VT structure 210 ( 4 ); and an instance of a contact bump 211 .

[0050] Segment 218(3) extends parallel to the X-axis from a first YX position loc(CS1, SLC3) to a second YX position loc(CS2, SLC3). At the first YX position loc(CS1, SLC3), segment 218(3) overlaps via 208(3). At the second YX position loc(CS2, SLC3), segment 218(3) protrudes under VT structure 210(4), which protrudes under an instance of contact bump 211. Due to transition segment 218(3), VT structure 210(4) and corresponding instances of contact bump 211 are offset from via 208(3).

[0051] The offset bump tower 204 ( 4 ) includes: an instance of a stacking section 214 ; a through-via 208 ( 4 ); an offset transition section 218 ( 4 ); a VT structure 210 ( 6 ); and an instance of a contact bump 211 .

[0052] Segment 218(4) extends parallel to the X-axis from a first YX position loc(CS1, SLC4) to a second YX position loc(CS5 / 6, SLC4). At the first YX position loc(CS1, SLC4), segment 218(4) overlaps via 208(4). At the second YX position loc(CS5 / 6, SLC4), segment 218(4) protrudes under VT structure 210(6), which protrudes under an instance of contact bump 211. Due to transition segment 218(4), VT structure 210(6) and corresponding instances of contact bump 211 are offset from via 208(4).

[0053] The non-offset bump tower 206 ( 1 ) includes: an instance of a stacking segment 214; a through hole 308 ( 21 ) ( Figure 3A ); Example of non-offset transition section 326 ( Figure 3A ); VT structure 210 (1); and an example of contact bump 211. Via 308 (21) ( Figure 3A ) and VT structure 210(1) are located at the same YX position, namely, YX position loc(CP1, SLC2). VT structure 210(1) is not substantially offset from through hole 308(21) with respect to the Y axis or the X axis ( Figure 3A ).

[0054] The non-offset bump tower 206 ( 2 ) includes: an instance of a stacking segment 214; a through hole 308 ( 23 ) ( Figure 3B ); Example of non-offset transition section 326 ( Figure 3B ); VT structure 210 (2); and an example of contact bump 211. Via 308 (23) ( Figure 3B ) and VT structure 210(2) are located at the same YX position, namely, YX position loc(CP1, SLC4). VT structure 210(2) is not substantially offset from through hole 308(23) with respect to the Y axis or the X axis ( Figure 3B ).

[0055] The non-offset bump tower 206 ( 3 ) includes: an instance of a stacking segment 214; a through hole 308 ( 20 ) ( Figure 3A ); Example of non-offset transition section 326 ( Figure 3A ); VT structure 210 (7); and an example of contact bump 211. Via 308 (20) ( Figure 3A) and VT structure 210 (7) are located at the same YX position, namely, YX position loc (CP2, SLC1). VT structure 210 (7) is not substantially offset from through hole 308 (20) with respect to the Y axis or the X axis ( Figure 3A ).

[0056] The non-offset bump tower 206 ( 4 ) includes: an instance of a stacked segment 214; a through hole 308 ( 22 ) ( Figure 3B ); Example of non-offset transition section 326 ( Figure 3B ); VT structure 210 (8); and an example of contact bump 211. Via 308 (22) ( Figure 3B ) and VT structure 210 (8) are located at the same YX position, namely, YX position loc (CP2, SLC3). VT structure 210 (8) is not substantially offset from through hole 308 (22) with respect to the Y axis or the X axis ( Figure 3B ).

[0057] exist Figure 2A , each of the vias 208(1)-208(4) is in column CS1. Thus, in some embodiments, relative to Figure 2A , each of the vias 208(1)-208(4) is depicted as being located in an outer region of the interconnect structure 202C. In some embodiments, each of the vias 208(1)-208(4) is depicted as being located in a peripheral region of the interconnect structure 202C. Figure 2A With respect to the X-axis in FIG. 2 , when the interconnect structure 202A( 1 ) is considered as a whole, the through-holes 208 ( 1 )- 208 ( 4 ) are arranged asymmetrically.

[0058] exist Figure 2A , the VT structures of adjacent offset bump towers are in different columns. With respect to adjacent offset bump towers 204(1) and 204(2), VT structures 210(3) and 210(5) are located in columns CS2 and CS5 / 6, respectively. With respect to adjacent offset bump towers 204(2) and 204(3), VT structures 210(5) and 210(4) are located in columns CS5 / 6 and CS2, respectively. With respect to adjacent offset bump towers 204(3) and 204(4), VT structures 210(4) and 210(6) are located in columns CS2 and CS5 / 6, respectively.

[0059] In some embodiments, each of the transition sections 218(1)-218(4) is described as having a regular polygonal shape. In some embodiments, a regular polygon is defined as a polygon in which all sides are equal in length and all interior angles are equal.

[0060] In some embodiments, each of the transition segments 218(1)-218(4) is described as having a convex polygonal shape. In some embodiments, a convex polygon is defined as a polygon where all interior angles are less than eighty degrees (180°). In some embodiments, a convex polygon is defined as a polygon where all diagonals are within the polygon. In some embodiments, each of the transition segments 218(1)-218(4) is described as having a rectangular shape. With respect to the Y-axis, each of the transition segments 218(1)-218(4) has a width that substantially corresponds to the minimum width of a segment in the transition layer, depending on the corresponding semiconductor process technology node.

[0061] With respect to the Y-axis, the length of each stacking segment 214 is sufficient to span a corresponding one of the vias 208(1)-208(4) or VT structures 210(1)-210(2) and 210(7)-210(8) and extend beyond each of the opposite sides of the corresponding via or VT structure at a minimum segment protrusion distance, which is associated with the corresponding metallization layer according to the corresponding semiconductor process technology node. The length of a given stacking segment is substantially less than the length of a given line segment. Conversely, the length of a given line segment is substantially greater than the length of a given stacking segment.

[0062] exist Figure 1A , each of columns CS2-CS7 has a corresponding instance of line segment 216. For each of columns CS2-CS7, the corresponding instance of line segment 216 represents a stack of instances of line segment 216 ( Figure 3A-3B ) in the uppermost instance of line segment 216. More generally, in some embodiments, for at least most of the columns CS1-CS7, each of at least most of the columns CS1 to CS7 has an instance of line segment 216.

[0063] Instances of line segment 216 and some instances of stack segment 214 are routing segments that form part of respective signal paths and are therefore configured to carry / conduct respective routing signals of circuits, etc. Examples of routing signals include input / output (I / O) signals, data signals, control signals, etc. Therefore, in some embodiments, such instances of line segment 216 are referred to as instances of routing line segment 216 and such instances of stack segment 214 are referred to as stack segment 214.

[0064] Some instances of stack segment 214 are respective parts of a power grid (PG) of a respective device. Thus, in some embodiments, such instances of stack segment 214 are referred to as PG instances of stack segment 214 and are configured to carry / conduct respective reference voltages of the device, such as VDD, VSS, etc. Figure 2A, the instances of stacked segments 214 in columns CP1 and CP2 are PG instances (PG columns), and thus the letter P in each of the alphanumeric strings CP1 and CP2 is intended to indicate that the corresponding column includes one or more PG instances in stacked segments 214. Figure 2A Columns CP1 and CP2 of FIG. 1 do not include routing instances of stacked segment 214, but not all columns that include one or more PG instances of stacked segment 214 do not include one or more routing instances of stacked segment 214; for example, see Figure 2D CP6 column, etc.

[0065] about Figure 2A In some embodiments, for at least a majority of columns CS1-CS7, each of the majority of columns does not include an instance of line segment 216 that is a PG line segment.

[0066] In some embodiments, each of columns CS1-CS7 does not include an instance of line segment 216 that is a PG line segment. Thus, the letter S in each alphanumeric string CS1-CS7 is intended to indicate that the corresponding column includes one or more routing instances of line segment 216. Figure 2A Each of columns CS1 - CS7 typically does not include a PG instance of line segment 216 , but not all columns that include one or more rotated instances of line segment 216 necessarily do not include one or more PG instances of line segment 216 .

[0067] According to another approach to an interconnect structure compatible with the HBM standard, only non-offset bump towers are used. Thus, the wire pairs according to the alternative approach of wire segments 216 are piecewise continuous wires formed by short segments that intersect each other at approximately 45 degree angles, resulting in staggered or wavy wire counterparts, which increases the length of the wire counterparts and reduces routability. In contrast, the use of offset bump towers, such as 204(1)-204(4), facilitates instances of wire segments 216 to be substantially straight, which shortens the length of instances of wire segments 216 and improves the routability of interconnect structure 202A compared to other approaches.

[0068] exist Figure 2A In some embodiments, with respect to the X-axis, the pitch of columns CS1-CS7 is a first multiple of the distance measurement unit, and the pitch of columns CS1-CS7 is a second multiple of the distance measurement unit.

[0069] exist Figure 2AIn some embodiments, columns CS1-CS7 are separated from each other by the same distance as column CP1 is separated from column CS1 and column CS7 is separated from column CP2 relative to the X-axis, i.e., in general, the pitch of columns CP1, CS1-CS7, and CP2 is a multiple of a distance measurement unit. In some embodiments, the third multiple is the same as the first multiple. In some embodiments, the distance measurement unit is 1.0 CPP. In some embodiments, CCP is an abbreviation for contact polysilicon pitch. The value of CPP is determined by the design rules and scale of the corresponding semiconductor process technology node. Here, the term "polysilicon" in the term CPP does not necessarily mean to include the corresponding based on Figure 3A-3B Rather, the term "polysilicon" is used to refer to gate lines in multi-chip systems that have interconnect structures formed of polysilicon. Rather, it represents a historical convenience—gate structures in ICs fabricated according to one or more previous semiconductor process technology nodes are typically formed of polysilicon, which has led to the term "polysilicon" being used colloquially to mean "gate line."

[0070] Figure 2B is a layout diagram of interconnect structure 202B according to some embodiments.

[0071] exist Figure 2B , interconnect structure 202B is an example of interconnect structure 102(1) or 102(2), etc. Figure 2B The organization of the interconnect structure 202B is shown to include not only Figure 2A Columns CP1, CS1-CS7 and CP2 and slices SCL1-SLC4 also include columns CP3-CP4 and CS8-CS14.

[0072] The interconnect structure 202B is Figure 2A The embodiment of the present invention is a combination of interconnect structure 202A(1) and a version of interconnect structure 202A(1), namely interconnect structure 202A(2). Relative to the position of interconnect structure 202A(1) on the Y axis, interconnect structure 202A(2) is a copy of interconnect structure 202A(1) that has been shifted along the Y axis by a distance of one slice relative to the position of interconnect structure 202A(1). In some embodiments, interconnect structure 202A(2) is described as having been shifted one slice to the left of interconnect structure 202A(1).

[0073] The organization of interconnect structure 202A(2) includes columns CP3-CP4 and CS8-CS14. Columns CP3-CP4 and CS8-CS14 of interconnect structure 202A(2) correspond to columns CPP-CP2 and CS1-CS7 of interconnect structure 202A(1). Figure 2B On the X-axis in FIG. 1 , column CP3 of interconnect structure 202A(2) overlaps column CP2 of interconnect structure 202A(1), so the overlapping columns are Figure 2BColumn CP3 shares components / structures with column CP2.

[0074] Figure 2C is a layout diagram of interconnect structure 202C according to some embodiments.

[0075] Figure 2C The interconnect structure 202C is similar to Figure 2A For the sake of brevity, the discussion will focus on the differences between interconnect structure 202C and interconnect structure 202A(1) rather than the similarities.

[0076] exist Figure 2C , interconnect structure 202C is an example of interconnect structure 102(1) or 102(2), etc. Figure 2C The organization of interconnect structure 202C is shown to include columns CP5, CS15-CS19, and CP6, and slices SCL5-SLC8.

[0077] Interconnect structure 202C includes: offset bump towers 204(5)-204(8); non-offset bump towers 206(5)-206(8); uppermost vias 208(5)-208(8) in the corresponding via stack (not shown, but see Figure 3A The through hole stack 322(1)-322(3) in Figure 3B ; stacked section 214; line section 216; offset transition section 218(5)-218(8); non-offset transition section (not shown, but see Figure 3A-3B etc.); VT structures 210 (9)-210 (16); and contact bumps 211.

[0078] The offset bump tower 204 ( 5 ) includes: an instance of a stacking section 214 ; a via 208 ( 5 ); an offset transition section 218 ( 5 ); a VT structure 210 ( 11 ); and an instance of a contact bump 211 .

[0079] Segment 218(5) extends parallel to the X-axis from a first YX position loc(CS17, SLC5) to a second YX position loc(CS15, SLC5). At the first YX position loc(CS17, SLC5), segment 218(5) overlaps via 208(5). At the second YX position loc(CS17, SLC5), segment 218(5) protrudes under VT structure 210(11), which protrudes under an instance of contact bump 211. Due to transition segment 218(5), VT structure 210(11) and corresponding instances of contact bump 211 are offset from via 208(5).

[0080] The offset bump tower 204 ( 6 ) includes: an instance of a stacking section 214 ; a through-via 208 ( 6 ); an offset transition section 218 ( 6 ); a VT structure 210 ( 13 ); and an instance of a contact bump 211 .

[0081] Segment 218(6) extends parallel to the X-axis from a first YX position loc(CS17, SLC6) to a second YX position loc(CS18, SLC6). At the first YX position loc(CS17, SLC6), segment 218(6) overlaps via 208(6). At the second YX position loc(CS18, SLC6), segment 218(6) protrudes under VT structure 210(13), which protrudes under an instance of contact bump 211. Due to transition segment 218(6), VT structure 210(13) and corresponding instances of contact bump 211 are offset from via 208(6).

[0082] The offset bump tower 204 ( 7 ) includes: an instance of a stacking section 214 ; a through-via 208 ( 7 ); an offset transition section 218 ( 7 ); a VT structure 210 ( 12 ); and an instance of a contact bump 211 .

[0083] Segment 218(7) extends parallel to the X-axis from a first YX position loc(CS17, SLC7) to a second YX position loc(CS15, SLC6). At the first YX position loc(CS17, SLC7), segment 218(7) overlaps via 208(7). At the second YX position loc(CS15, SLC6), segment 218(7) protrudes under VT structure 210(12), which protrudes under an instance of contact bump 211. Due to transition segment 218(7), VT structure 210(12) and corresponding instances of contact bump 211 are offset from via 208(7).

[0084] The offset bump tower 204 ( 8 ) includes: an instance of a stacking section 214 ; a through-via 208 ( 8 ); an offset transition section 218 ( 8 ); a VT structure 210 ( 14 ); and an instance of a contact bump 211 .

[0085] Segment 218(8) extends parallel to the X-axis from a first YX position loc(CS17, SLC8) to a second YX position loc(CS18, SLC8). At the first YX position loc(CS17, SLC8), segment 218(8) overlaps via 208(8). At the second YX position loc(CS18, SLC8), segment 218(8) protrudes under VT structure 210(14), which protrudes under an instance of contact bump 211. Due to transition segment 218(8), VT structure 210(14) and corresponding instances of contact bump 211 are offset from via 208(8).

[0086] exist Figure 2C , each of vias 208(5)-208(8) is in column CS17. Therefore, relative to Figure 2C In some embodiments, each of through holes 208(5)-208(8) is located in a central region of interconnect structure 202C. Figure 2C , each of the through holes 208(5)-208(8) is depicted as being located in an interior region of the interconnect structure 202C. In some embodiments, relative to Figure 2C , each of the through holes 208(5)-208(8) is depicted as being located in the middle region of the interconnect structure 202C. Thus, when the interconnect structure 202C is considered as a whole, relative to Figure 2C The through holes 208(5)-208(8) are arranged symmetrically along the X-axis.

[0087] exist Figure 2C , VT structures 210(11) and 210(12) are located in column CS15, while VT structures 210(13) and 210(14) are located in column CS18. Figure 2C , the VT structures 210 ( 11 )- 210 ( 14 ) and corresponding instances of the contact bump 211 are arranged asymmetrically with respect to the X-axis.

[0088] exist Figure 2C, the VT structures of the offset bump towers in adjacent slices are in different columns. With respect to the corresponding offset bump towers 204(5) and 204(6) in adjacent slices SCL5 and SLC6, the VT structures 210(11) and 210(13) are respectively located in columns CS15 and CS18. With respect to the corresponding offset bump towers 204(6) and 204(7) in adjacent slices SCL6 and SLC7, the VT structures 210(13) and 210(12) are respectively located in columns CS18 and CS15. With respect to the corresponding offset bump towers 204(7) and 204(8) in adjacent slices SCL7 and SLC8, the VT structures 210(12) and 210(14) are respectively located in columns CS15 and CS18.

[0089] Figure 2D is a layout diagram of interconnect structure 202D according to some embodiments.

[0090] Figure 2D The interconnect structure 202D is similar to Figure 2A For the sake of brevity, the discussion will focus on the differences between interconnect structure 202D and interconnect structure 202A(1) rather than the similarities.

[0091] exist Figure 2D , interconnect structure 202D is an example of interconnect structure 102(1) or 102(2), etc. Figure 2D The organization of the interconnect structure 202D is shown to include columns CP7, CS20-CS26, and CP8, and slices SCL9-SLC17.

[0092] exist Figure 2D In the embodiment, section line IIIE-IIIE' is an offset section line, wherein the cutting plane of the offset section is stepped or offset at one or more right-angle bends. In some embodiments, the cutting plane that produces the offset section is called a piecewise continuous cutting plane. Section line IIID-IIID' corresponds to Figure 3D The cross-sectional view 330D of FIG. The cross-sectional line IIIE-IIIE' corresponds to Figure 3E Cross-sectional view 330E.

[0093] exist Figure 2D , interconnect structure 202D is an example of interconnect structure 102(1) or 102(2), etc. Figure 2D The organization of interconnect structure 202D is shown to include columns CP7, CS20-CS26, and CP8, and slices SCL1-SLC4.

[0094] exist Figure 2D , line segment 216 in columns CS20-CS26 corresponds to Figure 3D-Figure 3E Line segment 316 in row RW11 of .

[0095] Interconnect structure 202D includes: offset bump towers 204(1)-204(12); non-offset bump towers 206(9)-206(12); uppermost vias 208(9)-208(12) in the corresponding via stack (for via 208(9), see Figure 3D For via stack 322(8) in FIG. 208(10), see Figure 3E The via stack 322 (10), etc. in the embodiment; the stack section 214; the line section 216; the offset transition section 218 (9)-218 (12); the non-offset transition section (326, Figure 3D-Figure 3E VT structures 210 ( 19 )- 210 ( 24 ); and contact bumps 211 .

[0096] The offset bump tower 204 ( 9 ) includes: an instance of a stacking section 214 ; a through-via 208 ( 9 ); an offset transition section 218 ( 9 ); a VT structure 210 ( 19 ); and an instance of a contact bump 211 .

[0097] Segment 218(9) extends parallel to the X-axis from a first YX position loc(CP7, SLC9) to a second YX position loc(CS21, SLC9). At the first YX position loc(CP7, SLC9), segment 218(9) overlaps via 208(9). At the second YX position loc(CS21, SLC9), segment 218(9) protrudes under VT structure 210(19), which protrudes under an instance of contact bump 211. Due to transition segment 218(9), VT structure 210(19) and corresponding instances of contact bump 211 are offset from via 208(9).

[0098] The offset bump tower 204 ( 10 ) includes: an instance of a stacking section 214 ; a through-via 208 ( 10 ); an offset transition section 218 ( 10 ); a VT structure 210 ( 21 ); and an instance of a contact bump 211 .

[0099] The segment 218(10) is partially parallel to the X-axis and partially parallel to the Y-axis, extending from a first YX position loc(CP7, SLC12) to a second YX position loc(CS24 / 25, SLC10), where CS24 / 25 represents the gap between columns CS24 and CS25. At the first YX position loc(CP7, SLC12), the segment 218(10) overlaps the via 208(10). At the second YX position loc(CS24 / 25, SLC10), the segment 218(10) protrudes under the VT structure 210(21), which protrudes under an instance of the contact bump 211. Due to the transition segment 218(10), the VT structure 210(21) and the corresponding instance of the contact bump 211 are offset from the via 208(10).

[0100] The offset bump tower 204 ( 11 ) includes: an instance of a stacking section 214 ; a through-via 208 ( 11 ); an offset transition section 218 ( 11 ); a VT structure 210 ( 20 ); and an instance of a contact bump 211 .

[0101] The segment 218(11) is partially parallel to the X-axis and partially parallel to the Y-axis, extending from a first YX position loc(CP7, SLC14) to a second YX position loc(CS21, SLC13). At the first YX position loc(CP7, SLC14), the segment 218(11) overlaps the via 208(11). At the second YX position loc(CS21, SLC13), the segment 218(11) protrudes under the VT structure 210(20), and the VT structure 210(20) protrudes under the instance of the contact bump 211. Due to the transition segment 218(11), the VT structure 210(20) and the corresponding instance of the contact bump 211 are offset from the via 208(9).

[0102] The offset bump tower 204 ( 12 ) includes: an instance of a stacking section 214 ; a through-via 208 ( 12 ); an offset transition section 218 ( 12 ); a VT structure 210 ( 22 ); and an instance of a contact bump 211 .

[0103] The segment 218(12) is partially parallel to the X-axis and partially parallel to the Y-axis, extending from a first YX position loc(CP7, SLC17) to a second YX position loc(CS24 / 25, SLC16). At the first YX position loc(CP7, SLC17), the segment 218(12) overlaps the through hole 208(12). At the second YX position loc(CS24 / 25, SLC16), the segment 218(12) protrudes under the VT structure 210(22), and the VT structure 210(22) protrudes under the instance of the contact bump 211. Due to the transition segment 218(12), the VT structure 210(22) and the corresponding instance of the contact bump 211 are offset from the through hole 208(12).

[0104] In some embodiments, the offset transition section 218(9) is described as having a regular polygonal shape. In some embodiments, the transition section 218(9) is described as having a convex polygonal shape.

[0105] In some embodiments, each of the offset transition sections 218(10)-218(12) is described as an irregular polygon. In some embodiments, each transition section 218(10)-218(12) is described as a concave polygon. In some embodiments, the transition section 218(10) is described as a concave polygon having a Z shape. In some embodiments, each transition section 218(11)-218(12) is described as a concave polygon having a P shape. In some embodiments, each transition section 218(11)-218(12) is described as a concave polygon having an L shape.

[0106] exist Figure 2D , each of the through holes 208(9)-208(12) is in the CP7 column. Thus, in some embodiments, relative to Figure 2D , each of the vias 208(9)-208(12) is depicted as being located in an outer region of the interconnect structure 202D. In some embodiments, each of the vias 208(9)-208(12) is depicted as being located in a peripheral region of the interconnect structure 202D. Figure 2D With respect to the X-axis in FIG. 2 , when the interconnect structure 202D is considered as a whole, the through-holes 208 ( 9 )- 208 ( 12 ) are arranged asymmetrically.

[0107] exist Figure 2D, the VT structures of the offset bump towers in adjacent slices are in different columns. With respect to adjacent offset bump towers 204(9) and 204(10), VT structures 210(19) and 210(21) are located in columns CS21 and CS24 / 25, respectively. With respect to adjacent offset bump towers 204(10) and 204(11), VT structures 210(21) and 210(20) are located in columns CS5 / 6 and CS21, respectively. With respect to adjacent offset bump towers 204(11) and 204(12), VT structures 210(20) and 210(22) are located in columns CS21 and CS24 / 25, respectively.

[0108] exist Figure 2D , the instances of stacked segments 214 in the non-offset bump towers 206(9) and 206(10) are PG instances in stacked segments 214 and are configured to carry / conduct the corresponding reference voltages of the device, such as VDD, VSS, etc. The instances of stacked segments 214 in the offset bump towers 204(9)-204(12) are instances of routing of stacked segments 214. Thus, column CP7 is an example to illustrate the above point, that not all columns that include one or more PG instances of stacked segments 214 do not also include one or more routing instances of stacked segments 314.

[0109] Figure 3A-3B are respective cross-sectional views 330A and 330B of an interconnect structure according to some embodiments.

[0110] and Figure 3A-3B The device corresponding to the cross section 330A-330B includes Figure 2A An example of a device of the interconnect structure 202A(1). Figure 3A The cross section 330A corresponds to Figure 2A Section IIIA-IIIA'. Figure 3B The cross section 330B corresponds to Figure 2A Section IIIB-IIIB'. It should be recalled that Figure 2A Each of the section line IIIA-IIIA' and the section line IIIB-IIIB' is an offset section line, wherein the cutting plane of the offset section is a piecewise continuous cutting plane.

[0111] exist Figure 3A-3B In the other cross-sectional views disclosed herein, an orthogonal Cartesian coordinate system is assumed, wherein the first direction is parallel to the X-axis, the second direction is parallel to the Y-axis, and the third direction is parallel to the Z-axis. Figure 3A-3B All components in each of the sections (and in other sections disclosed herein) are indicated by corresponding reference numerals.

[0112] Sections 330A-330B follow the Figure 2AThe numbering scheme is similar to the layout diagram of the . While some components correspond, some components are different. To help identify corresponding but different components, Figure 3A-3B The numbering convention uses a 3-series number for sections 330A-330B, while Figure 2A Use 2 series numbering. For example, Figure 3A The offset transition section 318(2) in corresponds to Figure 2A The offset transition section 218(2) in Figure 3B The offset transition section 318(3) in corresponds to Figure 2A The mid-offset transition section 218 (3). For the sake of brevity, the discussion will focus more on Figure 3A-3B and Figure 2A differences, not similarities.

[0113] As usually in Figure 3A Viewed from left to right in the figure, cross section 330A includes: offset bump tower 304(2); non-offset bump towers 306(3) and 306(1); via stacks 322(1), 322(2) and 322(3); uppermost vias 308(20), 308(2) and 308(21); stack segment 314; vias other than the uppermost via, i.e., via 324; line segment 316; offset transition segment 318(2); non-offset transition segment 326; VT structures 310(7), 310(5) and 310(1); and an instance of contact bump 311.

[0114] Each instance of the non-offset transition section 326 is sized sufficiently to span the corresponding VT structure 310(1) and 310(7) and extend a minimum VT overhang distance beyond the opposite sides of the corresponding VT structure 310(1) and 310(7), the minimum VT overhang distance being related to the transition layer according to the corresponding semiconductor process technology node.

[0115] exist Figure 3A in (and in Figure 3B-Figure 3C ), the transition layer corresponds to row RW1 and the metallization layer corresponds to columns RW3-RW9. Relative to the Z axis, the interconnect layers are not labeled but generally correspond to the gaps between the rows. The uppermost vias 308(20), 308(2) and 308(21) are located in the interconnect layer corresponding to the gap between rows RW1 and RW2. VT structures 310(7), 310(5) and 310(1) are located in the interconnect layer corresponding to the gap between the layer including the instance of contact bump 311 and row RW1. In some embodiments, at least the lowermost instance of via 324 is a through silicon via (TSV).

[0116] The offset section 318(2) extends parallel to the X-axis from a first XZ position loc(CS1, RW1) to a second XZ position loc(CS5 / 6, RW1), where CS5 / 6 represents the gap between columns CS5 and CS6. At the first XZ position loc(CS1, RW1), the section 318(2) overlaps the via 308(2). At the second XZ position loc(CS5 / 6, RW1), the section 318(2) protrudes under the VT structure 310(5), which protrudes under an instance of the contact bump 311. Due to the transition section 318(2), the VT structure 310(5) and the corresponding instance of the contact bump 311 are offset from the via 308(2).

[0117] exist Figure 3B , viewed generally from left to right, cross section 330B includes: offset bump tower 304(3); non-offset bump towers 306(4) and 306(2); via stacks 322(4), 322(5) and 322(6); uppermost vias 308(22), 308(3) and 308(23); stack segment 314; vias other than the uppermost via, i.e., via 324; line segment 316; offset transition segment 318(3); non-offset transition segment 326; VT structures 310(8), 310(4) and 310(2); and an instance of contact bump 311.

[0118] The offset section 318(3) extends parallel to the X-axis from a first XZ position loc(CS1, RW1) to a second XZ position loc(CS2, RW1). At the first XZ position loc(CS1, RW1), the section 318(3) overlaps the through hole 308(3). At the second XZ position loc(CS2, RW2), the section 318(3) protrudes under the VT structure 310(4), and the VT structure 310(4) protrudes under the instance of the contact bump 311. Due to the transition section 318(3), the VT structure 310(4) and the corresponding instance of the contact bump 311 are offset from the through hole 308(3).

[0119] exist Figure 3B , the offset section 318(3) extends beyond the second XZ position loc(CS2, RW1) to the third position loc(CS5 / 6, RW1). In some embodiments, the portion of the offset section 318(3) extending beyond the second XZ position loc(CS2, RW1) is optional and can be omitted, as shown by the dashed box 328(1).

[0120] Figure 3C is a cross-sectional view 330C of an interconnect structure according to some embodiments.

[0121] Figure 3C The cross-sectional view 330C is similar to Figure 3B For the sake of brevity, the discussion will focus on the differences between cross-sectional view 330C and cross-sectional view 330B, rather than the similarities.

[0122] exist Figure 3C , in the offset bump tower 304(5), the offset segment 318(3) extends beyond the second XZ position loc(CS2, RW1) to the third position loc(CS5 / 6, RW1). The cross-sectional view 330C also includes the VT structure 310(5) at the third position loc(CS5 / 6, RW1), and a corresponding instance of the contact bump 311 at the third position loc(CSR5 / 6, RW1). In some embodiments, the offset transition segment 318(3) is described as a multi-bump transition segment because the transition segment 318 protrudes below the VT structures 310(4) and 310(5). In some embodiments, Figure 3C Described as Figure 3A and Figure 3B combination.

[0123] Figure 3D-Figure 3E are respective cross-sectional views 330D and 330E of an interconnect structure according to some embodiments.

[0124] and Figure 3D-Figure 3E The device corresponding to the cross section 330D-330E includes Figure 2A An example of a device having an interconnect structure 202A(1). Figure 3D The cross section 330D corresponds to Figure 2D Cross section IIID-IIID'. Figure 3E The section 330E corresponds to Figure 2D Section IIIE-IIIE'. It should be recalled that Figure 2D The section line IIIE-IIIE' is an offset section line, wherein the cutting plane of the offset section is a piecewise continuous cutting plane.

[0125] Figure 3D-Figure 3E The corresponding sections 330D-330E follow the Figure 2D The numbering scheme is similar to the layout diagram of the . While some components correspond, some components are different. To help identify corresponding but different components, Figure 3D-Figure 3E The numbering convention uses 3 series numbers for sections 330D-330E, while Figure 2D Use 2 series numbering. For example, Figure 3D The offset transition section 318(9) in corresponds to Figure 2D The offset transition section 218(9) in Figure 3E The offset transition section 318(10) in corresponds to Figure 2DFor the sake of brevity, the discussion will focus more on the offset transition section 218 (10). Figure 3D-Figure 3E and Figure 2D differences, not similarities.

[0126] Figure 3D-Figure 3E The corresponding cross-section 330D-330E is similar to Figure 3A-3B For the sake of brevity, the discussion will focus more on Figure 3D-Figure 3E and Figure 3A-3B differences, not similarities.

[0127] As usually in Figure 3D Looking from left to right in the figure, cross section 330D includes: offset bump tower 304 (9); non-offset bump tower 306 (11); via stack 322 (23) and 322 (8); uppermost vias 308 (24) and 308 (9); stack segment 314; vias other than the uppermost via, i.e., via 324; line segment 316; offset transition segment 318 (9); non-offset transition segment 326; VT structures 310 (23) and 310 (19); and an instance of contact bump 311.

[0128] exist Figure 3D-Figure 3E , the transition layer corresponds to row RW9 and the metallization layer corresponds to columns RW10-RW17. Relative to the Z axis, the interconnect layer is not labeled but generally corresponds to the gap between the rows. The uppermost vias 308(24) and 308(9) are located in the interconnect layer corresponding to the gap between rows RW9 and RW10. VT structures 310(23) and 310(19) are located in the interconnect layer corresponding to the gap between the layer including the instance of contact bump 311 and row RW9. In some embodiments, at least the lowermost instance of via 324 is a TSV.

[0129] The offset section 318(9) extends parallel to the X-axis from a first ZX position loc(CP3, RW9) to a second ZX position loc(CS21 / 22, RW9), where CS21 / 22 represents the gap between columns CS21 and CS22. At the first XZ position loc(CP3, RW9), the section 318(9) overlaps the through hole 308(9). At the second position loc(CS21 / 22, RW9), the section 318(9) protrudes under the VT structure 310(19), which protrudes under one instance of the contact bump 311. Due to the transition section 318(9), the VT structure 310(19) and the corresponding instance of the contact bump 311 are offset from the through hole 308(9).

[0130] exist Figure 3D, the offset section 318(9) extends beyond the second XZ position loc(CP3, RW9) to the third position loc(CS25, RW9). In some embodiments, the portion of the offset section 318(9) extending beyond the second XZ position loc(CS21 / 22, RW9) is optional and can be omitted, as shown in the dashed box 328(2).

[0131] exist Figure 3E , viewed generally from left to right, cross section 330E includes: a portion of offset bump tower 304(10); non-offset bump towers 306(12) and 306(9); via stacks 322(9) and 322(10); uppermost vias 308(25) and 308(10); stack segment 314; vias other than the uppermost via, i.e., via 324; line segment 316; offset transition segment 318(10); non-offset transition segment 326; VT structures 310(24), 310(21), and 310(17); and an instance of contact bump 311.

[0132] The offset section 318 (10) is partially parallel to the X-axis and partially parallel to the Y-axis, from the first XZ position ( Figure 3E , because the corresponding section line IIIE-IIIE' is an offset section line) extends to the second XZ position loc(CS20, RW9), and extends from the second XZ position loc(CS20, RW9) to the third XZ position loc(CS24 / 25, RW9), where CS24 / 25 represents the gap between rows CS24 and CS25. At the first YX position, segment 318(10) overlaps with through hole 308(10) ( Figure 3E 308 (10). At a third XZ position loc (CS24 / 25, RW9), segment 318 (10) protrudes below VT structure 310 (21), and VT structure 310 (21) protrudes below an instance of contact bump 311. Due to transition segment 318 (10), VT structure 310 (21) and the corresponding instance of contact bump 311 are offset from through hole 308 (10).

[0133] Figure 4 is a flow chart 400 of a method of manufacturing a memory device according to some embodiments.

[0134] According to some embodiments, the method of flowchart (schematic flow chart) 400 may be implemented, for example, using EDA system 600 ( Figure 6 , discussed below) and IC manufacturing system 700 ( Figure 7 , discussed later). Examples of devices that can be manufactured according to the method of flowchart 400 include devices based on the layout diagrams disclosed herein, devices corresponding to the cross-sectional diagrams disclosed herein, and the like.

[0135] exist Figure 4 4, the method of flowchart 400 includes blocks 402-404. At block 402, a layout diagram is generated, which includes, among other things, one or more layout diagrams disclosed herein, a layout diagram corresponding to one or more of the cross-sectional diagrams disclosed herein, etc. According to some embodiments, for example, an EDA system 600 ( Figure 6 , discussed below) to implement block 402. Flow proceeds from block 402 to block 404.

[0136] At block 404, based on the layout diagram, at least one of the following is performed: (A) one or more photolithography exposures are performed, or (B) one or more photolithography masks are manufactured, or (C) one or more components in a device (eg, semiconductor device) layer are manufactured. Figure 7 Discussion of IC manufacturing system 700 in FIG.

[0137] Figure 5 is a flow chart 510 of a method of manufacturing a device according to some embodiments.

[0138] Flowchart 510 is Figure 4 4. Flowchart 510 includes blocks 512-524. The example provided in the context of flowchart 510 assumes that the first, second, and third orthogonal directions are, for example, parallel to the X-axis, Y-axis, and Z-axis, respectively. According to some embodiments, the method of flowchart 510 may be performed, for example, using IC manufacturing system 700 ( Figure 7 , discussed below). Examples of devices that can be manufactured according to the method of flowchart 710 include devices based on the layout diagrams disclosed herein, devices corresponding to the cross-sectional diagrams disclosed herein, and the like.

[0139] At block 512, an offset bump tower is formed. Examples of an offset bump tower include Figure 2A The offset bosses 204(1)-204(4), Figure 2C 204(5)-204(8) Figure 2D 204(9)-204(12) or the like. Block 512 includes block 514.

[0140] At block 514, a via stack is formed at a first location. Examples of via stacks include Figure 3A The through hole stack 322 (1)-322 (3), Figure 3B 322(4)-322(6) Figure 3D 322(7)-322(8) Figure 3E 322(9)-322(10) or the like. Block 514 includes block 516.

[0141] At block 516, vias in the interconnect layers and conductive segments in the metallization layers are alternately formed. Examples of metallization layers include Figure 3A-3C In the RW2-RW9 rows, Figure 3D-Figure 3E The metallization layers corresponding to rows RW10-RW17 in FIG.

[0142] At block 518, for a first group of two or more offset bump towers, the first group of via stacks corresponds to a first column, wherein the interconnect structure is arranged in an array organized into columns, rows, and slices. Examples of the first group include Figure 2A The group of offset bump towers 204(1)-204(2) aligned with the CS1 column in Figure 2C The group of offset bump towers 204(5)-204(8) aligned with column CS17 in Figure 2D The group of offset bump towers 204(9)-204(12) aligned in column CP7 and so on.

[0143] The flow exits block 518 and returns to block 516. The flow exits block 516 and returns to block 514. From block 514, the flow proceeds to block 520.

[0144] At block 520, an offset transition section is formed in the transition layer to extend to the uppermost via in the corresponding via stack at the first location and correspondingly to the second location. Examples of offset transition sections include Figure 2A The offset transition section 218(1)-218(4) in Figure 2C 218(5)-218(5) Figure 2D 218(9)-218(12) or the like. For example, Figure 2A The offset transition section 218(2) extends from the first YX position loc(CS1, SLC2) to the second YX position loc(CS5 / 6, SLC2). Figure 2C The offset transition section 218 (6) extends from the first YX position loc (CS17, SLC6) to the second YX position loc (CS18, SLC6). For example, Figure 2D The offset transition section 218 ( 10 ) extends from the first YX position loc ( CP7 , SLC12 ) to the second YX position loc ( CS24 / 25 , SLC10 ). Flow proceeds from block 520 to block 522 .

[0145] At block 522, a VT structure is formed accordingly on the transition section at the second location. Examples of VT structures include Figure 2A VT structure 210(3)-210(5) Figure 2C VT structure 210(11)-210(14), Figure 2DVT structure 2010(19)-210(22) etc. For example, Figure 2A The VT structure 210(5) is located at the second YX position loc(CS5 / 6, SLC2). For example, Figure 2C The VT structure 210 (13) is located at the second YX position loc (CS18, SLC6). For example, Figure 2D The VT structure 210 (21) is located at the second YX position loc (CS24 / 25, SLC10). Flow proceeds from block 522 to block 524.

[0146] At block 524, contact bumps are formed on the VT structures at the second locations accordingly. Examples of contact bumps at the second locations include Figure 2A Medium VT structure 210(3)-210(6), Figure 2B Medium VT structure 210(11)-210(14), Figure 2D An example of contact bump 211 on VT structures 210(19)-210(22) in FIG.

[0147] In some embodiments, block 512 forms offset bump towers and non-offset bump towers. Examples of non-offset bump towers include Figure 2A The non-offset bump towers 206(1)-206(4), Figure 2C 206(5)-206(8) Figure 2D 206(9)-206(12) etc.

[0148] In some embodiments, where block 512 forms an offset bump tower and a non-offset bump tower, block 520 forms an offset transition section and a non-offset transition section. In contrast to the offset transition section, the non-offset transition section does not substantially extend beyond the corresponding first position. Examples of non-offset transition sections include Figure 3A-3E The non-offset transition section 326, etc.

[0149] In some embodiments, where block 512 forms offset bump towers and non-offset bump towers, and where block 520 forms offset transition sections and non-offset transition sections, block 512 positions at least one given non-offset bump tower such that the via stack of the given non-offset bump tower is also aligned with the first column of block 518. Examples of a given non-offset bump tower include Figure 2D of non-offset concave block towers 206(9)-206(10) or the like.

[0150] In some embodiments, block 518 further forms a first set of two or more offset bump towers to exclude contact bumps configured for a reference voltage. Examples of a first set of contact bumps that exclude contact bumps configured for a reference voltage include Figure 2AThe offset bump tower groups 204(1)-204(2) aligned with the columns CS1 in Figure 2C Column CS17 in the aligned offset bump tower group 204(5)-204(8) and so on.

[0151] In some embodiments, block 522 forms the VT structures, and thus block 524 forms the contact bumps of adjacent offset bump towers, which are correspondingly located in different columns. Examples of adjacent offset bump towers where the VT structures are in different columns include Figure 2A The offset bump towers 204(1)-204(4), Figure 2C 204(5)-204(8) Figure 2D 204(9)-204(12) or similar provisions.

[0152] In some embodiments, block 522 forms at least some VT structures, and thus block 524 forms corresponding at least some contact bumps in slices that do not include via stacks corresponding to the offset bump towers. Examples of forming VT structures in slices that do not include via stacks corresponding to the offset bump towers include VT structures 210(21) of offset bump tower 204(10) (where VT structures 210(21) are in slice SLC10), VT structures 210(22) of offset bump tower 204(12) (where VT structures 210(22) are in slice SLC16), etc.

[0153] In some embodiments, block 518 aligns the first group of corresponding via stacks to the center region of the array so that the first column is located in the center region of the array. An example of a first group of via stacks being aligned so that the first column is located in the center region of the array is a group of offset bump towers 204(5)-204(8) aligned with column CS17, where column CS17 is located Figure 2C The central area of ​​the interconnect structure 202C.

[0154] In some embodiments, block 522 forms at least some of the VT structures, and thus block 524 forms corresponding at least some of the contact bumps, respectively, in different columns on opposite sides of the first column. Examples of VT structures in different columns on opposite sides of the first column include Figure 2C VT structures 210(11)-210(14), wherein VT structures 210(11)-210(12) are located on a first side / upper side of column CS17, and VT structures 210(13)-210(14) are located on a second side / lower side of column CS17.

[0155] In some embodiments, block 522 forms at least some of the VT structures, and thus block 524 forms corresponding at least some of the contact bumps, correspondingly positioned asymmetrically relative to the first column. Examples of VT structures asymmetrically positioned relative to the first column include Figure 2CVT structures 210(11)-210(14), wherein VT structures 210(11)-210(12) are located in column CS15 on the first side / upper side of column CS17, and VT structures 210(13)-210(14) are located in column CS18 on the second side / lower side of column CS17.

[0156] Figure 6 is a block diagram of an electronic design automation (EDA) system 600 according to some embodiments.

[0157] In some embodiments, the EDA system 600 includes an automatic placement and routing (APR) system. In some embodiments, the EDA system 600 is a general-purpose computing device including a hardware processor 602 and a non-transitory computer-readable storage medium 604. The storage medium 604 is encoded with, among other things, a computer program code 606, i.e., a set of executable instructions. The execution of the instructions 606 by the hardware processor 602 represents (at least in part) an EDA tool that implements, for example, a method for generating a layout diagram disclosed herein, a method for generating a layout diagram disclosed herein, or a layout diagram corresponding to a device disclosed herein, according to one or more embodiments (hereinafter referred to as the process and / or method). Part or all of the method.

[0158] Storage medium 604 stores, among other things, a layout diagram 611 , such as the layout diagrams disclosed herein.

[0159] The processor 602 is electrically coupled to the computer readable storage medium 604 via the bus 608. The processor 602 is also electrically coupled to the I / O interface 610 via the bus 608. The network interface 612 is also electrically connected to the processor 602 via the bus 608. The network interface 612 is connected to the network 614 so that the processor 602 and the computer readable storage medium 604 can be connected to external elements via the network 614. The processor 602 is configured to execute the computer program code 606 encoded in the computer readable storage medium 604 so that the system 600 can be used to perform part or all of the process and / or method. In one or more embodiments, the processor 602 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0160] In one or more embodiments, the computer-readable storage medium 604 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 604 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 604 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0161] In one or more embodiments, the storage medium 604 stores computer program code 606 configured to enable the system 600 (where such execution represents (at least in part) an EDA tool) to perform some or all of the processes and / or methods. In one or more embodiments, the storage medium 604 also stores information that facilitates the execution of some or all of the processes and / or methods. In one or more embodiments, the storage medium 604 stores a standard cell library 607 including standard cells disclosed herein. In some embodiments, the storage medium 604 stores one or more layout diagrams 611.

[0162] The EDA system 600 includes an I / O interface 610. The I / O interface 610 is coupled to an external circuit. In one or more embodiments, the I / O interface 610 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or cursor direction keys for transmitting information and commands to the processor 602.

[0163] The EDA system 600 also includes a network interface 612 coupled to the processor 602. The network interface 612 allows the system 600 to communicate with a network 614 to which one or more other computer systems are connected. The network interface 612 includes: a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, part or all of the process and / or method is implemented in two or more systems 600.

[0164] The system 600 is configured to receive information through the I / O interface 610. The information received through the I / O interface 610 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by the processor 602. The information is transmitted to the processor 602 via the bus 608. The EDA system 600 is configured to receive information related to a user interface (UI) through the I / O interface 610. The information is stored in the computer readable medium 604 as the UI 642.

[0165] In some embodiments, part or all of the processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, part or all of the processes and / or methods are implemented as a software application that is part of an add-on software application. In some embodiments, part or all of the processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the processes and / or methods are implemented as a software application used by the EDA system 600. In some embodiments, the system is implemented using a software application such as that available from CADENCEDESIGN SYSTEMS, INC. or another suitable layout generation tool to generate a layout including standard cells.

[0166] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or storage units, such as optical disks (such as DVDs), magnetic disks (such as hard disks), semiconductor memories (such as ROMs), RAMs, memory cards, etc. One or more.

[0167] Figure 7 is a block diagram of an integrated circuit (IC) manufacturing system 700 and its associated IC manufacturing flow, according to some embodiments.

[0168] In some embodiments, based on Figure 6 The layout diagram generated by block 602, the IC manufacturing system 700 implements Figure 6 Block 604 of the present invention includes using the manufacturing system 700 to manufacture at least one of: (A) one or more semiconductor masks or (B) at least one component in an early semiconductor integrated circuit layer. In some embodiments, the IC manufacturing system 700 implements Figure 5 Flowchart of the process.

[0169] exist Figure 7In the present invention, the IC manufacturing system 700 includes entities that interact in the design, development and manufacturing cycles and / or services related to manufacturing IC devices 760, such as a design room 720, a mask room 730, and an IC manufacturing plant / manufacturer ("fab") 750. The entities in the system 700 are connected by a communication network. In some embodiments, the communication network is a single network. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or fewer other entities. In some embodiments, two or more of the design room 720, the mask room 730, and the IC manufacturing plant 750 are owned by a single larger company. In some embodiments, two or more of the design room 720, the mask room 730, and the IC manufacturing plant 750 coexist in a common facility and use common resources.

[0170] The design office (or design team) 720 generates an IC design layout 722. The IC design layout 722 includes various geometric patterns designed for the IC device 760. The geometric patterns correspond to the patterns of the metal, oxide or semiconductor layers of the various components that constitute the IC device 760 to be manufactured. The layers are combined to form various IC features. For example, a portion of the IC design layout 722 includes various IC components, such as active areas, gate terminals, source and drain, metal lines or through holes for interlayer interconnection, and openings for bonding pads formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Depending on the context, the source / drain region can be referred to as a source or drain individually or collectively. The design office 720 implements an appropriate design program to form the IC design layout 722. The design process includes one or more of a logical design, a physical design, or a location and a route. The IC design layout 722 is presented in one or more data files with geometric pattern information. For example, the IC design layout 722 is represented in a GDSII file format or a DFII file format.

[0171] The mask chamber 730 includes data preparation 732 and mask manufacturing 734. The mask chamber 730 uses the IC design layout 722 to manufacture one or more masks 735 for manufacturing various layers of the IC device 760 according to the IC design layout 720. The mask chamber 730 performs mask data preparation 732, wherein the IC design layout 722 is converted into a representative data file ("RDF"). The mask data preparation 732 provides the RDF to the mask manufacturing 734. The mask manufacturing 734 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) or a semiconductor wafer. The design layout is manipulated by the mask data preparation 732 to conform to the specific characteristics of the mask writer and / or the requirements of the IC manufacturing plant 750. In Figure 7, mask data preparation 732, mask manufacturing 734, and mask 735 are shown as separate elements. In some embodiments, mask data preparation 732 and mask manufacturing 734 are collectively referred to as mask data preparation.

[0172] In some embodiments, mask data preparation 732 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts IC design layout 722. In some embodiments, mask data preparation 732 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution adjustment features, phase shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, an inverse lithography technique (ILT) is further used, which treats OPC as an inverse imaging problem.

[0173] In some embodiments, mask data preparation 732 includes a mask rule checker (MRC) that checks the IC design layout processed by OPC using a set of mask creation rules that contain certain geometric and / or connection constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for the constraints during mask fabrication 734, which may undo some of the modifications performed by OPC to satisfy the mask creation rules.

[0174] In some embodiments, mask data preparation 732 includes a lithography process check (LPC), which simulates a process to be performed by the IC fabrication plant 750 to fabricate an IC device 760. The LPC simulates the process based on the IC design layout 722 to fabricate a simulated fabricated device, such as the IC device 760. The processing parameters in the LPC simulation may include parameters related to various processes of the IC fabrication cycle, parameters related to tools used to fabricate the IC, and / or other aspects of the fabrication process. The LPC takes into account various factors, such as spatial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, etc., or combinations thereof. In some embodiments, after the LPC fabricates the simulated fabricated device, if the shape of the simulated device is not close enough to meet the design rules, the OPC and / or MRC are repeated to further refine the IC design layout 722.

[0175] For the sake of clarity, the above description of mask data preparation 732 is simplified. In some embodiments, mask data preparation 732 includes additional features, such as modifying the logic operation (LOP) of the IC design layout according to manufacturing rules. In addition, the processes applied to IC design layout 722 during data preparation 732 can be performed in a variety of different orders.

[0176] After mask data preparation 732 and during mask manufacturing 734, a mask 735 or a group of masks 735 are manufactured based on the modified IC design layout. In some embodiments, a pattern is formed on a mask (photomask or reticle) using an electron beam (e-beam) or a plurality of electron beams based on the modified IC design layout. The mask is formed by various techniques. In some embodiments, the mask is formed using binary techniques. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque area and transmitted through the transparent area. In one example, a binary mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque area of ​​the mask. In another example, a mask is formed using a phase shift technique. In a phase shift mask (PSM), various features in a pattern formed on the mask are configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase shift mask is an attenuated PSM or an alternating PSM. The masks generated by mask manufacturing 734 are used in various processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafers, used in etching processes to form various etched regions in semiconductor wafers, and / or used in other suitable processes.

[0177] IC manufacturing plant 750 is an IC manufacturing enterprise, including one or more manufacturing facilities for manufacturing various IC products. In some embodiments, IC manufacturing plant 750 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end manufacturing (front-end of line (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility can provide back-end manufacturing (back-end of line (BEOL) manufacturing) for interconnection and packaging of IC products, and a third manufacturing facility can provide other services for the foundry business.

[0178] IC manufacturing plant 750 uses mask 735 manufactured by mask chamber 730 and manufacturing tool 752 to manufacture IC device 760. Therefore, IC manufacturing plant 750 uses IC design layout 722 at least indirectly to manufacture IC device 760. In some embodiments, semiconductor wafer 753 is manufactured by IC manufacturing plant 750 using mask 735 to form IC device 760. Semiconductor wafer 753 includes a silicon substrate or other suitable substrate with material layers formed thereon. The semiconductor wafer also includes one or more of various doped regions, dielectric features, multi-level interconnects, etc. (formed in subsequent manufacturing steps).

[0179] In some embodiments, an interconnect structure (for a multi-chip interposer) includes: a first through-hole stack located at a first position in a position, the position being defined correspondingly relative to a first direction and a second direction perpendicular to each other, the first through-hole stack including through-holes stacked on each other in a third direction perpendicular to each of the first direction and the second direction; and a transition section located in a transition layer and overlapping and coupled to a topmost through-hole in the first through-hole stack, the transition section being conductive and extending in at least the first direction or the second direction to overlap with a second position in a position offset from the first position; and a first contact bump located at a second position and located above the first through-hole stack and coupled to the first through-hole stack.

[0180] In some embodiments, the first transition section has a convex polygonal shape.

[0181] In some embodiments, the first transition section has a concave polygonal shape.

[0182] In some embodiments, the interconnect structure further includes: a transition via (VT) structure located at the second position, and the transition via structure is located between the transition section and the first contact bump and couples the transition section and the first contact bump together.

[0183] In some embodiments, the vias in the first via stack are located in a corresponding interconnect layer, the interconnect layer includes vias other than the uppermost via in the first via stack; the first via stack also includes conductive segments located in a corresponding metallization layer; and the interconnect layer and the metallization layer are staggered.

[0184] In some embodiments, an interconnect structure (for a multi-chip interposer) includes offset bump towers, each bump tower including: a through-hole stack located at a corresponding first position in a position, the positions being correspondingly defined relative to first and second directions perpendicular to each other, the through-hole stack including through-holes stacked on each other in a third direction perpendicular to each of the first and second directions; and a contact bump located at a corresponding second position offset from the first position in at least the first direction or the second direction, the contact bump being coupled to the through-hole stack.

[0185] In some embodiments, each offset bump tower also includes: a transition segment located in the transition layer and overlapping and coupled with the topmost through hole in the through hole stack at a first position, the transition segment is conductive and extends in at least the first direction or the second direction to overlap with the second position; and a transition through hole (VT) structure located at the second position, and the transition through hole structure is located between the transition segment and the contact bump and couples the transition segment and the contact bump together.

[0186] In some embodiments, the vias in each via stack are located in a corresponding interconnect layer; each via stack also includes conductive segments in a corresponding metallization layer; the interconnect layer and the metallization layer are staggered; the conductive segments in the corresponding metallization layer are aligned with corresponding rows extending in a first direction, and the rows include an array; the rows are stacked on each other relative to a third direction; the array is further composed of columns; and for a first group of at least two offset bump towers, the corresponding via stack of the first group is aligned with the first column.

[0187] In some embodiments, the first column does not include a contact bump configured for a reference voltage.

[0188] In some embodiments, the array is organized into slices; each slice extends in the second direction and the third direction; each via stack is aligned with a corresponding one of the slices relative to the first direction; and the contact bumps of adjacent offset bump towers are respectively located in different columns.

[0189] In some embodiments, at least some of the dices including one or more contact bumps are dices that do not include via stacks.

[0190] In some embodiments, the first column is located in a central region of the array relative to the second direction.

[0191] In some embodiments, with respect to the second direction, the contact bumps are also located in different columns on opposite sides of the first column.

[0192] In some embodiments, the contact bumps are arranged asymmetrically with respect to the first column with respect to the second direction.

[0193] In some embodiments, the contact bumps of the offset bump tower are wiring contact bumps; and the first column includes a power grid (PG) contact bump configured for a reference voltage.

[0194] In some embodiments, the interconnect structure also includes non-offset bump towers, each bump tower including a through-hole stack at a corresponding third position, the through-hole stack including through-holes stacked on top of each other in a third direction, and a PG contact bump at the third position, the PG contact bump coupled to the through-hole stack; and wherein: at least a first non-offset bump tower in the non-offset bump tower is located in a first column; and the PG contact bumps of the first column are included in the first non-offset bump tower.

[0195] In some embodiments, a method (of forming an interconnect structure for a multi-chip interposer) includes: forming an offset bump tower, including: forming a through-hole stack at a corresponding first position among positions, the positions being correspondingly defined relative to first and second directions perpendicular to each other, each through-hole stack including corresponding through-holes stacked on each other in a third direction perpendicular to each of the first and second directions; and forming a contact bump at a corresponding second position correspondingly offset from the first position in at least the first direction or the second direction, the contact bump being correspondingly coupled to the through-hole stack.

[0196] In some embodiments, forming the offset bump tower also includes, before forming the contact bump, for each offset bump tower: forming a transition segment, the transition segment is located in the transition layer and is located at a first position on the topmost through hole in the through hole stack and coupled to the topmost through hole, the transition segment is conductive and extends in at least the first direction or the second direction to overlap with the second position; and forming a transition via (VT) structure on the second position and the transition segment; for each offset bump tower, forming the contact bump also includes forming a contact bump at the second position on the corresponding transition segment.

[0197] In some embodiments, the vias in each via stack are located in a corresponding interconnect layer; each via stack also includes a conductive segment located in a corresponding metallization layer; and forming the via stack includes: alternately forming interconnect layers and metallization layers so as to form a via in a given one of the interconnect layers, and then forming a conductive segment in a corresponding given one of the metallization layers.

[0198] In some embodiments, conductive segments in corresponding metallization layers are aligned with corresponding rows extending in a first direction, the rows comprising an array; the rows are stacked correspondingly with respect to a third direction; the array is further composed of columns; forming a through-hole stack comprises: for a first group of at least two offset bump towers, aligning the corresponding through-hole stacks of the first group to a first column in the columns.

[0199] Those skilled in the art will readily appreciate that one or more of the disclosed embodiments achieve one or more of the above advantages. After reading the above description, those skilled in the art will be able to effect various changes, substitutions of equivalents, and various other embodiments broadly disclosed herein. Therefore, the protection granted herein is limited only by the definitions contained in the attached claims and their equivalents.

Claims

1. An interconnect structure for a multi-chip interposer, the interconnect structure comprising: a first through-hole stack located at a first position among positions defined respectively with respect to first and second directions perpendicular to each other, the first through-hole stack comprising through-holes stacked on each other in a third direction perpendicular to each of the first and second directions; and a transition section located in the transition layer and overlapping and coupled to an uppermost via in the first via stack, the transition section being conductive and extending at least in the first direction or the second direction to overlap with a second position of the positions offset from the first position; as well as The first contact bump is located at the second position and is located above the first via stack and coupled to the first via stack.

2. The interconnect structure according to claim 1, further comprising: A transition via structure is located at the second position, and the transition via structure is located between the transition section and the first contact bump and couples the transition section and the first contact bump together.

3. The interconnect structure of claim 1 , wherein: The vias in the first via stack are located in a corresponding interconnect layer, the interconnect layer including vias other than an uppermost via in the first via stack; The first via stack further includes: A conductive segment located in a corresponding metallization layer; as well as The interconnect layers and the metallization layers are interleaved.

4. An interconnect structure for a multi-chip interposer, the interconnect structure comprising: An offset lug tower, each offset lug tower comprising: a through-hole stack located at a respective first position of positions respectively defined relative to first and second directions perpendicular to each other, the through-hole stack comprising through-holes stacked on each other in a third direction perpendicular to each of the first and second directions; and A contact bump is located at a corresponding second position offset from the first position in at least the first direction or the second direction, the contact bump being coupled to the via stack.

5. The interconnect structure of claim 4, wherein: Each offset lug tower also includes: a transition section located in the transition layer and overlapping and coupled with an uppermost via in the via stack at the first position, the transition section being conductive and extending in at least the first direction or the second direction to overlap with the second position; and A transition via structure is located at the second position, and the transition via structure is located between the transition section and the contact bump and couples the transition section and the contact bump together.

6. The interconnect structure of claim 4, wherein: The vias in each of the via stacks are located in a corresponding interconnect layer; Each of the via stacks further comprises: A conductive segment located in a corresponding metallization layer; The interconnect layers and the metallization layers are interleaved; the conductive segments in the respective metallization layers are aligned with corresponding rows extending in the first direction, the rows comprising an array; the rows are stacked upon one another relative to the third direction; The array is further comprised of columns; and For a first group of at least two of the offset bump towers, corresponding via stacks of the first group are aligned with a first column.

7. The interconnect structure of claim 6, wherein: The first column does not include a contact bump configured for a reference voltage.

8. The interconnect structure of claim 6, wherein: The array is organized into slices; Each of the slices extends in the second direction and the third direction; With respect to the first direction, each via stack is aligned with a corresponding one of the slices; as well as The contact bumps of adjacent offset bump towers are correspondingly located in different columns.

9. A method of forming an interconnect structure for a multi-chip interposer, the method comprising: An offset lug tower is formed, comprising: forming via stacks at respective first positions among positions respectively defined with respect to first and second directions perpendicular to each other, each of the via stacks comprising respective vias stacked on each other in a third direction perpendicular to each of the first and second directions; and Contact bumps are formed at respective second positions that are respectively offset from the first positions in at least the first direction or the second direction, the contact bumps being respectively coupled to the via stacks.

10. The method according to claim 9, wherein: Forming the offset bump tower further comprises: Before forming the contact bump, and For each offset bump tower, forming a transition section in the transition layer and located above and coupled to an uppermost via in the via stack at the first position, the transition section being conductive and extending in at least the first direction or the second direction to overlap with the second position; and forming a transition through-hole structure at the second position and the transition section; and Forming the contact bump further includes: For each offset bump tower, Contact bumps are formed at the second positions on the corresponding transition sections.

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