A SWISS-Multi-Cavity LLC Three-Phase Single-Stage AC / DC Three-Level Charge Control Method

Abstract

The present invention relates to the technical field of converters, and discloses a SWISS - multi - cavity LLC three - phase single - stage AC / DC three - level charge control method, including: Modulation method: The three - phase voltage of the low - frequency Swiss rectifier circuit is converted into the port voltage; The high - frequency resonance is input into the resonant cavity through high - frequency switching changes, and the input time is determined by the duty cycle; Control method: The charge control method is adopted; Digital control method: The frequency count and duty - cycle count entering the a - cavity are used to set the normal operating mode and PWM mode of the tubes in states 1 and 2 to be turned on and off; The normal operating mode and PWM mode entering the b - cavity, and the b - cavity is staggered by 90° from the a - cavity, and then the c - cavity and d - cavity modes are entered. The present invention improves the dynamic performance of the converter, enhances the response speed of the converter through the four - cavity parallel scheme and charge per - cycle control, and can correct the closed - loop PI, making the result more accurate and the response faster. It reduces the design difficulty of the compensator.

Description

Technical Field

[0001] The present invention relates to the technical field of new energy converter level charge control, and particularly to a SWISS-multi-chamber LLC three-phase single-stage AC / DC three-level charge control method. Background Art

[0002] In recent years, with the rapid economic development, problems such as energy shortage, environmental pollution, and climate warming have become increasingly prominent. Finding economic, clean, and renewable new energy is an effective means to solve these problems.

[0003] Building a new power system dominated by new energy is the future development direction of the power industry. In the new power system, the isolated AC / DC converter is the grid interface and core unit connecting new energy power generation such as photovoltaic and wind power, as well as energy storage systems. Therefore, in many application scenarios, the research on isolated AC / DC converters is of great significance.

[0004] Currently, the isolated AC / DC converter usually adopts a two-stage structure. The front stage adopts a three-phase PFC converter structure to complete the three-phase current control task, cope with various grid distortion problems, and ensure the power quality of the grid. The rear stage adopts an isolated DCDC structure to achieve electrical isolation between the power supply side and the load side and achieve stable output voltage under different load conditions. However, due to two-stage power conversion, this structure has disadvantages such as low conversion efficiency and high cost. In addition, the two-stage structure also requires a large-sized bus capacitor (usually an inexpensive and short-life electrolytic capacitor) to buffer the energy of the front and rear stage converters, which will reduce the reliability of the converter and limit the optimization of its power density.

[0005] With the continuous update and development of power electronics technology, the academic and industrial communities expect to find an AC / DC converter structure with higher energy transfer efficiency, more compact structure, and lower cost. Compared with the two-stage structure, the single-stage ACDC converter structure can improve the overall efficiency and power density of the converter by reducing the energy conversion level and removing the intermediate DC bus capacitor, which better meets the design requirements of current AC / DC power supply equipment. In recent years, the single-stage AC / DC converter structures studied can be divided into two categories: 1) the dual-active-bridge structure based on phase-shift control (Baranwal R, Iyer K V, Basu K, et al. A Reduced Switch Count Single-Stage Three-Phase Bidirectional Rectifier With High-Frequency Isolation[J]. IEEE Transactions on Power Electronics, 2018.) and 2) the matrix conversion structure composed of bidirectional switches with complex conduction sequences (Afsharian J, Xu D D, Wu B, et al. The Optimal PWM Modulation and Commutation Scheme for a Three-Phase Isolated Buck Matrix-Type Rectifier[J]. IEEE Transactions on Power Electronics, 2017:110-124.). Although these structures can also achieve single-stage ACDC energy conversion through complex control strategies, they cannot ensure that all switching devices achieve soft switching under full-load conditions, which limits the popularization and application of this type of converter.

[0006] Technical terms:

[0007] Three-phase single-stage AC / DC resonant converter: A converter that uses a resonant converter to achieve three-phase AC / DC conversion, as Figure 1 shown. This converter controls the transmitted energy of the resonant converter by adjusting the switching frequency, thereby controlling the input current and output voltage. The converter uses the resonant converter to achieve soft-switching of high-frequency switches, reducing switching losses and obtaining higher converter efficiency. In addition, compared with the two-stage AC / DC converter, the single-stage AC / DC converter does not require a bus capacitor and only needs a single-stage structure to complete energy conversion, thus achieving a higher power density.

[0008] SWISS rectifier: The SWISS rectifier is a new type of single-phase, step-down, three-phase AC-DC rectifier with power factor correction function, asFigure 2 As shown, it has excellent performance such as operating with unity power factor, low switching losses, low switching stress, low current harmonic distortion rate, and fully adjustable output bus voltage over the entire range. It can achieve single-stage electrical isolation and is very suitable for electric vehicle charging.

[0009] Charge control strategy: As Figure 3 shown, a current transformer is used to sample the resonant cavity current, and the sampled current passes through a resistor parameter voltage , and voltage generates a current signal through a voltage-controlled current source, and the integral voltage is obtained by integrating on the capacitor. To suppress sub-harmonic oscillations and improve stability, two current sources linearly charge or discharge the ramp compensation capacitor , and the charging and discharging currents are both , and the ramp compensation voltage is obtained. The integral voltage and the ramp compensation voltage are added to obtain . It is input to two comparators and compared with the integral threshold and 0 respectively. Initially equal to 0 triggers the RS flip-flop to set, and the resonant cavity starts to have current, starts to rise. When is equal to the integral threshold , it triggers the RS flip-flop to reset, pulls up the reset signal res, and discharges the integral capacitor.

[0010] Scheme of the first prior art:

[0011] The literature (Du Shixiang. Charge Control of LLC Converter and Its Digital Implementation [D]. Nanjing University of Aeronautics and Astronautics, 2021. DOI: 10.27239 / d.cnki.gnhhu.2021.000434.) proposed an LLC charge control strategy, which greatly improved the dynamic response of LLC. Disadvantages of the first prior art: The charge control method is only applicable to two-level, and only PI is used for regulation. It is difficult to design the compensator at high power.

[0012] Scheme of the second prior art:

[0013] Literature (Zhang Binfeng. Research on Single-Stage Isolated SWISS-Type Three-Phase AC / DC Converter [D]. Nanjing University of Aeronautics and Astronautics, 2020. DOI: 10.27239 / d.cnki.gnhhu.2020.002412.) Based on the research of the basic principle and control strategy of the SWISS-type converter, combined with the characteristics of the full-bridge structure, a single-stage isolated SWISS-type ACDC converter based on the full-bridge structure suitable for the hybrid use of Si and SiC devices is proposed, and a new modulation strategy is proposed to solve the power coupling problem of the two full-bridges, and at the same time achieve the soft switching of the main power devices. Disadvantages of the prior art II: The switching frequency is still limited to 90 kHz, and the application advantages of SiC MOSFET have not been fully demonstrated.

[0014] Technical solution of the prior art III:

[0015] Literature (X. Li, J. Sun, L. Guo, M. Gao, H. Hu and M. Xu, "A Three-Phase Single-Stage ac / dc Converter Based on Swiss Rectifier and Three-Level LLC Topology," in IEEE Transactions on Power Electronics, vol. 38, no. 2, pp. 1958-1972, Feb. 2023, doi: 10.1109.) proposed a three-phase single-stage AC / DC converter topology based on Swiss rectification and a series half-bridge three-level LLC resonant cavity. Three levels are input in one cycle, and the LLC input voltage is changed by adjusting the switching frequency fs and the duty cycle DPN. Disadvantages of the prior art III: Using average current control, the dynamic response speed is slow and it is difficult to adjust the closed-loop control.

[0016] Solution of the prior art IV:

[0017] Reference (B. Zhang, S. Xie, Z. Li, P. Zhao and J. Xu, "An Optimized Single-Stage Isolated Swiss-Type AC / DC Converter Based on Single Full-Bridge With Midpoint-Clamper," in IEEE Transactions on Power Electronics, vol. 36, no. 10, pp. 11288-11297, Oct. 2021, doi: 10.1109.) adopted a Swiss-type DAB single-stage AC / DC converter, introduced space current vector modulation to share the pressure of phase-shift control, narrowed the adjustment range of the phase-shift angle, and thus expanded the soft-switching range. Disadvantages of the prior art 4: For the single-stage AC / DC converter based on the DAB topology, it is difficult to achieve soft-switching in the full load range. Summary of the Invention

[0018] To overcome the deficiencies of the prior art, the present invention adopts a SWISS-multi-cavity LLC three-phase single-stage AC / DC three-level charge control method, which can improve the transmission power and enhance the response speed of the converter.

[0019] To achieve the above invention objective, the present invention adopts the following technical solutions:

[0020] A SWISS-multi-cavity LLC three-phase single-stage AC / DC three-level charge control method, the steps are as follows:

[0021] 1) Modulation strategy and control method;

[0022] (1) The switching logic of the three groups of bidirectional switches , , in the low-frequency Swiss rectifier circuit and the conversion relationship between the three-phase voltage ( , , ) and the port voltage ( , , ). The bidirectional switch tubes , , are alternately turned on at the cross moment of the two-phase voltages. When the three-phase voltage changes, the three phase voltages , , all become the port voltages , , ;

[0023] (2) The high-frequency resonance change part, through high-frequency switching - and - , the voltage , , is input into the resonator; within one period, , , three levels are input into the resonator, the largest one of is input in the first half period, and the remaining two phases are input in the other half period. The input time is determined by the duty cycle D;

[0024] 2) The control adopts the charge control method:

[0025] The output current is used as the outer loop, and the outer loop is used to control the stability of the output current. Its output is the peak value of the input current ; Multiply by the phase information of phase P and phase N ([[]] ) and ([[]] ) to obtain the reference currents of phase P and phase N ([[[]] and ); The inner loop controls [[[]] and to track the reference currents [[[]] and , to achieve PFC of the three-phase current, and the integral thresholds of charge control are respectively output through PI [[[]] and ;

[0026] If [[[]] > , then [[[]] controls [[[]] , [[[]] controls [[[]] ;

[0027] If [[[]] < , then [[[]] controls [[[]] , [[[]] controls [[[]] ;

[0028] Sample the resonant current of a resonator with a current transformer. The sampled current passes through the resistor Rs to obtain the voltage Vs. After the voltage Vs is inverted by an inverter, it is integrated on the integrator; at the same time the non-inverting input terminal of [[[]] , this bias voltage provides an additional constant integration current for the integration capacitor, namely the ramp compensation current Iramp, and finally the integration capacitor generates an integration voltage ;

[0029] The sampling coefficient of the resonant circuit is written as:

[0030]

[0031] Integration voltage Through the comparator and the integration threshold , Compare, output a rising edge to digital control, thereby controlling the operating frequency fs and duty cycle D of the high-frequency switch;

[0032] If it is affected by external interference, such as the output current drops below the reference value, the error increases. The IMAX output by the outer loop PI will rise. Eventually, both IPref and INref will rise, and the errors with IP and IN will also increase. After passing through the PI of the inner loop, the two integration thresholds will also rise, the frequency will decrease, and the duty cycle will increase, making the gain increase, so as to increase the output current until it equals the reference value; Since the final period is controlled by comparing the integration threshold and the integration voltage through the comparator, it is a cycle-by-cycle control with a fast response speed;

[0033] Digital control process:

[0034] ①. At the initial moment, the count Count1 of cavity a is 0, and the integration capacitor voltage is 0; After power supply, the integration capacitor Ci starts to charge,

[0035] The frequency count Count1 of cavity a and the duty cycle count Count_PFC also start to accumulate;

[0036] At the same time, when > , it is set to state 1 and turn on the transistor S1; when < , it is set to state 2 and turn on the transistor S2;

[0037] ②. When the integration capacitor voltage just reaches the integration threshold Vcomp2 of the duty cycle D, output a rising edge posedge2;

[0038] ③. If the rising edge posedge2 is detected, the count of Count_PFC is cleared, and at the same time, turn off the transistor S1 (state 1) or S2 (state 2);

[0039] ④. When the voltage of the integrating capacitor just reaches the integrating threshold Vcomp1 of the frequency, an ascending edge posedge1 is output, and at the same time, the reset switch res on the integrating capacitor Ci is closed for discharging;

[0040] ⑤. If the ascending edge posedge1 is detected, the count Count1 in chamber a starts to decrease; if the count Count1 in chamber 1 has not reached the lower limit of the cycle length at this time, let the count continue to accumulate until the count value is equal to the lower limit of the cycle, then the count starts to decrease and enters the PWM mode;

[0041] ⑥. When the decrease of Count1 starts, turn on the transistor S2 (state 1) or S1 (state 2); if it enters the PWM mode, when the ascending edge posedge2 is detected, start to turn on the transistor S2 (state 1) or S1 (state 2);

[0042] ⑦. When Count1 decreases to 0, turn off the transistor S2 (state 1) or S1 (state 2);

[0043] ⑧. During the period from the clearing of the Count_PFC count to the detection of the ascending edge posedge1, turn on the transistor Sy1;

[0044] The driving of chamber b is exactly the same as that of chamber a, staggered by 90°. In order to achieve a 90° stagger through charge control, the following control strategy is made:

[0045] 1). When the ascending edge posedge1 is detected in chamber a, assign the value of Count1 at this time to the intermediate variables Temp2 and T_PWM simultaneously. If it enters the PWM mode, then Temp2 is equal to the minimum cycle time;

[0046] 2). When the ascending edge posedge2 is detected in chamber a, assign the value of Count_PFC at this time to an intermediate variable DB;

[0047] 3). At the initial moment, the count Count2 in chamber b starts the same as that in chamber a. By the second cycle, when Count1 is equal to 0.5*Temp2 during accumulation, set Count2 to 0; then Count2 starts counting again, so as to achieve the purpose of a 90° stagger;

[0048] 4). When Count2 is greater than 0 and less than DB, turn on the transistor S4 (state 1) or S3 (state 2);

[0049] 5). When Count2 is greater than DB and less than Temp2, turn on Sy2;

[0050] 6). When Count2 is greater than Temp2, turn on the transistor S3 (state 1) or S4 (state 2);

[0051] 7), If it enters the PWM mode, turn on the transistor Sy2 when Count2 is less than Temp2 - T_PWM; turn on the transistor S3 (state 1) or S4 (state 2) when Count2 is greater than Temp2 - T_PWM;

[0052] Similarly, for the detection and setting of cavity c and cavity d, for cavity c, when the rising edge posedge1 is detected in cavity 1, set Count3 to 0; in the PWM mode, set Count3 to 0 when Count1 is equal to the minimum value of the period; for cavity d, when Count1 of cavity 1 decreases to 0.5 * Temp2, set Count4 to 0.

[0053] A SWISS - multi - cavity LLC three - phase single - stage AC / DC three - level charge control method, which adopts a charge control method: the charge for charging the integration voltage through the current of the main circuit is Vsum minus the ramp compensation voltage Vramp, then the integration threshold v comp1 、v comp2 corresponds to the charge quantity Q in1 、Q in2 as

[0054] Q i n 1 = C i K S [ v s u m ( t 2 ) − v r a m p ( t 2 ) ] Q i n 2 = C i K S [ v s u m ( t 1 ) − v r a m p ( t 1 ) ]

[0055] v ramp (t1) and v ramp (t2) correspond to the ramp compensation voltage values of t1 and t2 respectively;

[0056] The ramp compensation is generated by the ramp compensation current charging the ramp compensation capacitor, so there is:

[0057]

[0058] And the charge can be expressed by the integral of the resonant current

[0059]

[0060] Taking cavity a as an example, when at 0 - t1, the switch transistor S2 is turned on, and the current flows into the resonant cavity. When at t1 - t2, the switch transistor Sy1 is turned on, and the current flows into the resonant cavity;

[0061]

[0062] From the above formulas, the expression of the integration threshold is obtained by combining;

[0063]

[0064]

[0065] Calculate the integration threshold v according to the parameters involved in the above formula comp1 and v comp2 using the switching frequency of the previous switching period and duty cycle to replace, and then combine the current reference values i Y_ref and i N_ref of the N-phase and Y-phase at this time to calculate the required V comp1 and V comp2 :

[0066]

[0067] In the PWM working mode, the derivation of the calculation formula for the integration thresholds v comp1 and v comp2 is similar to that in the PFM working mode and can be expressed as:

[0068]

[0069] where D PWM_pre is the ratio of the time entering the PWM mode in the previous period to half of the period time;

[0070] Due to certain errors between the switching frequency of the previous period and the current period and between the duty cycle of the previous period and the current period, and various errors also exist in actual experiments, only directly calculating the integration thresholds v comp1 and v comp2 will result in poor control effect of the three-phase input current; therefore, on the basis of direct calculation, the calculation error is corrected through closed-loop regulation; after obtaining the integration threshold.

[0071] Due to the adoption of the above technical solution, the present invention has the following advantages:

[0072] A three-level charge control method for a SWISS-multi-cavity LLC three-phase single-stage AC / DC converter of the present invention is to incorporate an LLC resonant circuit into the SWISS-type AC / DC conversion process. By means of the LLC resonant cavity, soft switching of high-frequency switching tubes is achieved to reduce switching losses. At the same time, by utilizing the wide gain characteristic of LLC, the three-phase input current control and output voltage control are completed by adjusting the switching frequency of the LLC resonant cavity. To increase the transmission power, a four-cavity parallel LLC scheme is adopted for the resonant cavity. Meanwhile, to improve the response speed of the converter, a charge control strategy is introduced; and the charge control adopts a method of direct calculation plus closed-loop correction, further enhancing the response speed of the converter and reducing the design difficulty of the compensator. The specific features are as follows:

[0073] 1) The present invention proposes a three-level charge control strategy for a SWISS-four-cavity LLC multi-connected three-phase single-stage AC / DC conversion module. Integrate the resonant current, and control the conduction and turn-off of the high-frequency tube by comparing the integral voltage with the integral threshold. And the digital control logic of charge control and the control logic of four-cavity interleaving are described in detail when the three-level input is applied. The dynamic performance of the converter is improved by the cycle-by-cycle control of charge control. It solves the problems that the dynamic response speed of the SWISS-three-phase single-stage ACDC is slow under direct frequency control, the closed-loop control is difficult to adjust, and the compensator is difficult to design.

[0074] 2) To solve the problems that it is difficult to design a PI controller and the closed-loop is difficult to control in traditional charge control under high power in ACDC, this paper also proposes a charge control strategy of direct calculation plus closed-loop error correction. Mainly through mathematical derivation, the integral threshold is expressed by the reference current, switching frequency, and duty cycle. In this way, in digital control, the magnitude of the integral threshold can be directly calculated. And since the switching frequency and duty cycle cannot be known in real time, the switching frequency and duty cycle of the previous cycle are adopted, there is a certain error, so the correction of the closed-loop PI is introduced to make the result more accurate and the response faster. It solves the problem that it is difficult to design a PI controller in the application scenario of high-power ACDC for traditional charge control. Description of the Drawings

[0075] Figure 1 It is the structure diagram of a three-phase single-stage AC / DC resonant converter.

[0076] Figure 2 It is the structure diagram of a SWISS rectifier.

[0077] Figure 3 It is the structure diagram of the charge control strategy.

[0078] Figure 4 It is the topology diagram of a 40kW SWISS-4-cavity LLC three-phase single-stage AC / DC.

[0079] Figure 5 is the conversion relationship diagram between the three-phase voltage ( , , ) and the port voltage ( , , ).

[0080] Figure 6 is the charge control diagram.

[0081] Figure 7 is the control block diagram for controlling the operating frequency fs and duty cycle D of the high-frequency switch.

[0082] Figure 8 is the diagram of the charge Vsum obtained by charging the integration voltage with the main circuit current minus the ramp compensation voltage Vramp.

[0083] Figure 9 is the final control block diagram.

[0084] Figure 10 is the normal operating mode diagram of cavity a.

[0085] Figure 11 is the PWM operating mode diagram of cavity a.

[0086] Figure 12 is the normal operating mode diagram of cavity b.

[0087] Figure 13 is the PWM operating mode diagram of cavity b. Detailed implementation method

[0088] A SWISS - multi - cavity LLC three - phase single - stage AC / DC three - level charge control method adopts a topology of 40kW SWISS - 4 - cavity LLC three - phase single - stage AC / DC. Four groups of LLC circuits are connected in parallel, applying the same switching frequency, and the switching logics are mutually offset by 90 degrees. As Figure 4 shown, the parameters of the four LLC resonant cavities are exactly equal. Although their input voltages are mutually offset by 90º, the voltage waveforms are exactly the same. Therefore, the currents in the four resonant cavities are completely symmetric, also mutually offset by 90 degrees, and satisfy the equivalent relationship = 0.

[0089] Modulation strategy and control method

[0090] The switching logic of the three bidirectional switches , , in the low - frequency Swiss rectifier circuit and the three - phase voltage ( , , ) and the port voltage ( , , ), the conversion relationship between them is as Figure 5 shown. The bidirectional switch , , is only turned on alternately at the moment when the two-phase voltages cross. No matter how the three-phase voltages change, the three-phase voltages , , will all become the port voltages , , .

[0091] For the high-frequency resonance change part, through the high-frequency switching - and - , the voltages , , are input into the resonant cavity. Within one cycle, the three levels of , , are input into the resonant cavity. The largest one among the three levels is input in the first half cycle, and the remaining two phases are input in the other half cycle. The input time is determined by the duty cycle D. The control adopts the charge control strategy:

[0092] Charge control strategy 1:

[0093] The output current is used as the outer loop, and the outer loop is used to control the stability of the output current. Its output is the peak value of the input current

[0094] . Multiply by the phase information of phase P and phase N ([[]] ) and ([[]] ) to obtain the reference currents of phase P and phase N ( ) and ( and ). The inner loop controls and to track the reference currents and to achieve the PFC of the three-phase current. The integral thresholds of the charge control are respectively output through PI as and . If > , then controls , controls . If < , then controls , Control . The charge control section is as follows Figure 6 shown. It uses a current transformer to sample the resonant current of a resonant cavity. The sampled current passes through a resistor Rs to generate a parameter voltage Vs. After the voltage Vs is inverted by an inverter, it is integrated on an integrator. At the same time the non-inverting input terminal of the is connected to a bias voltage . This bias voltage provides an additional constant integration current for the integration capacitor, that is, the ramp compensation current Iramp. Finally, the integration capacitor generates an integration voltage

[0095] The sampling coefficient of the resonant circuit can be written as:

[0096]

[0097] The integration voltage is compared with an integration threshold by a comparator , and a rising edge is output to the digital control to control the operating frequency fs and duty cycle D of the high-frequency switch.

[0098] The control block diagram is as Figure 7 shown:

[0099] If it is affected by external interference, such as the output current drops below the reference value, the error increases. The IMAX output by the outer loop PI will rise. Eventually, both IPref and INref will rise, and the errors with IP and IN will also increase. After passing through the inner loop PI, the two integration thresholds will also rise, the frequency decreases, and the duty cycle increases, making the gain increase, so as to increase the output current until it equals the reference value. Since the final period is controlled by comparing the integration threshold and the integration voltage through a comparator, it is a cycle-by-cycle control with a fast response speed.

[0100] Charge control strategy 2:

[0101] In charge control strategy 1, only PI is used for closed-loop control. However, in ACDC, the current reference value and vary in AC. The PI regulator has an infinite gain at the DC point, but it is difficult to achieve a static error-free tracking of the AC quantity. To improve the control rate and dynamic response speed, reduce THD, and simplify the compensator design, a direct calculation method is introduced.

[0102] The charge that charges the integration voltage through the current of the main circuit is actually Vsum minus the ramp compensation voltage Vramp. As Figure 8 shown, the integration thresholds v comp1 , v comp2 and the charge quantity Q in1, Q in2 The corresponding relationship is

[0103] Q i n 1 = C i K S [ v s u m ( t 2 ) − v r a m p ( t 2 ) ] Q i n 2 = C i K S [ v s u m ( t 1 ) − v r a m p ( t 1 ) ]

[0104] v ramp (t1) and v ramp (t2) respectively correspond to the ramp compensation voltage values of t1 and t2.

[0105] The ramp compensation is generated by charging the ramp compensation capacitor with the ramp compensation current. Therefore, we have:

[0106]

[0107] And the charge can be expressed by the integral of the resonant current

[0108]

[0109] Taking the a cavity as an example, when 0 - t1, the switch tube S2 is turned on, and the current flows into the resonant cavity. When at the time of t1 - t2, the switch tube Sy1 is turned on, and the current flows into the resonant cavity.

[0110]

[0111] From the above equations, the expression of the integration threshold can be obtained by simultaneous equations.

[0112]

[0113]

[0114] We can directly calculate the integration thresholds v comp1 and v comp2 according to the parameters involved in the above formula. However, the frequency fs and the duty cycle D in the formula cannot be known in advance, and the frequencies and duty cycles of adjacent switching cycles do not differ much. Therefore, the switching frequency and the duty cycle of the previous switching cycle can be used to replace them. Then, combined with the current reference values i Y_ref and i N_ref of the N phase and the Y phase at this time, the required V comp1 and V comp2 are calculated as follows:

[0115]

[0116] Under the PWM working mode, for the integration threshold v comp1 and v comp2 The derivation of the calculation formula is similar to that of the PFM working mode and can be expressed as:

[0117]

[0118] where D PWM_pre is the ratio of the time entering the PWM mode to half of the cycle time in the previous cycle.

[0119] Due to certain errors in the switching frequency of the previous cycle and the current cycle, as well as the duty cycle of the previous cycle and the current cycle, and various errors also exist in actual experiments. Only using direct calculation to obtain the integration thresholds v comp1 and v comp2 will result in poor control effect of the three-phase input current. Therefore, on the basis of direct calculation, the calculation error can be corrected through closed-loop regulation. After obtaining the integration threshold, the subsequent process is the same as that of the charge control strategy 1.

[0120] Then the final control block diagram is as Figure 9 shown as:

[0121] The charge control strategy 2 introduces a direct calculation method on the basis of 1. Because the PI calculation is an accumulative calculation and the calculation process is relatively slow. If direct calculation is introduced, most of the calculations can be carried out before the PI, which can greatly reduce the time for the PI to perform accumulative calculations, thereby improving the speed of dynamic response, and can also greatly reduce the difficulty of designing the PI controller.

[0122] Digital control process:

[0123] 1. At the initial moment, the count Count1 of cavity a is 0, and the voltage of the integration capacitor is 0. After power supply, the integration capacitor Ci starts to charge, and the frequency count Count1 and the duty cycle count Count_PFC of cavity a also start to accumulate. At the same time, when > , it is set to state 1 and the transistor S1 is turned on. When < , it is set to state 2 and the transistor S2 is turned on.

[0124] 2. When the voltage of the integration capacitor just reaches the integration threshold Vcomp2 of the duty cycle D, an up edge posedge2 is output.

[0125] 3. If the up edge posedge2 is detected, the count of Count_PFC is cleared, and at the same time, the transistor S1 (state 1) or S2 (state 2) is turned off.

[0126] 4. When the voltage of the integrating capacitor just reaches the integration threshold Vcomp1 of the frequency, an ascending edge posedge1 is output, and at the same time, the reset switch res on the integrating capacitor Ci is closed for discharging.

[0127] 5. If the ascending edge posedge1 is detected, the count Count1 of cavity a starts to decrease. If the count Count1 of cavity 1 has not reached the lower limit of the cycle length at this time, the count continues to accumulate until the count value equals the lower limit of the cycle, then the count starts to decrease and enters the PWM mode.

[0128] 6. When the decrease of Count1 starts, turn on the tube S2 (state 1) or S1 (state 2). If the PWM mode is entered, when the ascending edge posedge2 is detected, start to turn on the tube S2 (state 1) or S1 (state 2).

[0129] 7. When Count1 decreases to 0, turn off the tube S2 (state 1) or S1 (state 2).

[0130] 8. During the period from the clearing of the count Count_PFC to the detection of the ascending edge posedge1, turn on the tube Sy1.

[0131] As Figure 10 is shown in the normal operation mode diagram of cavity a and Figure 11 is shown in the PWM operation mode diagram of cavity a.

[0132] The driving of cavity b is exactly the same as that of cavity a, staggered by 90°. In order to achieve the 90° stagger through charge control, the following control strategy is made:

[0133] 1. When the ascending edge posedge1 is detected in cavity a, assign the value of Count1 at this time to the intermediate variables Temp2 and T_PWM simultaneously. If the PWM mode is entered, then Temp2 is equal to the minimum cycle time.

[0134] 2. When the ascending edge posedge2 is detected in cavity a, assign the value of Count_PFC at this time to an intermediate variable DB.

[0135] 3. At the initial moment, the count Count2 of cavity b starts the same as that of cavity a. By the second cycle, when Count1 is equal to 0.5*Temp2 during the accumulation, set Count2 to 0. Immediately afterwards, Count2 starts counting again to achieve the purpose of 90° stagger.

[0136] 4. When Count2 is greater than 0 and less than DB, turn on the tube S4 (state 1) or S3 (state 2).

[0137] 5. When Count2 is greater than DB and less than Temp2, turn on Sy2.

[0138] 6. When Count2 is greater than Temp2, turn on transistor S3 (state 1) or S4 (state 2).

[0139] 7. If the PWM mode is entered, turn on transistor Sy2 when Count2 is less than Temp2 - T_PWM; turn on transistor S3 (state 1) or S4 (state 2) when Count2 is greater than Temp2 - T_PWM.

[0140] As Figure 12 shown in the normal operating mode diagram of cavity b and Figure 13 shown in the PWM operating mode diagram of cavity b.

[0141] The same principle applies to cavities c and d. For cavity c, Count3 is set to 0 when the rising edge posedge1 is detected in cavity 1, and in PWM mode, Count3 is set to 0 when Count1 is equal to the minimum value of the period. For cavity d, Count4 is set to 0 when Count1 in cavity 1 decreases and is equal to 0.5 * Temp2.

[0142] The three-level charge control strategy of the above-mentioned SWISS-four-cavity LLC multi-connected three-phase single-stage AC / DC conversion module integrates the resonant current, controls the on and off of the high-frequency transistors by comparing the integral voltage with the integral threshold, and details the digital control logic of charge control and the control logic of four-cavity interleaving when the input is three-level. The dynamic performance of the converter is improved through the cycle-by-cycle control of charge control.

[0143] And to solve the problems that it is difficult to design the PI controller and difficult to control the closed-loop under high power in traditional charge control, the present invention proposes a charge control strategy of direct calculation plus closed-loop error correction. Mainly through mathematical derivation, the integral threshold is expressed by the reference current, switching frequency, and duty cycle, so that the size of the integral threshold can be directly calculated in digital control. And because the switching frequency and duty cycle cannot be known in real time, the switching frequency and duty cycle of the previous cycle are adopted, which has a certain error. Therefore, the correction of the closed-loop PI is introduced to make the result more accurate and the response faster.

[0144] The application fields of the present invention include: 1) charging piles; 2) distributed systems; 3) energy storage systems; 4) AC / DC microgrids; 5) power electronic transformers; 6) large-scale new energy transmission; among which, when applied to charging piles, the multi-chamber topology can enable the charging pile to have a large power, improve the charging speed of the charging pile, and then by using the current charge control method, it can quickly output a more stable output voltage and current suitable for a specific electric vehicle, and can also have a faster adjustment for the interference generated by the outside world, and quickly and stably output the voltage and current.

Claims

1. A SWISS-multi-cavity LLC three-phase single-stage AC / DC three-level charge control method, characterized in that: The steps are as follows: 1) Modulation strategy and control method; (1) The switching logic of the three bidirectional switches S ay , S by , S cy in the low-frequency Swiss rectifier circuit, and the conversion relationship between the three-phase voltages U A , U B , U C and the port voltages U P , U Y , U N . The bidirectional switch tubes S ay , S by , S cy are alternately turned on at the moment of the two-phase voltage crossover. When the three-phase voltage changes, the three phase voltages U A , U B , U C all become the port voltages U P , U Y , U N ; (2) High-frequency resonance change part, by high-frequency switching S1 - S8 and S y1 -S y8 , input voltage U P , U Y , U N into the resonant cavity; within one cycle, input U P , U Y , U N three levels into the resonant cavity, input |U P |, |U Y |, |U N |, the largest one among them, and the remaining two phases are input in the other half cycle. The input time is determined by the duty cycle D; 2) The control adopts the charge control method: The output current is used as the outer loop, and the outer loop is used to control the stability of the output current, and its output is the peak value I of the input current Max ; Multiply I Max by the phase information sinθ of the P phase and the N phase P and sinθ N to obtain the reference currents I Pref and I Nref of the P phase and the N phase; The inner loop controls I P and I N to track the reference currents I Pref and I Nref , implement the PFC of the three-phase current, and respectively output the integral thresholds V COMP1 and V COMP2 of the charge control through PI; If |U P | > |U N |, then I P controls V COMP1 , and I N controls V COMP2 ; If |U P | < |U N |, then I N controls V COMP1 , and I P controls V COMP2 Sample the resonant current of a resonant cavity using a current transformer. The sampled current passes through a resistor Rs to generate a parameter voltage Vs. After the voltage Vs is inverted by an inverter, it is integrated on an integrator. At the same time, a bias voltage is connected to the inverting input terminal of OP2. The other input terminal is connected in the circuit such that the non-inverting input terminal of the operational amplifier OP2 is connected to a ramp compensation resistor Ri. The bias voltage provides an additional constant integration current for the integration capacitor, that is, a ramp compensation current Iramp. Finally, the integration capacitor generates an integration voltage V SUM ; The sampling coefficient of the resonant circuit is written as: The parameter meanings of N, Rs, R1, R2, and Ri in the coefficient calculation formula are: N is the number of turns of the secondary side of the transformer, Rs is the sampling resistor, R1 and R2 are the resistors of the operational amplifier OP1, and Ri is the ramp compensation resistor; Integral voltage V SUM Compare with the comparator and the integral threshold V COMP1 , V COMP2 to perform comparison, output a rising edge to digital control, thereby controlling the operating frequency fs and duty cycle D of the high-frequency switch; If affected by external interference and the output current drops below the reference value, the error increases. The IMAX output by the outer loop PI will rise. Eventually, both IPref and INref will rise, and the error from IP and IN also increases. After passing through the PI of the inner loop, the two integral thresholds also increase, the frequency decreases, and the duty cycle increases, resulting in an increase in gain, thereby increasing the output current until it equals the reference value; Since the final period is controlled by comparing the integral threshold and the integral voltage through a comparator, it is a cycle-by-cycle control with a fast response speed; Digital control method: ①. At the initial moment, the count Count1 of cavity a is 0, and the integral capacitor voltage V SUM is 0; after power supply, the integral capacitor C i starts to charge. The frequency count Count1 of cavity a and the duty cycle count Count_PFC also start to accumulate; Meanwhile, when |U P | > |U N |, turn on transistor S1; when |U P | < |U N |, turn on transistor S2; ②. When the voltage V of the integrating capacitor SUM just reaches the integration threshold Vcomp2 of the duty cycle D, output a rising edge posedge2; ③. If the rising edge posedge2 is detected, the count of Count_PFC is cleared, and at the same time, the transistor S1 or S2 is turned off; ④. When the integral capacitor voltage just reaches the integral threshold Vcomp1 of the frequency, a rising edge posedge1 is output, and at the same time, the reset switch res on the integral capacitor Ci is closed for discharging; ⑤. If the rising edge posedge1 is detected, the count Count1 of cavity a starts to decrease; if the count Count1 of cavity a has not reached the lower limit of the cycle length at this time, let the count continue to accumulate until the count value equals the lower limit of the cycle, then the count starts to decrease and enters the PWM mode; ⑥. When Count1 starts to decrease, the transistor S2 or S1 is turned on; if it enters the PWM mode, when the rising edge posedge2 is detected, the transistor S2 or S1 starts to be turned on; ⑦. When Count1 decreases to 0, the transistor S2 or S1 is turned off; ⑧. During the period from when the count of Count_PFC is cleared to when the rising edge posedge1 is detected, the transistor Sy1 is turned on; The driving of cavity b is exactly the same as that of cavity a, staggered by 90°; Similarly, for the detection and setting of cavities c and d, for cavity c, Count3 is set to 0 when the rising edge posedge1 is detected in cavity a, and in the PWM mode, Count3 is set to 0 when Count1 equals the minimum value of the cycle; for cavity d, Count4 is set to 0 when Count1 of cavity a decreases and equals 0.5 * Temp2; The parameter meaning of Temp2 is an intermediate variable.

2. The method for three-level charge control of a single-stage AC / DC LLC with multiple cavities and three phases according to claim 1, wherein: The control adopts the charge control method: The charge for charging the integration voltage by the current through the main circuit is Vsum minus the ramp compensation voltage Vramp, and the integration threshold v comp1 、V comp2 The correspondence with the charge quantity Q in1 、Q in2 is as follows Q in1 = C i K s [v sum (t2) - v ramp (t2)]Q in2 = C i K s [v sum (t1) - v ramp (t1)] v ramp (t1) and v ramp (t2) respectively correspond to the ramp compensation voltage values of t1 and t2; The ramp compensation is generated by charging the ramp compensation capacitor with the ramp compensation current, so there is: And the charge can be expressed by the integral of the resonant current Taking cavity a as an example, when from 0 to t1, switch S2 is turned on and current i N flows into the resonant cavity. When at the time from t1 to t2, switch Sy1 is turned on and current i y flows into the resonant cavity; From the above formulas, the expression of the integral threshold is obtained by combining; Calculate the integration threshold v based on the parameters involved in the above formula comp1 and v comp2 using the switching frequency f S_pre and duty cycle D pre of the previous switching period, and then combine with the current current reference values of the N-phase and Y-phase iY_rcf and iY _rcf to calculate the required V comp1 and V comp2 : Under the PWM operating mode, for the integration threshold v comp1 and v comp2 The derivation of the calculation formula is similar to that in the PFM operating mode and can be expressed as: Among them, D PWM_pre is the ratio of the time entering the PWM mode in the previous period to half of the period time; Due to certain errors between the switching frequency of the previous cycle and that of the current cycle, as well as between the duty cycle of the previous cycle and that of the current cycle, and various errors also exist in actual experiments, simply calculating directly to obtain the integration thresholds v comp1 and v comp2 will result in poor control effect of the three-phase input current; therefore, on the basis of direct calculation, the calculation error is corrected through closed-loop regulation.

3. The SWISS multi - cavity LLC three - phase single - stage AC / DC three - level charge control method according to claim 1, wherein: The charge control adopted by the digital control method realizes a 90° stagger. The specific control method is as follows: 1) When a rising edge posedge1 is detected in chamber a, the value of Count1 at this time is simultaneously assigned to the intermediate variable Temp2 and T_PWM. If the PWM mode is entered, then Temp2 is equal to the minimum period time; 2) When a rising edge posedge2 is detected in cavity a, assign the value of Count_PFC at this time to an intermediate quantity D B ; 3) At the initial moment, the count Count2 in chamber b starts the same as in chamber a. By the second cycle, when Count1 is equal to 05 * Temp2 during accumulation, Count2 is set to 0; immediately afterwards, Count2 starts counting again to achieve the purpose of staggering by 90°; 4) When Count2 is greater than 0 and less than DB, turn on transistor S4 or S3; 5) When Count2 is greater than D B and less than Temp2, turn on Sy2; 6) When Count2 is greater than Temp2, turn on transistor S3 or S4; 7) If the PWM mode is entered, then turn on transistor Sy2 when Count2 is less than Temp2 - T_PWM; turn on transistor S3 or S4 when Count2 is greater than Temp2 - T_PWM.

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