Comparator and compensating tube-based negative single-particle transient reinforcing circuit and method

Abstract

The invention provides a negative single-particle transient reinforcing circuit and method based on a comparator and a compensating tube. The negative single-particle transient reinforcing circuit comprises the comparator, a connecting tube, the compensating tube, a capacitor, a seventh resistor and an eighth resistor. The seventh resistor and the eighth resistor form a resistor network, and reference voltage is arranged between the seventh resistor and the eighth resistor; the positive input end of the comparator is connected with a reference voltage, the negative input end of the comparator is connected with an output voltage Vout, the control end of the comparator is connected with a control voltage Ven, and the output end of the comparator is connected with the grid electrodes of the connecting tube and the compensating tube; the source electrode of the connecting tube is respectively connected with the source electrode of the compensating tube, one end of the capacitor and the grid electrode of the power tube, and the other end of the capacitor is grounded. According to the reinforcing circuit, when a negative single-particle transient pulse arrives, the power tube and the error amplifier are isolated, and charges flowing out of the negative single-particle transient pulse are compensated through the connecting tube; therefore, the effect of reducing the influence of the negative single-particle transient pulse is achieved, and a reinforcing effect is achieved.

Description

Technical Field

[0001] The present application relates to the technical field of transient reinforcement circuits, and in particular to a negative single-particle transient reinforcement circuit and method based on a comparator and a compensation tube. Background Art

[0002] Particle transient effects are caused by the energy transfer of particles to electrons in the medium. When a particle (such as an electron or photon) passes through a medium, it interacts with atoms or molecules in the medium, causing electrons to be excited or stripped from their atomic orbitals. These excited or ionized states exist only for a moment and decay rapidly. In this process, holes are formed, which move in the surrounding medium until they recombine with other electrons. The time scale of this recombination process is shorter than the time scale of the interaction between the electron and the medium, so it can be considered that all electrons recombine simultaneously in a period of time. Single particle transient effects can be used to develop highly sensitive single particle sensors. By combining sensitive media with electronic detectors, when particles pass through the medium and cause transient effects, this signal can be captured by the electronic detector. This single particle sensor can be used in environmental monitoring, life science research and other fields; single particle transient effects can be used to evaluate the reliability of electronic devices. In electronic devices, single particle transient effects may cause misoperation or device damage, so it is very important for the reliability evaluation of electronic devices. Through simulation or experiment, the response of electronic devices under single particle transient effects can be studied, and the resistance of Apple devices to particle radiation can be studied, thereby guiding the design and manufacture of electronic devices.

[0003] LDO refers to low-dropout linear regulator, which is mainly used to convert unstable DC voltage into stable DC output voltage. Low-dropout linear regulator is a new generation of integrated circuit regulator. The biggest difference between it and the three-terminal regulator is that the low-dropout linear regulator is a micro-chip system with very low self-consumption. It can be used for current main channel control. The chip integrates hardware circuits such as mosfet with extremely low online on-resistance, Schottky diode, sampling resistor and voltage divider resistor, and has overcurrent protection, overtemperature protection, precision reference source, differential amplifier, delay and other functions. Low-dropout linear regulator usually has extremely low self-noise and high power supply rejection ratio. The current LDO does not have a reinforcement circuit. When a negative single-particle transient pulse arrives, it is easy to affect the LDO. Therefore, it is necessary to design a negative single-particle transient reinforcement circuit. Summary of the invention

[0004] The present application provides a negative single particle transient reinforcement circuit and method based on a comparator and a compensation tube to solve the problem that the current LDO is easily affected by negative single particle transient pulses. When a negative single particle transient pulse arrives, the power tube and the error amplifier are isolated to reduce the impact of the negative single particle transient pulse.

[0005] The present application provides a negative single-particle transient reinforcement circuit based on a comparator and a compensation tube, the negative single-particle transient reinforcement circuit comprising a comparator, a connecting tube, a compensation tube, a capacitor, a seventh resistor and an eighth resistor;

[0006] The seventh resistor and the eighth resistor form a resistor network, and a reference voltage Vout_min is set between the seventh resistor and the eighth resistor;

[0007] The positive input terminal of the comparator is connected to the reference voltage Vout_min, the negative input terminal of the comparator is connected to the output voltage Vout, the control terminal is connected to the control voltage Ven, and the output terminal of the comparator is connected to the gates of the connecting tube and the compensation tube;

[0008] The source electrode of the connecting tube is respectively connected to the source electrode of the compensation tube, one end of the capacitor, and the gate electrode of the power tube, and the other end of the capacitor is grounded;

[0009] The drain of the connecting tube is connected to the output end of the error amplifier, the source of the power tube is connected to one end of the fifth resistor, the other end of the fifth resistor is respectively connected to the negative input end of the error amplifier and one end of the sixth resistor, and the other end of the sixth resistor is grounded;

[0010] The positive input terminal of the error amplifier is connected to the Vref reference voltage terminal.

[0011] Preferably, the comparator is composed of a bias circuit, a first-stage differential amplifier circuit, a second-stage differential-to-single-ended output circuit and an output buffer circuit, and the bias circuit is sequentially connected to the first-stage differential amplifier circuit, the second-stage differential-to-single-ended output circuit and the output buffer circuit.

[0012] Preferably, the first-stage differential amplifier circuit includes a second transistor, a first differential input transistor, a second differential input transistor, a first load tube, a second load tube, a first reset tube and a second reset tube. The source of the second transistor is grounded, and the gate is connected to the gate of the eighth transistor in the bias circuit. The drain of the second transistor is respectively connected to the source of the first differential input transistor and the source of the second differential input transistor. The drain of the first differential input transistor is respectively connected to the drain of the first load tube and the drain of the first reset tube; the drain of the second differential input transistor is respectively connected to the drain of the second reset tube and the drain of the second load tube.

[0013] Preferably, the second-stage differential-to-single-ended output circuit comprises a third transistor, a third differential input transistor, a fourth differential input transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a third load transistor, a fourth load transistor, a fifth load transistor, a sixth load transistor, a third reset transistor and a fourth reset transistor, the gate of the third transistor is connected to the gate of the eighth transistor, the source of the third transistor is grounded, and the drain of the third transistor is respectively connected to the source of the third differential input transistor and the source of the fourth differential input transistor;

[0014] The drain of the third differential input transistor is connected to the drain of the fifth load transistor, the drain of the fourth differential input transistor is connected to the drain of the fourth load transistor, the gate of the third differential input transistor is respectively connected to the drain of the third load transistor and the drain of the sixth transistor, the source of the sixth transistor is grounded, and the drain of the sixth transistor is connected to the drain of the fourth transistor;

[0015] The drain of the fourth differential input transistor is respectively connected to the drain of the fourth load transistor and the drain of the fourth reset transistor, the gate of the fourth differential input transistor is respectively connected to the drain of the fourth load transistor and the drain of the seventh transistor, the source of the seventh transistor is grounded, and the drain of the seventh transistor is also connected to the drain of the fifth transistor;

[0016] The gate electrode of the fifth load tube is connected to the gate electrode of the sixth load tube and to the drain electrode of the third reset tube.

[0017] Preferably, the output buffer circuit is formed by three inverters connected in series, and the input end of the inverter is connected to the drain of the fourth differential input transistor.

[0018] Preferably, the bias circuit includes a fifth reset tube, a first transistor and an eighth transistor, a fourth resistor, a first resistor, a second resistor and a third resistor connected in series are connected between the drain of the fifth reset tube and the drain of the eighth transistor, the source of the eighth transistor is grounded, the drain of the first transistor is connected to the drain of the eighth transistor, and the source of the first transistor is grounded.

[0019] Preferably, the reinforcement method of the negative single event transient reinforcement circuit based on the comparator and the compensation tube comprises the following steps:

[0020] A. Before the LDO enters the normal working state, the control signal Ven is at a low level, the comparator does not work, the output of the comparator is at a low level, the connecting tube is turned on, the compensation tube is disconnected, the error amplifier discharges the gate of the power tube, Vg becomes high, and the LDO output voltage Vout becomes high;

[0021] B. When the LDO enters the normal working state, the control voltage Ven is at a high level, and the comparator starts to work. At this time, the LDO output voltage Vout is greater than the reference voltage Vout_min formed by the resistor network, and the output of the comparator is at a low level. The connecting tube remains turned on, the compensation tube remains turned off, and the LDO works stably.

[0022] C. When a negative single-particle transient pulse occurs, the output Vout of the LDO is less than the reference voltage Vout_min, the comparator output is high, the connecting tube is disconnected, the compensation tube is turned on, the capacitor begins to maintain the gate voltage of the power tube, and the compensation tube begins to slowly discharge the gate of the power tube to compensate for the charge flowing out of the negative single-particle transient pulse;

[0023] D. With the charge compensation, the gate voltage Vg of the power tube gradually increases, and the LDO output voltage Vout gradually increases. When the LDO output voltage Vout rises to a value greater than the reference voltage Vout_min formed by the resistor network, the negative single-particle transient pulse of the error amplifier EA has ended.

[0024] E. The output voltage of the comparator returns to a low level, the connecting tube P11 is turned on, the compensation tube N13 is disconnected, the gate of the power tube N12 is connected to the output end of the error amplifier, and the LDO returns to normal working state.

[0025] Beneficial effect: The reinforcement circuit of the present invention isolates the power tube and the error amplifier when a negative single-particle transient pulse arrives, and compensates for the charge flowing out of the negative single-particle transient pulse through the connecting tube, thereby reducing the effect of the negative single-particle transient pulse and playing a reinforcement role.

[0026] The above description is only an overview of the technical solution of the embodiment of the present application. In order to more clearly understand the technical means of the embodiment of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, a brief introduction will be given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 It is the circuit principle diagram of the present invention;

[0029] Figure 2 is a schematic diagram of a comparator circuit of the present invention;

[0030] Figure 3 This is a schematic diagram of the LDO output results before and after reinforcement;

[0031] Figure 4 The schematic diagram of the unreinforced LDO. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used in the specification of the application are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification, claims and drawings of this application are intended to cover non-exclusive inclusions.

[0034] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiments" in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0035] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0036] See also Figure 1-Figure 3 The present invention discloses a negative single particle transient reinforcement circuit based on a comparator and a compensation tube, the negative single particle transient reinforcement circuit includes a comparator, a connecting tube P11, a compensation tube N13, a capacitor C1, a seventh resistor R7 and an eighth resistor R8;

[0037] The seventh resistor R7 and the eighth resistor R8 form a resistor network, and a reference voltage Vout_min is set between the seventh resistor R7 and the eighth resistor R8;

[0038] The positive input terminal of the comparator is connected to the reference voltage Vout_min, the negative input terminal of the comparator is connected to the output voltage Vout, the control terminal is connected to the control voltage Ven, and the output terminal of the comparator is connected to the gates of the connecting tube P11 and the compensation tube N13;

[0039] The source of the connecting tube P11 is respectively connected to the source of the compensation tube N13, one end of the capacitor C1, and the gate of the power tube N12, and the other end of the capacitor C1 is grounded;

[0040] The drain of the connecting tube P11 is connected to the output end of the error amplifier, the source of the power tube N12 is connected to one end of the fifth resistor R5, the other end of the fifth resistor R5 is respectively connected to the negative input end of the error amplifier and one end of the sixth resistor R6, and the other end of the sixth resistor R6 is grounded;

[0041] The positive input terminal of the error amplifier is connected to the Vref reference voltage terminal.

[0042] Among them, the connecting tube P11 plays an isolation role, and controls the output of the error amplifier EA and the gate of the power tube N12 according to the output of the comparator CMP. The compensation tube N13 is also controlled by the output of the comparator CMP, and is used to slowly compensate the lost charge on the gate of the power tube N12 during the negative pulse. The capacitor C1 is responsible for maintaining the stability of the gate voltage of the power tube N1 when the connecting tube P11 is disconnected, and also has a filtering effect.

[0043] In the present invention, the comparator is composed of a bias circuit, a first-stage differential amplifier circuit, a second-stage differential-to-single-ended output circuit and an output buffer circuit, and the bias circuit is sequentially connected to the first-stage differential amplifier circuit, the second-stage differential-to-single-ended output circuit and the output buffer circuit.

[0044] Among them, the first-stage differential amplifier circuit includes a second transistor N2, a first differential input transistor N3, a second differential input transistor N4, a first load tube P1, a second load tube P4, a first reset tube P2 and a second reset tube P3, the source of the second transistor N2 is grounded, and the gate is connected to the gate of the eighth transistor N0 in the bias circuit, the drain of the second transistor N2 is respectively connected to the source of the first differential input transistor N3 and the source of the second differential input transistor N4, the drain of the first differential input transistor N3 is respectively connected to the drain of the first load tube P1 and the drain of the first reset tube P2; the drain of the second differential input transistor N4 is respectively connected to the drain of the second reset tube P3 and the drain of the second load tube P4;

[0045] The second-stage differential-to-single-ended output circuit includes a third transistor N5, a third differential input transistor N6, a fourth differential input transistor N7, a fourth transistor P5, a fifth transistor P6, a sixth transistor N8, a seventh transistor N11, a third load transistor N9, a fourth load transistor N10, a fifth load transistor P8, a sixth load transistor P10, a third reset transistor P7 and a fourth reset transistor P9, wherein the gate of the third transistor N5 is connected to the gate of the eighth transistor N0, the source of the third transistor N5 is grounded, and the drain of the third transistor N5 is respectively connected to the source of the third differential input transistor N6 and the source of the fourth differential input transistor N7;

[0046] The drain of the third differential input transistor N6 is connected to the drain of the fifth load transistor P8, the drain of the fourth differential input transistor N7 is connected to the drain of the fourth load transistor N10, the gate of the third differential input transistor N6 is respectively connected to the drain of the third load transistor N9 and the drain of the sixth transistor N8, the source of the sixth transistor N8 is grounded, and the drain of the sixth transistor N8 is connected to the drain of the fourth transistor P5;

[0047] The drain of the fourth differential input transistor N7 is respectively connected to the drain of the fourth load transistor N10 and the drain of the fourth reset transistor P9, the gate of the fourth differential input transistor N7 is respectively connected to the drain of the fourth load transistor N10 and the drain of the seventh transistor N11, the source of the seventh transistor N11 is grounded, and the drain of the seventh transistor N11 is also connected to the drain of the fifth transistor P6;

[0048] The gate of the fifth load tube P8 is connected to the gate of the sixth load tube P10 and connected to the drain of the third reset tube P7;

[0049] The output buffer circuit is formed by three inverters connected in series, and the input end of the inverter is connected to the drain of the fourth differential input transistor N7;

[0050] The bias circuit includes a fifth reset tube P0, a first transistor N1 and an eighth transistor N0. A fourth resistor R0, a first resistor R1, a second resistor R2 and a third resistor R3 connected in series are connected between the drain of the fifth reset tube P0 and the drain of the eighth transistor N0. The source of the eighth transistor N0 is grounded, the drain of the first transistor N1 is connected to the drain of the eighth transistor N0, and the source of the first transistor N1 is grounded.

[0051] When the control terminal voltage Vcmp_en is at a high level, the comparator enters a normal working state. The second transistor N2 copies the current on the bias circuit. At this time, the differential amplifier receives two input voltages Vin_m and Vin_p. The end with a higher voltage gets more current, so the voltage Vom1 or Vop1 on its drain is smaller. These two voltages control the conduction state of the fourth transistor P5 and the fifth transistor P6. The end with a smaller voltage in Vom1 and Vop1 produces a larger current, which pulls up Vop2 or Vom2. At the same time, since the sixth transistor N8 and the seventh transistor N11 form a positive feedback, the voltage difference between Vop2 and Vom2 is amplified as a differential input for differential to single-ended conversion. The fifth load tube P8 and the sixth load tube P10 convert the differential signal into a single-ended signal as an output.

[0052] Working principle: The reinforcement method of the negative single-particle transient reinforcement circuit based on the comparator and the compensation tube includes the following steps:

[0053] A. Before the LDO enters the normal working state, the control signal Ven is at a low level, the comparator does not work, the output of the comparator is at a low level, the connecting tube P11 is turned on, the compensation tube N13 is turned off, the error amplifier discharges the gate of the power tube N12, Vg becomes high, and the LDO output voltage Vout becomes high;

[0054] B. When the LDO enters the normal working state, the control voltage Ven is high, and the comparator starts to work. At this time, the LDO output voltage Vout is greater than the reference voltage Vout_min formed by the resistor network, and the output of the comparator is low. The connecting tube P11 remains turned on, the compensation tube N13 remains turned off, and the LDO works stably.

[0055] C. When a negative single-particle transient pulse occurs, the output Vout of the LDO is less than the reference voltage Vout_min, the comparator output is high, the connecting tube P11 is disconnected, the compensation tube N13 is turned on, the capacitor C1 starts to maintain the gate voltage of the power tube N12, and the compensation tube N13 starts to slowly discharge the gate of the power tube N12 to compensate for the charge flowing out of the negative single-particle transient pulse;

[0056] D. With the charge compensation, the gate voltage Vg of the power tube N12 gradually increases, and the LDO output voltage Vout gradually increases. When the LDO output voltage Vout rises to a value greater than the reference voltage Vout_min formed by the resistor network, the negative single-particle transient pulse of the error amplifier EA has ended.

[0057] E. The output voltage of the comparator returns to a low level, the connecting tube P11 is turned on, the compensation tube N13 is disconnected, the gate of the power tube N12 is connected to the output end of the error amplifier, and the LDO returns to normal working state.

[0058] In summary, the reinforcement circuit of the present invention isolates the power tube and the error amplifier when a negative single-particle transient pulse arrives, and compensates for the charge flowing out of the negative single-particle transient pulse through the connecting tube, thereby reducing the influence of the negative single-particle transient pulse and playing a reinforcement role.

[0059] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A negative single event transient reinforcement circuit based on a comparator and a compensation tube, characterized in that: The negative single event transient reinforcement circuit includes a comparator, a connecting tube P11, a compensation tube N13, a capacitor C1, a seventh resistor R7 and an eighth resistor R8; The seventh resistor R7 and the eighth resistor R8 form a resistor network, and a reference voltage Vout_min is set between the seventh resistor R7 and the eighth resistor R8; The positive input terminal of the comparator is connected to the reference voltage Vout_min, the negative input terminal of the comparator is connected to the output voltage Vout, the control terminal is connected to the control voltage Ven, and the output terminal of the comparator is connected to the gates of the connecting tube P11 and the compensation tube N13; The source of the connecting tube P11 is respectively connected to the source of the compensation tube N13, one end of the capacitor C1, and the gate of the power tube N12, and the other end of the capacitor C1 is grounded; The drain of the connecting tube P11 is connected to the output end of the error amplifier, the source of the power tube N12 is connected to one end of the fifth resistor R5, the other end of the fifth resistor R5 is respectively connected to the negative input end of the error amplifier and one end of the sixth resistor R6, and the other end of the sixth resistor R6 is grounded; The positive input terminal of the error amplifier is connected to the Vref reference voltage terminal.

2. The negative single event transient reinforcement circuit based on a comparator and a compensation tube according to claim 1, characterized in that: The comparator is composed of a bias circuit, a first-stage differential amplifier circuit, a second-stage differential-to-single-ended output circuit and an output buffer circuit. The bias circuit is sequentially connected to the first-stage differential amplifier circuit, the second-stage differential-to-single-ended output circuit and the output buffer circuit.

3. The negative single event transient reinforcement circuit based on a comparator and a compensation tube according to claim 2, characterized in that: The first-stage differential amplifier circuit includes a second transistor N2, a first differential input transistor N3, a second differential input transistor N4, a first load tube P1, a second load tube P4, a first reset tube P2 and a second reset tube P3. The source of the second transistor N2 is grounded, and the gate is connected to the gate of the eighth transistor N0 in the bias circuit. The drain of the second transistor N2 is respectively connected to the source of the first differential input transistor N3 and the source of the second differential input transistor N4. The drain of the first differential input transistor N3 is respectively connected to the drain of the first load tube P1 and the drain of the first reset tube P2; the drain of the second differential input transistor N4 is respectively connected to the drain of the second reset tube P3 and the drain of the second load tube P4.

4. The negative single event transient reinforcement circuit based on a comparator and a compensation tube according to claim 2, characterized in that: The second-stage differential-to-single-ended output circuit includes a third transistor N5, a third differential input transistor N6, a fourth differential input transistor N7, a fourth transistor P5, a fifth transistor P6, a sixth transistor N8, a seventh transistor N11, a third load transistor N9, a fourth load transistor N10, a fifth load transistor P8, a sixth load transistor P10, a third reset transistor P7 and a fourth reset transistor P9, the gate of the third transistor N5 is connected to the gate of the eighth transistor N0, the source of the third transistor N5 is grounded, and the drain of the third transistor N5 is respectively connected to the source of the third differential input transistor N6 and the source of the fourth differential input transistor N7; The drain of the third differential input transistor N6 is connected to the drain of the fifth load transistor P8, the drain of the fourth differential input transistor N7 is connected to the drain of the fourth load transistor N10, the gate of the third differential input transistor N6 is respectively connected to the drain of the third load transistor N9 and the drain of the sixth transistor N8, the source of the sixth transistor N8 is grounded, and the drain of the sixth transistor N8 is connected to the drain of the fourth transistor P5; The drain of the fourth differential input transistor N7 is respectively connected to the drain of the fourth load transistor N10 and the drain of the fourth reset transistor P9, the gate of the fourth differential input transistor N7 is respectively connected to the drain of the fourth load transistor N10 and the drain of the seventh transistor N11, the source of the seventh transistor N11 is grounded, and the drain of the seventh transistor N11 is also connected to the drain of the fifth transistor P6; The gate of the fifth load tube P8 is connected to the gate of the sixth load tube P10 and to the drain of the third reset tube P7.

5. The negative single event transient reinforcement circuit based on a comparator and a compensation tube according to claim 2, characterized in that: The output buffer circuit is formed by three inverters connected in series, and the input end of the inverter is connected to the drain of the fourth differential input transistor N7.

6. The negative single event transient reinforcement circuit based on a comparator and a compensation tube according to claim 2, characterized in that: The bias circuit includes a fifth reset tube P0, a first transistor N1 and an eighth transistor N0. A fourth resistor R0, a first resistor R1, a second resistor R2 and a third resistor R3 connected in series are connected between the drain of the fifth reset tube P0 and the drain of the eighth transistor N0. The source of the eighth transistor N0 is grounded, the drain of the first transistor N1 is connected to the drain of the eighth transistor N0, and the source of the first transistor N1 is grounded.

7. A method for reinforcing a negative single event transient reinforcement circuit based on a comparator and a compensation tube according to claim 1, characterized in that: The reinforcement method includes the following steps: A. Before the LDO enters the normal working state, the control signal Ven is at a low level, the comparator does not work, the output of the comparator is at a low level, the connecting tube P11 is turned on, the compensation tube N13 is turned off, the error amplifier discharges the gate of the power tube N12, Vg becomes high, and the LDO output voltage Vout becomes high; B. When the LDO enters the normal working state, the control voltage Ven is high, and the comparator starts to work. At this time, the LDO output voltage Vout is greater than the reference voltage Vout_min formed by the resistor network, and the output of the comparator is low. The connecting tube P11 remains turned on, the compensation tube N13 remains turned off, and the LDO works stably. C. When a negative single-particle transient pulse occurs, the output Vout of the LDO is less than the reference voltage Vout_min, the comparator output is high, the connecting tube P11 is disconnected, the compensation tube N13 is turned on, the capacitor C1 starts to maintain the gate voltage of the power tube N12, and the compensation tube N13 starts to slowly discharge the gate of the power tube N12 to compensate for the charge flowing out of the negative single-particle transient pulse; D. With the charge compensation, the gate voltage Vg of the power tube N12 gradually increases, and the LDO output voltage Vout gradually increases. When the LDO output voltage Vout rises to a value greater than the reference voltage Vout_min formed by the resistor network, the negative single-particle transient pulse of the error amplifier EA has ended. E. The output voltage of the comparator returns to a low level, the connecting tube P11 is turned on, the compensation tube N13 is disconnected, the gate of the power tube N12 is connected to the output end of the error amplifier, and the LDO returns to normal working state.

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