Adaptive Level Circuit, Chip and Electronic Device

Abstract

The present application provides an adaptive level circuit, a chip, and an electronic device. Among them, the adaptive level circuit is applied to a first chip, and the first chip includes at least two power supply terminals; the adaptive level circuit includes a level matching unit and at least two level control sub-units; the level matching unit obtains a first level signal of a second chip communicating with the first chip through a first power supply terminal among the at least two power supply terminals, compares the first level signal with at least one second level signal of at least one second power supply terminal, and generates a first control signal, where the second power supply terminal is a power supply terminal other than the first power supply terminal among the at least two power supply terminals; a target selection signal is generated according to the first control signal, and the target selection signal is used to determine a target level control sub-unit from among the at least two level control sub-units; the target level control sub-unit adjusts its own level to the same first level as the second chip according to the target selection signal.

Description

Technical Field

[0001] This application belongs to the field of communication technologies, and particularly relates to an adaptive level circuit, a chip, and an electronic device. Background Art

[0002] Currently, the power supply levels designed by each IC manufacturer are inconsistent, and in actual applications, it is not possible to simply connect them directly with wires, otherwise serious problems such as chip burnout, leakage, and data errors will occur.

[0003] The existing solution is to design an external circuit to connect different chips so that different chips can achieve level conversion through this external circuit, which increases the size of the circuit board. Summary of the Invention

[0004] This application provides an adaptive level circuit, a chip, and an electronic device, aiming to add a level adaptation function to the chip.

[0005] In a first aspect, this application provides an adaptive level circuit applied to a first chip, where the first chip includes at least two power supply terminals; the adaptive level circuit includes a level matching unit and at least two level control sub-units;

[0006] The level matching unit obtains a first level signal of a second chip communicating with the first chip through a first power supply terminal among the at least two power supply terminals, compares the first level signal with at least one second level signal of at least one second power supply terminal, and generates a first control signal, where the second power supply terminal is a power supply terminal other than the first power supply terminal among the at least two power supply terminals; a target selection signal is generated according to the first control signal, and the target selection signal is used to determine a target level control sub-unit from the at least two level control sub-units;

[0007] The target level control sub-unit adjusts its own level to the same first level as the second chip according to the target selection signal.

[0008] In combination with the first solution, in one embodiment, the level matching unit includes a comparison subunit and at least two signal generation subunits; the comparison subunit includes at least two signal interfaces, and the at least two signal interfaces are connected to the at least two power supply terminals, and each signal interface is used to obtain a level signal; the comparison subunit obtains the first level signal from the first power supply terminal through the first signal interface among the at least two signal interfaces, and compares the first level signal with the at least one second level signal to generate the first control signal; the at least two signal generation subunits are respectively matched with the first control signal, and the target signal generation subunit that is successfully matched among the at least two signal generation subunits generates the target selection signal according to the first control signal.

[0009] In combination with the first solution, in one embodiment, the comparison subunit includes at least one comparator, and the at least one comparator obtains a first level signal and at least one second level signal; the at least one comparator is used to perform at least one - level comparison on the first level signal and the at least one second level signal to generate the first control signal.

[0010] In combination with the first solution, in one embodiment, the at least two signal generation subunits include a first signal generation subunit and a second signal generation subunit. The first signal generation subunit and the second signal generation subunit are respectively matched with the first control signal. When the voltage of the first control signal is the same as the conduction voltage of the first signal generation subunit, the first signal generation subunit generates the target selection signal according to the first control signal; when the voltage of the first control signal is the same as the conduction voltage of the second signal generation subunit, the second signal generation subunit generates the target selection signal according to the first control signal.

[0011] In combination with the first solution, in one embodiment, the first signal generation subunit includes a first switching tube, a second switching tube, a first resistor, a second resistor, a third resistor, and a first capacitor: the controlled end of the first switching tube is connected to one end of the first resistor and the output end of the comparison subunit to access the first control signal; the input end of the first switching tube is connected to one end of the second resistor, one end of the third resistor, and one end of the first capacitor. The other end of the second resistor, the other end of the first capacitor, and the input end of the second switching tube are all connected to the first power supply. The other end of the third resistor is connected to the controlled end of the second switching tube. The output end of the second switching tube is connected to the communication bus, and the other end of the first resistor and the output end of the first switching tube are both grounded.

[0012] In combination with the first solution, in one embodiment, the second signal generation subunit includes a third switching tube, a fourth resistor, a fifth resistor, and a second capacitor; the controlled end of the first switching tube, one end of the fourth resistor, one end of the fifth resistor, and one end of the second capacitor are all connected to the output end of the comparison subunit to access the first control signal; the other end of the fourth resistor, the other end of the second capacitor, and the input end of the third switching tube are all connected to a second power supply, the other end of the fifth resistor is connected to the controlled end of the third switching tube, and the output end of the third switching tube is connected to the communication bus.

[0013] In combination with the first solution, in one embodiment, the voltages between the at least two level control subunits are all different; the at least two level control subunits are respectively connected to the at least two signal generation subunits one by one to obtain a target selection signal from the corresponding signal generation subunit; when the target level control subunit among the at least two level control subunits receives the target selection signal, the voltage of the first chip is adjusted to the same first voltage as that of the second chip according to the target selection signal.

[0014] In combination with the first solution, in one embodiment, the target selection signal includes a first selection signal and a second selection signal; the at least two level control subunits include a first level control subunit and a second level control subunit; the first level control subunit includes a fourth switching tube, a fifth switching tube, a sixth resistor, and a seventh resistor; the second level control subunit includes an eighth resistor and a ninth resistor; the data bus includes a first segment data bus and a second segment data bus, and the clock bus includes a first segment clock bus and a second segment clock bus; the first ends of the sixth resistor and the seventh resistor are both connected to the first selection signal, and the other end of the sixth resistor is connected to the controlled end of the fourth switching tube; the input end and the output end of the fourth switching tube are respectively connected to the first segment data bus and the second segment data bus; the other end of the seventh resistor is connected to the controlled end of the fifth switching tube; the input end and the output end of the fifth switching tube are respectively connected to the first segment clock bus and the second segment clock bus; the first ends of the eighth resistor and the ninth resistor are both connected to the first selection signal, the other end of the eighth resistor is connected to the first segment data bus, and the other end of the ninth resistor is connected to the first segment clock bus.

[0015] In a second aspect, the present application provides a chip including the adaptive voltage circuit as described in the first aspect.

[0016] In a third aspect, the present application provides an electronic device including the adaptive voltage circuit as described in the first aspect, or including the chip as described in the second aspect.

[0017] It can be seen that in the present application, the adaptive level circuit is applied to the first chip, and the first chip includes at least two power supply terminals; the adaptive level circuit includes a level matching unit and at least two level control sub-units; the level matching unit obtains the first level signal of the second chip communicating with the first chip through the first power supply terminal among the at least two power supply terminals, compares the first level signal with at least one second level signal of at least one second power supply terminal, and generates a first control signal, where the second power supply terminal is the power supply terminal other than the first power supply terminal among the at least two power supply terminals; a target selection signal is generated according to the first control signal, and the target selection signal is used to determine a target level control sub-unit from the at least two level control sub-units; the target level control sub-unit adjusts its own level to the same first level as the second chip according to the target selection signal. In this way, the level adaptive function can be provided for the chip, enabling the chip to automatically adjust its own level to be the same as that of other chips in communication, and there is no need to design an additional external circuit for assistance, while realizing the level adaptive function, the size of the circuit board is reduced. Description of the Drawings

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0019] Figure 1 It is a connection schematic diagram when the first chip and the second chip communicate provided by the embodiment of the present application;

[0020] Figure 2 It is the first structural schematic diagram of the adaptive level circuit provided by the embodiment of the present application;

[0021] Figure 3 It is the second structural schematic diagram of the adaptive level circuit provided by the embodiment of the present application;

[0022] Figure 4 It is the first circuit diagram of the comparison sub-unit provided by the embodiment of the present application;

[0023] Figure 5 It is the second circuit diagram of the comparison sub-unit provided by the embodiment of the present application;

[0024] Figure 6 It is the third circuit diagram of the comparison sub-unit provided by the embodiment of the present application;

[0025] Figure 7 It is the circuit diagram of the first signal generation sub-unit provided by the embodiment of the present application;

[0026] Figure 8 It is the circuit diagram of the second signal generation sub-unit provided by the embodiment of the present application;

[0027] Figure 9 It is the circuit diagram of the first level control sub-unit and the second level control sub-unit provided by the embodiment of the present application;

[0028] Figure 10 It is the structural schematic diagram of the electronic device provided by the embodiment of the present application. Detailed implementation manners

[0029] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present application.

[0030] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, systems, products or devices.

[0031] Referring to "embodiment" in this article means that a specific feature, structure or characteristic described in combination with the embodiment can be included in at least one embodiment of the present application. The phrase appears in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0032] Currently, the power supply levels are inconsistent when each IC manufacturer designs, and in actual application, it cannot be simply directly connected by wires, otherwise serious problems such as burning out the chip, leakage, and data error will occur. The existing solution is to design an external circuit to connect between different chips so that different chips can achieve level conversion through the external circuit, which increases the size of the circuit board.

[0033] To solve the above problems, an embodiment of the present application provides an adaptive level circuit. The adaptive level circuit can be applied to the scenario of inter-chip level adaptive matching. The level matching unit can obtain the first level signal of the second chip communicating with the first chip through the first power supply terminal among at least two power supply terminals, compare the first level signal with at least one second level signal of at least one second power supply terminal, and generate a first control signal, where the second power supply terminal is the power supply terminal other than the first power supply terminal among at least two power supply terminals; generate a target selection signal according to the first control signal, and the target selection signal is used to determine a target level control subunit from at least two level control subunits; the target level control subunit adjusts its own level to the same first level as the second chip according to the target selection signal. In this way, the level adaptive function can be provided for the chip, enabling the chip to automatically adjust its own level to the same as that of other chips in communication, and there is no need to design an additional external circuit for assistance, while realizing the level adaptive function, the circuit board size is reduced. This solution can be applied to a variety of scenarios, including but not limited to the above-mentioned application scenarios.

[0034] The following introduces the system architecture involved in the embodiments of the present application.

[0035] IIC (Inter-Integrated Circuit, also known as I2C or I²C) is a simple and flexible serial communication protocol used to connect microcontrollers and external devices, such as sensors, memories, displays, etc.

[0036] Basic principle

[0037] Two-wire system: I2C uses two wires for communication: serial data line (SDA) and serial clock line (SCL). The data on the SDA line is synchronously transmitted under the clock signal of the SCL line.

[0038] Master-slave structure: In I2C communication, devices are divided into master devices (usually microcontrollers) and slave devices (such as sensors or memories). The master device is responsible for initiating communication and controlling the timing of communication, while the slave device responds to the instructions of the master device.

[0039] Address addressing: Each I2C device has a unique 7-bit or 10-bit address, and the master device selects the communication object by sending the address of the target device.

[0040] Communication process

[0041] Start condition (Start): The master device sends a start signal, that is, the SDA line changes from high level to low level, while the SCL line remains at high level.

[0042] Transmission Address and Read / Write Bit: The master device transmits the address of the target device and specifies whether to read data or write data.

[0043] Address Acknowledgment (ACK): After receiving the address, the slave device sends an acknowledgment signal (ACK) indicating that it is ready to communicate with the master device.

[0044] Data Transmission: The master or slave device sends or receives data bits on the edge of the SCL clock signal.

[0045] Stop Condition: The master device sends a stop signal, i.e., the SDA line changes from low level to high level while the SCL line remains at high level.

[0046] Advantages

[0047] Full-Duplex Communication: I2C supports data transmission from the master device to the slave device and vice versa, enabling full-duplex communication.

[0048] Multiple Device Connection: The I2C bus supports multiple devices to be connected to the same bus, and the communication target can be selected by the device address.

[0049] Application Areas

[0050] Sensor Interface: Many sensors (such as temperature sensors, humidity sensors, acceleration sensors, etc.) use the I2C interface to communicate with microcontrollers.

[0051] The following details the specific method.

[0052] Please refer to Figures 1 to 3, the present application also provides an adaptive level circuit, which is applied to the first chip IC1. The first chip IC1 includes at least two power supply terminals; the adaptive level circuit includes a level matching unit 210 and at least two level control sub-units 220; the at least two power supply terminals include a first power supply terminal VCC1 and at least one second power supply terminal VCC2. The first power supply terminal VCC1 and the at least one second power supply terminal VCC2 are respectively connected to the level matching unit 210, and the output terminal of the level matching unit 210 is respectively connected to the at least two level control sub-units 220; the level matching unit 210 obtains a first level signal VCC_01 of the second chip IC2 for communicating with the first chip IC1 through the first power supply terminal VCC1 among the at least two power supply terminals, compares the first level signal VCC_01 with at least one second level signal VCC_02 of at least one second power supply terminal VCC2, and generates a first control signal CTR1, wherein the second power supply terminal VCC2 is a power supply terminal other than the first power supply terminal VCC1 among the at least two power supply terminals; a target selection signal is generated according to the first control signal CTR1, and the target selection signal is used to determine a target level control sub-unit from the at least two level control sub-units; the target level control sub-unit adjusts its own level to the same first level as the second chip IC2 according to the target selection signal.

[0053] In a specific implementation, the adaptive level circuit is integrated in the first chip IC1. When the first chip IC1 communicates with the second chip IC2, the first power supply terminal VCC1 among the at least two power supply terminals on the first chip IC1 with the same power supply level as the second chip IC2 will obtain the first level signal VCC_01 of the second chip IC2 and then transmit it to the level matching unit 210.

[0054] If no other chips are connected, then at least one second power supply terminal VCC2 other than the first power supply terminal VCC1 among the at least two power supply terminals is floating, that is, the second level signal VCC_02 is 0; the level matching unit 210 compares the first level signal VCC_01 with the 0 level, and then outputs the first control signal CTR1 that is the same as the first level signal VCC_01.

[0055] If the second power supply terminal VCC2 is also connected to other chips (such as the third chip), the level signal of the second power supply terminal VCC2 connected to other chips is obtained, and then the second level signal VCC_02 is greater than 0; the level matching unit 210 compares the first level signal VCC_01 with the second level signal VCC_02; if the first level signal VCC_01 is greater than the second level signal VCC_02, the first control signal CTR1 identical to the first level signal VCC_01 is output; if the first level signal VCC_01 is less than the second level signal VCC_02, the first control signal CTR1 identical to the second level signal VCC_02 is output.

[0056] It can be understood that there can be multiple second power supply terminals VCC2 to obtain multiple second level signals VCC_02. The first level signal VCC_01 is compared with multiple second level signals VCC_02 multiple times, and finally the one with the highest level among the first level signal VCC_01 and the multiple second level signals VCC_02 is determined for output to obtain the first control signal CTR1. Essentially, the first level signal is the power supply voltage of the second chip, and the second level signal is essentially the power supply voltage of the third chip and other chips connected to the communication bus; therefore, it can be understood that the first level signal and the second level signal can be 1.8V (such as Figure 1 the VCC_1V8 shown) or 3.3V (such as Figure 1 the VCC_3V3 described), or voltage values Figure 1 shown in

[0057] is just one of them and is not limited here.

[0058] It can be seen that in this embodiment, the level matching unit 210 obtains the first level signal VCC_01 of the second chip IC2 communicating with the first chip IC1 through the first power supply terminal VCC1 among at least two power supply terminals, compares the first level signal VCC_01 with at least one second level signal VCC_02 of at least one second power supply terminal VCC2, and generates a first control signal CTR1, where the second power supply terminal VCC2 is the power supply terminal other than the first power supply terminal VCC1 among at least two power supply terminals; a target selection signal is generated according to the first control signal CTR1, and the target selection signal is used to determine a target level control sub-unit from at least two level control sub-units 220; the target level control sub-unit adjusts its own level to the same first level as the second chip IC2 according to the target selection signal. In this way, the level adaptive function can be provided for the chip, enabling the chip to automatically adjust its own level to be the same as that of other chips in communication, and there is no need to design an additional external circuit for assistance, while realizing the level adaptive function, the circuit board size is reduced.

[0059] In one example, please continue to refer to Figure 3 , the level matching unit 210 includes a comparison sub-unit 211 and at least two signal generation sub-units 212; the comparison sub-unit 211 includes at least two signal interfaces; the at least two signal interfaces include a first signal interface P1 and at least one second signal interface P2, the first power supply terminal VCC1 is connected to the first signal interface P1, the at least one second power supply terminal VCC2 is connected to the at least one second signal interface P2 in one-to-one correspondence, the output terminal of the comparison sub-unit is connected to the control terminals of the at least two signal generation sub-units, the at least two signal generation sub-units are connected to the at least two level control sub-units in one-to-one correspondence, and the at least two signal generation sub-units are connected in series on the communication bus.

[0060] The comparison sub-unit 211 obtains the first level signal VCC_01 from the first power supply terminal VCC1 through the first signal interface P1 among the at least two signal interfaces, and compares the first level signal VCC_01 with the at least one second level signal VCC_02 to generate the first control signal CTR1; the at least two signal generation sub-units 212 are respectively matched with the first control signal CTR1, and the target signal generation sub-unit that is successfully matched among the at least two signal generation sub-units 212 generates the target selection signal according to the first control signal CTR1.

[0061] In a specific implementation, at least two signal interfaces of the comparison subunit 211 are connected in one-to-one correspondence with at least two power supply terminals of the first chip IC1. The first signal interface P1 among the at least two signal interfaces obtains the first level signal VCC_01 of the first power supply terminal VCC1, and the other signal interfaces (which can be denoted as the second signal interface P2) obtain the second level signal VCC_02 through the second power supply terminal VCC2. Then, the comparison subunit 211 compares the first level signal VCC_01 with the second level signal VCC_02 to generate the first control signal CTR1, and at the same time outputs the first control signal CTR1 to at least two signal generation subunits 212 for matching with the first control signal CTR1 by the at least two signal generation subunits 212. If the conduction voltage of a certain signal generation subunit 212 is the same as the first control signal CTR1, it is determined that the signal generation subunit 212 is the target signal generation subunit. The target signal generation subunit is turned on under the control of the first control signal CTR1 to generate the target selection signal and outputs it to the corresponding level control subunit 220.

[0062] Specifically, please refer to Figures 4 - 6 , the comparison subunit includes at least one comparator, and the at least one comparator obtains the first level signal VCC_01 and at least one second level signal VCC_02; the at least one comparator is used to perform at least one-level comparison on the first level signal VCC_01 and the at least one second level signal VCC_02 to generate the first control signal CTR1.

[0063] Optionally, please refer to Figure 4 , when the comparison subunit 211 includes one comparator (i.e., the first comparator U1A), the comparator respectively obtains the first level signal VCC_01 and the second level signal VCC_02 for comparison to generate the first control signal CTR1.

[0064] Please refer to Figure 5 and Figure 6 , when the comparison subunit 211 includes multiple comparators, the multiple comparators are combined to form a multi-stage comparator, and the multi-stage comparator can compare the first level signal VCC_01 with multiple second level signals VCC_02 to obtain the first control signal CTR1.

[0065] Taking two comparators and three comparators as examples to illustrate the case of multiple comparators.

[0066] Please refer to Figure 5When the comparison subunit 211 includes two comparators, which are respectively denoted as the first comparator U1A and the second comparator U2A, the first input terminal of the first comparator U1A is the first signal interface P1 for accessing the first level signal VCC_01; the output terminal of the first comparator U1A is connected to the first input terminal of the second comparator U2A; the second input terminal of the first comparator U1A and the second input terminals of the second comparator U2A are both the second signal interface P2, to which the corresponding second level signal VCC_02 can be accessed (the second level signal VCC_02 can be floating at 0 or be the level signal of other chips except the first chip IC1 and the second chip IC2), and the output terminal of the second comparator U2A is respectively connected to at least two signal generation subunits 212.

[0067] Specifically, first, the first comparator U1A compares the first level signal VCC_01 with the second level signal VCC_02 accessed by the second input terminal of the first comparator U1A, outputs the maximum level signal among them as the first signal to be compared OUT1, and outputs the first signal to be compared OUT1 to the first input terminal of the second comparator U2A; then, the second comparator U2A compares the accessed second level signal VCC_02 with the first signal to be compared OUT1, obtains the maximum level signal among them as the first control signal CTR1, and outputs the first control signal CTR1 to at least two signal generation subunits 212 through the second comparator U2A.

[0068] Please refer to Figure 6 When the comparison subunit 211 includes three comparators, which are respectively denoted as the first comparator U1A, the second comparator U2A, and the third comparator U3A, the first input terminal of the first comparator U1A is the first signal interface P1 for accessing the first level signal VCC_01; the second input terminal of the first comparator U1A, the first input terminal and the second input terminal of the second comparator U2A are all the second signal interface P2, to which the corresponding second level signal VCC_02 can be accessed (the second level signal VCC_02 can be floating at 0 or be the level signal of other chips except the first chip IC1 and the second chip IC2); the output terminal of the first comparator U1A is connected to the first input terminal of the third comparator U3A, the output terminal of the second comparator U2A is connected to the second input terminal of the third comparator U3A, and the output terminal of the third comparator U3A is respectively connected to at least two signal generation subunits 212.

[0069] Specifically, first, the first comparator U1A compares the first level signal VCC_01 with the second level signal VCC_02 connected to the second input terminal of the first comparator U1A, outputs the maximum level signal among them as the first signal to be compared OUT1, and outputs the first signal to be compared OUT1 to the first input terminal of the third comparator U3A; then, the second comparator U2A compares the two second level signals VCC_02 connected thereto, outputs the maximum level signal among them as the second signal to be compared OUT2, and outputs the second signal to be compared OUT2 to the second input terminal of the third comparator U3A; finally, the third comparator U3A compares the first signal to be compared OUT1 and the second signal to be compared OUT2, obtains the maximum level signal among them as the first control signal CTR1, and outputs the first control signal CTR1 to at least two signal generation subunits 212 through the third comparator U3A.

[0070] It can be understood that at least two signal generation subunits 212 need to be provided, corresponding to at least two different levels respectively, so that it is necessary to perform level matching and level adjustment. The working principle of at least two signal generation subunits 212 in the present application will be described below by taking an example of two signal generation subunits 212.

[0071] In a possible embodiment, please continue to refer to Figure 3 , at least two signal generation subunits 212 include a first signal generation subunit and a second signal generation subunit. The first signal generation subunit and the second signal generation subunit are respectively matched with the first control signal CTR1. When the voltage of the first control signal CTR1 is the same as the conduction voltage of the first signal generation subunit, the first signal generation subunit generates the target selection signal according to the first control signal CTR1; when the voltage of the first control signal CTR1 is the same as the conduction voltage of the second signal generation subunit, the second signal generation subunit generates the target selection signal according to the first control signal CTR1.

[0072] Specifically, please refer to Figure 7, the first signal generation subunit includes a first switching transistor Q1, a second switching transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3, and a first capacitor C1: the controlled terminal of the first switching transistor Q1 is connected to one end of the first resistor R1 and the output terminal of the comparison subunit 211 to access the first control signal CTR1; the input terminal of the first switching transistor Q1 is connected to one end of the second resistor R2, one end of the third resistor R3, and one end of the first capacitor C1, the other end of the second resistor R2, the other end of the first capacitor C1, and the input terminal of the second switching transistor Q2 are all connected to the first power supply, the other end of the third resistor R3 is connected to the controlled terminal of the second switching transistor Q2, the output terminal of the second switching transistor Q2 is connected to the communication bus, and the other end of the first resistor R1 and the output terminal of the first switching transistor Q1 are both grounded. Please refer to Figure 8 , the second signal generation subunit includes a third switching transistor Q3, a fourth resistor R4, a fifth resistor R5, and a second capacitor C2; one end of the fourth resistor R4, one end of the fifth resistor R5, and one end of the second capacitor C2 are all connected to the output terminal of the comparison subunit 211 to access the first control signal CTR1; the other end of the fourth resistor R4, the other end of the second capacitor C2, and the input terminal of the third switching transistor Q3 are all connected to the second power supply; the other end of the fifth resistor R5 is connected to the controlled terminal of the third switching transistor Q3, and the output terminal of the third switching transistor Q3 is connected to the communication bus.

[0073] In a specific implementation, the conduction voltages of the first switching transistor Q1 and the third switching transistor Q3 are different. When the comparison subunit 211 outputs the first control signal CTR1, the controlled terminals of the first switching transistor Q1 and the third switching transistor Q3 receive the first control signal CTR1 simultaneously; at this time, if the voltage of the first control signal CTR1 satisfies the conduction voltage of the first switching transistor Q1, the first switching transistor Q1 will be driven to conduct, and then the second switching transistor Q2 will be driven to conduct, and the first voltage of the first power supply will be output as the target selection signal to the corresponding level control subunit 220. If the voltage of the first control signal CTR1 satisfies the conduction voltage of the third switching transistor Q3, the third switching transistor Q3 will be driven to conduct, and then the second voltage of the second power supply will be output as the target selection signal to the corresponding level control subunit 220. Among them, the first voltage can be 1.8V, and the second voltage can be 3.3V. It can be understood that the voltage values of the first voltage and the second voltage can be selected according to the actual situation, and only an explanatory description is made here without specific limitations.

[0074] It can be understood that the number of signal generation subunits 212 can also exceed two, and can be set according to the number of voltages to be adapted. For example, if three levels of 1.8V, 3.3V, and 5V need to be adapted, three signal generation subunits 212 can be set to be adapted to the three levels. Similarly, if more levels need to be adapted, more signal generation subunits 212 can be set, which is not limited herein.

[0075] It can be seen that in this embodiment, the levels of the second chip IC2 can be automatically matched by the signal generation subunit 212, which improves the intelligence of the signal generation subunit 212 and at the same time improves the reliability of the adaptive level circuit.

[0076] The technical solution of the present application will be described below by taking the IIC bus as an example. It can be understood that the solution of the present application can also be applied to other bus or chip communication scenarios. IIC is only used to explain this solution and is not limited herein.

[0077] In a possible embodiment, please refer to Figure 3 and Figure 9 , the levels between the at least two level control subunits 220 are all different; the at least two level control subunits 220 are connected to the at least two signal generation subunits 212 in one-to-one correspondence to obtain a target selection signal from the corresponding signal generation subunit 212; when the target level control subunit among the at least two level control subunits 220 receives the target selection signal, the level of the first chip IC1 is adjusted to the same first level as the second chip IC2 according to the target selection signal.

[0078] Specifically, the target selection signal includes a first selection signal OUT3 and a second selection signal OUT4; the at least two level control sub-units 220 include a first level control sub-unit 221 and a second level control sub-unit 222; the first level control sub-unit 221 includes a fourth switching transistor Q4, a fifth switching transistor Q5, a sixth resistor R6, and a seventh resistor R7; the second level control sub-unit 222 includes an eighth resistor R8 and a ninth resistor R9; the data bus includes a first-segment data bus IC1_SDA and a second-segment data bus IC2_SDA, and the clock bus includes a first-segment clock bus IC1_SCL and a second-segment clock bus IC2_SCL; the first ends of the sixth resistor R6 and the seventh resistor R7 are both connected to the first selection signal OUT3, and the other end of the sixth resistor R6 is connected to the controlled end of the fourth switching transistor Q4; the input end and the output end of the fourth switching transistor Q4 are respectively connected to the first-segment data bus IC1_SDA and the second-segment data bus IC2_SDA; the other end of the seventh resistor R7 is connected to the controlled end of the fifth switching transistor Q5; the input end and the output end of the fifth switching transistor Q5 are respectively connected to the first-segment clock bus IC1_SCL and the second-segment clock bus IC2_SCL; one end of the eighth resistor R8 and one end of the ninth resistor R9 are both connected to the second selection signal OUT4, the other end of the eighth resistor R8 is connected to the first-segment data bus IC1_SDA, and the other end of the ninth resistor R9 is connected to the first-segment clock bus IC1_SCL.

[0079] In specific implementation, the number of the level control sub-units 220 is the same as the number of the signal generation sub-units 212, that is, the at least two level control sub-units 220 are connected to the at least two signal generation sub-units 212 in a one-to-one correspondence. Taking two level control sub-units 220 as an example, the first level control sub-unit 221 is connected to the first signal generation sub-unit, and the second level control sub-unit 222 is connected to the second signal generation sub-unit. When the first signal generation sub-unit generates a target selection signal, the first level control sub-unit 221 obtains the target selection signal and turns on the fourth switching transistor Q4 according to the target selection signal to pull up the data bus and the clock bus to a first voltage, so that the communication bus between the first chip IC1 and the second chip IC2 is all at the first level. When the second signal generation sub-unit generates a target selection signal, the second level control sub-unit 222 obtains the target selection signal and turns on the fifth switching transistor Q5 according to the target selection signal to pull up the data bus and the clock bus to a second voltage, so that the communication bus between the first chip IC1 and the second chip IC2 is all at the first level.

[0080] It can be seen that in this embodiment, based on the control of the target selection signal, the level of the first chip IC1 can be adjusted to the first level of the second chip IC2 communicating with it, and at least two level control sub-units 220 respectively correspond to different levels, improving the isolation of level adjustment.

[0081] In a possible embodiment, the level matching unit 210 may be a data processing unit inside the first chip IC1. This data processing unit obtains the first level signal VCC_01 of the second chip IC2 communicating with the first chip IC1 through the first power supply terminal VCC1 among the at least two power supply terminals, compares the first level signal VCC_01 with at least one second level signal VCC_02 of at least one second power supply terminal VCC2, and generates a first control signal CTR1; generates the target selection signal according to the first control signal CTR1, and the target selection signal is used to determine a target level control sub-unit from the at least two level control sub-units 220; the target level control sub-unit adjusts its own level to the same first level as the second chip IC2 according to the target selection signal.

[0082] Furthermore, when the level matching unit is the data processing unit, during the communication process, after the level of the first chip IC1 is adjusted, the first level is monitored. Continuously collect the first level to obtain a set of sampling signals to form a first sampling signal set, calculate the autocorrelation function based on this first sampling signal set to obtain multiple similarity values. For two adjacent similarity values, if the currently calculated similarity value is the same as the previously calculated similarity value, it is determined that the first chip IC1 is still communicating with the second chip IC2; if the autocorrelation function value becomes smaller, it is determined that the level has changed.

[0083] In order to avoid false triggering of the shutdown mechanism of the data processing unit for the signal generation sub-unit 212 due to level fluctuations, the multiple calculated similarity values are statistically analyzed to determine the proportion of the similarity values equal to the first similarity value among the multiple similarity values. After comparing this proportion with a preset value, it is determined whether to trigger the shutdown mechanism to improve the accuracy of triggering the shutdown mechanism. If the proportion is less than the preset value, the shutdown mechanism is triggered, the target selection signal is stopped from being output to the target level control sub-unit, a new first level signal VCC_01 is re-obtained for corresponding level matching processing to obtain a new target selection signal, and then the new target selection signal is output to the target level control sub-unit. At the same time, the monitoring of the first level is entered again, and this is used as an example for cycling. If the proportion is greater than or equal to the preset value, the sampling of the next cycle is continued to calculate a new proportion to determine whether the shutdown mechanism needs to be triggered in the next cycle.

[0084] In addition, the level matching unit may further include a comparison subunit, at least two signal generation subunits 212, and the data processing unit. The data processing unit is respectively connected to at least two signal generation subunits 212 to perform switching control on at least two signal generation subunits 212. At the same time, the data processing unit is also connected to the communication bus or the first signal interface P1 of the comparison subunit to detect the first level. Specifically, during the communication process, after the level adjustment of the first chip IC1 is completed, the data processing unit obtains and monitors the first level. The data processing unit collects the first level to obtain a first sampling signal set, calculates the autocorrelation function based on the first sampling signal set to obtain multiple similarity values, determines the proportion of the similarity values equal to the first similarity value among the multiple similarity values in the multiple similarity values, where the first similarity value is the first calculated similarity value among the multiple similarity values. If the proportion is greater than a preset value, a turn-off signal is sent to the target signal generation subunit to control the target signal generation subunit to turn off.

[0085] In a specific implementation, the first level is continuously collected to obtain a set of sampling signals to form a first sampling signal set, and the autocorrelation function is calculated based on the first sampling signal set to obtain multiple similarity values. For two adjacent similarity values, if the currently calculated similarity value is the same as the previously calculated similarity value, it is determined that the first chip IC1 is still communicating with the second chip IC2. If the autocorrelation function value becomes smaller, it is determined that the level has changed. To avoid false triggering of the turn-off mechanism of the data processing unit for the signal generation subunit 212 due to level fluctuations, the multiple calculated similarity values are statistically analyzed to determine the proportion of the similarity values equal to the first similarity value among the multiple similarity values. After comparing this proportion with the preset value, it is determined whether to trigger the turn-off mechanism to improve the accuracy of triggering the turn-off mechanism. If the proportion is less than the preset value, the turn-off mechanism is triggered, the target selection signal is no longer output to the target level control subunit, a new first level signal VCC_01 is obtained for corresponding level matching processing to obtain a new target selection signal, the new target selection signal is output to the target level control subunit, and at the same time, the monitoring of the first level is resumed, and this process is cycled as an example. If the proportion is greater than or equal to the preset value, the sampling of the next cycle is continued to calculate a new proportion to determine whether the turn-off mechanism needs to be triggered in the next cycle.

[0086] Specifically, the calculation process of the similarity value is as follows:

[0087] For a set of collected sampling signals , the autocorrelation function is defined as:

[0088] , where t is the sampling interval duration and T is the current moment;

[0089] Integrate the initial sampling signal in a set of sampled signals collected and the signal at the next moment to obtain a similarity value; then continue to set = , and then integrate and the signal at the next moment to obtain the next similarity value, and so on until each sampled signal in the set of sampled signals is calculated. Calculate the proportion of equal autocorrelation function values among the multiple autocorrelation function values obtained. If the proportion is greater than the preset value, it is determined that the level has changed; if the proportion is less than or equal to the preset value, it is determined that the level has not changed.

[0090] It can be seen that in this embodiment, the data processing unit samples the first level to obtain a sampled value, calculates the autocorrelation function of two sampled values in adjacent power supply cycles, and determines whether the first level has changed according to the calculated autocorrelation function, thereby avoiding repeated comparison of levels and calculation of target selection signals when there is no change, and reducing the calculation amount of the data processing unit.

[0091] This application also provides a chip, including the above-mentioned adaptive level circuit. Specifically, the chip in this embodiment can be the above-mentioned first chip. The first chip can be the main control chip of the main device, or the slave control chip in the slave device, or a communication chip for communication, which is not limited herein. When the first chip is the main control chip, the second chip and other chips connected are all slave control chips; when the first chip is the slave control chip, the second chip and other chips connected include the main control chip and the slave control chip.

[0092] When the adaptive level circuit is applied to the main control chip, the level matching unit obtains at least one first level signal of at least one slave control chip and generates a first selection signal according to the at least one first level signal; the level control unit adjusts its own level to the same first level as the target chip according to the first selection signal, and the target chip is one of the at least one slave chips;

[0093] When the adaptive level circuit is applied to the slave control chip, the level matching unit obtains the second level signal of the main control chip and generates a second selection signal according to the second level signal; the level control unit adjusts its own level to the same second level as the main chip or the slave chip according to the second selection signal.

[0094] It can be seen that in this embodiment, the level adaptive function can be provided for the chip, enabling the chip to automatically adjust its own level to be the same as that of other chips in communication, and there is no need to design an additional external circuit for assistance, thus reducing the circuit board size while implementing the level adaptive function.

[0095] This application also provides an electronic device, which includes the above-mentioned adaptive level circuit or includes the above-mentioned chip.

[0096] As Figure 10 shown, the electronic device 10 includes at least one processor 11; a display screen 12; and a memory 13, and may also include a communication interface 15 and a bus 14. Among them, the processor 11, the display screen 12, the memory 13, and the communication interface 15 can communicate with each other through the bus 14. The display screen 12 is set to display a user guidance interface preset in the initial setting mode. The communication interface 15 can transmit information. The processor 11 can call the logical instructions in the memory 13 to execute the method in the above-mentioned embodiment. It can be understood that the processor can be the above-mentioned first chip IC1.

[0097] Optionally, the electronic device 10 can be a mobile electronic device, or an electronic device or other devices, and there is no unique limitation here.

[0098] In addition, when the above-mentioned logical instructions in the memory 13 are implemented in the form of a software functional unit and sold or used as an independent product, they can be stored in a computer-readable storage medium.

[0099] The memory 13, as a computer-readable storage medium, can be set to store software programs and computer-executable programs, such as the program instructions or modules corresponding to the method in the embodiments of the present disclosure. The processor 11 executes functional applications and data processing by running the software programs, instructions, or modules stored in the memory 13, that is, implements the method in the above-mentioned embodiment.

[0100] The memory 13 may include a program storage area and a data storage area. Among them, the program storage area can store an operating system and applications required for at least one function; the data storage area can store data created according to the use of the electronic device 10, etc. In addition, the memory 13 may include a high-speed random access memory and may also include a non-volatile memory. For example, various media such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disc that can store program codes can also be a transient storage medium.

[0101] An embodiment of the present application also provides a computer storage medium. The computer storage medium stores a computer program for electronic data exchange, and the computer program causes the computer to execute some or all of the steps of any one of the methods described in the foregoing method embodiments. The computer includes an electronic device.

[0102] An embodiment of the present application also provides a computer program product. The computer program product includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause the computer to execute some or all of the steps of any one of the methods described in the foregoing method embodiments. The computer program product can be a software installation package, and the computer includes an electronic device.

[0103] It should be understood that in various embodiments of the present application, the magnitudes of the sequence numbers of the foregoing processes do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0104] In several embodiments provided by the present application, it should be understood that the disclosed methods, devices, and systems can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation; for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling, direct coupling, or communication connection can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be in electrical, mechanical, or other forms.

[0105] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0106] In addition, in each embodiment of the present invention, the functional units can be integrated into one processing unit, or each unit can be physically included separately, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware, or in the form of a combination of hardware and software functional units.

[0107] The integrated units implemented in the form of software functional units can be stored in a computer-readable storage medium. The above-mentioned software functional units stored in a storage medium include several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute some steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: USB flash drives, mobile hard disks, magnetic disks, optical discs, volatile memories, or non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of random access memory (RAM) are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchlink dynamic random access memory (SLDRAM), and direct rambus random access memory (DR RAM). And other various media that can store program codes.

[0108] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions without departing from the spirit and scope of the present invention, and can make various modifications and alterations, including combinations of the above different functions and implementation steps, including software and hardware implementation manners, all within the protection scope of the present invention.

Claims

1. An adaptive level circuit, characterized in that: Applied to a first chip, the first chip includes at least two power supply terminals; the adaptive level circuit includes a comparison subunit, at least two signal generation subunits and at least two level control subunits; the comparison subunit includes at least two signal interfaces; The at least two power supply terminals include a first power supply terminal and at least one second power supply terminal, the at least two signal interfaces include a first signal interface and at least one second signal interface, the first power supply terminal is connected to the first signal interface, the at least one second power supply terminal is connected to the at least one second signal interface in a one-to-one correspondence, the output terminal of the comparison subunit is connected to the control terminal of the at least two signal generation subunits, the at least two signal generation subunits are connected to the at least two level control subunits in a one-to-one correspondence, and the at least two signal generation subunits are connected in series on the communication bus; The first chip acquires a first level signal of a second chip communicating with the first chip through the first power supply terminal, and transmits the first level signal to the comparison subunit through the first signal interface; The comparison subunit compares the first level signal with at least one second level signal of at least one second power supply terminal to generate a first control signal, wherein the second power supply terminal is a power supply terminal other than the first power supply terminal among the at least two power supply terminals; the at least one second level signal includes a level signal of at least one third chip, or includes at least one zero level signal; the second chip and at least one third chip are both connected to the communication bus of the first chip; The at least two signal generating subunits are matched with the first control signal respectively, and a target signal generating subunit that successfully matches among the at least two signal generating subunits generates a target selection signal according to the first control signal, wherein the target selection signal is used to determine a target level control subunit from the at least two level control subunits; The target level control subunit adjusts its own level to the same first level as that of the second chip according to the target selection signal.

2. The adaptive level circuit according to claim 1, characterized in that: It also includes a data processing unit, the data processing unit is respectively connected to the at least two signal generating subunits, and connected to the communication bus or the first signal interface of the comparing subunit; The data processing unit collects the first level to obtain a first sampling signal set; Calculating an autocorrelation function according to the first sampling signal set to obtain a plurality of similarity values; Determine the proportion of similarity values ​​in the multiple similarity values ​​that are equal to the first similarity value; wherein the first similarity value is the first calculated similarity value in the multiple similarity values; If the proportion is less than a preset value, a shutdown signal is sent to the target signal generating subunit to control the target signal generating subunit to be shut down.

3. The adaptive level circuit according to claim 1, characterized in that: The comparison subunit includes at least one comparator, which obtains a first level signal and at least one second level signal; the at least one comparator is used to perform at least one level comparison on the first level signal and the at least one second level signal to generate the first control signal.

4. The adaptive level circuit according to claim 1, characterized in that: The at least two signal generating subunits include a first signal generating subunit and a second signal generating subunit, The first signal generating subunit and the second signal generating subunit are matched with the first control signal respectively. When the voltage of the first control signal is the same as the on-voltage of the first signal generating subunit, the first signal generating subunit generates the target selection signal according to the first control signal; when the voltage of the first control signal is the same as the on-voltage of the second signal generating subunit, the second signal generating subunit generates the target selection signal according to the first control signal.

5. The adaptive level circuit according to claim 4, characterized in that: The first signal generating subunit includes a first switch tube, a second switch tube, a first resistor, a second resistor, a third resistor and a first capacitor: The controlled end of the first switch tube is connected to one end of the first resistor and the output end of the comparison subunit to access the first control signal; the input end of the first switch tube is connected to one end of the second resistor, one end of the third resistor and one end of the first capacitor, the other end of the second resistor, the other end of the first capacitor and the input end of the second switch tube are all connected to the first power supply, the other end of the third resistor is connected to the controlled end of the second switch tube, the output end of the second switch tube is connected to the communication bus, and the other end of the first resistor and the output end of the first switch tube are both grounded.

6. The adaptive level circuit according to claim 4, characterized in that: The second signal generating subunit includes a third switch tube, a fourth resistor, a fifth resistor and a second capacitor; The controlled end of the third switch tube, one end of the fourth resistor, one end of the fifth resistor and one end of the second capacitor are all connected to the output end of the comparison subunit to access the first control signal; The other end of the fourth resistor, the other end of the second capacitor and the input end of the third switch tube are all connected to the second power supply, the other end of the fifth resistor is connected to the controlled end of the third switch tube, and the output end of the third switch tube is connected to the communication bus.

7. The adaptive level circuit according to any one of claims 2 to 6, characterized in that: The levels of the at least two level control subunits are different; the at least two level control subunits are connected to the at least two signal generation subunits in a one-to-one correspondence to obtain the target selection signal from the corresponding signal generation subunit; When the target level control subunit of the at least two level control subunits receives the target selection signal, the level of the first chip is adjusted to the same first level as that of the second chip according to the target selection signal.

8. The adaptive level circuit according to claim 7, characterized in that: The target selection signal includes a first selection signal and a second selection signal; the at least two level control subunits include a first level control subunit and a second level control subunit; The first level control subunit includes a fourth switch tube, a fifth switch tube, a sixth resistor and a seventh resistor; The second level control subunit includes an eighth resistor and a ninth resistor; the data bus includes a first segment data bus and a second segment data bus, and the clock bus includes a first segment clock bus and a second segment clock bus; The first end of the sixth resistor and the first end of the seventh resistor are both connected to the first selection signal, and the other end of the sixth resistor is connected to the controlled end of the fourth switch tube; the input end and the output end of the fourth switch tube are respectively connected to the first segment data bus and the second segment data bus; the other end of the seventh resistor is connected to the controlled end of the fifth switch tube; the input end and the output end of the fifth switch tube are respectively connected to the first segment clock bus and the second segment clock bus; One end of the eighth resistor and one end of the ninth resistor are both connected to the first selection signal, the other end of the eighth resistor is connected to the first data bus, and the other end of the ninth resistor is connected to the first clock bus.

9. A chip, characterized in that: The method comprises an adaptive level circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that: The method comprises the adaptive level circuit as claimed in any one of claims 1 to 8, or comprises the chip as claimed in claim 9.

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