An offset cancellation circuit

Abstract

The present invention discloses an offset cancellation circuit, comprising: a signal conditioning unit for processing an input signal and outputting a first current signal, an offset cancellation unit for removing an offset current in the first current signal and outputting a second current signal, and a zero-gain unit for processing the second current signal and eliminating an offset voltage, and finally outputting a target signal, wherein the offset cancellation unit specifically comprises: a chopper, a digital-to-analog converter, a successive approximation register logic module and a comparator connected in sequence, and through multi-level offset cancellation, the overall circuit accuracy is improved, the processing capability of weak signals is enhanced, the anti-interference capability is improved and the noise is reduced, and the stability of long-term operation is ensured, and the circuit has broad application prospects in the field of high-precision signal processing.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to an offset elimination circuit. Background Art

[0002] Offset cancellation circuits are widely used in the field of integrated circuits. Offsets may occur due to manufacturing process deviations, temperature effects, and power supply voltage fluctuations. For example, in the manufacturing process of integrated circuits, it is difficult to achieve completely accurate consistency in process steps such as photolithography and doping, which will lead to certain deviations in component parameters and thus offset voltages. On the other hand, if there is no stable power supply voltage, when the power supply voltage fluctuates, it will affect the working state of the internal circuit, destroying the symmetry of the differential input stage and generating offset voltage. When amplifying the signal, this offset voltage will be amplified together, causing errors in the output signal. When processing small signals, the offset voltage may be inconsistent with the input signal. The output signal is at the same order of magnitude, or even exceeds the input signal, which will cause the baseline of the signal to shift, resulting in deviations in subsequent signal processing and analysis. In severe cases, it will cause signal distortion, affecting the performance and accuracy of the system. In actual applications, it is found that the offset circuit in the prior art only performs a single offset elimination and cannot achieve the expected signal output effect. Further research found that the output signal processing of the amplifier and the offset elimination using a successive approximation register are difficult to achieve a good synergistic effect, and will lose a certain amount of signal accuracy. Therefore, it has become an urgent problem to realize the full process of offset elimination and design an offset elimination circuit that achieves high-efficiency synergy. Summary of the invention

[0003] In order to solve the above-mentioned problems existing in the prior art, the present application provides an offset cancellation circuit, which realizes full-process signal optimization, enhances signal stability and anti-interference performance, and overcomes the shortcomings of the above-mentioned prior art through the coordinated cooperation of a signal conditioning unit, an offset cancellation unit and a zero gain unit.

[0004] In order to achieve the above object, the present invention adopts the following technical solutions:

[0005] An offset cancellation circuit, comprising:

[0006] A signal conditioning unit, used for processing an input signal and outputting a first current signal, specifically comprising: a filter and a first amplifier, wherein the input signal enters the first amplifier through the filter;

[0007] an offset elimination unit, used to remove the offset current in the input first current signal and output a second current signal, specifically comprising: a chopper, a digital-to-analog converter, a successive approximation register logic module and a comparator connected in sequence, wherein the output end of the comparator is connected to the successive approximation register logic module, and the successive approximation register logic module processes the analog signal output by the digital-to-analog converter according to a clock control signal, a reset signal and a comparator signal generated by the comparator, so as to eliminate the offset current in the first current signal;

[0008] A zero gain unit is used to process the second current signal, eliminate the offset voltage of the second amplifier in the zero gain unit, and output the target signal. The chopper is connected to the output end of the first amplifier, and the output end of the first amplifier is connected to the inverting input end of the second amplifier through the seventh switch, the first capacitor, the third switch and the second capacitor. The non-inverting input end of the second amplifier is connected to the reference voltage, the first end of the second capacitor is connected to the output end of the second amplifier through the third capacitor and the fifth switch, and the output end of the second amplifier is connected to the non-inverting input end of the comparator and the signal output end of the offset elimination circuit.

[0009] Among them, the signal conditioning unit improves the quality and strength of the signal, enhances the detectability of the signal, provides a good foundation for subsequent offset elimination and signal processing, and reduces the difficulty of subsequent processing circuits to process weak signals; the offset elimination unit accurately controls the digital-to-analog converter to output a compensation signal that is equal to the offset current and opposite in direction through the successive approximation register logic module combined with the feedback signal of the comparator, effectively removes the offset current in the first current signal, significantly improves the accuracy and stability of the signal, reduces the signal deviation and distortion caused by the offset current, and enables the subsequent processing circuit to operate based on more accurate signals, thereby improving the performance of the entire circuit system; the zero-stabilizing gain unit ensures that the output signal more accurately restores the characteristics of the input signal in amplitude and phase through the coordinated cooperation of the capacitor and the second amplifier, avoiding additional signal interference and noise caused by the offset voltage of the second amplifier; through the coordinated cooperation of the signal conditioning unit, the offset elimination unit and the zero-stabilizing gain unit, the whole process signal optimization is realized, the noise level of the signal is reduced, the linearity and gain stability of the signal are improved, and the entire circuit system can maintain high-precision signal processing capabilities during long-term operation.

[0010] Preferably, one end of the chopper is connected to the output end of the first amplifier and the zero-stabilizing gain unit, and the other end of the chopper is connected to the digital-to-analog converter, the digital-to-analog converter is connected to the successive approximation register logic module and the reference current, the successive approximation register logic module is connected to the reset signal, the clock control signal and the output end of the comparator, the comparator is connected to the clock control signal, the inverting input end of the comparator is connected to the reference voltage, and the non-inverting input end of the comparator is connected to the signal output end of the offset elimination circuit. This connection method forms a complete feedback control loop, the chopper modulates the signal and inputs it to the digital-to-analog converter, the successive approximation register logic module adjusts the output of the digital-to-analog converter according to the output signal of the comparator, thereby realizing accurate elimination of the offset current, and through closed-loop control, it can automatically adapt to different input signals and offset conditions, adjust the compensation signal in real time, improve the accuracy and stability of offset elimination, and ensure that the circuit can effectively remove the offset current under various working conditions.

[0011] Preferably, the zero-gain unit specifically includes: a first switch, a second switch, the third switch, a fourth switch, the fifth switch, the sixth switch, the seventh switch, a first capacitor, a second capacitor, the third capacitor and the second amplifier; the first end of the seventh switch is connected to the output end of the first amplifier and one end of the chopper, the first end of the first switch and the first end of the first capacitor are both connected to the second end of the seventh switch, the second end of the first capacitor is connected to the first end of the second switch and the first end of the third switch, the second end of the third switch is connected to the first end of the second capacitor, the first end of the third capacitor and the first end of the sixth switch, the second end of the third capacitor is connected to the first end of the fifth switch, the second end of the second capacitor is connected to the inverting input end of the second amplifier and the first end of the fourth switch, the non-inverting input end of the second amplifier is connected to the reference voltage, the output end of the second amplifier is connected to the non-inverting input end of the comparator, the signal output end of the offset cancellation circuit, the second end of the fifth switch, the second end of the sixth switch and the second end of the fourth switch, and the second end of the first switch, the second end of the second switch, the non-inverting input end of the second amplifier and the first end of the sixth switch are all connected to an external reference voltage. Through different combination states of multiple switches and the charging and discharging process of the capacitor, the offset voltage can be collected, stored and compensated at different stages. The capacitor is used to store the offset voltage information, and combined with the work of the second amplifier, the offset voltage of the second amplifier can be effectively eliminated. It can be adjusted according to actual needs, which improves the flexibility and accuracy of offset voltage elimination. By reasonably configuring switches and capacitors, the offset voltage can be effectively controlled without adding too many complex circuits, thereby reducing circuit cost and power consumption.

[0012] Further preferably, in the acquisition state, the second switch and the seventh switch are closed, and the remaining switches are opened, and the second amplifier is not in the working state.

[0013] Further preferably, in the storage state, the second switch, the sixth switch and the seventh switch are closed, and the remaining switches are opened, the offset voltage is stored on the second capacitor, the voltage on the first capacitor maintains the voltage in the acquisition state, and the voltage stored in the third capacitor is 0.

[0014] Further preferably, in the maintenance state, the first switch, the third switch and the fifth switch are closed, and the remaining switches are opened. The staged operation mode is clarified to provide an accurate data basis for offset elimination, which greatly improves the accuracy of offset elimination. The stored offset voltage can effectively compensate for the offset of the second amplifier, avoid its interference with the signal, improve the accuracy and stability of the output signal, and the circuit can continuously compensate for the offset voltage for a long time, thereby enhancing the reliability of the entire circuit system, and is suitable for application scenarios with high requirements for signal stability and accuracy.

[0015] Preferably, the filter is a high-pass filter, which improves the quality of the input signal, makes the signal entering the first amplifier purer, reduces the impact of low-frequency noise on subsequent processing, and helps to improve the anti-interference ability and signal processing accuracy of the entire circuit system.

[0016] Further preferably, the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch and the seventh switch are all CMOS switches, which improves the switching speed, reduces the loss and distortion of the signal during the switching process, improves the performance and stability of the entire zero-gain unit, and is also conducive to the integrated design of the circuit and reduces the cost.

[0017] Preferably, the operational amplifier used by the first amplifier and the second amplifier is one of LM741, AD829, LM324, TL071 and OPA2134.

[0018] Preferably, the comparator is one of LM324, LM358, TL081, LM339, LM393 and OP27.

[0019] Compared with the prior art, the beneficial results of the present invention are that the present invention provides an offset cancellation circuit, which, after the coordinated processing of the signal conditioning unit, the offset cancellation unit and the zero gain unit, realizes the full process optimization of the signal from input to output, improves the quality of the output signal, and expands the signal processing range, realizes the processing capability of weak small signals, minimizes the errors and interference in the signal, and makes the signal more stable and accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings provide further description of the embodiments, and the accompanying drawings are incorporated into and constitute a part of this specification. The accompanying drawings illustrate the embodiments and are used together with the description to explain the principles of the present invention. It will be easy to recognize other embodiments and many expected advantages of the embodiments, because they become better understood by reference to the following detailed description. Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0021] Figure 1 is a structural block diagram of an offset cancellation circuit according to a specific embodiment of the present invention;

[0022] Figure 2 is a circuit diagram of an offset cancellation circuit according to a specific embodiment of the present invention;

[0023] Figure 3 is a circuit diagram of an offset elimination circuit operating in a collection state according to a specific embodiment of the present invention;

[0024] Figure 4 is a circuit diagram of an offset cancellation circuit operating in a storage state according to a specific embodiment of the present invention;

[0025] Figure 5 1 is a circuit diagram of an offset cancellation circuit operating in a holding state according to a specific embodiment of the present invention.

[0026] The meaning of the numbers in the figure are: A1-first amplifier; A2-second amplifier; COM-comparator; B1-filter; B2-chopper; C1-first capacitor; C2-second capacitor; C3-third capacitor; K1-first switch; K2-second switch; K3-third switch; K4-fourth switch; K5-fifth switch; K6-sixth switch; K7-seventh switch. DETAILED DESCRIPTION

[0027] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It should also be noted that, for ease of description, only the parts related to the relevant invention are shown in the accompanying drawings.

[0028] In the description of the present invention, it should be noted that the terms "comprises", "includes" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. The terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0029] In the description of the present invention, it should be noted that, unless otherwise clearly stipulated and limited, the terms "installed", "provided with", "mounted / connected", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection. It can be a mechanical connection or an electrical connection. It can be a direct connection or an indirect connection through an intermediate medium. It can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0030] To facilitate understanding by those skilled in the art, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0031] Figure 1 FIG. 4 shows a structural block diagram of an offset elimination circuit according to a specific embodiment of the present application. Figure 1 As shown, it includes: a signal conditioning unit, an offset elimination unit and a zero-stabilizing gain unit, the signal input terminal IN is connected to one end of the signal conditioning unit, the other end of the signal conditioning unit is connected to one end of the zero-stabilizing gain unit and one end of the offset elimination unit, the other end of the zero-stabilizing gain unit is connected to the other end of the offset elimination unit, and is connected to the signal output terminal OUT.

[0032] In a specific embodiment, the signal conditioning unit amplifies the input signal and outputs a first current signal. After amplification, the amplitude of the signal is improved and can be more easily detected and processed by subsequent circuits, which can improve the sensitivity of the entire system to weak signals, enable the system to more accurately perceive and respond to changes in the input signal, and the amplified signal can better match the input range of the zero-stabilizing gain unit and other subsequent processing circuits; the offset cancellation unit can generate a current equal to the offset current to remove the offset current in the first current signal, thereby achieving offset cancellation and outputting a second current signal after offset cancellation; after removing the offset current, the stability of the signal is significantly improved, reducing signal jitter and errors caused by the offset, making subsequent processing results more accurate. In order to make the system more stable and reliable, the signal after preliminary processing by the signal conditioning unit and the offset elimination unit enters the zero-stabilizing gain unit, that is, the second current signal, which makes the signal processed by the system more accurate and improves the anti-interference performance. At the same time, the zero-stabilizing gain unit can eliminate the offset voltage of the second amplifier A2, so that the output target signal can not only restore the characteristics of the input signal more accurately in amplitude and phase, but also greatly reduce the noise level of the signal, and the waveform is smoother and purer. From the perspective of system performance, the linearity of the entire circuit is significantly improved, and the gain stability is further enhanced, which effectively avoids the degradation of system performance caused by the accumulation of offset voltage, and ensures that the system always maintains high-precision signal processing capabilities during long-term operation, and finally outputs the target signal to the signal output terminal OUT.

[0033] Optionally, the input signal can be a sensor output signal, a communication signal or a bioelectric signal. For example, the corresponding electrical signal is output according to the ambient temperature. Based on the Seebeck effect, the thermocouple will generate a thermoelectric potential proportional to the temperature difference at both ends. The thermoelectric potential signal is usually weak and may contain an offset component. It needs to be processed by an offset elimination circuit to accurately measure the temperature. It can also be a pressure sensor signal. Due to factors such as the manufacturing process, the output signal may have an offset. The offset elimination circuit can improve the accuracy of pressure measurement. It can also be an acceleration sensor signal. The input signal reflects the magnitude and direction of the acceleration, but there will be an offset error. The offset elimination circuit can correct it so that the device can sense movement more accurately. On the other hand, weak radio frequency signals need to be amplified and offset eliminated to improve signal quality and ensure accurate demodulation and decoding. The processing of electrocardiogram signals or electroencephalogram signals by the offset elimination circuit can improve the quality of the signal and contribute to the diagnosis and research of neurological diseases.

[0034] In a specific embodiment, the filter is a high-pass filter. Optionally, if a small signal such as an electrocardiogram signal is processed, the cutoff frequency of the high-pass filter may be 0.05 Hz to 0.5 Hz to balance baseline drift suppression and low-frequency signal retention.

[0035] Figure 2 A circuit diagram of an offset cancellation circuit according to a specific embodiment of the present application is shown in FIG. Figure 2 As shown, an offset elimination circuit includes: a signal conditioning unit, an offset elimination unit and a zero-stabilizing gain unit. The signal conditioning unit is used to process an input signal and output a first current signal. The signal conditioning unit specifically includes: a filter B1 and a first amplifier A1. The input signal enters the first amplifier A1 through the filter B1, that is, the signal input terminal IN is connected to one end of the filter B1. Optionally, the filter B1 can be a high-pass filter. The filter B1 can reduce the noise input to the first amplifier A1 and improve the signal-to-noise ratio of the input signal. The other end of the filter B1 is connected to the input end of the first amplifier A1, and the output end of the first amplifier A1 is connected to the offset elimination unit and the zero-stabilizing gain unit.

[0036] In a specific embodiment, the offset elimination unit is used to remove the offset current in the input first current signal and output a second current signal, and specifically includes: a chopper B2, a digital-to-analog converter, a successive approximation register module and a comparator COM connected in sequence, one end of the chopper B2 is connected to the output end of the first amplifier A1 and the zero gain unit, the other end of the chopper B2 is connected to the digital-to-analog converter, the digital-to-analog converter is connected to the successive approximation register logic module and the reference current Iref, the successive approximation register logic module is connected to the reset signal RST, the clock control signal CLK and the output end of the comparator COM, the comparator COM is connected to the clock control signal CLK, the inverting input end of the comparator COM is connected to the reference voltage Vref, and the non-inverting input end of the comparator COM is connected to the signal output end OUT of the offset elimination circuit.

[0037] In a specific embodiment, the chopper B2 performs chopping processing on the input first current signal to obtain a chopping signal, the digital-to-analog converter processes the reference current Iref generated by the external reference circuit to obtain a corresponding analog signal through digital-to-analog conversion, and the comparator COM generates a comparator signal by comparing the reference voltage Vref with the voltage signal output by the zero gain unit.

[0038] In a specific embodiment, the reference voltage Vref is a specific voltage value used as a comparison standard and is generated by an external reference circuit. The reference voltages at different locations in the circuit may be generated by different external reference circuits.

[0039] In a specific embodiment, the chopper B2 is a device that performs operations such as boosting, reducing or converting an input signal, can output a signal that meets specific requirements, can filter the first current signal to extract the chopping signal, and can effectively suppress the input reference noise in the offset elimination unit.

[0040] In a specific embodiment, a successive approximation register (SCR) logic module gradually determines a compensation signal equal to the offset current by a successive approximation method based on a comparison signal output by a comparator, in combination with a reset signal RST and a clock control signal CLK, and continuously adjusts the analog signal output by a digital-to-analog converter to match the effect of the offset current, and finally finds a digital code that can completely offset the offset current, thereby achieving accurate measurement and compensation of the offset current, improving system stability and accuracy, and effectively reducing errors and interference in the circuit, so that the system can maintain a high performance level under various working conditions, ensuring the quality and reliability of the output signal. Optionally, a synchronous successive approximation register logic or an asynchronous successive approximation register logic can be used.

[0041] In a specific embodiment, the comparator COM compares the comparator reference voltage Vref with the output voltage of the zero-stabilizing gain unit to generate a comparator signal. When the offset voltage in the input signal is large, there is a difference between the zero-stabilizing gain unit and the reference voltage Vref. The comparator COM outputs a comparator signal and inputs it into a successive approximation register logic module, wherein the comparator signal can be a low level and a high level, the low level is a binary 0, and the high level is a binary 1. The successive approximation register logic module eliminates the offset current in the first current signal according to the comparator signal, the reset signal RST and the clock control signal CLK, that is, generates a signal equal to the offset current, and outputs a second current signal.

[0042] In a specific embodiment, when a reset signal RST is received, the register logic module initializes the internal successive approximation register to a specific state, usually setting the most significant bit (MSB) to 1 and the remaining bits to 0. The reset signal ensures that each operation starts from a known initial state to prevent residual data from previous operations from affecting the current offset current elimination process.

[0043] After the initialization is completed, the module is in a ready state, waiting for the input of the clock control signal CLK and the comparator signal to start the successive approximation process.

[0044] In the first clock cycle, the current digital value in the successive approximation register is sent to the digital-to-analog converter, which converts the digital value into the corresponding analog voltage or current signal. Since the most significant bit of the successive approximation register is 1 and the remaining bits are 0 at the beginning, the digital-to-analog converter outputs the analog value corresponding to the most significant bit being 1. The comparator compares the output voltage of the zero-gain unit with the comparator reference voltage Vref. If the output voltage of the zero-gain unit is greater than the comparator reference voltage Vref, the comparator outputs a high level; if it is less than the comparator reference voltage Vref, the comparator outputs a low level, and the comparator signal is input into the successive approximation register logic module.

[0045] In a specific embodiment, the successive approximation register logic module updates the value of the successive approximation register according to the comparator signal. If the comparator output is a high level, it means that the analog value output by the current digital-to-analog converter is not large enough and the highest bit 1 needs to be retained; if it is a low level, the highest bit is cleared to zero, and multiple rounds of comparisons are performed subsequently. In each subsequent clock cycle, the successive approximation register logic module shifts the digital value in the register right by one bit and sets the next bit, that is, the second highest bit, to 1. The digital-to-analog converter outputs the analog value corresponding to the new digital value, and the comparator compares again and outputs a new comparator signal. The successive approximation register logic module decides whether to retain the value of the current bit based on the new comparator signal. This process is repeated until all bits of the successive approximation register are processed.

[0046] After the successive approximation process, the digital value finally stored in the successive approximation register corresponds to a signal equal to the offset current. The digital value is again converted into an analog signal through the digital-to-analog converter. The magnitude of the analog signal is equal to the offset current, but the direction is opposite. This compensation analog signal is combined with the first current signal through a subtraction circuit to offset the offset current in the first current signal and obtain a second current signal after the offset is eliminated.

[0047] When the successive approximation process is completed, the successive approximation register logic module outputs the final processing result, that is, the second current signal. At this point, the offset current has been effectively eliminated, and the system can continue to process and apply the second current signal. If a new round of offset current elimination operation is required, the successive approximation register logic module will wait for the next reset signal RST to arrive, and then repeat the above initialization and successive approximation process.

[0048] Optionally, the successive approximation register is combined with the self-calibration technology. When the system is started or periodically self-calibrated, a known reference signal is input in the self-calibration mode, and the successive approximation register logic module completes the conversion to obtain a digital output. Since the reference signal is known, the deviation between the output digital value and the theoretical value reflects the influence of the offset. This deviation is recorded, and in subsequent normal operation, the recorded value is used to correct the conversion result of the actual input signal. In the self-calibration stage, the successive approximation register logic module control circuit switches to the reference signal input state to complete the analog-to-digital conversion of the reference signal. The difference between the conversion result and the theoretical reference value is calculated by the digital logic circuit and stored in the register. In normal operation, each time the successive approximation register logic module completes the conversion of the actual input signal, the output digital code is adjusted according to the stored difference, thereby eliminating the offset current.

[0049] The clock control signal CLK is generated by an external clock control signal circuit, and the reset signal RST is generated by an external reset circuit, which can be a power-on reset circuit or a reset circuit such as a watchdog timer. The clock control signal CLK is analyzed and processed based on the combinational logic through the low-frequency signal generated inside the circuit to generate a high-frequency clock control signal CLK that meets the operating frequency of the successive approximation register logic module and the comparator COM, which can avoid interference of the external high-frequency control signal input on the internal circuit.

[0050] In a specific embodiment, the comparator COM and the successive approximation register logic module are connected to the same clock control signal CLK.

[0051] In a specific embodiment, the second current signal after preliminary processing by the offset elimination unit enters the zero-stabilizing gain unit, amplifies the signal and performs other processing, and outputs a target signal that meets the output requirements, specifically including: a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a fifth switch K5, a sixth switch K6, a seventh switch K7, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a second amplifier A2; the first end of the seventh switch K7 is connected to the output end of the first amplifier A1 and one end of the chopper B2, the first end of the first switch K1 and the first end of the first capacitor C1 are both connected to the second end of the seventh switch K7, the second end of the first capacitor C1 is connected to the first end of the second switch K2 and the first end of the third switch K3, the second end of the third switch K3 is connected to the first end of the second capacitor C2, the first end of the third capacitor C3 and the sixth switch The first end of the first switch K6, the second end of the third capacitor C3 is connected to the first end of the fifth switch K5, the second end of the second capacitor C2 is connected to the inverting input end of the second amplifier A2 and the first end of the fourth switch K4, the non-inverting input end of the second amplifier A2 is connected to the reference voltage, the output end of the second amplifier A2 is connected to the non-inverting input end of the comparator COM, the signal output end OUT of the offset cancellation circuit, the second end of the fifth switch K5, the second end of the sixth switch K6 and the second end of the fourth switch K4, the second end of the first switch K1, the second end of the second switch K2, the non-inverting input end of the second amplifier A2 and the first end of the sixth switch K6 are all connected to the external second amplifier reference voltage VREF, the external second amplifier reference voltage VREF is generated by an external reference circuit, and optionally, the external second amplifier reference voltage VREF is the same. The zero-stabilizing gain unit realizes more refined processing of the signal and eliminates the offset voltage of the second amplifier A2 in the zero-stabilizing gain unit. The structure of the zero-stabilizing gain unit has been verified to be most suitable for the offset elimination circuit of this embodiment, and can achieve the goals of high precision, low noise, flexible gain control and efficient offset elimination. Its modularity, low power consumption and high anti-interference ability make it suitable for high-precision signal processing systems, such as sensor interfaces, medical equipment and industrial measurement.

[0052] It should be noted that the first amplifier A1 and the second amplifier A2 in the present application are operational amplifiers.

[0053] Optionally, the external second amplifier reference voltage VREF and the comparator reference voltage Vref may be generated by the same external reference circuit or by different external reference circuits.

[0054] In a specific embodiment, the first switch K1, the second switch K2, the third switch K3, the fourth switch K4, the fifth switch K5, the sixth switch K6 and the seventh switch K7 may be CMOS switches, bipolar transistor switches and mechanical switches, etc. Preferably, CMOS (complementary metal oxide semiconductor) switches are used, which are easy to be integrated into a chip and support high-density design.

[0055] Figure 3 FIG. 4 shows a schematic diagram of an offset elimination circuit operating in an acquisition state. Figure 3 As shown, in the acquisition state, the second switch K2 and the seventh switch K7 are closed, and the first switch K1, the third switch K3, the fourth switch K4, the fifth switch K5 and the sixth switch K6 are opened. The second amplifier A2 is not in a working state, which can save power consumption and reduce costs. At this time, the first capacitor C1 stores the difference between the input voltage and the reference voltage VREF of the second amplifier A2.

[0056] Figure 4 FIG. 4 shows a circuit diagram of an offset cancellation circuit operating in a storage state. Figure 4 As shown, the second switch K2, the sixth switch K6 and the seventh switch K7 are closed, the first switch K1, the third switch K3, the fourth switch K4 and the fifth switch K5 are opened, the offset voltage is stored on the second capacitor C2, the voltage on the first capacitor C1 maintains the voltage in the acquisition state, and the voltage stored in the third capacitor C3 is 0.

[0057] In a specific embodiment, the storage state is completed before the maintenance state, the storage state does not need to be synchronized with the acquisition state, the working time of the second amplifier is shorter, power consumption is greatly saved, and it is more suitable for the offset elimination work of the offset elimination unit.

[0058] Figure 5 FIG. 4 shows a circuit diagram of an offset elimination circuit operating in a maintenance state. Figure 5As shown, the first switch K1, the third switch K3 and the fifth switch K5 are closed, and the second switch K2, the fourth switch K4, the sixth switch K6 and the seventh switch K7 are disconnected. At this time, the second amplifier A2 works normally. When the third switch K3 is turned on, the second end of the second capacitor C2 is connected to the reverse input end of the second amplifier A2, and is in a high-impedance state. According to the virtual short circuit characteristic of the input end of the operational amplifier, the voltage of the reverse input end is always maintained constant. Then the first end of the second capacitor C2 follows the charge conservation law, and the voltage is the reference voltage VREF. The voltage of the second end of the second capacitor C2 is the difference between the reference voltage VREF and the offset voltage. Then the zero-stabilized gain unit offsets the offset component while having an amplification effect, so that the signal output by the second amplifier A2 does not contain an offset voltage. Through the switch configuration and the capacitor feedback network, combined with the virtual short characteristics of the operational amplifier, high-precision, low-noise offset voltage elimination is achieved, and the scalability is strong. On the basis of eliminating the offset current by the offset elimination unit, the signal output is further refined to obtain a high-quality output signal, which is suitable for high-requirement fields such as precision measurement, sensor interface and medical electronics.

[0059] Optionally, for ultra-low offset scenarios, multiple stages of zero-stabilized gain units can be cascaded to achieve step-by-step error correction and improve the accuracy of the circuit system.

[0060] The present application provides an offset elimination circuit. After amplification and transformation conditioning by a signal conditioning unit, the offset elimination unit eliminates the offset current to achieve preliminary signal refinement processing. At the same time, the zero gain unit can eliminate the offset voltage of the second amplifier A2 and output a high-quality output signal. Only the offset elimination unit can only solve the offset current problem in the signal, and cannot optimize the strength and quality of the input signal, and it is also difficult to process the offset voltage of the subsequent amplifier. If there is only a zero-gain unit, the signal cannot be amplified and preprocessed at the source, nor can the offset current of the input signal itself be effectively eliminated. The circuit with all three features performs amplification enhancement and preliminary noise processing from the signal input, then eliminates the offset current, and finally solves the amplifier offset voltage problem, realizing the optimization of the entire process from signal input to output, and expanding the scope of application of the circuit, ensuring the long-term stable operation of the system, and the inventor has fully simulated an offset elimination circuit of the present application, and the experimental results verify that it can achieve the desired effect. When it is applied to medical detection equipment applications with extremely high signal accuracy requirements, after eliminating the offset voltage and current, the output target signal is more accurate, making the detection results of bioelectric signals such as electrocardiograms and electroencephalograms more accurate and reliable, providing a more valuable reference for doctors' diagnosis. In the field of industrial automation control, accurate signals can ensure the accurate acquisition of sensor data and the precise control of actuators, and improve the stability of the production process and product quality. In communication systems, the improvement of anti-interference performance helps to reduce the bit error rate in signal transmission, enhance the reliability and stability of communication, and ensure the accurate transmission of information.

[0061] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above invention concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.

Claims

1. An offset cancellation circuit, characterized in that: include: A signal conditioning unit, used for processing an input signal and outputting a first current signal, specifically comprising: a filter and a first amplifier, wherein the input signal enters the first amplifier through the filter; an offset elimination unit, used to remove the offset current in the input first current signal and output a second current signal, specifically comprising: a chopper, a digital-to-analog converter, a successive approximation register logic module and a comparator connected in sequence, wherein the output end of the comparator is connected to the successive approximation register logic module, and the successive approximation register logic module processes the analog signal output by the digital-to-analog converter according to a clock control signal, a reset signal and a comparator signal generated by the comparator, so as to eliminate the offset current in the first current signal; a zero-stabilizing gain unit, used for processing the second current signal, eliminating the offset voltage of the second amplifier in the zero-stabilizing gain unit, and outputting a target signal, wherein the chopper is connected to the output end of the first amplifier, the output end of the first amplifier is connected to the inverting input end of the second amplifier through the seventh switch, the first capacitor, the third switch and the second capacitor, the non-inverting input end of the second amplifier is connected to the reference voltage, the first end of the second capacitor is connected to the output end of the second amplifier through the third capacitor and the fifth switch, and the output end of the second amplifier is connected to the non-inverting input end of the comparator and the signal output end of the offset elimination circuit; One end of the chopper is connected to the output end of the first amplifier and the zero-stabilizing gain unit, the other end of the chopper is connected to the digital-to-analog converter, the digital-to-analog converter is connected to a successive approximation register logic module and a reference current, the successive approximation register logic module is connected to the reset signal, the clock control signal and the output end of the comparator, the comparator is connected to the clock control signal, the inverting input end of the comparator is connected to a reference voltage, and the non-inverting input end of the comparator is connected to the signal output end of the offset cancellation circuit; The zero-stabilizing gain unit specifically includes: a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a first capacitor, a second capacitor, the third capacitor and the second amplifier; the first end of the seventh switch is connected to the output end of the first amplifier and one end of the chopper, the first end of the first switch and the first end of the first capacitor are both connected to the second end of the seventh switch, the second end of the first capacitor is connected to the first end of the second switch and the first end of the third switch, the second end of the third switch is connected to the first end of the second capacitor, the first end of the third capacitor and the first end of the sixth switch, the second end of the third capacitor is connected to the first end of the fifth switch, the second end of the second capacitor is connected to the inverting input end of the second amplifier and the first end of the fourth switch, the non-inverting input end of the second amplifier is connected to the reference voltage, the output end of the second amplifier is connected to the non-inverting input end of the comparator, the signal output end of the offset cancellation circuit, the second end of the fifth switch, the second end of the sixth switch and the second end of the fourth switch, and the second end of the first switch, the second end of the second switch, the non-inverting input end of the second amplifier and the first end of the sixth switch are all connected to an external reference voltage.

2. The offset cancellation circuit according to claim 1, characterized in that: In the acquisition state, the second switch and the seventh switch are closed, and the other switches are opened, and the second amplifier is not in the working state.

3. The offset cancellation circuit according to claim 2, characterized in that: In the storage state, the second switch, the sixth switch and the seventh switch are closed, and the other switches are opened, the offset voltage is stored on the second capacitor, the voltage on the first capacitor maintains the voltage in the acquisition state, and the voltage stored in the third capacitor is 0.

4. The offset cancellation circuit according to claim 1, characterized in that: In the maintaining state, the first switch, the third switch and the fifth switch are closed, and the remaining switches are opened.

5. The offset cancellation circuit according to claim 1, characterized in that: The filter is a high pass filter.

6. The offset cancellation circuit according to claim 1, characterized in that: The first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch and the seventh switch are all CMOS switches.

7. The offset cancellation circuit according to claim 1, characterized in that: The operational amplifier used by the first amplifier and the second amplifier is one of LM741, AD829, LM324, TL071 and OPA2134.

8. The offset cancellation circuit according to claim 1, characterized in that: The comparator is one of LM324, LM358, TL081, LM339, LM393 and OP27.

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