Viterbi decoder with double read-out backtracking ping-pong structure and data transmission and backtracking method

Abstract

The invention discloses a Viterbi decoder with a double-read backtracking ping-pong structure and a data transmission and backtracking method. The Viterbi decoder comprises an input stream data selection unit, an output stream selection unit and a data buffer area, wherein the data buffer area comprises a first data buffer area and a second data buffer area; the first data buffer area and the second data buffer area are respectively connected with the input stream data selection unit and the output stream selection unit; the input stream data selection unit is further connected with the upstream module, and the output stream selection unit is further connected with the downstream module. In the invention, based on the expansion and deepening of the existing Viterbi decoder technology, the system rate is increased to the maximum by adding a ping-pong structure, and the existing DRTB structure is not changed too much.

Description

Technical Field

[0001] The invention belongs to the technical field of decoders, and in particular relates to a Viterbi decoder with a double-readout backtracking ping-pong structure, a data transmission and backtracking method. Background Art

[0002] The Viterbi decoding algorithm is a maximum likelihood decoding algorithm, first proposed by Viterbi in 1967. The algorithm uses a trellis diagram to describe the state transition in the encoding process, and uses branch metrics and path metrics to select the most likely decoding path. The branch metric represents the difference between the output codeword corresponding to each path in the trellis diagram and the received codeword, while the path metric is the cumulative result of the branch metric values ​​of the most likely path to each state node in the trellis diagram.

[0003] In the prior art, for example, the technical solution described in the patent with publication number CN117978321A is: a decoding method applied to a Viterbi decoder, which evaluates the channel quality through the Viterbi decoder, and adjusts the traceback length and the decoding length according to the evaluation results, thereby achieving adaptive adjustment of the channel quality to improve decoding performance and reduce power consumption.

[0004] The Viterbi decoder in the prior art often uses a method of backtracking once per clock cycle to perform backtracking (TB) when the backtracking depth is reached. For a memory with a depth of 2L, backtracking requires 2L clock cycles, and the decoding delay is relatively large. For the Viterbi decoder of the punctured convolutional code (n, 1, K), a zero padding operation must be performed before it is sent to the decoder for decoding. Generally, after n soft values ​​enter the zero padding module in parallel in one clock cycle, at least two clock cycles of zero padding data must be generated and output to the decoder in parallel in sequence. If a clock cycle can only be backtracked once, the soft value input to the decoder needs to wait for at least one clock cycle, otherwise the decoding rate cannot keep up with the input rate, and the memory overflows or data is overwritten, causing decoding errors, which seriously limits the decoder throughput. Summary of the invention

[0005] The purpose of the present invention is to provide a Viterbi decoder, data transmission and backtracking method with a dual readout backtracking ping-pong structure to solve the problem in the prior art proposed in the background technology that the decoding rate cannot keep up with the input rate, the memory overflows or data is overwritten to cause decoding errors, and the throughput of the decoder is seriously limited.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A Viterbi decoder with a dual-readout traceback ping-pong structure comprises an input stream data selection unit, an output stream selection unit and a data buffer; wherein the data buffer comprises a first data buffer and a second data buffer; the first data buffer and the second data buffer are connected to the input stream data selection unit and the output stream selection unit respectively;

[0008] The input stream data selection unit is also connected to the upstream module, and the output stream selection unit is also connected to the downstream module.

[0009] According to the above technical solution, the data buffer adopts RAM or FIFO.

[0010] According to the above technical solution, using the Viterbi decoder according to any one of claims 1 to 2, the data transmission method of the Viterbi decoder comprises the following steps:

[0011] Step S1, the input data stream is allocated to the data buffer through the input stream data selection unit;

[0012] Step S2, when data is allocated to the data buffer, the data buffer allocates data alternately to the first data buffer and the second data buffer;

[0013] Step S3: the data buffer outputs the data to the output stream selection unit.

[0014] According to the above technical solution, in step S2, the data buffer is alternately allocated as follows: when the first data buffer is full, the input stream data selection unit writes the data into the second buffer, and passes the data in the first data buffer to the output stream selection unit; when the second buffer is full, the data is written into the first buffer through the input stream data selection unit, and the data in the second buffer is passed to the output stream selection unit.

[0015] A data tracing back method for a Viterbi decoder with a dual readout tracing back ping-pong structure, the data tracing back method for a Viterbi decoder comprising the following steps:

[0016] Step A1, determining the backtracking starting point, that is, storing the value of the state register after reaching the backtracking depth;

[0017] Step A2, start backtracking, where at the same time only one DRTB_MEM is writing and one DRTB_MEM is backtracking; for the backtracking starting state D i With two states D that may backtrack i-1 and D i-1 At the same time, backtracking is performed, that is, when reading Di=d i D i-1 =d i-1 and D i-1 =d i-1 ;

[0018] Step A3, after reading the three traceback values ​​of step A2, determine the value of Di-1 according to the value of Di;

[0019] Step A4, repeat the above steps in the re-determined traceback state until the decoding is completed.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] In the present invention, the existing Viterbi decoder technology is expanded and deepened, and the system rate is increased to the maximum by adding a ping-pong structure, without making too many changes to the existing DRTB structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the structure of the dual readout backtracking ping-pong structure of the present invention;

[0023] Figure 2 It is a data transmission schematic diagram of the dual readout backtracking ping-pong structure of the present invention. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] Embodiment 1

[0026] like Figure 1 As shown, a Viterbi decoder with a dual readout traceback ping-pong structure includes an input stream data selection unit, an output stream selection unit, and a data buffer; wherein the data buffer includes a first data buffer and a second data buffer; the first data buffer and the second data buffer are connected to the input stream data selection unit and the output stream selection unit, respectively;

[0027] The input stream data selection unit is also connected to the upstream module, and the output stream selection unit is also connected to the downstream module.

[0028] The data buffer uses RAM or FIFO.

[0029] A data transmission method of a Viterbi decoder with a dual readout traceback ping-pong structure, the data transmission method of the Viterbi decoder comprising the following steps:

[0030] Step S1, the input data stream is allocated to the data buffer through the input stream data selection unit;

[0031] Step S2, when data is allocated to the data buffer, the data buffer allocates data alternately to the first data buffer and the second data buffer;

[0032] Step S3: the data buffer outputs the data to the output stream selection unit.

[0033] In step S2, the data buffers are alternately allocated as follows: when the first data buffer is full, the input stream data selection unit writes the data into the second buffer, and passes the data in the first data buffer to the output stream selection unit; when the second buffer is full, the data is written into the first buffer through the input stream data selection unit, and the data in the second buffer is passed to the output stream selection unit.

[0034] A data tracing back method for a Viterbi decoder with a dual readout tracing back ping-pong structure, the data tracing back method for a Viterbi decoder comprising the following steps:

[0035] Step A1, determining the backtracking starting point, that is, storing the value of the state register after reaching the backtracking depth;

[0036] Step A2, start backtracking, where at the same time only one DRTB_MEM is writing and one DRTB_MEM is backtracking; for the backtracking starting state D i With two states D that may backtrack i-1 and D i-1 At the same time, backtracking is performed, that is, when reading Di=d i D i-1 =d i-1 and D i-1 =d i-1 ;

[0037] Step A3, after reading the three traceback values ​​of step A2, determine the value of Di-1 according to the value of Di;

[0038] Step A4, repeat the above steps in the re-determined traceback state until the decoding is completed.

[0039] In the present invention, the existing Viterbi decoder technology is expanded and deepened, and the system rate is increased to the maximum by adding a ping-pong structure, without making too many changes to the existing DRTB structure.

[0040] This embodiment provides a specific implementation method.

[0041] like Figure 2As shown, step 1: determine the backtracking starting point. After reaching the backtracking depth, the state register with state 100 has the smallest path metric value (most similar), so the backtracking starting point is state 100. At this time, backtracking has not been performed, and it is unknown that the value stored therein is 0; but it can only come from state 000 and state 001.

[0042] Step 2: Start backtracking. Backtrack the backtracking starting state 100 and the possible backtracking states 000 and 001 at the same time. That is, read Di-1'=0 and Di-1''=1 at the same time as Di=0.

[0043] Step 3: While reading the three values ​​in step 2, determine whether the value of Di-1 is Di-1'=0 or Di-1''=1 according to the value of Di; since Di=0, the backtracking starting point state 100 comes from the upper branch state, that is, the 000 state. Since Di-1'=0, the next backtracking starting point is state 000.

[0044] Step 4: Repeat the above steps at the newly determined backtracking state 000 until the decoding is completed. Since steps 2 and 3 are completed in the same clock cycle, that is, backtracking is performed twice in one clock cycle.

[0045] Embodiment 2

[0046] This embodiment is a further refinement of the first embodiment.

[0047] The principle of improving system speed by ping-pong structure is as follows:

[0048] When two function blocks are connected for data flow, due to the difference in instantaneous data rate (such as the data frequency of the previous module is 100MHz and the data frequency of the next module is 50MHz) or data sequence (such as the previous module outputs data in sequence, and the next module needs to receive data in reverse order), the two modules cannot work at the same time, limiting the system performance. To solve this problem, a ping-pong buffer structure can be used to connect the two modules, which is equivalent to "trading area for speed".

[0049] The processing flow of ping-pong operation:

[0050] The input data stream is distributed alternately to two data buffers (commonly used RAM, FIFO, etc.) buffer1 and buffer2 through the data selection unit (MUX_MODULE). For example, data is distributed to buffer1 first. When buffer1 is full, MUX_MODULE switches the data stream to buffer2, and the data in buffer1 is output to the subsequent module for processing; when buffer2 is full, MUX_MODULE switches the data stream to buffer1, and the data in buffer2 is output to the subsequent module for processing, and so on.

[0051] This embodiment provides a specific implementation method.

[0052] The traditional 16x32 memory is divided into two 16x16 sub-memories "memory 1 (RAM_half0)" and "memory 2 (RAM_half1)", which store the path information of odd columns and even columns respectively, and their 4-bit depth addresses are the same. At the backtracking time t0, the depth address is 31, and one bit is selected from the 16 bits output by the two sub-memory RAM_half0 and RAM_half1 (assuming that RAM_half0 outputs d0 and RAM_half1 outputs d1), and together with the value of the current state address (set to [a3, a2, a1, a0]), the state address of the next clock cycle is obtained (the state address is shifted left by two bits and then spliced ​​with d0 and d1 to obtain [a1, a0, d0, d1]). At the next backtracking time, the above process is repeated, the depth address is 30, and To the state address [d0, d1, d0', d1']; and so on, until the backtracking time t31, the depth address is 0, and the final state address is obtained. During the backtracking process, it should be noted that the upper two bits of the state address value at each moment (such as a3, a2 in [a3, a2, a1, a0] at time t0) are the decoding results generated during the backtracking process. In addition, since the bit value d1 selected by RAM_half1 is determined by the output d0 of RAM_half0, if d0==0, then d1==d1', if d0==1, then d1==d1", RAM_half1 can be divided into two sub-memories of size 16x16, "memory 2A (RAM_half1A)" and "memory 2B (RAM_half1B)", which store the path information of odd states and even states respectively. The data read from RAM_half0 is used as the control signal, and a two-to-one circuit (2MUX1) is used to select one of the two data read from the two memories RAM_half1A and RAM_half1B. Then, the depth address of each memory is reduced by 1, and the state address is shifted left by two bits, and the data read from "memory 1" and the data selected by the two-to-one circuit are used as its lower two bits to form a new state address.

[0053] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0054] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A Viterbi decoder with a dual readout traceback ping-pong structure, characterized in that: It includes an input stream data selection unit, an output stream selection unit and a data buffer; wherein the data buffer includes a first data buffer and a second data buffer; the first data buffer and the second data buffer are connected to the input stream data selection unit and the output stream selection unit respectively; The input stream data selection unit is also connected to the upstream module, and the output stream selection unit is also connected to the downstream module.

2. The Viterbi decoder with dual readout traceback ping-pong structure according to claim 1, characterized in that: The data buffer uses RAM or FIFO.

3. A data transmission method of a Viterbi decoder with a dual readout traceback ping-pong structure, characterized in that: Using the Viterbi decoder according to any one of claims 1 to 2, the data transmission method of the Viterbi decoder comprises the following steps: Step S1, the input data stream is allocated to the data buffer through the input stream data selection unit; Step S2, when data is allocated to the data buffer, the data buffer allocates data alternately to the first data buffer and the second data buffer; Step S3: the data buffer outputs the data to the output stream selection unit.

4. The data transmission method of the Viterbi decoder with dual readout traceback ping-pong structure according to claim 3, characterized in that: In step S2, the data buffers are alternately allocated as follows: when the first data buffer is full, the input stream data selection unit writes the data into the second buffer, and passes the data in the first data buffer to the output stream selection unit; when the second buffer is full, the data is written into the first buffer through the input stream data selection unit, and the data in the second buffer is passed to the output stream selection unit.

5. A data traceback method for a Viterbi decoder with a dual readout traceback ping-pong structure, characterized in that: Using the Viterbi decoder according to any one of claims 1 to 2, the data traceback method of the Viterbi decoder comprises the following steps: Step A1, determining the backtracking starting point, that is, storing the value of the state register after reaching the backtracking depth; Step A2, start backtracking, where at the same time only one DRTB_MEM is writing and one DRTB_MEM is backtracking; for the backtracking starting state D i With two states D that may backtrack i-1 and D i-1 At the same time, backtracking is performed, that is, when Di=d is read out i D i-1 =d i-1 and D i-1 =d i-1 ; Step A3, after reading the three traceback values ​​of step A2, determine the value of Di-1 according to the value of Di; Step A4, repeat the above steps in the re-determined traceback state until the decoding is completed.

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