Time synchronization method and device, switching equipment and computer readable storage medium

Abstract

The invention relates to a time synchronization method and device, switching equipment and a computer readable storage medium. The method is applied to a switching chip in switching equipment. The precise time protocol domain where the switching equipment is located comprises adjacent equipment of the switching equipment; the method comprises the following steps: acquiring clock mode data; under the condition that the clock mode data represents a point-to-point transparent clock, assigning a path delay amount between the switching equipment and adjacent equipment to a point-to-point delay parameter corresponding to the adjacent equipment; under the condition that the clock mode data represents the end-to-end transparent clock, the point-to-point delay parameter is set to be zero; receiving a synchronization protocol frame sent by adjacent equipment, and determining a receiving timestamp; updating a correction domain in the synchronization protocol frame according to the point-to-point delay parameter; forwarding the synchronization protocol frame, and determining a sending timestamp; before the correction domain is forwarded, the correction domain is updated according to a difference between the transmit timestamp and the receive timestamp. By adopting the method, the precision of time synchronization can be ensured.

Description

Technical Field

[0001] The present application relates to the field of network technology, and in particular to a time synchronization method, apparatus, switching device and computer-readable storage medium. Background Art

[0002] IEEE 1588 is a precision clock synchronization protocol standard for network measurement and control systems, which accurately defines PTP (Precision Time Protocol). In a PTP domain, the internal forwarding delay between devices will affect the synchronization accuracy. Therefore, IEEE 1588 introduces the concept of transparent clock.

[0003] In traditional technologies, the software layer is responsible for processing received PTP frames and calculating forwarding delays. However, when the software processes received PTP frames, it is affected by factors such as the operating system's scheduling strategy and protocol stack processing efficiency, and the accuracy of time synchronization cannot be guaranteed. Summary of the invention

[0004] Based on this, it is necessary to provide a time synchronization method, apparatus, switching device and computer-readable storage medium that can ensure the accuracy of time synchronization in response to the above technical problems.

[0005] In a first aspect, the present application provides a time synchronization method, which is applied to a switching chip in a switching device; the precision time protocol domain where the switching device is located includes adjacent devices of the switching device; The method comprises: Get clock mode data; In the case where the clock mode data represents a point-to-point transparent clock, assigning a path delay between the switching device and the adjacent device to a point-to-point delay parameter corresponding to the adjacent device; In a case where the clock mode data represents an end-to-end transparent clock, setting a point-to-point delay parameter corresponding to the adjacent device to zero; Receiving a synchronization protocol frame sent by the adjacent device, and determining a receiving timestamp corresponding to the synchronization protocol frame; updating a correction field in the synchronization protocol frame according to the point-to-point delay parameter; Forwarding the synchronization protocol frame, and determining a sending timestamp corresponding to the synchronization protocol frame; Before the correction field in the synchronization protocol frame is forwarded, the correction field in the synchronization protocol frame is updated according to the difference between the sending timestamp and the receiving timestamp corresponding to the synchronization protocol frame.

[0006] In a second aspect, the present application also provides a time synchronization device, including: An acquisition module, used for acquiring clock mode data through a switching chip in a switching device; the precision time protocol domain where the switching device is located includes adjacent devices of the switching device; A mode setting module, configured to assign a path delay between the switching device and the adjacent device to a point-to-point delay parameter corresponding to the adjacent device when the clock mode data represents a point-to-point transparent clock; and to set the point-to-point delay parameter corresponding to the adjacent device to zero when the clock mode data represents an end-to-end transparent clock; A receiving module, used for receiving a synchronization protocol frame sent by the adjacent device, and determining a receiving timestamp corresponding to the synchronization protocol frame; A first updating module, configured to update a correction field in the synchronization protocol frame according to the point-to-point delay parameter; A sending module, used for forwarding the synchronization protocol frame and determining a sending timestamp corresponding to the synchronization protocol frame; The second updating module is used to update the correction field in the synchronization protocol frame according to the difference between the sending timestamp and the receiving timestamp corresponding to the synchronization protocol frame before the correction field in the synchronization protocol frame is forwarded.

[0007] In a third aspect, the present application further provides a switching device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps in the above method when executing the computer program.

[0008] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps in the above method when executed by a processor.

[0009] In a fifth aspect, the present application also provides a computer program product, including a computer program, which implements the steps in the above method when executed by a processor.

[0010] The above-mentioned time synchronization method, device, switching device, storage medium and computer program product obtain clock mode data through the switching chip in the switching device; when the clock mode data represents a point-to-point transparent clock, the path delay between the switching device and the adjacent device is assigned to the point-to-point delay parameter corresponding to the adjacent device; when the clock mode data represents an end-to-end transparent clock, the point-to-point delay parameter corresponding to the adjacent device is set to zero; the clock mode data determines whether the switching chip implements an end-to-end transparent clock or a point-to-point transparent clock. For precise time protocol domains with different time synchronization requirements, different clock mode data are adaptively set to enable the switching chip to implement different clock modes to adapt to the time synchronization requirements of the precise time protocol domain, thereby ensuring the accuracy of time synchronization in the precise time protocol domain. The synchronization protocol frame sent by the adjacent device is received through the switching chip, and the receiving timestamp corresponding to the synchronization protocol frame is determined; the correction field in the synchronization protocol frame is updated according to the point-to-point delay parameter. In the point-to-point transparent clock mode, the point-to-point delay parameter corresponding to the adjacent device is equal to the path delay between the switching device and the adjacent device, while in the end-to-end transparent clock mode, the point-to-point delay parameter corresponding to the adjacent device is equal to 0. Only by changing the point-to-point delay parameter corresponding to the adjacent device, the logical multiplexing of different clock modes can be realized, which greatly reduces the calculation complexity. Then, the synchronization protocol frame is forwarded through the switching chip to determine the sending timestamp corresponding to the synchronization protocol frame; before the correction field in the synchronization protocol frame is forwarded, the correction field in the synchronization protocol frame is updated according to the difference between the sending timestamp and the receiving timestamp corresponding to the synchronization protocol frame, so that the receiver of the synchronization protocol frame can obtain accurate time information, thereby ensuring the accuracy of time synchronization in the precise time protocol domain. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A flowchart of a time synchronization method provided in an embodiment of the present application.

[0012] Figure 2 This is a diagram of the internal structure of a switching chip provided in an embodiment of the present application.

[0013] Figure 3 A simplified flowchart of a time synchronization method provided in an embodiment of the present application.

[0014] Figure 4 A structural block diagram of a time synchronization device provided in an embodiment of the present application.

[0015] Figure 5 An internal structure diagram of a switching device provided in an embodiment of the present application.

[0016] Figure 6 An internal structure diagram of another switching device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0018] In an exemplary embodiment, Figure 1 As shown, a time synchronization method is provided, which is described by taking the method applied to a switching chip in a switching device as an example, and includes the following steps 102 to 114.

[0019] Step 102, obtaining clock mode data.

[0020] The clock mode data is used to characterize the clock mode, which includes at least one of a point-to-point transparent clock mode and an end-to-end transparent clock mode.

[0021] Exemplarily, the switching chip is a core component in the switching device and is an integrated circuit for realizing data exchange. The switching device is a device in the precision time protocol domain. The precision time protocol domain refers to a network to which the precision time protocol is applied, that is, the PTP domain. There is a master clock in a precision time protocol domain, and all devices in the domain are synchronized with the master clock. The switching chip may include a non-management port for external data transmission and reception. The switching chip may obtain clock mode data from the outside through its own non-management port. The switching chip may also obtain pre-configured clock mode data from its own storage space.

[0022] In some embodiments, the switch chip may obtain pre-configured clock mode data from an external storage space through a non-management port.

[0023] Step 104: When the clock mode data represents a point-to-point transparent clock, assign the path delay between the switching device and the adjacent device to the corresponding point-to-point delay parameter of the adjacent device.

[0024] Among them, Peer-to-Peer Transparent Clock (P2PTC) is a clock mode in the Precision Time Protocol. In the peer-to-peer transparent clock clock mode, each device in the Precision Time Protocol domain is considered equal, and each device can initiate path delay measurement. Adjacent devices refer to devices in the Precision Time Protocol domain that directly establish communication links with switching devices. It can be understood that in the Precision Time Protocol domain, adjacent devices can communicate directly with switching devices without communicating through third-party devices. Path delay refers to the point-to-point delay between the switching device and the adjacent device.

[0025] Exemplarily, the switching chip can initiate path delay measurement when the clock mode data represents a point-to-point transparent clock, obtain the path delay between the switching device where the switching chip is located and the adjacent device, and use the path delay as the parameter value of the point-to-point delay parameter corresponding to the adjacent device.

[0026] Step 106: When the clock mode data represents an end-to-end transparent clock, the point-to-point delay parameter corresponding to the adjacent device is set to zero.

[0027] Among them, End-to-End Transparent Clock (E2ETC) is a clock mode in the Precision Time Protocol. In this clock mode, only the slave clock in the Precision Time Protocol domain initiates link delay measurement.

[0028] It is understandable that because the end-to-end transparent clock does not support that each device in the precision time protocol domain can initiate path delay measurement, the end-to-end transparent clock does not involve point-to-point delay. The switching chip can use zero as the parameter value of the point-to-point delay parameter corresponding to the adjacent device when the clock mode data represents the end-to-end transparent clock.

[0029] Step 108: Receive a synchronization protocol frame sent by an adjacent device, and determine a receiving timestamp corresponding to the synchronization protocol frame.

[0030] The synchronization protocol frame refers to a precise time protocol frame including a synchronization message Sync (Synchronization Message), that is, a Sync frame. The synchronization protocol frame can be generated by an adjacent device or received by an adjacent device from the precise time protocol domain. The receiving timestamp corresponding to the synchronization protocol frame is used to characterize the time when the switching chip receives the synchronization protocol frame. It can be understood that the source of the synchronization protocol frame is the master clock in the precise time protocol domain, and each device in the precise time protocol domain will forward the synchronization protocol frame to the slave clock in the precise time protocol domain.

[0031] Exemplarily, in the precision time protocol domain, the synchronization protocol frame generated by the master clock is forwarded from the upstream device to the downstream device until it is forwarded to the slave clock. The port physical layer (PHY) of the switching device can receive the synchronization protocol frame from the upstream adjacent device. In the switching device, the synchronization protocol frame is transmitted from the port physical layer to the switching chip. The switching chip can determine the timestamp when it receives the target field in the synchronization protocol frame, and obtain the receiving timestamp corresponding to the synchronization protocol frame.

[0032] It can be understood that although the frame is logically regarded as a whole, the fields in the frame have a sequence in physical transmission. By selecting a target field, recording the receiving timestamp corresponding to the frame when the target field in the frame is received, and recording the sending timestamp corresponding to the frame when the target field in the frame is sent, the accuracy of the timestamp recording in the switching chip can be guaranteed.

[0033] In some embodiments, the target field may be, but is not limited to, a preamble or a frame start delimiter, etc.

[0034] Step 110: Update the correction field in the synchronization protocol frame according to the point-to-point delay parameter.

[0035] The correction field is used to compensate for the transmission delay in the precision time protocol domain.

[0036] Exemplarily, the switching chip can update the correction field in the synchronization protocol frame by superimposing the point-to-point delay parameter on the field value of the correction field in the synchronization protocol frame. Assuming that the field value of the correction field in the synchronization protocol frame is recorded as Tcf, the point-to-point delay parameter is recorded as PDelay, and the field value of the updated correction field is recorded as Tcf', then Tcf'=Tcf+PDelay.

[0037] Step 112: forward the synchronization protocol frame and determine the sending timestamp corresponding to the synchronization protocol frame.

[0038] The sending timestamp corresponding to the synchronization protocol frame is used to indicate the time when the switching chip forwards the synchronization protocol frame.

[0039] Exemplarily, the switching chip may forward the synchronization protocol frame to a downstream adjacent device, determine the timestamp when the switching chip forwards the target field in the synchronization protocol frame, and obtain a sending timestamp corresponding to the synchronization protocol frame.

[0040] In some embodiments, the switching chip may forward the synchronization protocol frame to a port physical layer of the switching device, and send the synchronization protocol frame to a precision time protocol domain through the port physical layer.

[0041] Step 114: before the correction field in the synchronization protocol frame is forwarded, update the correction field in the synchronization protocol frame according to the difference between the sending timestamp and the receiving timestamp corresponding to the synchronization protocol frame.

[0042] Exemplarily, the physical transmission order of the target field in the synchronization protocol frame takes precedence over the correction field. The switching chip can determine the timestamp when it forwards the target field in the synchronization protocol frame, and before forwarding the correction field in the synchronization protocol frame itself, it updates the correction field in the synchronization protocol frame by superimposing the difference between the sending timestamp and the receiving timestamp corresponding to a synchronization protocol frame on the field value of the correction field in the synchronization protocol frame. The correction field in the synchronization protocol frame sent by the switching chip is the correction field updated according to the difference between the sending timestamp and the receiving timestamp corresponding to the synchronization protocol frame. Assume that the field value of the correction field in the synchronization protocol frame is denoted as Tcf, the sending timestamp and the receiving timestamp corresponding to the synchronization protocol frame are denoted as T2 and T1 respectively, and the field value of the updated correction field is denoted as Tcf', then Tcf'=Tcf+T2-T1.

[0043] In the above time synchronization method, the clock mode data is obtained through the switching chip in the switching device; when the clock mode data represents a point-to-point transparent clock, the path delay between the switching device and the adjacent device is assigned to the point-to-point delay parameter corresponding to the adjacent device; when the clock mode data represents an end-to-end transparent clock, the point-to-point delay parameter corresponding to the adjacent device is set to zero; the clock mode data determines whether the switching chip implements an end-to-end transparent clock or a point-to-point transparent clock. For precise time protocol domains with different time synchronization requirements, different clock mode data are adaptively set to enable the switching chip to implement different clock modes to adapt to the time synchronization requirements of the precise time protocol domain, thereby ensuring the accuracy of time synchronization in the precise time protocol domain. The synchronization protocol frame sent by the adjacent device is received through the switching chip, and the receiving timestamp corresponding to the synchronization protocol frame is determined; the correction field in the synchronization protocol frame is updated according to the point-to-point delay parameter. In the point-to-point transparent clock mode, the point-to-point delay parameter corresponding to the adjacent device is equal to the path delay between the switching device and the adjacent device, while in the end-to-end transparent clock mode, the point-to-point delay parameter corresponding to the adjacent device is equal to 0. Only by changing the point-to-point delay parameter corresponding to the adjacent device, the logical multiplexing of different clock modes can be realized, which greatly reduces the calculation complexity. Then, the synchronization protocol frame is forwarded through the switching chip to determine the sending timestamp corresponding to the synchronization protocol frame; before the correction field in the synchronization protocol frame is forwarded, the correction field in the synchronization protocol frame is updated according to the difference between the sending timestamp and the receiving timestamp corresponding to the synchronization protocol frame, so that the receiver of the synchronization protocol frame can obtain accurate time information, thereby ensuring the accuracy of time synchronization in the precise time protocol domain.

[0044] In some embodiments, obtaining clock mode data includes any one of the following processing: obtaining pre-configured clock mode data from a storage space; obtaining clock mode data sent by a master clock in a precision time protocol domain; obtaining negotiated clock mode data by negotiating with devices other than switching devices in the precision time protocol domain.

[0045] In some embodiments, the flash memory of the switch chip is pre-configured with clock mode data. The switch chip can obtain the pre-configured clock mode data from its own flash memory.

[0046] In some embodiments, the master clock can send clock mode data to the precision time protocol domain. In the precision time protocol domain, the clock mode data will be transmitted to the neighboring device of the switching device, and the neighboring device will further transmit the clock mode data to the switching device. In the switching device, the clock mode data will be transmitted from the port physical layer to the switching chip.

[0047] In some embodiments, the switching chip may send a negotiation request to the precision time protocol domain, and determine the clock mode data through negotiation with the device in the precision time protocol domain.

[0048] In this embodiment, the acquisition of clock mode data can be achieved by obtaining pre-configured clock mode data from a storage space, obtaining clock mode data sent by a master clock in a precision time protocol domain, or by negotiating with devices other than switching devices in the precision time protocol domain to obtain negotiated clock mode data, so that the switching chip can implement the clock mode represented by the clock mode data to adapt to the time synchronization requirements of the precision time protocol domain and ensure the accuracy of time synchronization in the precision time protocol domain.

[0049] In some embodiments, when the clock mode data represents a point-to-point transparent clock, the path delay between the switching device and the adjacent device is assigned to the point-to-point delay parameter corresponding to the adjacent device, including: when the clock mode data represents a point-to-point transparent clock, generating a first peer delay request protocol frame, and using the timestamp when the first peer delay request protocol frame is generated as the original timestamp in the first peer delay request protocol frame; sending the first peer delay request protocol frame to the adjacent device, determining the sending timestamp corresponding to the first peer delay request protocol frame; and correcting the domain in the first peer delay request protocol frame. Before being sent, the correction field in the first peer delay request protocol frame is updated according to the difference between the sending timestamp corresponding to the first peer delay request protocol frame and the original timestamp in the first peer delay request protocol frame; the first peer delay response protocol frame replied by the adjacent device to the first peer delay request protocol frame is received, and the receiving timestamp corresponding to the first peer delay response protocol frame is determined; the path delay amount between the switching device and the adjacent device is determined according to the first peer delay response protocol frame and the receiving timestamp corresponding to the first peer delay response protocol frame; the path delay amount is assigned to the corresponding point-to-point delay parameter of the adjacent device.

[0050] The peer delay request protocol frame refers to a precise time protocol frame including a peer delay request message (Peer Delay Request Message, PDelay_Req). The peer delay response protocol frame refers to a precise time protocol frame including a peer delay response message (Peer Delay Response Message, PDelay_Resp).

[0051] Exemplarily, the switching chip may include a management unit. The switching chip may obtain the first peer delay request protocol frame generated by the management unit through the management port when the clock mode data represents a point-to-point transparent clock. The management unit may obtain a timestamp from a local time counter when generating the first peer delay request protocol frame, and use the timestamp as an original timestamp (Origin Timestamp) in the first peer delay request protocol frame.

[0052] The switching chip may send the first peer delay request protocol frame to the port physical layer of the switching device, and send the first peer delay request to the adjacent device through the port physical layer of the switching device. The switching chip may obtain a timestamp from a local time counter when sending the target field in the first peer delay request protocol frame, and use the timestamp as a sending timestamp corresponding to the first peer delay request protocol frame.

[0053] The physical transmission order of the target field in the first peer delay request protocol stack takes precedence over the correction field. The switching chip can update the correction field in the first peer delay request protocol frame by superimposing the difference between the sending timestamp corresponding to the first peer delay request protocol frame and the original timestamp in the first peer delay request protocol frame to the field value of the correction field in the first peer delay request protocol frame before sending the correction field in the first peer delay request protocol frame. The first peer delay request protocol frame finally sent by the switching chip, wherein the correction field is the correction field updated according to the difference between the sending timestamp corresponding to the first peer delay request protocol frame and the original timestamp in the first peer delay request protocol frame. Assume that the field value of the correction field in the first peer delay request protocol frame is recorded as Tcf, the sending timestamp corresponding to the first peer delay request protocol frame and the original timestamp in the first peer delay request protocol frame are recorded as T2 and To respectively, and the field value of the updated correction field is recorded as Tcf', then Tcf'=Tcf+T2-To.

[0054] An adjacent device may receive a first peer delay request protocol frame, determine the timestamp when the first peer delay request protocol frame is received, and obtain a receiving timestamp corresponding to the first peer delay request protocol frame. A first peer delay response protocol frame is generated for the first peer delay request protocol frame. Among them, the correction field in the first peer delay response protocol frame is the same as the correction field in the first peer delay request protocol frame. A first peer delay response protocol frame is sent, the timestamp when the first peer delay response protocol frame is sent is determined, and a sending timestamp corresponding to the first peer delay response protocol frame is obtained. Before the adjacent device sends the correction field in the first peer delay response protocol frame, the adjacent device may update the correction field in the first peer delay response protocol frame by superimposing the difference between the sending timestamp corresponding to the first peer delay response protocol frame and the receiving timestamp corresponding to the first peer delay request protocol frame onto the field value of the correction field in the first peer delay response protocol frame.

[0055] The switching chip can receive the first peer delayed response protocol frame through the port physical layer of the switching device, and obtain a timestamp from a local time counter when it receives the target field in the first peer delayed response protocol frame to obtain a receiving timestamp corresponding to the first peer delayed response protocol frame.

[0056] The switch chip can determine the path delay between the switch device and the adjacent device through the management unit according to the first peer delay response protocol frame and the receiving timestamp corresponding to the first peer delay response protocol frame, and use the path delay as the point-to-point delay parameter corresponding to the adjacent device.

[0057] In some embodiments, the switching device may include a management unit, and the management unit may be a functional unit outside the switching chip.

[0058] In this embodiment, when the clock mode data represents a point-to-point transparent clock, the switching chip generates a first peer delay request protocol frame and uses the timestamp when the first peer delay request protocol frame is generated as the original timestamp in the first peer delay request protocol frame; sends the first peer delay request protocol frame to the adjacent device, determines the sending timestamp corresponding to the first peer delay request protocol frame, and actively initiates path delay measurement to the adjacent device. In addition, considering the delay inside the switching chip, before the correction domain in the first peer delay request protocol frame is sent, the correction domain in the first peer delay request protocol frame is updated according to the difference between the sending timestamp corresponding to the first peer delay request protocol frame and the original timestamp in the first peer delay request protocol frame, so as to ensure that the original timestamp and the correction domain in the first peer delay request protocol frame jointly indicate an accurate sending timestamp, thereby ensuring time accuracy. Afterwards, the switching chip receives the first peer delay response protocol frame replied by the adjacent device to the first peer delay request protocol frame, and determines the receiving timestamp corresponding to the first peer delay response protocol frame. Furthermore, the switching chip determines the path delay between the switching device and the adjacent device based on the first peer delay response protocol frame and the receiving timestamp corresponding to the first peer delay response protocol frame; and assigns the path delay to the point-to-point delay parameter corresponding to the adjacent device, thereby ensuring the accuracy of time synchronization.

[0059] In some embodiments, the switching chip includes a management port and a non-management port; the management port is a port for the management unit to send and receive data; the non-management port is a port for the switching chip to send and receive data externally; receiving a first opposite-end delay response protocol frame that an adjacent device replies to a first opposite-end delay request protocol frame, and determining a receiving timestamp corresponding to the first opposite-end delay response protocol frame, including: receiving a first opposite-end delay response protocol frame that an adjacent device replies to the first opposite-end delay request protocol frame through a non-management port, and determining a receiving timestamp corresponding to the first opposite-end delay response protocol frame through a transceiver processing unit of the non-management port; the method also includes: sending the first opposite-end delay response protocol frame to the management port; receiving the first opposite-end delay response protocol frame through the management port; The sending processing unit adds a preset tag header and a receiving timestamp corresponding to the first opposite-end delayed response protocol frame to the first opposite-end delayed response protocol frame; transmits the first opposite-end delayed response protocol frame to the management unit through the management port; parses the receiving timestamp corresponding to the first opposite-end delayed response protocol frame from the first opposite-end delayed response protocol frame according to the preset tag header by the management unit; determines the path delay amount between the switching device and the adjacent device according to the first opposite-end delayed response protocol frame and the receiving timestamp corresponding to the first opposite-end delayed response protocol frame, including: determining the path delay amount between the switching device and the adjacent device according to the first opposite-end delayed response protocol frame and the receiving timestamp corresponding to the first opposite-end delayed response protocol frame by the management unit.

[0060] Exemplarily, the non-management port is a port through which the switching chip exchanges data with the port physical layer of the switching device. Each non-management port has a corresponding transceiver processing unit. The first peer delayed response protocol frame replied by the adjacent device will first be sent to the port physical layer of the switching device, and the first peer delayed response protocol frame will be transmitted to the switching chip through the non-management port, and the switching chip can receive the first peer delayed response protocol frame. The transceiver processing unit may include a receiving processing unit and a sending processing unit. The switching chip can obtain a timestamp from a local time counter when it receives the target field in the first peer delayed response protocol frame through the receiving processing unit of the non-management port, and obtain a receiving timestamp corresponding to the first peer delayed response protocol frame.

[0061] The receiving processing unit may send the first peer delayed response protocol frame to the management port. The transceiver processing unit of the management port may transmit the receiving timestamp corresponding to the first peer delayed response protocol frame to the management unit by embedding a preset tag header in the first peer delayed response protocol frame. Specifically, the switching chip may combine the preset tag header and the receiving timestamp corresponding to the first peer delayed response protocol frame into a tag through the transceiver processing unit of the management port, and then add it to the source Media Access Control (MAC) address field of the first peer delayed response protocol frame.

[0062] The switching chip can transmit the first peer delayed response protocol frame to the management port through the sending processing unit of the non-management port, and transmit the first peer delayed response protocol frame to the management unit through the management port. The switching chip can parse the first peer delayed response protocol frame through the management unit, and use the preset number of bytes of data after the preset tag header as the receiving timestamp corresponding to the first peer delayed response protocol frame. For example, the preset tag header is 0xE001, and the timestamp is 6 bytes, forming an 8-byte tag. The management unit can parse the preset tag header 0xE001, and use the 6 bytes of data after the preset tag header as the receiving timestamp corresponding to the first peer delayed response protocol frame.

[0063] The switching chip can determine the path delay amount through the management unit according to the original timestamp and correction field in the first peer delay response protocol frame and the receiving timestamp corresponding to the first peer delay response protocol frame.

[0064] In some embodiments, the switching chip can calculate the time difference between the received timestamp corresponding to the first peer delayed response protocol frame and the original timestamp in the first peer delayed response protocol frame through the management unit, and calculate half of the difference between the time difference and the field value in the first peer delayed response protocol frame to obtain the path delay amount.

[0065] In this embodiment, the switching chip receives a first peer delayed response protocol frame that is a reply of an adjacent device to a first peer delayed request protocol frame through a non-management port, and determines a receiving timestamp corresponding to the first peer delayed response protocol frame through a transceiver processing unit of the non-management port; sends the first peer delayed response protocol frame to a management port; adds a preset tag header and a receiving timestamp corresponding to the first peer delayed response protocol frame to the first peer delayed response protocol frame through the transceiver processing unit of the management port; transmits the first peer delayed response protocol frame to the management unit through the management port; and embeds the receiving timestamp corresponding to the first peer delayed response protocol frame into the first peer delayed response protocol frame and transmits it to the management unit together without sending the above-mentioned receiving timestamp to the management unit separately, thereby reducing resource allocation. Furthermore, the management unit parses the receiving timestamp corresponding to the first peer delayed response protocol frame from the first peer delayed response protocol frame according to the preset tag header; the management unit can accurately determine the path delay between the switching device and the adjacent device according to the first peer delayed response protocol frame and the receiving timestamp corresponding to the first peer delayed response protocol frame, thereby ensuring the accuracy of time synchronization.

[0066] In some embodiments, the switching chip includes a local time counter; receiving a synchronization protocol frame sent by an adjacent device, and determining a receiving timestamp corresponding to the synchronization protocol frame, including: receiving a synchronization protocol frame from an adjacent device, and obtaining a timestamp from the local time counter when a frame start delimiter in the synchronization protocol frame is received, to obtain a receiving timestamp corresponding to the synchronization protocol frame; forwarding the synchronization protocol frame, and determining a sending timestamp corresponding to the synchronization protocol frame, including: forwarding the synchronization protocol frame, and obtaining a timestamp from the local time counter when a frame start delimiter in the synchronization protocol frame is sent, to obtain a sending timestamp corresponding to the synchronization protocol frame.

[0067] Exemplarily, the target field may be, but is not limited to, a frame start delimiter. The switching chip may receive a synchronization protocol frame from an adjacent device through a non-management port, and when a frame start delimiter in the synchronization protocol frame is received through a receiving processing unit of the non-management port, a timestamp is obtained from a local time counter to obtain a receiving timestamp corresponding to the synchronization protocol frame.

[0068] The switching chip can forward the synchronization protocol frame through the non-management port, and obtain the timestamp from the local time counter when the frame start delimiter in the synchronization protocol frame is sent through the sending processing port of the non-management port to obtain the sending timestamp corresponding to the synchronization protocol frame.

[0069] In this embodiment, by receiving a synchronization protocol frame from an adjacent device, a timestamp is obtained from a local time counter when a frame start delimiter in the synchronization protocol frame is received, and a receiving timestamp corresponding to the synchronization protocol frame is obtained; when forwarding the synchronization protocol frame, a timestamp is obtained from a local time counter when a frame start delimiter in the synchronization protocol frame is sent, and a sending timestamp corresponding to the synchronization protocol frame is obtained. The frame start delimiter is selected as a unified mark for the switching chip to record the receiving timestamp and sending timestamp when it receives and forwards the synchronization protocol frame, ensuring that the difference between the receiving timestamp and the sending timestamp can accurately indicate the delay from the switching chip receiving the synchronization protocol frame to forwarding the synchronization protocol frame.

[0070] In some embodiments, the method also includes: receiving a delay request protocol frame sent by an adjacent device, and determining a receiving timestamp corresponding to the delay request protocol frame; forwarding the delay request protocol frame, and determining a sending timestamp corresponding to the delay request protocol frame; and updating the correction field in the delay request protocol frame according to the difference between the sending timestamp and the receiving timestamp corresponding to the delay request protocol frame before the correction field in the delay request protocol frame is forwarded.

[0071] The delay request protocol frame refers to a precision time protocol frame including a delay request message (Delay Request Message, Delay_Req). It can be understood that the source of the delay request protocol frame is the slave clock in the precision time protocol domain, and each device in the precision time protocol domain will forward the delay request protocol frame to the master clock in the precision time protocol domain.

[0072] Exemplarily, in the precision time protocol domain, the delay request protocol frame generated by the slave clock will be forwarded from the downstream device to the upstream device until it is forwarded to the master clock. The switching chip can receive the delay request protocol frame from the downstream adjacent device through the non-management port, and when the receiving processing unit of the management port receives the target field in the delay request protocol frame, obtain the timestamp from the local time counter to obtain the receiving timestamp corresponding to the delay request protocol frame.

[0073] The switching chip can update the correction field in the delay request protocol frame according to the point-to-point delay parameter. Specifically, the switching chip can update the correction field in the delay request protocol frame by superimposing the point-to-point delay parameter on the field value of the correction field in the delay request protocol frame.

[0074] The switching chip can forward the delay request protocol frame to the port physical layer of the switching device through the sending processing unit of the non-management port, and obtain the timestamp from the local time counter when forwarding the target field in the delay request protocol frame to obtain the sending timestamp corresponding to the delay request protocol frame. The switching chip can forward the delay request protocol frame to the upstream adjacent device through the port physical layer of the switch. The physical transmission order of the target field in the delay request protocol frame takes precedence over the correction field in the delay request protocol frame. Before forwarding the correction field in the delay request protocol frame by itself, the switching chip can update the correction field in the delay request protocol frame according to the difference between the sending timestamp and the receiving timestamp corresponding to the delay request protocol frame through the sending processing unit of the non-management port.

[0075] In some embodiments, the switching chip can update the correction field in the delay request protocol frame by adding the difference between the sending timestamp and the receiving timestamp corresponding to the delay request protocol frame to the correction field in the delay request protocol frame before the correction field in the delay request protocol frame is forwarded. Assuming that the field value of the correction field in the delay request protocol frame is recorded as Tcf, the sending timestamp and the receiving timestamp corresponding to the delay request protocol frame are recorded as T2 and T1 respectively, and the field value of the updated correction field is recorded as Tcf', then Tcf'=Tcf+T2-T1.

[0076] In this embodiment, the switching chip receives a delay request protocol frame sent by an adjacent device and determines a receiving timestamp corresponding to the delay request protocol frame; forwards the delay request protocol frame and determines a sending timestamp corresponding to the delay request protocol frame; before the correction field in the delay request protocol frame is forwarded, the correction field in the delay request protocol frame is updated according to the difference between the sending timestamp and the receiving timestamp corresponding to the delay request protocol frame, so that the correction field can accurately indicate the residence time of the delay request protocol frame in the switching device, thereby ensuring the accuracy of time synchronization.

[0077] In some embodiments, the method also includes: receiving a second peer delay request protocol frame sent by an adjacent device, determining a receive timestamp corresponding to the second peer delay request protocol frame; modifying the second peer delay request protocol frame to obtain a second peer delay response protocol frame; sending a second peer delay response protocol frame to the adjacent device, determining a send timestamp corresponding to the second peer delay response protocol frame; and updating a correction field in the second peer delay response protocol frame according to a difference between a send timestamp corresponding to the second peer delay response protocol frame and a receive timestamp corresponding to the second peer delay request protocol frame before the correction field of the second peer delay response protocol frame is sent.

[0078] Exemplarily, the adjacent device can actively initiate the path delay measurement, generate the second peer delay request protocol frame, and send the second peer delay request protocol frame to the switching device. The second peer delay request protocol frame will first be sent to the port physical layer of the switching device, and then sent to the switching chip through the non-management port. The switching chip can receive the second peer delay request protocol frame through the non-management port, and when the receiving processing unit of the non-management port receives the target field in the second peer delay request protocol frame, obtain the timestamp from the local time counter to obtain the receiving timestamp corresponding to the second peer delay request protocol frame.

[0079] The switching chip may modify the second peer delay request protocol frame through the receiving processing unit to obtain a second peer delay response protocol frame.

[0080] The switching chip can send a second peer delayed response protocol frame to an adjacent device through a sending processing unit of a non-management port, and when it sends the target field in the second peer delayed response protocol frame, obtain a timestamp from a local time counter to obtain a sending timestamp corresponding to the second peer delayed response protocol frame.

[0081] The physical transmission order of the target field in the second peer delay response protocol frame takes precedence over the correction field. The switching chip can update the correction field in the second peer delay response protocol frame by superimposing the difference between the sending timestamp corresponding to the second peer delay response protocol frame and the receiving timestamp corresponding to the second peer delay request protocol frame on the field value in the correction field in the second peer delay response protocol frame through the sending processing unit of the non-management port before sending the correction field of the second peer delay response protocol frame itself.

[0082] In some embodiments, the fields in the second peer delay request protocol stack include a destination media access control (MAC) address, a source media access control (MAC) address, a two-step synchronization flag, a source port identifier, a request reception timestamp, a requesting port identifier, and a message type identifier, etc. The switching chip can modify the fields in the second peer delay request protocol frame, and the modified second peer delay request protocol frame is the second peer delay response protocol frame.

[0083] Specifically, if the destination media access control address in the second peer delay request protocol frame is a multicast address, the destination media access control address of the second peer delay request protocol frame is modified to the destination media access control address in the second peer delay request protocol frame; otherwise, the destination media access control address of the second peer delay request protocol frame is modified to the source media access control address in the second peer delay request protocol frame.

[0084] The source media access control address of the second peer delay request protocol frame is modified to the media access control address of the non-management port that directly receives the second peer delay request protocol frame sent by the adjacent device.

[0085] The message type identifier of the second peer delay request protocol frame is modified to the message type identifier of the peer delay response protocol frame. For example, if the message type identifier = 2 represents the peer delay request protocol frame, and the message type identifier = 3 represents the peer delay response protocol frame, the switching chip will change the message type identifier of the second peer delay request protocol frame to 3.

[0086] The two-step synchronization flag of the second peer delay request protocol frame is cleared. It can be understood that the second peer delay request protocol frame originates from an adjacent device, and the adjacent device can use two-step synchronization or one-step synchronization, but the switching chip uses one-step synchronization, so the two-step synchronization flag needs to be cleared.

[0087] The source port identifier of the second peer delay request protocol frame is modified to a port identifier corresponding to a non-management port that directly receives the second peer delay request protocol frame sent by the adjacent device.

[0088] The request receiving timestamp of the second peer delay request protocol frame is set to zero.

[0089] The request port identifier of the second peer delay request protocol frame is modified to the source port identifier.

[0090] After the second peer delay request protocol frame is modified as described above, the second peer delay response protocol frame can be obtained. It can be understood that the above modification is completed in the receiving processing unit of the non-management port, and no longer needs to be sent to the management unit for processing, which can avoid the delay inside the switching chip and ensure the accuracy of time synchronization.

[0091] In some embodiments, a non-management port in a switching chip that directly receives a protocol frame sent by a management port or an adjacent device is a receiving port of the protocol frame. A non-management port in a switching chip that directly sends a protocol frame to a management port or an adjacent device is a sending port of the protocol frame. It can be understood that the receiving port and the sending port of the protocol frame in the switching chip are scheduled by the switching matrix in the switching chip, and even for the same protocol frame, the receiving port and the sending port may not be the same.

[0092] In some embodiments, Figure 2 As shown, the internal structure diagram of the switching chip is provided. The switching chip includes a switching matrix, a management unit, a local time counter, a transceiver processing unit of the management port, and a receiving processing unit and a sending processing unit of the non-management port. Figure 2 Port 0, port 1, ..., port n in the switch chip are all non-management ports. The local time counter can provide timestamps to the receiving processing unit, the sending processing unit, and the management unit of the non-management port. The switching matrix can schedule the management port and the non-management port in the switching chip to realize the internal and external data exchange of the switching chip. The receiving processing unit of the non-management port is used to support the non-management port to receive protocol frames from outside the switching chip. The sending processing unit of the non-management port is used to support the non-management port to send protocol frames to the outside of the switching chip. The transceiver processing unit of the management port is used to support the management port to send protocol frames from inside the switching chip to the management unit, and to support the management port to send protocol frames from the management unit to the inside of the switching chip.

[0093] In this embodiment, the switching chip receives a second peer delay request protocol frame sent by an adjacent device, determines a receiving timestamp corresponding to the second peer delay request protocol frame; modifies the second peer delay request protocol frame to obtain a second peer delay response protocol frame; sends the second peer delay response protocol frame to the adjacent device, determines a sending timestamp corresponding to the second peer delay response protocol frame; before the correction field of the second peer delay response protocol frame is sent, updates the correction field in the second peer delay response protocol frame according to the difference between the sending timestamp corresponding to the second peer delay response protocol frame and the receiving timestamp corresponding to the second peer delay request protocol frame, so that the path delay measurement actively initiated by the adjacent device can be responded to at the hardware level of the switching chip without the involvement of the software layer, and the accuracy of time synchronization can be guaranteed.

[0094] In some embodiments, Figure 3 As shown, a simplified flow chart of the time synchronization method is provided. The switching chip includes a local time counter, a receiving processing unit and a sending processing unit of a non-management port, a switching matrix, and a sending and receiving processing unit of a management port. The switching matrix can schedule a non-management port as a sending port or a receiving port of a protocol frame. It can be understood that the non-management port that receives the protocol frame from the management port or the port physical layer of the switching device is the receiving port of the protocol frame. The non-management port to send the protocol frame to the management port or the port physical layer of the switching device is the sending port of the protocol frame.

[0095] The receiving processing unit of the receiving port can record the receiving timestamp T1 when the frame start delimiter in the protocol frame is received, and T1 will be forwarded along with the protocol frame. It can be understood that the receiving timestamp T1 is provided by the local event counter. T1 is forwarded along with the frame for use by the sending processing unit of the sending port.

[0096] The receiving processing unit of the receiving port can parse each field of the protocol frame to obtain the field value Tcr of the correction field. Specifically, the receiving processing unit can parse the fields of the currently received protocol frame while receiving the subsequent fields of the protocol frame to extract the message type identifier and the field value of the correction field.

[0097] The receiving processing unit of the receiving port can determine whether the message type identifier of the protocol frame is less than 4. If the message type identifier of the protocol frame is not less than 4, the protocol frame is not modified, and the protocol frame enters the switching matrix and is forwarded to the sending port. If the message type identifier of the protocol frame is less than 4, it is determined whether the protocol frame comes from the management port or is to be forwarded to the management port. If the protocol frame comes from the management port or is to be forwarded to the management port, the original timestamp To in the protocol frame is extracted, and the protocol frame is not modified and the subsequent steps are executed. If the protocol frame does not come from the management port or is to be forwarded to the management port, it is determined whether the message type identifier of the protocol frame is equal to 2. If the message type identifier of the protocol frame is equal to 2, the second opposite-end delay request protocol frame needs to be automatically replied, and the second opposite-end delay request protocol frame is modified to obtain the second opposite-end delay response protocol frame, and the protocol frame enters the switching matrix and is forwarded to the sending port. If the message type identifier of the protocol frame is not equal to 2, the point-to-point delay parameter is added to the correction field Tcr'=Tcr+Pdelay of the protocol frame, and the protocol frame enters the switching matrix and is forwarded to the sending port.

[0098] The protocol frames from the management port include the first peer delay request protocol frame (first PDelay_Req frame). The protocol frames to be forwarded to the management port include the first peer delay response protocol frame (first PDelay_Resp frame). The protocol frames with a message type identifier less than 4 include a synchronization (Sync) protocol frame with a message type identifier equal to 0, a delay request (Delay_Req) ​​protocol frame with a message type identifier equal to 1, a peer delay request (PDelay_Req) ​​protocol frame with a message type identifier equal to 2, and a peer delay response (PDelay_Resp) protocol frame with a message type identifier equal to 3.

[0099] It can be understood that in the synchronization process of the IEEE 1588 protocol, protocol frames with a message type identifier less than 4 include messages with a time concept, and the delay needs to be calculated. Therefore, protocol frames with a message type identifier not less than 4 do not need to be processed and are directly forwarded according to the rules. For protocol frames from the management port, it is necessary to consider the internal delay of the switch chip from the management port to the non-management port, so the original timestamp To is extracted here to facilitate the calculation of the delay. For protocol frames to be forwarded to the management port, the management unit needs to extract the original timestamp to determine the timestamp when the adjacent device sent the protocol frame, so as to facilitate the calculation of the delay.

[0100] The sending processing unit of the sending port starts to send the protocol frame and records the sending timestamp T2 when it sends the start delimiter of the protocol frame. Determine whether the message type identifier of the protocol frame is less than 4. If the message type identifier of the protocol frame is not less than 4, it is sent directly, the cyclic redundancy check (CRC) is regenerated, and the sending continues. If the message type identifier of the protocol frame is less than 4, it is determined whether the protocol frame is to be sent to the management unit. If the protocol frame is to be sent to the management unit, the label composed of the preset label header and the receiving timestamp T1 is embedded in the protocol frame, the cyclic redundancy check is regenerated, and the sending continues. If the protocol frame is not to be sent to the management unit, it is determined whether the protocol frame comes from the management port. If the protocol frame comes from the management port, the correction field Tcr=T2-To is updated, the cyclic redundancy check is regenerated, and the sending continues. If the protocol frame does not come from the management port, the correction field Tcr'=Tcr+T2-T1 is updated, the cyclic redundancy check is regenerated, and the sending continues.

[0101] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0102] Based on the same inventive concept, the embodiment of the present application also provides a time synchronization device for implementing the time synchronization method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more time synchronization device embodiments provided below can refer to the limitations on the time synchronization method above, and will not be repeated here.

[0103] In an exemplary embodiment, Figure 4 As shown, a time synchronization device 400 is provided, including: an acquisition module 402 , a mode setting module 404 , a receiving module 406 , a first updating module 408 , a sending module 410 and a second updating module 412 .

[0104] The acquisition module 402 is used to acquire clock mode data through a switching chip in a switching device; the precision time protocol domain where the switching device is located includes adjacent devices of the switching device.

[0105] The mode setting module 404 is used to assign the path delay between the switching device and the adjacent device to the point-to-point delay parameter corresponding to the adjacent device when the clock mode data represents a point-to-point transparent clock; when the clock mode data represents an end-to-end transparent clock, the point-to-point delay parameter corresponding to the adjacent device is set to zero.

[0106] The receiving module 406 is used to receive the synchronization protocol frame sent by the adjacent device and determine the receiving timestamp corresponding to the synchronization protocol frame.

[0107] The first updating module 408 is configured to update the correction field in the synchronization protocol frame according to the point-to-point delay parameter.

[0108] The sending module 410 is used to forward the synchronization protocol frame and determine the sending timestamp corresponding to the synchronization protocol frame.

[0109] The second updating module 412 is configured to update the correction field in the synchronization protocol frame according to the difference between the sending timestamp and the receiving timestamp corresponding to the synchronization protocol frame before the correction field in the synchronization protocol frame is forwarded.

[0110] In some embodiments, the acquisition module 402 is used to obtain pre-configured clock mode data from a storage space; obtain clock mode data sent by a master clock in a precision time protocol domain; and obtain negotiated clock mode data by negotiating with devices other than switching devices in the precision time protocol domain.

[0111] In some embodiments, the mode setting module 404 is used to generate a first peer delay request protocol frame when the clock mode data represents a point-to-point transparent clock, and use the timestamp when the first peer delay request protocol frame is generated as the original timestamp in the first peer delay request protocol frame; send the first peer delay request protocol frame to the adjacent device, and determine the sending timestamp corresponding to the first peer delay request protocol frame; before the correction field in the first peer delay request protocol frame is sent, update the correction field in the first peer delay request protocol frame according to the difference between the sending timestamp corresponding to the first peer delay request protocol frame and the original timestamp in the first peer delay request protocol frame; receive the first peer delay response protocol frame replied by the adjacent device to the first peer delay request protocol frame, and determine the receiving timestamp corresponding to the first peer delay response protocol frame; determine the path delay amount between the switching device and the adjacent device according to the first peer delay response protocol frame and the receiving timestamp corresponding to the first peer delay response protocol frame; assign the path delay amount to the point-to-point delay parameter corresponding to the adjacent device.

[0112] In some embodiments, the switching chip includes a management port and a non-management port; the management port is a port for the management unit to send and receive data; the non-management port is a port for the switching chip to send and receive data externally; the mode setting module 404 is used to receive a first opposite-end delay response protocol frame replied by an adjacent device to a first opposite-end delay request protocol frame through a non-management port, and determine a receiving timestamp corresponding to the first opposite-end delay response protocol frame through a transceiver processing unit of the non-management port; send the first opposite-end delay response protocol frame to the management port; add a preset tag header and a receiving timestamp corresponding to the first opposite-end delay response protocol frame to the first opposite-end delay response protocol frame through the transceiver processing unit of the management port; transmit the first opposite-end delay response protocol frame to the management unit through the management port; parse the receiving timestamp corresponding to the first opposite-end delay response protocol frame from the first opposite-end delay response protocol frame according to the preset tag header through the management unit; determine the path delay between the switching device and the adjacent device according to the first opposite-end delay response protocol frame and the receiving timestamp corresponding to the first opposite-end delay response protocol frame through the management unit.

[0113] In some embodiments, the switching chip includes a local time counter; a receiving module 406, which is used to receive a synchronization protocol frame sent by an adjacent device, and obtain a timestamp from the local time counter when a frame start delimiter in the synchronization protocol frame is received, to obtain a receiving timestamp corresponding to the synchronization protocol frame; a sending module 410, which is used to forward the synchronization protocol frame, and obtain a timestamp from the local time counter when the frame start delimiter in the synchronization protocol frame is forwarded, to obtain a sending timestamp corresponding to the synchronization protocol frame.

[0114] In some embodiments, a receiving module 406 is used to receive a delay request protocol frame sent by an adjacent device and determine a receiving timestamp corresponding to the delay request protocol frame; a sending module 410 is used to forward the delay request protocol frame and determine a sending timestamp corresponding to the delay request protocol frame; and a second updating module 412 is used to update a correction field in the delay request protocol frame according to a difference between a sending timestamp and a receiving timestamp corresponding to the delay request protocol frame before the correction field in the delay request protocol frame is forwarded.

[0115] In some embodiments, a receiving module 406 is used to receive a second peer delay request protocol frame sent by an adjacent device, determine a receiving timestamp corresponding to the second peer delay request protocol frame; modify the second peer delay request protocol frame to obtain a second peer delay response protocol frame; a sending module 410 is used to send a second peer delay response protocol frame to the adjacent device, and determine a sending timestamp corresponding to the second peer delay response protocol frame; a second updating module 412 is used to update a correction field in the second peer delay response protocol frame according to a difference between a sending timestamp corresponding to the second peer delay response protocol frame and a receiving timestamp corresponding to the second peer delay request protocol frame before the correction field of the second peer delay response protocol frame is sent.

[0116] Each module in the above-mentioned time synchronization device can be implemented in whole or in part by software, hardware or a combination thereof. Each module can be embedded in or independent of the processor in the switching device in the form of hardware, or can be stored in the memory in the switching device in the form of software, so that the processor can call and execute the corresponding operations of each module.

[0117] In an exemplary embodiment, a switching device is provided, and its internal structure diagram can be shown as follows: Figure 5 As shown. The switching device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the switching device is used to provide computing and control capabilities. The memory of the switching device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the switching device is used to exchange information between the processor and an external device. The communication interface of the switching device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a time synchronization method is implemented.

[0118] In an exemplary embodiment, a switching device is provided. The switching device may be a terminal, and its internal structure diagram may be as shown in FIG. Figure 6 As shown. The switching device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. The processor of the switching device is used to provide computing and control capabilities. The memory of the switching device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the switching device is used to exchange information between the processor and the external device. The communication interface of the switching device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be realized through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a time synchronization method is realized. The display unit of the switching device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the switching device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the switching device shell, or an external keyboard, touchpad or mouse.

[0119] Those skilled in the art will understand that Figure 5 or Figure 6 The structure shown in the figure is only a block diagram of a part of the structure related to the scheme of the present application, and does not constitute a limitation on the switching device to which the scheme of the present application is applied. The specific switching device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0120] In one embodiment, a switching device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above method embodiments when executing the computer program.

[0121] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0122] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0123] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0124] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0125] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A time synchronization method, characterized in that: A switching chip applied to a switching device; the precision time protocol domain where the switching device is located includes adjacent devices of the switching device; The method comprises: Get clock mode data; In the case where the clock mode data represents a point-to-point transparent clock, assigning a path delay between the switching device and the adjacent device to a point-to-point delay parameter corresponding to the adjacent device; In a case where the clock mode data represents an end-to-end transparent clock, setting a point-to-point delay parameter corresponding to the adjacent device to zero; Receiving a synchronization protocol frame sent by the adjacent device, and determining a receiving timestamp corresponding to the synchronization protocol frame; updating a correction field in the synchronization protocol frame according to the point-to-point delay parameter; Forwarding the synchronization protocol frame, and determining a sending timestamp corresponding to the synchronization protocol frame; Before the correction field in the synchronization protocol frame is forwarded, the correction field in the synchronization protocol frame is updated according to the difference between the sending timestamp and the receiving timestamp corresponding to the synchronization protocol frame.

2. The method according to claim 1, characterized in that The obtaining of clock mode data includes any one of the following processing: Get pre-configured clock mode data from storage space; Obtaining clock mode data sent by a master clock in the precision time protocol domain; The negotiated clock mode data is acquired by negotiating with devices other than the switching device in the precision time protocol domain.

3. The method according to claim 1, characterized in that When the clock mode data represents a point-to-point transparent clock, assigning the path delay between the switching device and the adjacent device to a point-to-point delay parameter corresponding to the adjacent device includes: In a case where the clock mode data represents a point-to-point transparent clock, generating a first peer delay request protocol frame, and using a timestamp when the first peer delay request protocol frame is generated as an original timestamp in the first peer delay request protocol frame; Sending the first peer delay request protocol frame to the adjacent device, and determining a sending timestamp corresponding to the first peer delay request protocol frame; Before the correction field in the first peer delay request protocol frame is sent, updating the correction field in the first peer delay request protocol frame according to the difference between the sending timestamp corresponding to the first peer delay request protocol frame and the original timestamp in the first peer delay request protocol frame; Receiving a first peer delay response protocol frame replied by the neighboring device to the first peer delay request protocol frame, and determining a receiving timestamp corresponding to the first peer delay response protocol frame; Determine the path delay between the switching device and the adjacent device according to the first peer delayed response protocol frame and a receiving timestamp corresponding to the first peer delayed response protocol frame; The path delay amount is assigned to the point-to-point delay parameter corresponding to the adjacent device.

4. The method according to claim 3, characterized in that The switching chip includes a management port and a non-management port; the management port is a port for the management unit to send and receive data; the non-management port is a port for the switching chip to send and receive data externally; The receiving a first peer delay response protocol frame replied by the neighboring device to the first peer delay request protocol frame, and determining a receiving timestamp corresponding to the first peer delay response protocol frame, comprises: Receiving, through the non-management port, a first peer delay response protocol frame that the adjacent device replies to the first peer delay request protocol frame, and determining, through the transceiver processing unit of the non-management port, a receiving timestamp corresponding to the first peer delay response protocol frame; The method further comprises: Sending the first peer delayed response protocol frame to the management port; Adding a preset tag header and a receiving timestamp corresponding to the first peer delayed response protocol frame to the first peer delayed response protocol frame through the transceiver processing unit of the management port; Transmitting the first peer delayed response protocol frame to the management unit through the management port; Parsing, by the management unit, the first peer delayed response protocol frame according to the preset tag header to obtain a receiving timestamp corresponding to the first peer delayed response protocol frame; The determining the path delay amount between the switching device and the adjacent device according to the first peer delayed response protocol frame and a receiving timestamp corresponding to the first peer delayed response protocol frame includes: The management unit determines the path delay amount between the switching device and the adjacent device according to the first opposite-end delayed response protocol frame and a receiving timestamp corresponding to the first opposite-end delayed response protocol frame.

5. The method according to claim 1, characterized in that The switching chip includes a local time counter; the receiving the synchronization protocol frame sent by the adjacent device and determining the receiving timestamp corresponding to the synchronization protocol frame includes: Receiving a synchronization protocol frame sent by the adjacent device, and acquiring a timestamp from the local time counter when a frame start delimiter in the synchronization protocol frame is received, to obtain a receiving timestamp corresponding to the synchronization protocol frame; The forwarding of the synchronization protocol frame and determining a sending timestamp corresponding to the synchronization protocol frame includes: The synchronization protocol frame is forwarded, and when a frame start delimiter in the synchronization protocol frame is forwarded, a timestamp is acquired from the local time counter to obtain a sending timestamp corresponding to the synchronization protocol frame.

6. The method according to claim 1, characterized in that The method further comprises: Receiving a delay request protocol frame sent by the adjacent device, and determining a receiving timestamp corresponding to the delay request protocol frame; forwarding the delay request protocol frame, and determining a sending timestamp corresponding to the delay request protocol frame; Before the correction field in the delay request protocol frame is forwarded, the correction field in the delay request protocol frame is updated according to the difference between the sending timestamp and the receiving timestamp corresponding to the delay request protocol frame.

7. The method according to any one of claims 1 to 6, characterized in that: The method further comprises: Receiving a second peer delay request protocol frame sent by the adjacent device, and determining a receiving timestamp corresponding to the second peer delay request protocol frame; Modifying the second peer delay request protocol frame to obtain a second peer delay response protocol frame; Sending the second peer delayed response protocol frame to the adjacent device, and determining a sending timestamp corresponding to the second peer delayed response protocol frame; Before the correction field of the second peer delay response protocol frame is sent, the correction field in the second peer delay response protocol frame is updated according to the difference between the sending timestamp corresponding to the second peer delay response protocol frame and the receiving timestamp corresponding to the second peer delay request protocol frame.

8. A time synchronization device, characterized in that: The device comprises: An acquisition module, used for acquiring clock mode data through a switching chip in a switching device; the precision time protocol domain where the switching device is located includes adjacent devices of the switching device; A mode setting module, configured to assign a path delay between the switching device and the adjacent device to a point-to-point delay parameter corresponding to the adjacent device when the clock mode data represents a point-to-point transparent clock; and to set the point-to-point delay parameter corresponding to the adjacent device to zero when the clock mode data represents an end-to-end transparent clock; A receiving module, used for receiving a synchronization protocol frame sent by the adjacent device, and determining a receiving timestamp corresponding to the synchronization protocol frame; A first updating module, configured to update a correction field in the synchronization protocol frame according to the point-to-point delay parameter; A sending module, used for forwarding the synchronization protocol frame and determining a sending timestamp corresponding to the synchronization protocol frame; The second updating module is used to update the correction field in the synchronization protocol frame according to the difference between the sending timestamp and the receiving timestamp corresponding to the synchronization protocol frame before the correction field in the synchronization protocol frame is forwarded.

9. A switching device, comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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