Method for forming semiconductor device and semiconductor device

Abstract

A method for forming a semiconductor device (1), the method comprising: forming a plurality of layer stacks (10a, 10b) on a substrate (4), the layer stacks being laterally spaced apart; each layer stack (10a, 10b) is converted into a field effect transistor (FET) stack (60a, 60b), each FET stack (60a, 60b) comprising a first FET (61) at a lower portion (15a, 15b) of the layer stack (10a, 10b) and a second FET (62) at an upper portion (16a, 16b) of the layer stack (10a, 10b), the first layer stack (10a) is converted into a first FET stack (60a), the first FET (61) and the second FET (62) in the first FET stack are p-type FETs, the second layer stack (10b) is converted into a second FET stack (60b), and the first FET (61) and the second FET (62) in the second FET stack (60b) are n-type FETs.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for forming the semiconductor device. Background Art

[0002] In order to realize more area- and power-efficient circuits, vertical semiconductor device structures are gaining more and more attention as an alternative to traditional planar semiconductor devices. A notable example is a stacked transistor device, which includes a complementary pair of field effect transistors (FETs) stacked on top of each other, i.e., a p-type FET (pFET) on top of an n-type FET (nFET) or vice versa. Summary of the invention

[0003] It is an object of the inventive concept to realize a compact semiconductor device. In particular, it is an object to realize a compact static random access memory. Another object of the inventive concept is to facilitate convenient and / or low-cost manufacturing of semiconductor devices. These and other objects of the inventive concept are met at least in part by the present invention as defined in the independent claims. Preferred embodiments are listed in the dependent claims.

[0004] According to a first aspect, there is provided a method for forming a semiconductor device, the method comprising:

[0005] forming a plurality of layer stacks on the substrate, the layer stacks being laterally spaced apart, each layer stack comprising channel layers of semiconductor material spaced apart by sacrificial layers, the plurality of layer stacks comprising at least a first layer stack and a second layer stack, each layer stack having a lower portion and an upper portion, the lower portion and the upper portion each comprising at least one channel layer;

[0006] For each layer stack, a dielectric layer associated with the layer stack is formed, the dielectric layer comprising:

[0007] a first portion arranged between a lower portion and an upper portion of an associated layer stack; and

[0008] a second portion extending laterally from a side of the associated layer stack, the second portion being supported by the sacrificial structure;

[0009] For the top of the first and second stacks:

[0010] forming a gate extending above, to one side of, and below the at least one channel layer of the upper portion, the gate replacing a sacrificial layer above and below the at least one channel layer of the upper portion;

[0011] For the lower part of the first and second stack layers, respectively:

[0012] forming another gate extending above, to one side and below the at least one channel layer of the lower portion, the gate replacing the sacrificial layers above and below the at least one channel layer of the lower portion and the sacrificial structure of the second portion of the supporting dielectric layer, wherein the lower gate and the upper gate include electrical contacts on vertically opposite sides of the layer stack;

[0013] Each layer stack is converted into a field effect transistor (FET) stack, each FET stack includes a first FET at a lower portion of the layer stack and a second FET at an upper portion of the layer stack, the first layer stack is converted into a first FET stack, the first FET and the second FET in the first FET stack are p-type FETs, and the second layer stack is converted into a second FET stack, the first FET and the second FET in the second FET stack are n-type FETs.

[0014] According to a second aspect, there is provided a semiconductor device arranged on a substrate, the semiconductor device comprising at least first and second field effect transistor (FET) stacks, each FET stack comprising:

[0015] A first FET and a second FET stacked on the first FET, each of the first FET and the second FET including at least one channel layer for charge transport and a gate extending above, to one side, and below the at least one channel layer, wherein the channel layers of the first FET and the second FET are parallel to each other and to the substrate;

[0016] wherein, for each of the first FET stack and the second FET stack,

[0017] The gates of the first FET and the second FET are separated by a dielectric layer;

[0018] The gates of the first FET and the second FET include electrical contacts on vertically opposing sides of the FET stack;

[0019] Wherein the first and second FETs in the first FET stack are p-type FETs and the first and second FETs in the second FET stack are n-type FETs.

[0020] According to the above, the method according to the first aspect can form a semiconductor device according to the second aspect. The advantages described in conjunction with the first aspect are equally applicable to the second aspect, and vice versa.

[0021] As mentioned, the FETs in the first FET stack are p-type FETs and the FETs in the second FET stack are n-type FETs. The term p-type FET may refer to a FET having a p-doped source / drain region in this article. The term n-type FET may refer to a FET having an n-doped source / drain region in this article. Hereinafter, the term pFET will be used interchangeably with p-type FET and the term nFET will be used interchangeably with n-type FET. The channel layer of the FET may be undoped or have a doping opposite to the doping of the source / drain region of the FET.

[0022] The inventors have appreciated that for at least certain types of semiconductor devices it is advantageous to stack FETs of the same type on top of each other.

[0023] Stacking FETs provides a compact semiconductor device. Stacking FETs of the same type on top of each other facilitates a process customized for that FET type. For example, an nFET may be provided with a different (e.g., larger) channel layer than a pFET. This may be difficult to achieve when nFETs and pFETs are included in the same FET stack. As will be discussed below, the present invention facilitates a compact semiconductor device because pFETs stacked on top of each other can be made with a small channel layer width to give a small footprint, while nFETs stacked on top of each other can be made with a slightly larger channel layer width to improve nFET performance. In other words, the pFET channel layer width may not have to be limited by the minimum nFET channel layer width.

[0024] In addition, stacking FETs of the same type on top of each other enables compact connections between FETs, thereby achieving a compact semiconductor device. For example, stacking FETs of the same type on top of each other enables connections already in the line front end portion of the semiconductor device, rather than connecting through interconnects in the line back end portion of the semiconductor device.

[0025] As a first example, the source or drain region of one FET in a FET stack can be directly connected to the source or drain region of another FET in the same FET stack, for example, by epitaxial merging. As a second example, the gate of one FET in a FET stack can be directly connected to the gate of another FET. Thus, two FETs in a FET stack can have a common gate. In the above, "directly connected" refers to connecting at the same vertical height as the FET stack.

[0026] The connection between FETs in the line front end portion of the semiconductor device relaxes the requirements for interconnection in the line back end portion of the semiconductor device, which in turn realizes a compact semiconductor device. In other words, the connection between FETs in the line front end portion of the semiconductor device can alleviate the wiring congestion in the line back end portion of the semiconductor device.

[0027] In addition, convenient and / or economical manufacturing (e.g., convenient back-end of line processing) is facilitated. For example, when the interconnect layer of the back-end of line portion of the semiconductor device is not congested, the interconnect can be manufactured using a simple and inexpensive lithography such as single print patterning, rather than a more complex and expensive lithography such as self-aligned double patterning (SADP) or self-aligned quad patterning (SAQP).

[0028] One semiconductor device in which stacking FETs of the same type on top of each other is particularly advantageous is a static random access memory (SRAM) cell. Thus, the semiconductor device may be an SRAM cell.

[0029] Thus, the method of the first aspect may include:

[0030] A latch circuit is formed, which is configured to store one bit by connecting the FETs in the FET stack. Thus, an SRAM cell can be formed.

[0031] In the following, a method for forming a semiconductor device will be discussed. Features of the final semiconductor device according to the second aspect will be discussed in conjunction with the processing steps of the first aspect.

[0032] Each layer stack may be considered as a fin including multiple layers. Each layer stack (eg, each fin) may include two opposing lateral side surfaces, two opposing lateral end surfaces, and a top surface. The bottom surface of each layer stack may face the substrate.

[0033] Forming a plurality of layer stacks may include providing (e.g., epitaxially growing) a plurality of layers on a substrate and patterning the fins from the plurality of layers. The channel layer and the sacrificial layer may include Si and / or Ge. The channel layer and the sacrificial layer may have different compositions. Thus, selective etching of the sacrificial layer is achieved. Specifically, the channel layer may include Si (e.g., only Si) and the sacrificial layer may include SiGe. For each layer stack, the sacrificial layer between the lower and upper portions may have a different SiGe composition than the sacrificial layer within the lower and / or upper portions. Thus, different etching rates for layers having different SiGe compositions are achieved. The channel layer may be referred to as a nanosheet.

[0034] The sacrificial structure can serve as a part of the replacement gate. Therefore, the gate can be produced in the gate last process. In other words, the sacrificial structure can serve as a dummy gate.

[0035] The sacrificial structure may include amorphous silicon or polycrystalline silicon.

[0036] The sacrificial structure may include material deposited in a trench between one side of the layer stack and the isolation wall. The material for the sacrificial structure may be deposited until it is above the height of the first portion of the dielectric layer. The material for the sacrificial structure may then be etched back to the height of the first portion of the dielectric layer.

[0037] As mentioned, the layer stacks are spaced apart laterally. After the layer stacks have been formed, they may be spaced apart by empty controls or gaps.

[0038] Converting the layer stack into a field effect transistor stack may include forming source / drain regions at opposite ends of the channel layer for both the upper and lower portions. The source / drain region may be a doped semiconductor region, such as a doped semiconductor region adjacent to the lateral end face of the layer stack, such as a doped semiconductor region epitaxially grown on the lateral end face of the layer stack. For example, a p-doped semiconductor may be grown on the lower portion of the first lateral end face of the first layer stack to form a source region, and a p-doped semiconductor may be grown on the upper portion of the second lateral end face of the first stack to form a drain region. Thus, the source / drain region of the first FET (as a pFET) of the first layer stack is formed. The source / drain region of the second FET (also as a pFET) of the first layer stack may be formed accordingly by growing on the upper portion of the lateral end face of the first layer stack. The source / drain region of the first and second FETs of the second layer stack may be formed in a similar manner, wherein n-doping is used instead of p-doping (to form an nFET).

[0039] The source / drain regions may be formed before or after the gate is formed. It is advantageous to form the source / drain regions before forming the gate (ie, in a gate last process). The gate may comprise a metal.

[0040] As described above, the dielectric layer associated with the layer stack can facilitate electrical isolation of the gates of the FETs of the same layer stack. The dielectric layer can be formed for all layer stacks of the semiconductor device. For layer stacks in which a common gate is preferred, at least a portion of the dielectric layer (e.g., at least a portion of the second portion of the dielectric layer) can be replaced later by an electrical conductor (e.g., a metal (e.g., a gate material)). The first portion of the dielectric layer can be referred to as (middle dielectric isolation MDI).

[0041] The gate or gate stack may include a gate dielectric layer followed by a gate work function metal (WFM) conformally coating the respective upper and lower channel layers.As mentioned, the gate of a portion extends above, to one side and below at least one channel of the portion.

[0042] In the final semiconductor device, the channel layer and the gate may form a fork-tab arrangement or a gate-all-around (GAA) arrangement.

[0043] In a fork-blade arrangement, the gate may extend above, on one side and below at least one channel layer of the FET. The remaining side of the at least one channel layer may abut against a dielectric wall.

[0044] In a GAA arrangement, the gate may also extend on the above-mentioned remaining side of the at least one channel layer. Thus, in this case, the gate may extend around the at least one channel layer.

[0045] Forming the gate may be done by conformal deposition. Prior to forming the gate, the sacrificial layer that the gate is intended to replace may be removed, for example by etching, for example by selective etching.

[0046] As mentioned, the lower gate as well as the upper gate comprise electrical contacts on vertically opposite sides of the layer stack. Thus, for each FET stack, the gates can be contacted from both above and below. For example, the (lower) first FET can contact the backside power delivery network (e.g. to a buried power rail (BPR)), while the (upper) second FET can contact the frontside power delivery network, or vice versa. The electrical contacts on vertically opposite sides of the layer stack facilitate compact semiconductor devices.

[0047] As shown above, the channel layer of the second layer stack may be wider than the channel layer of the first layer stack. Therefore, the second layer stack may be wider than the first layer stack.

[0048] At a given channel layer width, pFETs generally perform better than nFETs, and pFETs can, for example, switch faster than nFETs. If all pFETs and nFETs of a semiconductor device are made to have the same channel layer width, the performance of the nFETs may limit the minimum channel layer width. In this case, the pFETs may be larger than necessary. In contrast, in a semiconductor device according to the present invention, the pFET channel layer width may not have to be limited by the minimum nFET channel layer width, so that the pFET channel layer width may be smaller than the nFET channel layer width. As a result, space is saved. It may be further advantageous to balance nMOS and pMOS performance, such as balancing their switching speeds.

[0049] In view of the above, for the semiconductor device according to the second aspect, the channel layer of the second FET stack may be wider than the channel layer of the first FET stack.

[0050] In the following, the dielectric layers associated with each layer stack will be discussed.

[0051] For each layer stack, the first and second parts of the associated dielectric layer may be made of different materials. This facilitates the production of a common gate. For example, this facilitates the removal of the second part by selective etching. The first and second parts of the associated dielectric layer may have different compositions and / or different crystallinity. The first part of the associated dielectric layer may include silicon nitride (Si3N4) or / and silicon oxycarbide (SiOC) or / and silicon carbonitride (SiOCN) or / and SiON or / and SiBCN. The first part of the associated dielectric layer may include silicon oxide, such as oxidized polysilicon.

[0052] In view of the above, in the semiconductor device according to the second aspect, for each FET stack, the dielectric layer may include:

[0053] a first portion between at least one channel layer of the first FET and at least one channel layer of the second FET; and

[0054] a second portion between a gate extending to one side of at least one channel layer of the first FET and a gate extending to one side of at least one channel layer of the second FET;

[0055] The first portion and the second portion of the dielectric layer are made of different materials.

[0056] In the final semiconductor device, according to the second aspect, the FET stack in which the second portion of the dielectric layer remains can be regarded as a FET stack in which the first and second FETs have separate gates. The FET stack in which the second portion of the dielectric layer is removed (and therefore no longer exists) can be regarded as a FET stack in which the first and second FETs have a common gate. The method according to the first aspect can be used to produce a semiconductor device in which all FET stacks have separate gates for the first and second FETs or to produce a semiconductor device in which some or all FET stacks have a common gate for the first and second FETs.

[0057] For each layer stack, forming a dielectric layer associated with the layer stack may include:

[0058] A first portion of a dielectric layer is formed by replacing a sacrificial layer of a layer stack with a dielectric material. The replaced sacrificial layer may be a sacrificial layer between an upper portion and a lower portion of the layer stack. Forming the first portion of the dielectric layer may include removing (e.g., etching away) the sacrificial layer; subsequently depositing the first portion of the dielectric layer, thereby replacing the sacrificial layer. The sacrificial layer between the upper and lower portions of the layer stack may have a composition different from the composition of the sacrificial layers within the upper and lower portions of the layer stack. Thus, selective etching between the sacrificial layer between the upper and lower portions and the sacrificial layer between the upper and lower portions may be used to remove the sacrificial layer between the upper and lower portions at a different time than the sacrificial layer within the upper and lower portions. For example, the sacrificial layer between the upper and lower portions of the layer stack may include SiGe with a high at.%Ge (e.g., 30-50 at.%Ge) and the sacrificial layer within the upper and lower portions of the layer stack may include SiGe with a low at.%Ge (e.g., 10-20 at.%Ges). Thus, an etch with a rate dependent on the Ge / Si ratio can be used to remove the sacrificial layers between the upper and lower portions while leaving most of the sacrificial layers within the upper and lower portions intact. These sacrificial layers can be removed at a later time.

[0059] For each layer stack, forming a dielectric layer associated with the layer stack may include:

[0060] The second portion of the dielectric layer is formed by:

[0061] providing material for a sacrificial structure up to the height of the first portion of the dielectric layer;

[0062] A top layer of material provided for the sacrificial structure is oxidized to form a second portion of the dielectric layer supported by the sacrificial structure.

[0063] The material for the sacrificial structure may be provided by deposition, for example, in a trench between one side of the layer stack and the isolation wall. The material for the sacrificial structure may be deposited up to a height above the first portion of the dielectric layer, for example to the top of the layer stack, and then etched back to the height of the first portion of the dielectric layer. The material for the sacrificial structure may include amorphous silicon or polycrystalline silicon. Thus, the top layer of the amorphous silicon or polycrystalline silicon may be oxidized.

[0064] An alternative to the formation of the second portion of the dielectric layer described above may be to provide a dielectric up to the height of the first portion of the dielectric layer, for example by backfilling and etching back. In this case, the sacrificial layer below the second portion of the dielectric layer may also be a dielectric, which may be replaced by a gate.

[0065] Hereinafter, the source / drain regions will be discussed.

[0066] The method of the first aspect may include:

[0067] for each portion of each layer stack, source / drain regions are formed by epitaxial growth, these source / drain regions being arranged at opposite ends of the channel layer of these portions,

[0068] Wherein a dielectric spacer is formed over the source / drain region at the lower portion before the source / drain region at the upper portion is formed.

[0069] Thus, the device of the second aspect may include source / drain regions arranged at opposite ends of the channel layer of each portion,

[0070] Therein, for at least one FET stack, a source / drain region at a lower portion is separated from a source / drain region at an upper portion by a dielectric spacer.

[0071] When the source / drain region at the lower portion is spaced apart from the source / drain region at the upper portion by a dielectric spacer, the source / drain regions may be separated. Thus, the source / drain regions may be contacted individually.

[0072] Additionally or alternatively, some source / drain regions may be merged, such as epitaxially merged, as discussed below.

[0073] In the method of the first aspect,

[0074] For at least one layer stack, the dielectric spacer at the lower part may be removed again at one end of the channel layer before forming the source / drain region at the upper part, so that at said end of the channel layer the source / drain regions are epitaxially merged.

[0075] Therefore, with the semiconductor device of the second aspect, at one end of the channel layer of one layer stack, the source / drain region at the lower portion may be epitaxially merged with the source / drain region at the upper portion.

[0076] The merged source / drain regions may have a common contact, ie a single contact may be used for the merged source / drain regions.As mentioned previously, the merged source / drain regions may ease congestion in the back-end of line portion of a semiconductor device.

[0077] In the method of the first aspect, the plurality of layer stacks may include a third layer stack, the third layer stack being converted into a third FET stack, wherein the method comprises:

[0078] A common gate for the first and second FETs in the third FET stack is provided by performing the following operations for the third layer stack:

[0079] removing a second portion of the dielectric layer extending laterally from a side of the third layer stack; and

[0080] A gate is formed extending above, on one side and below at least one channel layer of both the lower and upper portions of the third layer stack so that the gate simultaneously controls the channel layers of both the lower and upper portions of the third layer stack, and the gate replaces the sacrificial layers above and below each channel layer of the lower and upper portions and the sacrificial structure of the second portion of the previously supported dielectric layer that was removed.

[0081] Thus, the semiconductor device of the second aspect may include a third FET stack,

[0082] Wherein the first and second FETs of the third FET stack have a common gate.

[0083] The common gate may be interconnected to another portion of the semiconductor device through a common contact.

[0084] As mentioned previously, a common gate can alleviate congestion in the back-end portion of a semiconductor device.

[0085] It will be appreciated that the gate of the lower part of the layer stack may be formed by a backside process.A backside process refers here to any process in which the lower part of the layer stack is accessible from the backside of the structure.

[0086] Thus, the method may include:

[0087] removing at least a portion of the substrate from a back side, the back side being a side of the substrate opposite the plurality of layer stacks;

[0088] Wherein, for any (or all) of the respective lower portions of the first, second or third layer stacks, forming the gate of the lower portion is completed from the back side after removing the portion of the substrate.

[0089] Forming the gate of the lower part of the first and second layer stack from the back side may be particularly useful.

[0090] The method of the first aspect may further include:

[0091] forming a dielectric wall that abuts one layer stack on the left and another layer stack on the right such that a pair of layer stacks are formed with the dielectric wall in between;

[0092] Therein, for each layer stack in the pair of layer stacks, the lower and upper gate electrodes are formed to extend to a side of the layer stack opposite to the dielectric wall.

[0093] Therefore, a pair of FET stacks converted from this pair of layer stacks can form a fork-piece arrangement.

[0094] It is advantageous if all FETs in the FET stack are of the same type.

[0095] All FETs in the FET stack may be of p-type; or

[0096] All FETs in the FET stack may be of n-type.

[0097] The FETs in the fork-piece arrangement can be very close together. Therefore, doping can be easier if all FETs in the pair of FET stacks are of the same type. In addition, if different channel layer widths are used for pFETs and nFETs, a symmetrical fork-piece arrangement can still be achieved if all FETs in the pair of FET stacks are of the same type. BRIEF DESCRIPTION OF THE DRAWINGS

[0098] The above and other objects, features and advantages of the inventive concept will be better understood through the following detailed description which is illustrative and non-restrictive with reference to the accompanying drawings. In the accompanying drawings, like reference numerals will be used for like elements unless otherwise specified.

[0099] Figure 1 and 2a -c shows a semiconductor device.

[0100] Figure 3a 8a - b to 8a - b illustrate a method for forming a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0101] In conjunction with the accompanying drawings, the technical content and detailed description of the present invention are described below according to preferred embodiments, which are not intended to limit the scope of the protection claimed. However, the present invention can be implemented in many different forms and should not be interpreted as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided for thoroughness and completeness, and to fully convey the scope of the present invention to those skilled in the art.

[0102] Hereinafter, the present invention will be explained in the case where the semiconductor device is an SRAM cell 2. The present invention is particularly advantageous in the case of the SRAM cell 2. In addition, the present invention can also be used with other devices.

[0103] Figure 1 A semiconductor device 1 in the form of an SRAM cell 2 is shown. Figure 1 The SRAM cell 2 is shown as a circuit diagram representing a latch circuit 3. The SRAM cell 2 shown includes six transistors, including four nFETs N1, N2, N3, N4 and two pFETs P1, P2. The transistors are connected to a word line WL; bit lines BL and BLB; and a power supply voltage VDD. Figure 2a -c schematically shows a semiconductor device 1 arranged on a substrate 4 and shows how four nFETs N1 , N2 , N3 , N4 and two pFETs P1 , P2 can be implemented using stacked FETs. Figure 2aA top view of a first FET stack 60a, a second FET stack 60b, and a third FET stack 60c is shown.

[0104] The first FET stack 60a, the second FET stack 60b, and the third FET stack 60c include Figure 1 8. The transistors of the SRAM cell 2 are shown in FIG. 2, as will be discussed below. It should be noted that the FETs shown are implemented in a fork-piece arrangement, in which the FET stacks are arranged in pairs and the FET stacks within a pair are separated by dielectric walls 80. Thus, the second FET stack 60b and the third FET stack 60c are paired. Similarly, the first FET stack 60a is paired with the fourth FET stack 60d. The fourth FET stack 60d will not be discussed in detail below because it is not part of the SRAM cell 2 formed by the first FET stack 60a, the second FET stack 60b, and the third FET stack 60c in this particular implementation. However, the fourth FET stack 60d can be part of another SRAM cell 2 or other circuit.

[0105] The FETs in the first FET stack 60a include p-type source / drain regions 50p, such that the FETs in the first FET stack 60a are pFETs. The FETs in the second FET stack 60b and the third FET stack 60c include n-type source / drain regions 50n, such that the FETs in the second FET stack 60b and the third FET stack 60c are nFETs. There is a gate region 52 between the source / drain regions 50p, 50n of each FET, such as in Figure 2a The gate region 52 includes the layer stacks 10a, 10b, 10c, 10d and gates 25, 26 discussed below. Figure 2a In FIG. 2 , the layer stacks 10 a , 10 b , 10 c , 10 d are drawn with dashed lines to indicate that they may be enclosed in gates 25 , 26 .

[0106] Figure 2b Shows the Figure 2a 2 is a cross section of the gate region 52 along the line AA′ indicated in FIG. Figure 2c Shows the Figure 2a 4 is a cross section of the source / drain regions 52n, 50p along the line BB' indicated in FIG.

[0107] exist Figure 2b and 2c , the connections to WL, BL, BLB, and VDD are shown (according to Figure 1 ).

[0108] As in Figure 2bAs seen in FIG. 1 , each FET stack 60a, 60b, 60c includes a first FET 61 and a second FET 62 stacked on the first FET 61. The figure indicates which FETs in the stacked FETs correspond to P1, P2, N1, N2, N3, and N4, respectively.

[0109] Each of the first FET 61 and the second FET 62 includes at least one channel layer 12 for charge transport. In this illustration, each FET has two channel layers 12. Therefore, each FET stack 60a, 60b, 60c can be regarded as having a lower portion 15a, 15b, 15c, including the channel layer 12 of the first FET 61; and an upper portion 16a, 16b, 16c, including the channel layer 12 of the second FET 62. Each of the first FET 61 includes a gate 25, which extends above, on one side, and below the at least one channel layer 12 of the lower portion 15a, 15b, 15c. Each of the first FET 62 includes a gate 26, which extends above, on one side, and below the at least one channel layer 12 of the lower portion 16a, 15b, 15c.

[0110] In the first FET stack 60a, the second FET stack 60b and the fourth FET stack 60d, the gates of the first FET 61 and the second FET 62 are separated by dielectric layers 31, 32, which include first and second portions 31, 32. The gates of the first FET 61 and the second FET 62 in the first FET stack 60a, the second FET stack 60b and the fourth FET stack 60d include electrical contacts 22 on vertically opposite sides of the respective FET stacks. In the illustration, the electrical contacts 22 are embedded in the interconnect dielectric layer 5. In the illustration, the substrate 4 on which the channel layer 12 has been grown is seen between the gate of the first FET 61 and the interconnect dielectric layer 5. Additionally or alternatively, the semiconductor device 1 may include a carrier substrate 4 (not shown) to support the FET stack when a portion or all of the substrate on which the channel layer 12 has been grown is removed. In the illustration, a shallow trench isolation region 6 is also shown.

[0111] Figure 2b An implementation is shown in which the channel layer 12 of the second FET stack 62b and the third FET stack 62c (comprising nFETs) is wider than the channel layer 12 of the first FET stack 62a (comprising pFETs).

[0112] Figure 2c 1 shows a cross section of the source regions 50n, 50p of the FET stacks 60a, 60b, 60c, 60d at one end of the channel layer 12. Figure 2a, there are drain regions 50n, 50p at opposite ends of the channel layer 12. In the third FET stack 60c, the source region 50n at the lower portion 15c is separated from the source region 50n at the upper portion 16c by a dielectric spacer 72. Therefore, the first FET 61 and the second FET 62 in the third FET stack 60c can be regarded as having separate source regions 50n, which can be contacted separately, as shown. In the first FET stack 60a and the second FET stack 60b, the source regions 50n, 50p at the lower portions 15a, 15b are merged with the source regions 50n and 50p at the upper portions 16a, 16b, respectively, for example, epitaxially merged.

[0113] In the following, the method according to the first aspect will be described. As an illustrative example, the method 100 will be in the production Figure 1 and 2a -c is described in the context of SRAM cell 2.

[0114] Figure 3a -b shows the formation of the layer stack 10a, 10b, 10c, 10d, the formation of the first portion 31 of the dielectric layer, and the formation of the dielectric wall 80 and the spacer wall 82. Figure 3a A top view of a layer stack 10 a , 10 b , 10 c , 10 d is shown, each comprising two opposite lateral side faces 17 and two opposite lateral end faces 18 . Figure 3b A cross-sectional view of what will later become gate region AA' is shown. Figure 3b In FIG. 1 , there are two pairs of layer stacks 11. One pair of layer stacks 11 includes layer stacks 10b, 10c for pFET stacks 60b, 60c. The other pair of layer stacks 11 includes layer stacks 10a, 10d for nFET stacks 60a, 60d.

[0115] A plurality of layers may be grown on the substrate 4, for example epitaxially, for example by chemical vapor deposition (CVD) or physical vapor deposition (PVD). The substrate 4 may be a silicon substrate 4. The plurality of layers may then be etched into layer stacks 10a, 10b, 10c, 10d. In this example, a first layer stack 10a, a second layer stack 10b, a third layer stack 10c, and a fourth layer stack 10d are formed. Each layer stack 10a, 10b, 10c, 10d includes a channel layer 12 and a sacrificial layer 14. The channel layer 12 may be a Si layer and the sacrificial layer 14 may be a SiGe layer. The channel layer 12 may be spaced apart by at least one sacrificial layer 14.

[0116] For each layer stack 10a, 10b, 10c, 10d, one sacrificial layer 14 may be replaced by a first portion 31 of a dielectric layer. This may be accomplished by selectively etching away the sacrificial layer 14 to be replaced (e.g., a sacrificial layer 14 comprising a high Ge content (30-50 at.% Ge in this example)) and depositing a dielectric material in the empty space left by the sacrificial layer 14. The dielectric material deposited in the empty space may include SiO2, or / and Si3N4, or / and SiOC, or / and SiOCN, or / and SiON, or / and SiC, or / and SiBCN. The dielectric material may be deposited by atomic layer deposition.

[0117] Figure 3b The layer stacks 10a, 10b, 10c, 10d are shown after the sacrificial layer 14 between the lower part 15a, 15b, 15c, 15d and the upper part 16a, 16b, 16c, 16d of the respective layer stacks 10a, 10b, 10c, 10d has been replaced by the first part 31 of the dielectric layer.

[0118] A dielectric wall 80 and a spacer 82 may be formed. In this example, a dielectric wall 80 is formed between the first layer stack 10a and the fourth layer stack 10d and a dielectric wall 80 is formed between the second layer stack 10b and the third layer stack 10c. In this example, each such dielectric wall 80 is adjacent to a layer stack on the left and adjacent to another layer stack on the right. Therefore, two pairs of layer stacks 11 are formed in this example, and each pair of layer stacks has a dielectric wall 80 in the middle of the pair of layer stacks 11. In addition, a spacer 82 may be formed between two pairs of layer stacks 11. In this example, this spacer 82 is formed, leaving a groove between the spacer 82 and the nearby layer stack. Figure 3b The layer stack 10a, 10b, 10c, 10d is shown after the formation of the dielectric walls 80 and the spacer walls 82 described above. Figure 3b It is also shown that a shallow trench isolation region 6 may be formed on or in the substrate 4. The shallow trench isolation region 6 may include SiO2.

[0119] In the following, examples of the dimensions of the features discussed above are given. The channel layer 12 may have a thickness of 3-10 nm. The first portion 31 of the dielectric layer may have a thickness of 10-30 nm. Therefore, the sacrificial layer 14 replaced by the first portion 31 of the dielectric layer may also have a thickness of 10-30 nm. Starting with a sacrificial layer 14 that is thinner than the thickness of the first portion 31 of the dielectric layer may be beneficial because etching is not necessarily completely selective. Therefore, the sacrificial layer 14 replaced by the first portion 31 of the dielectric layer may have a thickness of 5-20 nm. The remaining sacrificial layer 14 in FIG. 3 may have a thickness of 3-10 nm. The width of the first layer stack 10 a and the fourth layer stack 10 d, i.e., the distance between the opposite sides 17 of the first layer stack 10 a and the fourth layer stack 10 d, may be 5-25 nm. This may correspond to the channel layer width of the pFET of the finished device. The width of the second layer stack 10b and the third layer stack 10c, i.e., the distance between the opposite sides 17 of the second layer stack 10b and the third layer stack 10c, can be 5-25nm. This can correspond to the channel layer width of the nFET of the finished device. The ratio between the channel layer width of the nFET and the channel layer width of the pFET can be between 1:1 and 2:1. For example, the channel layer width of the pFET can be 10nm and the channel layer width of the nFET can be 15nm. The dielectric wall 80 and the isolation wall 82 can have a lateral thickness of 6-20nm.

[0120] Figure 4a -c shows the formation of source / drain regions 50n, 50p. The source / drain regions 50n, 50p may be epitaxially grown, for example by chemical vapor deposition (CVD).

[0121] In this example, the source / drain regions 50n, 50p are grown after forming the structure discussed in conjunction with FIG. 3 . Figure 4a -c is along Figure 2a and Figure 4d A cross-sectional view of the line BB' indicated in FIG.

[0122] The source / drain regions 50n, 50p may be grown on the end faces 18 of the layer stack 10a, 10b, 10c, 10d, as shown in FIG3. The source / drain regions 50n, 50p of the lower portion 15a, 15b, 15c, 15d may be grown before the source regions 50n, 50p of the upper portion 16a, 16b, 16c, 16d by masking the end faces 18 of the upper portion 16a, 16b, 16c, 16d (e.g., by a liner). The source / drain regions 50n, 50p may be doped in situ during epitaxial growth. N-doped source / drain regions 50n (in this example, drain / source regions 50n at the second layer stack 10b and the third layer stack 10c) can be grown before p-doped source / drain regions 50p (in this example, source / drain regions 50p at the first layer stack 10a and the fourth layer stack 10d), and vice versa. After the source / drain regions 50n, 50p of the lower portions 15a, 15b, 15c, 15d are grown, a dielectric material 70 can be deposited, and the dielectric material 70 covers the source / drain regions 50n, 50p of the lower portions 15a, 15b, 15c, 15d. This is Figure 4a The dielectric material 70 may be SiO2 or SiOC. The dielectric material 70 may be deposited by chemical vapor deposition (CVD), in particular, by flowable chemical vapor deposition (FCVD). Figure 4a As shown, the dielectric material 70 may be arranged to form dielectric spacers 72 over the source regions 50n, 50p at the lower portions 15a, 15b, 15c and 15d before forming the source / drain regions at the upper portions 15a, 15b, 15c, 15d. In other words, the dielectric material 70 may extend up to the first portion 31 between the lower portions 15a, 15b, 15c, 15d and the upper portions 16a, 16b, 16c, 16d of the dielectric layer.

[0123] The mask (eg, liner) for the end faces 18 of the upper portions 16a, 16b, 16c, 16d may subsequently be removed prior to growth of the source / drain regions 50n, 50p of the upper portions 16a, 16b, 16c, 16d.

[0124] Figure 4b It is shown that in the case where the source / drain regions 50n, 50p of the lower portion 15a, 15b, 15c, 15d and the upper portion 16a, 16b, 16c, 16d are to be spaced apart, the dielectric spacer 72 can be maintained for the growth of the drain / source regions 50n, 50p of the upper portion 16a, 16b, 16c, 16d. In this example, the dielectric spacer 72 is maintained for the third layer stack 10c and the fourth layer stack 10d.

[0125] Figure 4bIt is shown that in the case where the source / drain regions 50n, 50p of the lower portions 15a, 15b, 15c, 15d and the upper portions 16a, 16b, 16c, 16d are to be spaced apart, the dielectric spacer 72 can be recessed before the growth of the drain / source regions 50n, 50p of the upper portions 16a, 16b, 16c, 16d. In this example, the dielectric spacer 72 is removed for the first layer stack 10a and the second layer stack 10b. The dielectric spacer 72 can be recessed in any manner. The dielectric spacer 72 can be removed. The dielectric spacer 72 can be recessed, for example, by etching. The area where the dielectric spacer 72 should not be removed can be masked, for example, by photolithographic patterning.

[0126] Figure 4c It is shown that after forming the source / drain regions 50n, 50p of the lower portions 15a, 15b, 15c, 15d and the upper portions 16a, 16b, 16c, 16d, additional dielectric material 70 may be deposited to cover the source regions 50n, 50p of the upper portions 16a, 16b, 16c, 16d. The dielectric material 70 may then be polished (e.g., by chemical mechanical polishing) to facilitate further photolithography.

[0127] Figure 4d is a top view of the layer stack 10a, 10b, 10c, 10d after forming the source / drain regions 50n, 50p. For clarity of illustration, the dielectric material 70 is not shown.

[0128] Figure 5a -c shows the formation of the sacrificial structure 40 and the second portion 32 of the dielectric layer. Figure 5a -c is along Figure 2a A cross-sectional view along line AA' is shown.

[0129] In this example, the sacrificial structure 40 and the second portion 32 of the dielectric layer are formed after forming the source / drain regions 50 n , 50 p (discussed in conjunction with FIG. 4 ).

[0130] The material for the sacrificial structure 40 may be provided up to the height of the first portion 31 of the dielectric layer. Thus, the sacrificial structure 40 may be used as a dummy gate for a replacement gate process. The material for the sacrificial structure 40 may include amorphous silicon or polycrystalline silicon. The material for the sacrificial structure 40 may be deposited up to a height higher than the first portion 31 of the dielectric layer, such as Figure 5a The material used for the sacrificial structure 40 can then be etched back to the height of the first portion 31 of the dielectric layer, as shown. Figure 5b shown.

[0131] The top layer of material provided for the sacrificial structure 40 may then be oxidized to form the second portion 32 of the dielectric layer, such as Figure 5cAs shown. Thus, the second portion 32 of the dielectric layer may include oxidized amorphous silicon or oxidized polycrystalline silicon. The second portion 32 of the dielectric layer may have a thickness of 3-30 nm. The second portion 32 of the dielectric layer may have the same thickness as the first portion 31 of the dielectric layer, for example 10-30 nm. Alternatively, the second portion 32 of the dielectric layer may be thinner than the first portion 31 of the dielectric layer. The second portion 32 of the dielectric layer may have a thickness of 3-10 nm. The second portion 32 of the dielectric layer may extend laterally from one side 17 of the layer stack 10 a, 10 b, 10 c, 10 d to the isolation wall 82, as shown. Figure 5c shown.

[0132] Figure 6a -c shows that the gate 26 is formed at the upper portions 16a, 16b, 16c, 16d. Figure 6a -c also shows that a gate 25 is formed at the lower portion 15c, wherein in this figure a common gate is realized at the third layer stack 10c. Figure 6a -c is along Figure 2a A cross-sectional view along line AA' is shown.

[0133] In this example, the gates 25, 26 are formed after forming the sacrificial structure 40 and the second portion 32 of the dielectric layer (discussed in conjunction with FIG5). The gates 25, 26 may be metal gates.

[0134] For the layer stack in which a common gate is to be realized (in this example the third layer stack 10c), the second portion 32 of the dielectric layer can be removed. Furthermore, the sacrificial structure 40 supporting the second portion 32 of the dielectric layer can also be removed. This is Figure 6a The second portion 32 of the dielectric layer and the sacrificial structure 40 can be removed by etching. For layer stacks in which the second portion 32 of the dielectric layer should not be removed (in this example, the first layer stack 10a, the second layer stack 10b and the fourth layer stack 10d), the second portion 32 of the dielectric layer can be masked.

[0135] The sacrificial layer 14 can then be removed, for example, by etching, as shown. Figure 6b The channel layer 12, no longer supported by the sacrificial layer 14, may now be suspended between the source / drain regions 50n, 50p.

[0136] Then, gate electrodes 25 and 26 may be formed. Figure 6cAs shown. The gates 25, 26 may replace the removed sacrificial layer 14 here. The gates 25, 26 may also replace the removed sacrificial structure 40. The gates 25, 26 may be formed by first depositing a gate dielectric layer (e.g., a high-k dielectric) conformally coating the exposed channel layer 12. Subsequently, a gate work function metal (WFM) may be deposited on the gate dielectric layer. For clarity of illustration, the gate dielectric layer is not shown separately in the various figures, but it may be located at the interface between the gates 25, 26 and the channel layer 12 in the various figures. The WFM for the gates 25, 26 intended for pFETs may be different from the WFM for the gates 25, 26 intended for nFETs.

[0137] The gate dielectric layer may be formed of a conventional high-k dielectric such as HfO2, HfSiO, LaO, AlO, or ZrO. Each WFM may be formed of one or more active WFMs such as n-type WFMs such as TiAl or TiAlC and / or p-type WFMs such as TiN or TaN. The gate dielectric layer and the first WFM may be deposited by atomic layer deposition (ALD).

[0138] Figure 7 It is shown that contacts 22 are formed at the upper portions 16a, 16b, 16c, 16d. Figure 7 is along Figure 2a A cross-sectional view along line AA' is shown.

[0139] In this example, the contacts 22 at the upper portions 16a, 16b, 16c, 16d are formed after the gates 26 (discussed in conjunction with FIG. 6 ) are formed at the upper portions 16a, 16b, 16c, 16d.

[0140] An interconnect dielectric layer 5 may be deposited and patterned to form openings leading to the gates 26 of the upper portions 16a, 16b, 16c, 16d. Contacts 22 may then be formed in the openings, for example by depositing metal in the openings, and thereafter may be interconnected according to the desired circuit. Figure 7 Contacts 22 to the gates 26 of the upper portions 16a, 16b, 16c, 16d are shown. Contacts to the source / drain regions 50n, 50p of the upper portions 16a, 16b, 16c, 16d may be similarly formed.

[0141] Figure 8a -b shows the formation of the gate 25 at the lower portions 15a, 15b, 15d, where a common gate was not previously implemented (at the first layer stack 10a, the second layer stack 10b and the fourth layer stack 10d in this figure). Figure 8a -b is along Figure 2a A cross-sectional view along line AA' is shown. Figure 8a The gate formation shown in -b is an example of a backside process.

[0142] In this example, the gate 25 at the lower portion 15a, 15b, 15d where the common gate was not previously realized is formed at the upper portion 16a, 16b, 16c, 16d with a contact portion 22 (combined with Figure 7 discussion) was formed after that.

[0143] The back side of the substrate 4 used to form the layer stack 10a, 10b, 10c, 10d may be removed to access the lower portions 15a, 15b, 15c, 15d. This may include bonding the interconnect dielectric layer 5 over the upper portions 16a, 16b, 16c, 16d to a carrier substrate. Figure 8a The back side of the substrate 4 is shown removed. For clarity of illustration, the carrier substrate is not shown. The back side of the substrate 4 can be removed, for example, by grinding and / or backside etching. At the same time, portions of the shallow trench isolation 6 can be removed. During the removal of the back side of the substrate 4, the semiconductor device can be turned upside down, for example, to facilitate grinding and / or backside etching. Thus, Figure 8a It is drawn upside down.

[0144] The remaining sacrificial structure 40 and the sacrificial layer 14 of the lower portions 15a, 15b, 15c, 15d can be removed, for example, by etching, after removing the blocked shallow trench isolation regions 6. Figure 8b As shown, the gate 25 of the lower portion 15a, 15b, 15c, 15d can be subsequently formed. Here, the gate 25 can replace the above-mentioned removed structure. The gate 25 of the lower portion 15a, 15b, 15c, 15d can be formed similarly to the gate 26 of the upper portion 16a, 16b, 16c, 16d discussed in conjunction with FIG. 6.

[0145] Finally, contacts 22 at the lower portions 15a and 15b may be formed for both the gates 25 of the lower portions 15a, 15b, 15c, 15d and the source / drain regions 50n, 50p of the lower portions 15a, 15b, 15c, 15d. The contacts 22 may then be interconnected according to the desired circuit. In this example, the final device may be Figure 2a -c, wherein each layer stack 10a, 10b, 10c, 10d has been converted into a FET stack 60a, 60b, 60c, 60d.

[0146] In the above, the inventive concept has mainly been described with reference to a limited number of examples. However, as readily appreciated by a person skilled in the art, other examples than the ones disclosed above are equally possible within the scope of the inventive concept as defined by the appended claims.

Claims

1. A method for forming a semiconductor device, the method comprising: forming a plurality of layer stacks on a substrate, the layer stacks being laterally spaced apart, each layer stack comprising channel layers of semiconductor material spaced apart by sacrificial layers, the plurality of layer stacks comprising at least a first layer stack and a second layer stack, each layer stack having a lower portion and an upper portion, the lower portion and the upper portion each comprising at least one channel layer; For each layer stack, a dielectric layer associated with the layer stack is formed, the dielectric layer comprising: a first portion arranged between the lower portion and the upper portion of an associated layer stack; and a second portion extending laterally from a side of the associated layer stack, the second portion being supported by a sacrificial structure; For each upper portion of the first layer stack and the second layer stack: forming a gate extending above, to one side of, and below the at least one channel layer of the upper portion, the gate replacing a sacrificial layer above and below the at least one channel layer of the upper portion; For each lower portion of the first layer stack and the second layer stack: forming a further gate extending above, to one side and below the at least one channel layer of the lower portion, the gate replacing sacrificial layers above and below the at least one channel layer of the lower portion and the sacrificial structure supporting the second portion of the dielectric layer, wherein the lower gate and the upper gate are in electrical contact on vertically opposite sides of the layer stack; Each layer stack is converted into a field effect transistor FET stack, each FET stack includes a first FET at the lower part of the layer stack and a second FET at the upper part of the layer stack, the first layer stack is converted into a first FET stack, the first FET and the second FET in the first FET stack are p-type FETs, and the second layer stack is converted into a second FET stack, the first FET and the second FET in the second FET stack are n-type FETs. 2 . The method of claim 1 , wherein the channel layer of the second layer stack is wider than the channel layer of the first layer stack.

3. The method of claim 1, wherein: For each layer stack, the first portion and the second portion of the associated dielectric layer are made of different materials.

4. The method of claim 1, wherein: For each layer stack, forming a dielectric layer associated with the layer stack comprises: A first portion of the dielectric layer is formed by replacing a sacrificial layer of the layer stack with a dielectric material.

5. The method of claim 1, wherein: For each layer stack, forming a dielectric layer associated with the layer stack comprises: The second portion of the dielectric layer is formed by: providing material for the sacrificial structure up to the height of the first portion of the dielectric layer; A top layer of the material provided for the sacrificial structure is oxidized to form a second portion of the dielectric layer supported by the sacrificial structure. The method of claim 1 , wherein the sacrificial structure comprises amorphous silicon or polycrystalline silicon.

7. The method of claim 1, further comprising: for each portion of each layer stack, forming source / drain regions by epitaxial growth, said source / drain regions being arranged at opposite ends of the channel layer of said portion, Wherein a dielectric spacer is formed over the source / drain region at the lower portion before the source / drain region at the upper portion is formed.

8. The method according to claim 1, in, For at least one layer stack, the dielectric spacer at the lower portion is recessed again at one end of the channel layer before the source / drain region at the upper portion is formed, so that at the end of the channel layer, the source / drain regions are epitaxially merged.

9. The method of claim 1 , wherein the plurality of layer stacks includes a third layer stack, the third layer stack being converted into a third FET stack, wherein the method comprises: A common gate for the first FET and the second FET in the third FET stack is provided by performing the following operations for the third layer stack: removing a second portion of the dielectric layer extending laterally from a side of the third layer stack; as well as A gate is formed extending above, on one side and below at least one channel layer of both the lower and upper portions of the third layer stack so that the gate simultaneously controls the channel layers of both the lower and upper portions of the third layer stack, and the gate replaces the sacrificial layers above and below each channel layer of the lower and upper portions and the sacrificial structure of the removed second portion that previously supported the dielectric layer.

10. The method of claim 1, further comprising: forming a dielectric wall that abuts one layer stack on the left and another layer stack on the right, such that a pair of layer stacks are formed with the dielectric wall in between; For each of the pair of layer stacks, the lower and upper gate electrodes are formed to extend to a side of the layer stack opposite to the dielectric wall.

11. The method of claim 10, wherein the pair of layer stacks are converted into a pair of FET stacks, wherein All FETs in the FET stack are p-type; or All FETs in this FET stack are n-type.

12. The method of claim 1, further comprising: A latch circuit is formed that is configured to store one bit by connecting the FETs in the FET stack.

13. A semiconductor device arranged on a substrate, the semiconductor device comprising at least a first field effect transistor (FET) stack and a second FET stack, each FET stack comprising: a first FET and a second FET stacked on the first FET, each of the first FET and the second FET comprising at least one channel layer for charge transport and a gate extending above, to one side, and below the at least one channel layer, wherein the channel layers of the first FET and the second FET are parallel to each other and to the substrate; wherein, for each of the first FET stack and the second FET stack, The gates of the first FET and the second FET are separated by a dielectric layer; The gates of the first FET and the second FET are in electrical contact on vertically opposite sides of the FET stack; Wherein the first FET and the second FET in the first FET stack are p-type FETs and the first FET and the second FET in the second FET stack are n-type FETs. 14 . The semiconductor device of claim 13 , wherein a channel layer of the second FET stack is wider than a channel layer of the first FET stack.

15. The semiconductor device according to claim 13, wherein: For each FET stack, the dielectric layer includes: a first portion between at least one channel layer of the first FET and at least one channel layer of the second FET; and a second portion between a gate extending to one side of at least one channel layer of the first FET and a gate extending to one side of at least one channel layer of the second FET; The first portion and the second portion of the dielectric layer are made of different materials.

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