Semiconductor device and manufacturing and design method

Abstract

A semiconductor device includes at least a first cell and a second cell. Each of the first and second cells includes: a first well of a first conductivity type; a second well in the first well, wherein the second well has a second conductivity type opposite to the first conductivity type; and a discharge pin connected to the second well. The semiconductor device further includes a discharge path connected between the discharge pins of the first and second cells such that the second wells of the first and second cells are at the same potential. A method of manufacturing a semiconductor and a method of designing the semiconductor device are also described.

Description

Technical Field

[0001] The present disclosure relates to a standard cell with a deep N-well, and methods for manufacturing and designing a semiconductor device. Background Art

[0002] Modern manufacturing of integrated circuits typically uses deep micron process technology, where high-density plasma enhanced chemical vapor deposition (HDPECVD) and plasma etching are used to form transistor structures. Charge from the plasma process may accumulate on exposed conductive structures that can conduct to the gate region of the transistor, thereby causing gate leakage and affecting the threshold voltage V of the transistor. T Plasma induced damage (PID) or process antenna effect (PAE) occurs when the accumulated charge grows significantly and can crack the gate oxide layer that is designed to be thinner and thinner in advanced deep sub-micron processes. Summary of the invention

[0003] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0004] In one embodiment, a semiconductor device includes at least a first unit and a second unit. Each of the first and second units includes: a first well of a first conductivity type; a second well in the first well, wherein the second well has a second conductivity type opposite to the first conductivity type; and a discharge pin connected to the second well. The semiconductor device further includes a discharge path connected between the discharge pins of the first and second units so that the second wells of the first and second units are at the same potential.

[0005] According to one or more embodiments, the first well is a deep N-well, and the second well is an isolated P-well region disposed within the deep N-well.

[0006] According to one or more embodiments, the first cell further includes a bias node configured to be connected to a bias voltage level through a bias conductive path and configured to be connected to the second well.

[0007] According to one or more embodiments, the discharge pin and the bias node are connected to the second well through a contact region of the second conductivity type, and wherein the contact region has a doping density higher than that of the second well.

[0008] According to one or more embodiments, the signal path connected between the cells and the discharge path are different paths arranged in different metal layers of the semiconductor device.

[0009] According to one or more embodiments, the discharge path is arranged in a layer between the first well and a layer in which a signal path connecting between the cells is arranged.

[0010] According to one or more embodiments, the first cell further includes at least one transistor arranged in the second well.

[0011] In another embodiment, a method for manufacturing a semiconductor device includes manufacturing at least a first unit and a second unit. The method includes manufacturing each of the first and second units by: forming a first well of a first conductivity type; forming a second well in the first well, the second well having a second conductivity type opposite to the first conductivity type; forming a discharge pin on the second well; and forming a discharge path, the discharge path connecting the discharge pins of the first and second units so that the second wells of the first and second units are at the same potential.

[0012] According to one or more embodiments, the first well is a deep N-well, and the second well is an isolated P-well region within the deep N-well.

[0013] According to one or more embodiments, the method further includes forming a bias node on the second well and connecting the bias node to a bias conductive path such that the second well can be connected to a bias voltage level through the bias conductive path.

[0014] According to one or more embodiments, forming the discharge pin and the bias node on the second well includes forming a contact region of the second conductivity type in the second well, the contact region having a density higher than that of the second well.

[0015] According to one or more embodiments, forming the discharge path includes forming the discharge path in a first metal layer, and the method further includes forming a signal path connected between the cells in a second metal layer different from the first metal layer.

[0016] According to one or more embodiments, a first metal layer is between the second metal layer and the first well.

[0017] According to one or more embodiments, the method further comprises fabricating at least one transistor in the second well.

[0018] In yet another embodiment, a method for designing a semiconductor device includes: placing a first unit and a second unit, each having a first well of a first conductivity type and a second well within the first well, the second well having a second conductivity type opposite to the first conductivity type; configuring a discharge pin on the second well; and wiring the discharge pin of the first unit to the discharge pin of the second unit through a discharge path.

[0019] According to one or more embodiments, the first cell and the second cell are each a standard cell with a deep N-well and / or a tapless cell.

[0020] According to one or more embodiments, the method further comprises:

[0021] configuring a bias node on the second well of each of the first and second cells; and

[0022] The bias node is routed to a bias conductive path such that the second well can be connected to a bias voltage level through the bias conductive path.

[0023] According to one or more embodiments, the method further includes configuring the discharge path in a first metal layer, and configuring a signal path connected between the first unit and the second unit in a second metal layer different from the first metal layer.

[0024] According to one or more embodiments, the method further includes configuring the second metal layer to be higher than the first metal layer.

[0025] According to one or more embodiments, the first cell is a standard cell with a deep N-well and includes at least one transistor, and wherein the method further includes configuring the discharge path in a metal layer lower than a metal layer in which electrodes of the transistor are wired. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order that the manner in which the above-mentioned features of the present disclosure may be understood in detail, a more detailed description of the present disclosure may be obtained with reference to the embodiments, some of which are illustrated in the accompanying drawings. The accompanying drawings illustrate only typical embodiments of the present disclosure and should not limit the scope of the present disclosure, as the present disclosure may have other equally effective embodiments. The accompanying drawings are used to facilitate understanding of the present disclosure and are not necessarily drawn to scale. The advantages of the claimed subject matter will become apparent to those skilled in the art upon reading this specification in conjunction with the accompanying drawings, in which the same reference numerals are used to indicate the same elements, and in the accompanying drawings:

[0027] Figure 1 is a diagram of an NMOS transistor in a deep N-well of a standard cell;

[0028] Figure 2 is a diagram showing two isolated deep N-wells with NMOS transistors according to an embodiment;

[0029] Figure 3 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment;

[0030] Figure 4 It is a simplified schematic diagram of the unit in the CAD environment;

[0031] Figure 5 is a flowchart of a method for designing a semiconductor device according to an embodiment; and

[0032] Figure 6 yes Figure 2 FIG. 1 is a diagram of an NMOS transistor of a standard cell and shows an inserted LVS resistor. DETAILED DESCRIPTION

[0033] When designing an integrated circuit, so-called "standard cells" are placed and wired. Most standard cells consist of one or more transistors integrated to perform a specific function. Figure 1 An example NMOS transistor of a standard cell is shown. The NMOS transistor 100 of the standard cell is formed in a first well 102 which is a deep N-well, and within the first well 102 is a second well region 104. The second well region 104 is an isolated P-well region. One or more transistors of the standard cell are configured within the isolated P-well region 104, and Figure 1 Only one NMOS transistor is shown, which has a source electrode and a drain electrode connected to the N+ regions 106 and 108, respectively. A gate electrode 110 of the NMOS transistor is located between the N+ regions 106 and 108.

[0034] Since the NMOS transistor 100 is manufactured in the deep N well 102, a latch-up effect may occur when the PN junction between the isolated P well region 104 and the deep N well 102 is forward biased, which can destroy the circuit in a very short time. In order to avoid such damage caused by the latch-up effect, the PN junction needs to be reverse biased by connecting the deep N well 102 to a high voltage level (e.g., a power supply voltage VDD) and connecting the isolated P well region 104 to a lower voltage level (e.g., a bias voltage level VSS Bias). The P+ region 112 is formed in the isolated P well region 104 to provide a connection to the bias voltage level VSS_Bias. The deep N well 102 and the isolated P well region 104 provide good isolation of the transistor in one unit from other units in other isolated regions in the circuit, and are advantageous in terms of circuit performance. The P+ region 112 is depicted in this context as having a higher doping density than the isolated P well region 104.

[0035] Figure 2 1 and 2 show a first unit and a second unit of a semiconductor device according to an embodiment. The semiconductor device 200 includes a semiconductor device similar to Figure 1 The first cell 202 and the second cell 204 of the standard cell are shown in FIG. In addition, the first cell 202 has a discharge pin 206, and the second cell 204 has a discharge pin 208. The discharge pins 206 and 208 are arranged on the isolation P-well region of the cells 202 and 204. In the cells 202 and 204, similar to Figure 1 In the case of , P+ regions 205 and 207 are respectively fabricated in corresponding isolated P-well regions for providing connection to a bias voltage level VSS_Bias.

[0036] Charge accumulated in the isolated P-well region during the fabrication of a semiconductor device can cause an imbalance in the potential between the isolated domains of the cell. When a device formed in one isolated cell drives a device formed in another isolated cell (e.g., Figure 2 204), it may induce PID in, for example, the gate 212 of the driven cell 204, thus producing a low yield wafer. To prevent PID from occurring, according to an embodiment, the discharge pins 206 and 208 are connected to each other by a discharge path 210 represented as V_EQ. The discharge path 210 may be connected for achieving an equalized voltage level. The isolated P-well regions of the cells 202 and 204 are at the same potential generated by the discharge path 210 connected to the discharge pins 206 and 208. The electrodes of the transistors of the cells are connected to the external cells by metal traces, which results in the fabrication of a conductive layer pattern on the semiconductor wafer material. The discharge path 210 between the discharge pins 206 and 208 is arranged on a metal layer that is different from the metal layer arrangement of the signal path 216 represented by, for example, the V_SIG connection used to provide a connection between the gates 212 and 214. During the manufacture of semiconductor integrated circuits, the metal layers of the semiconductor device are "stacked", where one layer is deposited on another layer with a dielectric in between. In terms of the metal layer stack, the metal layer used to configure the discharge path 210 between the isolated P-well regions is below or above the same metal layer as the metal layer of the signal path 216 represented as V_SIG. It should be understood by those skilled in the art that as used herein, the term "discharge path" generally refers to a path between two or more isolated P-well regions, and is used to distribute charge between the P-wells, and thereby release charge from one (or more) of the P-well regions; it is not required that the charge be released to any external device. In other words, the discharge path can be alternatively described as a "charge sharing path". Figure 2 The discharge pins of the cell are preferably arranged on the peripheral area of ​​the cell.

[0037] Figure 1 and Figure 2The cell described in the embodiment uses an example of an NMOS transistor configured in a deep N-well. However, in a typical CMOS circuit, the cell may include a PMOS transistor, and the cell configuration of the above embodiment is also applicable. The deep N-well may contain more than one NMOS transistor.

[0038] Figure 3 is a flow chart of manufacturing a semiconductor device according to an embodiment. Only those steps related to the present disclosure and applicable to understanding the present disclosure are shown and described, but those skilled in the art should understand that the manufacture of a semiconductor device generally includes many or even hundreds of additional steps. Figure 2 The method is described with reference to an example semiconductor device of the present invention. Step 302 of the method forms a deep N-well on a substrate, for example, by implanting N-type dopant ions to a depth of about 100 nm. The N-type dopant includes phosphorus or arsenic ions. Step 304 then creates an isolated P-well region in the deep N-well, for example, by implanting P-type dopant into the deep N-well. The P-type dopant includes boron or indium ions.

[0039] Step 306 of the method is performed to form contacts on the isolated P-well region. The contacts fabricated on the isolated P-well region will include bias nodes (such as Figure 2 205 or 207 in the discharge path) and a discharge pin for connection in the discharge path (such as Figure 2 206 or 208 in FIG. 206). Referring to FIG. 206 or 208 in FIG. 206 as a simplified schematic diagram of a standard cell design Figure 4 , forming the contact 402 to include both the bias node VPP and the discharge pin VPPR. Also referring to Figure 2 , a contact 402 can be manufactured by first forming a P+ region (below the bias node 205 or 207) in the surface of the isolated P-well region, and then forming a metal region 402 above the P+ region. The metal region 402 includes a bias node (205 and 207) and a discharge pin (206 or 208), with a side area of ​​the metal region 402 acting as a bias node and a side area of ​​the metal region acting as a discharge pin. The discharge pin thus formed will be connected to a metal layer for providing a discharge path. The P+ region of the contact has an increased doping density relative to the rest of the P-well, which increases conductivity. The method further includes step 308, forming a discharge path (such as Figure 2 210 in ) to connect the discharge pins of the cells so that the isolated P-well regions of the cells are at the same potential. The step 308 of connecting to a discharge path may include forming a discharge path in a metal layer and connecting the discharge pins to the metal layer, for example, by means of vias that pass through the bottom metal and dielectric layers in the metal stack.

[0040] If the cell being manufactured is a standard cell having corresponding transistors in an isolated P-well region and thus having input / output signal pins for the transistors, step 310 proceeds with connecting the pins / electrodes of the transistors in the cell to the corresponding interconnect layers. Figure 2 The signal path 216 denoted as V_SIG in FIG. 3 is a metal layer above the metal layer used to configure the discharge path of step 308 .

[0041] Alternatively, the cell may also be generated in a design using a tapless standard library, in which the cell does not provide a signal input / output pin. The cell with discharge pins 206 and 208 according to an embodiment may replace the corresponding existing cell. It should be understood that the discharge path between the discharge pins formed in step 308 is formed in a metal layer stack, while the signal path formed in step 310 is formed in a separate metal layer. As described above, in order to avoid the PID effect, the discharge path is preferably established before the signal path, which means that the metal layer used to form the discharge path is lower than the metal layer used to form the signal path.

[0042] Figure 5 is a flow chart of a method for designing a semiconductor device. Figure 2 and Figure 4 The method is described by way of example with respect to a device of the type described herein. Designing a semiconductor device based on standard cells mainly involves placement and routing, including placing the cells and routing the connecting contacts of the cells in different interconnect layers.

[0043] Step 502 of the method is implemented to place the first cell and the second cell. As described above, the first cell and the second cell have corresponding deep N-well configurations and also have corresponding isolated P-well regions. Step 504 configures contacts ( Figure 4 Step 506 of the method configures a discharge pin on a P+ contact on the isolated P-well region of each of the first and second cells.

[0044] Step 508 continues with wiring the discharge pins of the cells to be connected together through the discharge path. Figure 3 Step 310, step 510 is to wire the electrodes of the transistors of the cell to the corresponding interconnect layers, and / or to wire the bias nodes ( Figure 2205 or 207 in the figure) is routed to the bias conductive path. Specifically, for example, this may include: routing the drain electrode 214 of the device 202 and the gate electrode 212 of another device 204 to the metal layer metal-m, and routing the discharge path 210 connecting the discharge pins 206 and 208 to the metal layer metal-n. In one or more embodiments, if metal-n is any M1-M2 (i.e., the first metal layer or the second metal layer), metal-m is configured to be M2 or higher than M2; if metal-n is in the range of M1-M5, metal-m is configured to be M5 or higher than M5, so that the interconnect layer is placed in a metal layer higher than the metal layer in which the discharge path is configured. As described above, the discharge path is established in a metal layer lower than the signal path to prevent the PID effect.

[0045] In step 512, a layout vs. schematic (LVS) check is performed on the designed semiconductor device. Figure 6 Show Figure 2 The LVS resistor between the discharge pin and the bias node of the semiconductor device. As described above and also from Figure 2 and Figure 4 As can be seen from the layout diagram of FIG. 1 , because both the discharge pin and the bias node are configured from the metal region 402 on the P+ contact in the isolated P-well region, the design tool generally does not allow the discharge pin and the bias node from the same metal region to be routed to different metal layers. The LVS resistor 602 shown is not a physical component. In fact, the LVS resistor 602 depicts the resistance between the discharge pin and the bias node (from a schematic perspective) to comply with the rules of the design tool. The LVS resistor 602 may be included in the LVS check to verify whether the designed layout complies with electrical execution. In a typical embodiment, the LVS resistor 602 has a resistance of approximately 300 milliohms. However, the resistance of the LVS resistor may be configured according to the manufacturing process and other applicable factors, and may be different between the NMOS transistor and the PMOS transistor.

[0046] The embodiment designs and configures a cell having an additional discharge pin obtained by extending an existing pin for configuring a bias path to prevent the PID effect. The cell of the embodiment is suitable for replacing an existing standard cell and has an optimized area.

[0047] Unless otherwise specified herein or clearly contradicted by the context, the use of the words "one" and "the" and similar indicators in the context of describing the subject matter (especially in the context of the attached claims) should be understood to cover the singular as well as the plural. The terms "coupled" and "connected" both mean that there is an electrical connection between the coupled or connected elements, and neither implies that there is no intermediate element. When describing transistors and their connections, the terms gate, drain and source can be used interchangeably with the terms "gate terminal", "drain terminal" and "source terminal". Unless otherwise indicated herein, the description of the range of values ​​herein is intended only to serve as a shorthand method for individually referring to each individual value falling within the range, and each individual value is incorporated into this specification as if it were individually described herein. In addition, the foregoing description is for illustrative purposes only, not for limiting purposes, because the scope of protection sought is limited by the claims set forth below and any equivalents thereof. Unless otherwise required, the use of any and all examples or exemplary language (e.g., "for example") provided herein is only to better illustrate the subject matter, without limiting the scope of the subject matter. The use of the term "based on" and other similar phrases to indicate conditions that produce a result in the claims and written description is not intended to exclude any other conditions that produce the result. No language in this specification should be construed as indicating that any non-claimed element is essential to practicing the claimed disclosure.

[0048] Preferred embodiments are described herein, including the best modes known to the inventors for performing the claimed subject matter. Of course, after reading the foregoing description, variations of those preferred embodiments will become apparent to those of ordinary skill in the art. The inventors expect that those of ordinary skill in the art will adopt such variations as appropriate, and the inventors intend to practice the claimed subject matter of the present invention in other ways than those specifically described herein. Therefore, the claimed subject matter includes all modifications and equivalents of the subject matter recited in the appended claims as permitted by applicable law. In addition, unless otherwise indicated herein or otherwise clearly contradictory to the context, any combination of the elements described above in all possible variations thereof is encompassed.

Claims

1. A semiconductor device, characterized in that: At least a first unit and a second unit are included, each of the first and second units comprising: a first well of a first conductivity type; a second well in the first well, wherein the second well has a second conductivity type opposite to the first conductivity type; and A discharge pin connected to the second well; wherein The semiconductor device further includes a discharge path connected between the discharge pins of the first and second cells so that the second wells of the first and second cells are at the same potential.

2. The semiconductor device according to claim 1, wherein: The first well is a deep N-well, and the second well is an isolated P-well region disposed within the deep N-well.

3. The semiconductor device according to claim 2, wherein: The first cell additionally includes a bias node configured to be connected to a bias voltage level through a bias conductive path and configured to be connected to the second well.

4. The semiconductor device according to claim 3, wherein: The signal path connected between the cell and the discharge path is a different path arranged in a different metal layer of the semiconductor device.

5. A method for manufacturing a semiconductor device comprising manufacturing at least a first unit and a second unit, characterized in that, The method comprises manufacturing each of the first and second units by: forming a first well of a first conductivity type; forming a second well in the first well, the second well having a second conductivity type opposite to the first conductivity type; forming a discharge pin on the second well; as well as A discharge path is formed, the discharge path connecting the discharge pins of the first and second cells so that the second wells of the first and second cells are at the same potential.

6. The method according to claim 5, characterized in that The first well is a deep N-well, and the second well is an isolated P-well region within the deep N-well.

7. The method according to claim 6, characterized in that Also included is forming a bias node on the second well and connecting the bias node to a bias conductive path so that the second well can be connected to a bias voltage level through the bias conductive path.

8. The method according to claim 7, characterized in that Forming the discharge path includes forming the discharge path in a first metal layer, and the method additionally includes forming a signal path connected between the cells in a second metal layer different from the first metal layer.

9. A method for designing a semiconductor device, characterized in that: include: placing a first unit and a second unit each having a first well of a first conductivity type and a second well in the first well, the second well having a second conductivity type opposite to the first conductivity type; configuring a discharge pin on the second well; as well as The discharge pin of the first cell is wired to the discharge pin of the second cell through a discharge path.

10. The method according to claim 9, characterized in that The method also includes configuring the discharge path in a first metal layer, and configuring a signal path connected between the first unit and the second unit in a second metal layer different from the first metal layer.

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