Array substrate, preparation method thereof and display device

Abstract

The invention discloses an array substrate, a preparation method thereof and a display device. The array substrate comprises a substrate, an active layer and a plurality of metal layers, the active layer and the multiple metal layers form a pixel circuit; the first end of the driving transistor is connected with the second end of the compensation transistor, the first end of the compensation transistor is connected with the second end of the first reset transistor, and the second end of the driving transistor is connected with the second end of the first light-emitting control transistor; in an active layer in one pixel circuit, a first end of a driving transistor, a second end of a compensation transistor and a second end of a first light-emitting control transistor are arranged at intervals to form a first active part, a second active part and a third active part which are arranged at intervals, the driving transistor is located in the first active part, and the third active part is located in the second active part. The compensation transistor and the first reset transistor are located in the second active portion, and the first light-emitting control transistor is located in the third active portion. Through the scheme, the current leakage problem can be improved, and the display effect is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Display (OLED) and flat-panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, the display effects of current OLED display products need to be improved. Summary of the invention

[0004] The main technical problem solved by the present application is to provide an array substrate and a preparation method thereof, and a display device to improve the leakage current problem and enhance the display effect.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide an array substrate, comprising a substrate, an active layer and a plurality of metal layers; the active layer is arranged on one side of the substrate; the plurality of metal layers are arranged on a side of the active layer away from the substrate; the active layer and the plurality of metal layers form a pixel circuit, the pixel circuit comprising a driving transistor, a compensation transistor, a first reset transistor and a first light emission control transistor, wherein the subthreshold swing of the driving transistor is greater than the subthreshold swing of the compensation transistor and the first reset transistor; the first end of the driving transistor is electrically connected to the second end of the compensation transistor, the first end of the compensation transistor is electrically connected to the second end of the first reset transistor, and the second end of the driving transistor is electrically connected to the second end of the first light emission control transistor; in the active layer in one of the pixel circuits, the first end of the driving transistor is spaced from the second end of the compensation transistor and the second end of the first light emission control transistor to form a first active portion, a second active portion and a third active portion spaced from each other, wherein the driving transistor is located in the first active portion, the compensation transistor and the first reset transistor are located in the second active portion, and the first light emission control transistor is located in the third active portion.

[0006] Preferably, the multiple metal layers include a first metal layer, at least one insulating layer is provided between the first metal layer and the active layer, a first via, a second via and a third via are provided in the at least one insulating layer, the first via connects the first metal layer and the first end of the driving transistor in the active layer, the second via connects the first metal layer and the second end of the first reset transistor in the active layer, the third via connects the first metal layer and the second end of the first light-emitting control transistor in the active layer, and the first metal layer fills at least part of the first via, the second via and the third via, so that the first active part is electrically connected to the second active part and the third active part.

[0007] Preferably, the at least one insulating layer includes a first insulating layer stacked on the side of the first metal layer facing the substrate, the first insulating layer includes a first sub-insulating layer and a second sub-insulating layer stacked, the second sub-insulating layer is located on the side of the first sub-insulating layer facing the substrate, and the first via hole, the second via hole and the third via hole all pass through the first sub-insulating layer and the second sub-insulating layer; wherein the first sub-insulating layer is formed after the dehydrogenation treatment of the active layer, and the second sub-insulating layer is formed before the dehydrogenation treatment.

[0008] Preferably, a plurality of fourth vias and a plurality of fifth vias are also provided in the at least one insulating layer, the first metal layer fills at least a portion of the fourth vias and the fifth vias, the fourth vias connect the first metal layer and the first active part, and the fifth vias connect the first metal layer and the second active part / the third active part.

[0009] Preferably, the material of the active layer includes semiconductor.

[0010] Preferably, the material of the active layer includes polysilicon.

[0011] To solve the above technical problems, another technical solution adopted in the present application is: a method for preparing an array substrate, comprising: forming an active layer on one side of a substrate, the active layer comprising a first active portion, a second active portion and a third active portion arranged at intervals; forming multiple metal layers on a side of the active layer away from the substrate, the active layer and the multiple metal layers forming a pixel circuit, the pixel circuit comprising a driving transistor, a compensation transistor, a first reset transistor and a first light-emitting control transistor, wherein the subthreshold swing of the driving transistor is greater than the subthreshold swing of the compensation transistor and the first reset transistor; wherein, in the active layer, the first end of the driving transistor is located in the first active portion, the second end of the compensation transistor is located in the second active portion, and the second end of the first light-emitting control transistor is located in the third active portion; the first end of the driving transistor is electrically connected to the second end of the compensation transistor, the first end of the compensation transistor is electrically connected to the second end of the first reset transistor, and the second end of the driving transistor is electrically connected to the second end of the first light-emitting control transistor.

[0012] Preferably, the step of forming multiple metal layers on the side of the active layer away from the substrate also includes: forming multiple insulating layers on one side of the active layer, the insulating layers including a first insulating layer; forming a first via, a second via and a third via on the insulating layer, wherein the first via is connected to the first end of the driving transistor in the active layer, the second via is connected to the second end of the first reset transistor in the active layer, and the third via is connected to the second end of the first light-emitting control transistor; forming a first metal layer on the side of the first insulating layer away from the substrate, wherein the first metal layer fills at least part of the first via, the second via and the third via, so that the first active part is electrically connected to the second active part and the third active part.

[0013] Preferably, the step of forming at least one insulating layer on one side of the active layer, wherein the insulating layer includes a first insulating layer, comprises: forming a second sub-insulating layer; hydrogenating the second sub-insulating layer; exposing the first end of the driving transistor in the active layer through a first temporary via hole, and dehydrogenating the active layer; forming a first sub-insulating layer on a side of the second sub-insulating layer away from the substrate to form the first insulating layer; and forming the first via hole, the second via hole and the third via hole on the first insulating layer.

[0014] Preferably, after the step of hydrogenating the second sub-insulating layer, the step further includes: exposing the first active part through a second temporary via hole; after the step of forming a first sub-insulating layer on the side of the second sub-insulating layer away from the substrate to form the first insulating layer, the step further includes: forming a plurality of fourth via holes and a plurality of fifth via holes on the first insulating layer, the fourth via holes connecting to the first active part, and the fifth via holes connecting to the second active part / the third active part; the step of forming a first metal layer on the side of the first insulating layer away from the substrate also includes: the first metal layer fills at least part of the fourth via holes and the fifth via holes so that the first metal layer is electrically connected to the second active part / the third active part.

[0015] In order to solve the above technical problems, another technical solution adopted in the present application is: to provide a display device, comprising the array substrate described in any embodiment or the array substrate prepared by the preparation method described in any embodiment.

[0016] The beneficial effect of the present application is as follows: different from the prior art, the first active part of the active layer in the array substrate of the present application is physically disconnected from the second active part and the third active part, and the movement path of the hydrogen ions generated during the dehydrogenation treatment is blocked. During the dehydrogenation treatment of the driving transistor, it is difficult for the free hydrogen ions to continue to move from the surface of the first active part across the disconnection to the surface of the second active part and the third active part, which greatly avoids the hydrogen ions from invading the interface between the second active part and the third insulating layer where the compensation transistor and the first reset transistor are located, thereby ensuring the device quality of the compensation transistor and the first reset transistor, ensuring that the compensation transistor and the first reset transistor have a smaller leakage current, and making the display panel have a good display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a top view of an embodiment of an array substrate of the present application;

[0018] Figure 2 is a cross-sectional view of an embodiment of an array substrate of the present application;

[0019] Figure 3 is a schematic structural diagram of a pixel circuit P of the present application;

[0020] Figure 4 yes Figure 1 Sectional view along AA direction;

[0021] Figure 5a is a top view of the active layer of the present application;

[0022] Figure 5b is a top view of the array substrate of the present application after the third metal layer is formed;

[0023] Figure 5c is a top view of the array substrate of the present application after the second metal layer is formed;

[0024] Figure 5d is a top view of the array substrate of the present application after the first temporary via hole and the second temporary via hole are formed;

[0025] Figure 5e is a top view of the array substrate of the present application before the first metal layer is formed;

[0026] Figure 6 It is a schematic flow chart of an implementation method of the preparation method of the present application;

[0027] Figure 7 It is a flowchart of step S120 of the present application;

[0028] Figure 8 It is a flowchart of step S121 of this application. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and effect of the present application clearer and more specific, the present application is further described in detail with reference to the accompanying drawings and examples. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0030] Existing display devices usually have poor display quality of black-state images and screen flickering, which seriously affects the display effect of the display device. The inventors have found that the reasons for the above problems are as follows: the pixel circuit of the existing display device generally uses a thin-film transistor made of low-temperature polysilicon (LTPS) material to drive the light-emitting device for light-emitting display. Due to the limitation of the process, the leakage current generated by the low-temperature polysilicon transistor is large, which will affect the effect of the storage capacitor in the pixel circuit to maintain the voltage, thereby affecting the expressiveness of the screen when displaying the black state image, reducing the contrast of the displayed image, and affecting the display quality. Since the leakage current generated by the low-temperature polysilicon transistor is large, it will aggravate the flickering phenomenon of the screen, seriously affecting the display effect of the display device.

[0031] In view of this, an array substrate 100 is provided. Figure 1The array substrate 100 includes a substrate (not labeled), an active layer 21 and a plurality of metal layers (not labeled). The active layer 21 is arranged on one side of the substrate; the plurality of metal layers are arranged on the side of the active layer 21 away from the substrate; the active layer 21 and the plurality of metal layers form a pixel circuit P, and the pixel circuit P includes a driving transistor T1, a compensation transistor T3, a first reset transistor T4 and a first light emission control transistor T6, wherein the subthreshold swing (SS) of the driving transistor T1 is greater than the subthreshold swing of the compensation transistor T3 and the first reset transistor T4.

[0032] Specifically, see Figure 2 The substrate 10 includes a stacked substrate 11 and a buffer layer 12. The side of the buffer layer 12 facing away from the substrate 11 has an array layer 20. The array layer 20 includes an active layer 21, a multi-layer insulating layer (not marked) and a multi-layer metal layer (not marked). The array layer 20 specifically includes an active layer 21, a third insulating layer 22, a third metal layer 23, a second insulating layer 24, a second metal layer 25, a first insulating layer 26 and a first metal layer 27 stacked in sequence. In the thin film transistor TFT made of low temperature polysilicon material, the material of the active layer 21 can be a semiconductor material such as polysilicon P-Si. The gate 231 in the thin film transistor TFT is located in the third metal layer 23 and is insulated from the active layer 21 by the third insulating layer 22. The source 271 and the drain 272 in the thin film transistor TFT are located in the first metal layer 27 and are insulated from the active layer 21 by the first insulating layer 26, the second insulating layer 24 and the third insulating layer 22. The insulating layer is provided with a via hole 261 penetrating the first insulating layer 26 , the second insulating layer 24 and the third insulating layer 22 . The via hole 261 connects the first metal layer 27 and the active layer 21 . The source electrode 271 and the drain electrode 272 are electrically connected to the active layer 21 after filling the via hole 261 .

[0033] The pixel circuit P includes a variety of structures, such as "3T1C", "4T1C", "7T1C" or "7T2C", where "T" represents a thin film transistor TFT and "C" represents a storage capacitor Cst. The number represents the number of components after the number.

[0034] Specifically, see Figure 3, the present application takes the pixel circuit P as a "7T1C" structure as an example for explanation. A pixel circuit P includes seven thin film transistors TFT and a storage capacitor Cst, wherein the seven thin film transistors TFT specifically include a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first reset transistor T4, a second light emission control transistor T5, a first light emission control transistor T6, and a second reset transistor T7. Among them, the first end of the driving transistor T1 is connected to the second end of the compensation transistor T3 and the second end of the second reset transistor T7, the second end of the driving transistor T1 is connected to the second end of the first light emission control transistor T6, and the first end of the compensation transistor T3 is connected to the second end of the first reset transistor T4.

[0035] In the preparation process of the thin film transistor TFT using low-temperature polycrystalline silicon, in order to make the driving transistor T1 have a more stable threshold voltage Vth and a higher subthreshold swing SS than other transistors, it is usually necessary to electrically adjust the driving transistor T1. The specific solution is to perform a hydrogenation treatment on the first insulating layer 26 after the film is formed, and then perform a dehydrogenation treatment on the exposed active layer 21 through the via 261 after etching to form the via 261. The inventors have found through research that during the dehydrogenation process, free hydrogen ions will move violently along the surface of the active layer 21 facing the third insulating layer 22, resulting in an increase in interface defects between the active layer 21 and the third insulating layer 22, resulting in an increase in the leakage current of the transistor. Since the leakage current generated by the compensation transistor T3 and the first reset transistor T4 will flow to the gate of the driving transistor T1, the voltage of the storage capacitor Cst connected to the gate of the driving transistor T1 will increase, and the driving current of the driving transistor T1 will decrease, thereby causing the brightness of the display screen to continue to decrease. Especially in low-frequency display modes, such as in the always on display (AOD) mode, the display screen is prone to flickering, which seriously affects the display effect.

[0036] See also Figure 5aIn the active layer 21 of a pixel circuit P, the first end of the driving transistor T1 (shown as D1 in the figure) and the second end of the compensation transistor T3 (shown as D2 in the figure) and the second end of the first light emission control transistor T6 (shown as D3 in the figure) are arranged at intervals to form a first active portion 211, a second active portion 212 and a third active portion 213 arranged at intervals, wherein the driving transistor T1 is located in the first active portion 211, the compensation transistor T3 and the first reset transistor T4 are located in the second active portion 212, and the first light emission control transistor T6 is located in the third active portion 213. It should be noted that the array substrate 100 has a plurality of pixel circuits P, and the pixel circuits P are arranged in an array along the first direction X and the second direction Y, and the second active portion 212 of a pixel circuit P and the third active portion 213 of another pixel circuit P adjacent thereto are connected to each other in the first direction X. Therefore, when the first active portion 211 is physically disconnected from the second active portion 212 and the third active portion 213, the movement path of the hydrogen ions is blocked. During the dehydrogenation treatment of the active layer 21, it is difficult for the free hydrogen ions to continue to move from the surface of the first active portion 211 across the disconnection to the surfaces of the second active portion 212 and the third active portion 213, which greatly avoids the hydrogen ions from invading the interface between the second active portion 212 and the third insulating layer 22 where the compensation transistor T3 and the first reset transistor T4 are located, thereby ensuring the device quality of the compensation transistor T3 and the first reset transistor T4, ensuring that the compensation transistor T3 and the first reset transistor T4 have a smaller leakage current, so that the display panel has a good display effect.

[0037] It should be noted that the driving transistor T1 and the compensation transistor T3 and the first light-emitting control transistor T6 in a pixel circuit P are only physically disconnected on the active layer 21, and it is necessary to reconnect the disconnected driving transistor T1 and the compensation transistor T3 and the first light-emitting control transistor T6 through other metal layers to ensure the normal conduction of the pixel circuit P.

[0038] In a specific embodiment, continue to refer to Figure 1 and Figure 4The via 261 includes a first via 2611, a second via 2612 and a third via 2613, all of which penetrate the first insulating layer 26, the second insulating layer 24 and the third insulating layer 22. The first via 2611 connects the first metal layer 27 and the first end D1 of the driving transistor T1 in the active layer 21, the second via 2612 connects the first metal layer 27 and the second end D2 of the first reset transistor T4 in the active layer 21, and the third via 2613 connects the first metal layer 27 and the second end D3 of the first light emission control transistor in the active layer 21. The first metal layer 27 fills part of the first via 2611, the second via 2612 and the third via 2613, so that the first active part 211 is electrically connected with the second active part 212 and the third active part 213. In this embodiment, the driving transistor T1, the compensation transistor T3 and the first light emission control transistor T6 that were originally disconnected are reconnected through the first metal layer 27 to ensure the normal conduction of the pixel circuit P. Since the metal layer where the source 271 and the drain 272 of the thin film transistor TFT are located is the first metal layer 27 , the source 271 , the drain 272 and the metal filling the first via 2611 , the second via 2612 and the third via 2613 can be formed simultaneously.

[0039] Optionally, the first insulating layer 26 includes a second sub-insulating layer and a first sub-insulating layer (not marked) stacked together, and the second sub-insulating layer is located on the side of the first sub-insulating layer facing the substrate. The first sub-insulating layer and the second sub-insulating layer are made of the same material, but the two film layers are formed successively, wherein the second sub-insulating layer is formed before the dehydrogenation treatment, and the first sub-insulating layer is formed after the dehydrogenation treatment. Specifically, a whole layer of the second sub-insulating layer is first formed on the surface of the second metal layer 25 by chemical vapor deposition (CVD), and the insulating layer is hydrogenated; then a first temporary via is formed, and the first temporary via passes through the second sub-insulating layer, the second insulating layer 24 and the third insulating layer 22, so that the first active part 211 corresponding to the first end of the driving transistor T1 is exposed to the first temporary via; then the exposed active layer 21 is dehydrogenated through the first temporary via. Since the first temporary via is only connected to the first active part 211, the second active part 212 and the third active part 213 are completely covered by the insulating layer at this time, so the dehydrogenation treatment can only affect the first active part 211, The electrical property of the driving transistor T1 corresponding to the first active part 211 is adjusted; after the electrical property adjustment is completed, the first sub-insulating layer is formed to form a complete first insulating layer 26. Since the first temporary via is filled in the first sub-insulating layer, it is necessary to form a first via 2611 at the position corresponding to the first temporary via, and form a second via 2612 and a third via 2613. The three types of vias all penetrate the first insulating layer 26, the second insulating layer 24 and the third insulating layer 22, so that the hydrogen ions generated by this dehydrogenation treatment are difficult to affect the second active part 212 and the third active part 213, thereby reducing the possibility of leakage current generated by the compensation transistor T3 and the first reset transistor T4.

[0040] Alternatively, if Figure 5eAs shown, the array substrate 100 is further provided with a plurality of fourth vias 2614 and a plurality of fifth vias 2615, all of which are used for electrical connection between the first metal layer 27 and the active layer 21, and the first metal layer 27 fills at least a portion of the fourth vias 2614 and the fifth vias 2615, wherein the plurality of fourth vias 2614 are connected to the first metal layer 27 and the first active portion 211, and the plurality of fifth vias 2615 are connected to the first metal layer 27 and the second active portion 212 / the third active portion 213. Specifically, the second temporary via hole is formed simultaneously with the first temporary via hole, and the second temporary via hole penetrates the second sub-insulating layer, the second insulating layer 24 and the third insulating layer 22 and exposes the first active part 211; the fourth via hole 2614 and the fifth via hole 2615 are formed simultaneously with the first via hole 2611, the second via hole 2612 and the third via hole 2613, wherein the fourth via hole 2614 is formed at the position corresponding to the second temporary via hole, and all via holes penetrate the first insulating layer 26, the second insulating layer 24 and the third insulating layer 22. That is, all via holes 261 connected with the first active part 211 are formed before the dehydrogenation treatment, and after the first active part 211 is dehydrogenated by the first temporary via hole and the second temporary via hole, the second via hole 2612, the third via hole 2613 and the fifth via hole 2615 connected with the second active part 212 / the third active part 213 are formed. The influence of the dehydrogenation process on the second active portion 212 / the third active portion 213 is further reduced, and the possibility of leakage current generated by the compensation transistor T3 and the first reset transistor T4 is reduced.

[0041] See also Figure 6 The present application also provides a method for preparing an array substrate, the method comprising:

[0042] Step S110: Figure 5a As shown, an active layer 21 is formed on one side of the substrate 10, and the active layer 21 includes a first active portion 211, a second active portion 212, and a third active portion 213 that are arranged at intervals. Specifically, a disconnected end of the first active portion 211 corresponds to the first end of the driving transistor T1 in the active layer 21, a disconnected end of the second active portion 212 corresponds to the second end of the compensation transistor T3 in the active layer 21, and a disconnected end of the third active portion 213 corresponds to the second end of the first light emission control transistor T6 in the active layer 21. The material of the active layer 21 can be polysilicon, and this step can form the patterned first active portion 211, the second active portion 212, and the third active portion 213 by etching the active layer 21.

[0043] Step S120: forming a plurality of metal layers on the side of the active layer 21 away from the substrate 10, the active layer 21 and the plurality of metal layers form a pixel circuit P, the pixel circuit P includes a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first reset transistor T4, a second light emission control transistor T5, a first light emission control transistor T6 and a second reset transistor T7, as shown in FIG. Figure 1 shown.

[0044] See also Figure 7 Specifically, step S120 also includes:

[0045] Step S121: Figure 5b and Figure 5c As shown, a plurality of insulating layers are formed on one side of the active layer 21, and the insulating layers include a first insulating layer 26, a second insulating layer 24, and a third insulating layer 22. This step specifically includes sequentially forming a third insulating layer 22, a third metal layer 23, a second insulating layer 24, a second metal layer 25, and a first insulating layer 26 on one side of the active layer 21.

[0046] Step S122: Figure 5e As shown, a first via hole 2611, a second via hole 2612 and a third via hole 2613 are formed on the insulating layer. Optionally, a plurality of fourth via holes 2614 and a fifth via hole 2615 may be formed in this step, both of which are used to connect the first metal layer 27 and the active layer 21. The fourth via hole 2614 may be understood as all via holes 261 connecting the first active part 211 and the first metal layer 27 except the first via hole 2611, and the fifth via hole 2615 may be understood as all via holes 261 connecting the second active part 212 / the third active part 213 and the first metal layer 27 except the second via hole 2612 and the third via hole 2613. Among them, the first via hole 2611 is connected to the first end D1 of the driving transistor T1 in the active layer 21, the second via hole 2612 is connected to the second end D2 of the first reset transistor T4 in the active layer 21, and the third via hole 2613 is connected to the second end D3 of the first light emission control transistor T6.

[0047] Step S123: Figure 1 and Figure 4 As shown, a first metal layer 27 is formed on a side of the first insulating layer 26 facing away from the substrate 10, wherein the first metal layer 27 fills at least a portion of the first via 2611, the second via 2612, and the third via 2613, so that the first active portion 211 is electrically connected to the second active portion 212 and the third active portion 213. Optionally, the first metal layer 27 may also fill at least a portion of the fourth via 2614 and the fifth via 2615, so that the first metal layer 27 is electrically connected to the second active portion 212 / the third active portion 213.

[0048] See also Figure 8 Specifically, step S121 may further include:

[0049] Step S1211: forming a second sub-insulating layer. The second sub-insulating layer is formed after the second metal layer.

[0050] Step S1212: hydrogenating the second sub-insulating layer. The hydrogenation can greatly reduce dangling bonds and interface defects.

[0051] Step S1213: Figure 5d As shown, the first end of the driving transistor in the active layer is exposed through the first temporary via 2161a, and the active layer is dehydrogenated, and the first temporary via 2161a corresponds to the subsequent first via 2161. Optionally, a plurality of second temporary vias 2614a can also be formed simultaneously in this step. The active layer at the corresponding position, i.e., the first active part, is exposed to the first temporary via 2161a and the second temporary via 2614a, so that it can be electrically connected to the first metal layer later. Dehydrogenation treatment can reduce defects or traps in the active layer. Specifically, the dehydrogenation treatment can only reach the first active part 211 through the first temporary via 2161a and the second temporary via 2614a to dehydrogenate the first active part 211. The dehydrogenation treatment is difficult to affect the second active part 212 / the third active part 213 covered by the insulating layer.

[0052] Step S1214: Form a first sub-insulating layer on the side of the second sub-insulating layer away from the substrate to form a first insulating layer. Since the first temporary via 2161a and the second temporary via 2614a are formed before the first sub-insulating layer, the above two vias are filled with the first sub-insulating layer. Therefore, it is still necessary to form a first via 2611 through all insulating layers corresponding to the first temporary via 2161a, and form a fourth via 2614 through all insulating layers corresponding to the second temporary via 2614a to expose the first active part. Since the second via 2612, the third via 2613 and the fifth via 2615 are formed after the dehydrogenation treatment, the hydrogen ions generated during the dehydrogenation treatment are difficult to affect the second active part 212 / the third active part 213.

[0053] The preparation method provided in the present application reduces the influence of electrical property regulation on the performance of other thin film transistors TFT in the pixel circuit P while ensuring that the driving transistor T1 has good electrical properties, thereby improving the display effect.

[0054] The present application also provides a display device, comprising the array substrate of any embodiment, and further comprising a light-emitting layer and a packaging layer sequentially stacked on the array substrate. The display device can be a mobile phone, a tablet computer, a television, or a wearable display device.

[0055] The above are only implementation methods of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; An active layer, arranged on one side of the substrate; A plurality of metal layers are arranged on a side of the active layer away from the substrate; The active layer and the multiple metal layers form a pixel circuit, the pixel circuit includes a driving transistor, a compensation transistor, a first reset transistor and a first light emission control transistor, wherein the subthreshold swing of the driving transistor is greater than the subthreshold swing of the compensation transistor and the first reset transistor; The first end of the driving transistor is electrically connected to the second end of the compensation transistor, the first end of the compensation transistor is electrically connected to the second end of the first reset transistor, and the second end of the driving transistor is electrically connected to the second end of the first light emission control transistor; In the active layer in one of the pixel circuits, the first end of the driving transistor is spaced apart from the second end of the compensation transistor and the second end of the first light emitting control transistor to form a first active portion, a second active portion and a third active portion that are spaced apart, wherein the driving transistor is located in the first active portion, the compensation transistor and the first reset transistor are located in the second active portion, and the first light emitting control transistor is located in the third active portion.

2. The array substrate according to claim 1, characterized in that: The multiple metal layers include a first metal layer, at least one insulating layer is provided between the first metal layer and the active layer, a first via, a second via and a third via are provided in the at least one insulating layer, the first via connects the first metal layer and the first end of the driving transistor in the active layer, the second via connects the first metal layer and the second end of the first reset transistor in the active layer, the third via connects the first metal layer and the second end of the first light-emitting control transistor in the active layer, and the first metal layer fills at least part of the first via, the second via and the third via, so that the first active part is electrically connected to the second active part and the third active part.

3. The array substrate according to claim 2, characterized in that: The at least one insulating layer includes a first insulating layer stacked on the side of the first metal layer facing the substrate, the first insulating layer includes a first sub-insulating layer and a second sub-insulating layer stacked, the second sub-insulating layer is located on the side of the first sub-insulating layer facing the substrate, and the first via hole, the second via hole and the third via hole all penetrate the first sub-insulating layer and the second sub-insulating layer; wherein the first sub-insulating layer is formed after the dehydrogenation treatment of the active layer, and the second sub-insulating layer is formed before the dehydrogenation treatment.

4. The array substrate according to claim 2, characterized in that: The at least one insulating layer is also provided with a plurality of fourth vias and a plurality of fifth vias, the first metal layer fills at least a portion of the fourth vias and the fifth vias, the fourth vias connect the first metal layer and the first active part, and the fifth vias connect the first metal layer and the second active part / the third active part.

5. The array substrate according to claim 1, characterized in that: The material of the active layer includes semiconductor; Preferably, the material of the active layer includes polysilicon.

6. A method for preparing an array substrate, characterized in that: An active layer is formed on one side of the substrate, wherein the active layer includes a first active portion, a second active portion and a third active portion which are arranged at intervals; A plurality of metal layers are formed on a side of the active layer away from the substrate, and the active layer and the plurality of metal layers form a pixel circuit, wherein the pixel circuit comprises a driving transistor, a compensation transistor, a first reset transistor and a first light emission control transistor, wherein a subthreshold swing of the driving transistor is greater than a subthreshold swing of the compensation transistor and the first reset transistor; wherein, in the active layer, a first end of the driving transistor is located in the first active portion, a second end of the compensation transistor is located in the second active portion, and a second end of the first light emission control transistor is located in the third active portion; a first end of the driving transistor is electrically connected to a second end of the compensation transistor, a first end of the compensation transistor is electrically connected to a second end of the first reset transistor, and a second end of the driving transistor is electrically connected to a second end of the first light emission control transistor.

7. The preparation method according to claim 6, characterized in that: The step of forming a plurality of metal layers on a side of the active layer away from the substrate further comprises: forming at least one insulating layer on one side of the active layer, wherein the insulating layer comprises a first insulating layer; forming a first via hole, a second via hole and a third via hole on the insulating layer, wherein the first via hole is connected to the first end of the driving transistor in the active layer, the second via hole is connected to the second end of the first reset transistor in the active layer, and the third via hole is connected to the second end of the first light emission control transistor; A first metal layer is formed on a side of the first insulating layer facing away from the substrate, wherein the first metal layer fills at least a portion of the first via hole, the second via hole and the third via hole, so that the first active portion is electrically connected to the second active portion and the third active portion.

8. The preparation method according to claim 7, characterized in that: The step of forming at least one insulating layer on one side of the active layer, wherein the insulating layer includes a first insulating layer, comprises: forming a second sub-insulating layer; performing a hydrogenation treatment on the second sub-insulating layer; exposing the first end of the driving transistor in the active layer through a first temporary via hole, and performing a dehydrogenation treatment on the active layer; A first sub-insulating layer is formed on a side of the second sub-insulating layer facing away from the substrate to form the first insulating layer.

9. The preparation method according to claim 8, characterized in that: After the step of hydrogenating the second sub-insulating layer, the step further includes: exposing the first active portion through a second temporary via hole; After the step of forming a first sub-insulating layer on a side of the second sub-insulating layer facing away from the substrate to form the first insulating layer, the method further comprises: forming a plurality of fourth via holes and a plurality of fifth via holes on the first insulating layer, wherein the fourth via holes are connected to the first active portion, and the fifth via holes are connected to the second active portion / the third active portion; The step of forming a first metal layer on a side of the first insulating layer facing away from the substrate further comprises: The first metal layer fills at least a portion of the fourth via hole and the fifth via hole, so that the first metal layer is electrically connected to the second active portion / the third active portion.

10. A display device, characterized in that: It comprises an array substrate as claimed in any one of claims 1 to 5 or an array substrate prepared by the preparation method as claimed in any one of claims 6 to 9.

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