Semiconductor device and power conversion device

Abstract

This semiconductor device is provided with: a gate voltage control circuit that applies an ON bias and an OFF bias to a gate terminal of a power semiconductor element in accordance with a first drive signal; and an off-bias voltage control circuit that changes the voltage level of the off-bias in accordance with the first drive signal and the second drive signal, and controls the application period of the changed off-bias.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to driving a semiconductor element for electric power. Background Art

[0002] One of the problems related to the reliability of power semiconductor elements is gate mis-triggering. When gate mis-triggering occurs, the high-voltage power supply on the upper branch side and the low-voltage power supply on the lower branch side of the phase in the power inverter that caused the mis-triggering are short-circuited. As a result, a large short-circuit current flows between the power supplies, causing an increase in the loss of the inverter device, and in the worst case, sometimes causing thermal runaway.

[0003] As a countermeasure for false triggering of the gate, a method of applying a negative bias between the gate and the source of a power semiconductor element is widely known. The false triggering of the gate is caused by the displacement current generated during the switching action of the power semiconductor element on the opposite branch side. The displacement current is proportional to the voltage change rate of the power conversion element on the opposite branch side, so the higher the speed of the switching action, the greater the displacement current, and as a result, it is easy to cause false triggering of the switch side element. Here, when a negative bias is applied at the timing of false triggering, the gate threshold voltage will not be exceeded and the upper and lower branch elements can be avoided from being short-circuited. The larger the negative bias, the greater the effect of preventing false triggering.

[0004] On the other hand, when a negative bias is applied between the gate and the source, in the past, the gate was driven in a manner that a negative bias was always applied during the cutoff action of the power semiconductor element. When the negative bias is applied for a long time like this, pressure is applied to the gate oxide film of the power semiconductor element. In a report related to a metal oxide semiconductor field effect transistor (SiC-MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor) made of silicon nitride, it is recorded that when the pressure on the gate oxide film increases, it becomes a cause of degradation of the characteristics and failure of the power semiconductor element. As a result, the overall reliability of the power inverter system is reduced.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2013-219874

[0008] Non-patent literature

[0009] Non-patent literature 1: Andreas Marz and 3 others, “Comparison of SiC MOSFET gate-drive concepts to suppress parasitic turn-on in low inductance power modules,” EPE, 2017. Summary of the invention

[0010] In Patent Document 1, the voltage applied to the gate terminal of the power semiconductor element includes two voltages, namely, a first voltage and a second voltage whose voltage level is lower than the first voltage. The disconnection action of the power semiconductor element is performed using the first voltage, but the voltage of the first voltage is generally not greater than the negative bias applied to the gate terminal. That is, the switching loss of the power semiconductor element increases compared to the case of using the second voltage. On the other hand, when the first voltage is increased, the switching loss is improved by speeding up the connection action, but until the connection action of the power semiconductor element on the opposite branch side including the dead time after the disconnection action is completed, a negative bias (for example, a second voltage) whose voltage is greater than the first voltage must be continuously applied to the gate. Therefore, the above-mentioned problem of pressure on the gate oxide film occurs, and there is a contradictory relationship that the reliability of the power converter as a whole is reduced.

[0011] In the case of non-patent document 1, a negative bias is applied to the gate terminal of the branch element during the period from the start of the disconnection operation of the power semiconductor element to the end of the connection operation of the power semiconductor element on the opposite branch side. That is, a negative bias is continuously applied to the gate terminal of the branch element during the dead time and the switching operation. Therefore, in a system with a large setting value of the dead time, there is a possibility that the effect of reducing the pressure on the gate oxide film is insufficient.

[0012] The present disclosure is made to solve the above-mentioned problems, and an object of the present disclosure is to provide a semiconductor device and a power conversion device capable of improving the reliability of a power semiconductor element.

[0013] A semiconductor device according to a certain embodiment comprises: a gate voltage control circuit that applies an on bias and an off bias to a gate terminal of a power semiconductor element according to a first drive signal; and an off bias voltage control circuit that changes the voltage level of the off bias according to the first drive signal and a second drive signal and controls the application period of the changed off bias.

[0014] A power conversion device according to a certain embodiment comprises: a first power semiconductor element; a second power semiconductor element, which is arranged on the opposite branch side connected in series with the first power semiconductor element; and first and second gate drive circuits, which are arranged corresponding to the first and second power semiconductor elements, respectively, and drive the corresponding power semiconductor elements according to first and second drive signals. Each gate drive circuit includes: a gate voltage control circuit, which applies a conduction bias and an off-bias to the gate terminal of the power semiconductor element according to the corresponding drive signal; and an off-bias voltage control circuit, which changes the voltage level of the off-bias according to the first and second drive signals, and controls the application period of the changed off-bias.

[0015] The semiconductor device and the power conversion device according to the present disclosure can improve the reliability of power semiconductor elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a block diagram for explaining the function of the gate drive circuit 100 of the power semiconductor device according to the first embodiment.

[0017] Figure 2 This is a diagram for explaining the specific configuration of the first control circuit 21 and the second control circuit 31 according to the first embodiment.

[0018] Figure 3 This is a diagram for explaining a timing chart when the gate driving circuit 100 according to the first embodiment controls the gate of the power semiconductor element 10 .

[0019] Figure 4 This is a diagram for explaining the gate driving circuit 101 according to the second embodiment.

[0020] Figure 5 This is a diagram for explaining a timing chart when the gate driving circuit 101 according to the second embodiment controls the gate of the power semiconductor element.

[0021] Figure 6 This is a block diagram for explaining the function of gate drive circuit 100# of the power semiconductor device according to the third embodiment.

[0022] Figure 7 This is a diagram for explaining the specific configuration of first control circuit 21# and second control circuit 31# according to the third embodiment.

[0023] Figure 8 1 is a diagram for explaining the waveform of the gate voltage Vgs of the SiC-MOSFET to which the gate drive circuit 100 of the present disclosure is applied.

[0024] Fig. 9This is a diagram for explaining a timing chart when the gate driving circuit 101 according to the fifth embodiment controls the gate of the power semiconductor element.

[0025] Fig.10 This is a block diagram for explaining the functions of the integrated drive circuit 102 according to the sixth embodiment.

[0026] Fig.11 This is a block diagram showing the configuration of a power conversion system according to the seventh embodiment. DETAILED DESCRIPTION

[0027] Implementation method 1.

[0028] Hereinafter, a gate drive circuit of a power semiconductor device as an example of the present disclosure will be described.

[0029] Figure 1 This is a block diagram for explaining the function of the gate driving circuit 100 according to the first embodiment.

[0030] Reference Figure 1 The gate drive circuit 100 controls the gate of the power semiconductor element 10 connected between the DC high voltage power sources according to the input of the external drive signal IN1 and the external drive signal IN2. Specifically, the gate drive circuit 100 controls the so-called switching operation of switching the on and off operation of the power semiconductor element 10.

[0031] The power semiconductor element 10 is equivalent to a switching element of the main circuit in the inverter circuit of the power conversion device. For example, it is a 2in1 half-bridge circuit, a 4in1 full-bridge circuit, or an element of a 6in1 three-phase inverter. These circuit structures form the inverter output voltage through PWM control, so a high voltage of more than several hundred V is applied between the drain and the source in the element in the cut-off operation. In addition, a large current corresponding to the system of the power conversion device flows in the element in the conduction operation. Regarding these operation states, the gate voltage that turns the power semiconductor element 10 on and off is controlled according to the external drive signal IN1.

[0032] The gate driving circuit 100 includes a gate voltage control circuit 20 and an off bias voltage control circuit 30 .

[0033] The gate voltage control circuit 20 controls the on bias and off bias of the gate of the power semiconductor element 10 .

[0034] The gate voltage control circuit 20 includes a first control circuit 21 and a first switching circuit 22 .

[0035] The first control circuit 21 controls the gate control signal in accordance with the input external drive signal IN1 so that the power semiconductor element 10 performs a desired switching operation. Specifically, the gate control signal is set to "1" during the period when the power semiconductor element 10 should be turned on, and the gate control signal is set to "0" during the period when the power semiconductor element 10 should be turned off. These two-value voltage signals can be formed by generating a pulse waveform using a communication signal source such as a 5V system or a 3.3V system of a logic circuit.

[0036] The first switching circuit 22 is disposed between the gate of the power semiconductor element 10 and the first control circuit 21. The first switching circuit 22 has a high side connected to the positive voltage source Vdd and a low side connected to the second switching circuit 32.

[0037] The first switching circuit 22 includes an NPN transistor 22A, a PNP transistor 22B, and a resistor 22C.

[0038] The NPN transistor 22A and the PNP transistor 22B are connected in series.

[0039] The NPN transistor 22A is connected to a positive voltage source Vdd and to an output node.

[0040] The PNP transistor 22B is connected to the output node and the output node of the second switching circuit 32 .

[0041] The gates of the NPN transistor 22A and the PNP transistor 22B are connected to the first control circuit 21 via the resistor 22C.

[0042] The first switching circuit 22 can switch the current path according to the gate control signal output from the first control circuit 21. As a result, the path through which the gate current of the power semiconductor element 10 flows changes, which is equivalent to switching the charging and discharging of the gate. Therefore, the first switching circuit 22 plays a role in switching the gate voltage applied to the gate of the power semiconductor element 10 and controlling the on-off operation of the power semiconductor element 10.

[0043] The off bias voltage control circuit 30 controls the level of the off bias applied to the gate in the off operation of the power semiconductor element 10 according to the external drive signal IN1 and the external drive signal IN2. Specifically, in the off bias voltage control circuit 30, since it is a voltage level in the off operation of the power semiconductor element 10, there is a possibility that it exceeds the gate threshold voltage of the power semiconductor element 10 in the case of a positive value, so it is set to be always 0V or less.

[0044] In addition, the number of switching of the off bias level is set to two as an example.

[0045] In the present embodiment, the external drive signal IN1 and the external drive signal IN2 are used for switching between the two cut-off bias levels. The external drive signal IN1 is the same as the input signal to the first control circuit 21. The external drive signal IN2 needs to provide the gate drive circuit 100 with timing information of the gate mis-triggering (also referred to as the self-turn-on phenomenon) of the power semiconductor element 10 described later. The external drive signal IN2 is provided as a unit independent of the external drive signal IN1.

[0046] The off bias voltage control circuit 30 includes a second control circuit 31 and a second switching circuit 32 .

[0047] The second control circuit 31 outputs an off-bias voltage control signal based on the input of the external drive signal IN1 and the external drive signal IN2, and the off-bias voltage control signal can arbitrarily adjust the voltage level and application period of the off-bias applied to the gate of the power semiconductor element 10. The specific method will be described later.

[0048] The second switching circuit 32 is connected to the second control circuit 31 , the first switching circuit 22 , and the source electrode of the power semiconductor element 10 .

[0049] The second switching circuit 32 has a high side connected to the source electrode of the power semiconductor element 10 , and a low side connected to the negative voltage source Vneg.

[0050] The second switching circuit 32 includes an NPN transistor 32A, a PNP transistor 32B, and a resistor 32C.

[0051] The NPN transistor 32A and the PNP transistor 32B are connected in series.

[0052] The NPN transistor 32A is connected to the source electrode of the power semiconductor element 10 and is connected to an output node. The output node is connected to the first switching circuit 22.

[0053] The PNP transistor 32B is connected to the output node and the negative voltage source Vneg.

[0054] The gates of the NPN transistor 32A and the PNP transistor 32B are connected to the second control circuit 31 via the resistor 32C.

[0055] The second switching circuit 32 switches the off bias level of the gate according to the off bias voltage control signal generated by the second control circuit 31. Specifically, the reference potential Vs and the negative voltage source Vneg based on the source potential of the power semiconductor element 10 are switched. That is, by switching the source potential of the power semiconductor element 10, the off bias level applied to the gate of the power semiconductor element 10 is switched.

[0056] Hereinafter, the state in which the reference potential Vs is connected will be referred to as a “shallow off bias”, and the state in which the negative voltage source Vneg is connected will be referred to as a “deep off bias” as needed.

[0057] However, the shallow off bias and deep off bias applied to the gate of the power semiconductor element 10 are based on the off operation of the power semiconductor element 10. Therefore, it cannot be uniquely determined only by the operation of the second switching circuit 32, and the shallow off bias and deep off bias applied to the gate of the power semiconductor element 10 are switched by the first switching circuit 22 only during the off operation of the power semiconductor element 10. In other words, the off bias level applied to the gate of the power semiconductor element 10 is controlled according to the states of the gate voltage control circuit 20 and the off bias voltage control circuit 30.

[0058] As components not shown in the figure, the first control circuit 21 and the second control circuit 31 may include passive components such as resistors, capacitors, and diodes, and RC filters. They may also be equipped with Schmitt trigger components for adjusting the transmission signal. In addition, the first control circuit 21 has a delay line (which can be implemented by a delay IC or a buffer circuit) for delaying the transmission signal for a certain period of time, and the second control circuit 31 has a logic operation circuit for performing logic operations such as logical OR and logical AND of the transmission signal.

[0059] In addition, as a component not shown in the figure, the first switching circuit 22 and the second switching circuit 32 are totem pole circuit structures in which switch elements are arranged in upper and lower branches, and can perform two-stage control on the output according to the input gate control signal. Specifically, it can be a push-pull circuit including the high-side element composed of NPN transistors and the low-side element composed of PNP transistors as described above, or other structures can be adopted.

[0060] Figure 2 This is a diagram for explaining the specific configuration of the first control circuit 21 and the second control circuit 31 according to the first embodiment.

[0061] Reference Figure 2 , the first control circuit 21 includes a control unit 21A and a delay circuit 21B.

[0062] The control unit 21A receives the external drive signal IN1 as an input signal and generates a regulated signal, which can be realized by, for example, a capacitor for voltage retention, a diode element for preventing reverse conduction, or a Schmitt trigger element for regulating a transmission signal.

[0063] The delay circuit 21B receives the output signal of the control unit 21A and delays the output signal by a certain amount of time to generate a delayed signal. For example, it can be a delay line that delays the transmission signal by a certain amount of time, and the delay line can be composed of a logic IC or a buffer element.

[0064] By configuring the first control circuit 21 in this way, Figure 1 The gate control signal input to the first switching circuit 22 shown is delayed by a certain amount of time based on the external drive signal IN1. According to the delay amount of the gate control signal, the operation of the first switching circuit 22 can also be delayed by the same amount of time. Therefore, the timing of the switching operation of the power semiconductor element 10 is also delayed by the same amount of time as a whole. In addition, the gate delay amount of the power semiconductor element 10 can be variably set by each element having a plurality of terminals in the logic IC and buffer element constituting the delay line, or by independently setting the delay amount of the logic IC and the buffer element, or by using a jumper pin to switch the connection destination of the circuit.

[0065] The second control circuit 31 includes delay circuits 31A and 31B, inverters IV0 and IV1 , AND circuits AD0 and AD1 , and a NOR circuit NR.

[0066] The AND circuit AD0 receives the external drive signal IN1 via the delay circuit 31A and the external drive signal IN1 via the inverter IV0 , and outputs an AND logical operation result to the NOR circuit NR.

[0067] The AND circuit AD1 receives the external drive signal IN2 and the external drive signal IN2 via the delay circuit 31B and the inverter IV1 , and outputs the AND logic operation result to the NOR circuit NR.

[0068] The NOR circuit NR receives inputs from the AND circuits AD0 and AD1 and outputs a NOR logic operation result.

[0069] The delay circuits 31A and 31B are delay circuits for generating delay signals. For example, they can be composed of an RC filter as a general delay time adjustment circuit, and more preferably, they have a Schmitt trigger element for adjusting the transmission signal. In addition, the delay amounts of the delay circuits 31A and 31B can be adjusted to different delay amounts.

[0070] The NOR circuit NR normally outputs an off bias voltage control signal ("1").

[0071] As a result, the NPN transistor 32A of the second switching circuit 32 is turned on.

[0072] On the other hand, when the external drive signal IN1 changes from "1" to "0", the AND circuit AD0 outputs a one-shot pulse signal proportional to the delay amount of the delay circuit 31A. In response, the NOR circuit NR turns on the PNP transistor 32B of the second switching circuit 32 in response to the period of the one-shot pulse signal.

[0073] In addition, when the external drive signal IN2 changes from "0" to "1", the AND circuit AD1 outputs a one-shot pulse signal proportional to the delay amount of the delay circuit 31B. In response, the NOR circuit NR turns on the PNP transistor 32B of the second switching circuit 32 in response to the period of the one-shot pulse signal.

[0074] The second control circuit 31 is a logic operation circuit that receives two signals, the external drive signals IN1 and IN2, performs logic operations such as logical OR and logical AND on the two signals, and generates a cutoff bias voltage control signal based on two output signals. For example, it can be composed of a discrete IC element with only one built-in element, or it can be composed of a 2in1 logic IC with two logic functions. It can also be a structure that has at least one AND element and at least one OR element that perform logic operations.

[0075] By providing the delay circuits 31A and 31B, it is possible to generate an off-bias voltage control signal that follows the external drive signal IN1 and the external drive signal IN2 and adjust the timing of the signal.

[0076] Specifically, the application timing and application time of the deep off bias Vneg applied to the gate of the power semiconductor element 10 can be determined according to the delay amount of the delay circuits 31A and 31B. In addition, the resistor and capacitor of the RC filter of the delay circuits 31A and 31B can also be composed of a variable resistor and a variable capacitor. In such a configuration, the application timing and application time of the deep off bias Vneg of the power semiconductor element 10 can be variably set.

[0077] According to the first embodiment, the control unit 21A and the delay circuit 21B are provided inside the first control circuit 21 included in the gate voltage control circuit 20, and the delay circuits 31A and 31B are provided inside the second control circuit 31 included in the off bias voltage control circuit 30, so that an appropriate off bias level control signal can be generated, and the timing and application time of the deep off bias Vneg of the power semiconductor element 10 can be determined. As a result, the reliability of the power semiconductor element 10 is improved.

[0078] Next, a specific operation of the gate driving circuit 100 according to the first embodiment will be described.

[0079] Figure 3 This is a diagram for explaining a timing chart when the gate driving circuit 100 according to the first embodiment controls the gate of the power semiconductor element 10 .

[0080] Reference Figure 3 , showing the difference between the operation of the gate drive circuit 100 according to Embodiment 1 and the comparative example. The horizontal axis represents time, and the vertical axis represents the external drive signal IN1, the external drive signal IN2, and the gate voltage Vgs of the power semiconductor element 10, respectively.

[0081] At time t0, the gate drive circuit 100 starts discharging to the gate of the power semiconductor element 10 in response to the change of the external drive signal IN1 from "1" to "0". That is, the power semiconductor element 10 performs an off operation. The gate charge charged during the on operation is extracted, so the gate voltage Vgs of the power semiconductor element starts to decrease.

[0082] First, the gate voltage Vgs drops sharply from the on-bias voltage Vdd. Next, while the drain-source voltage Vds (not shown) of the power semiconductor element 10 begins to rise, the gate voltage Vgs maintains a certain constant voltage value. This period is called the Miller period, and it lasts until the change in the parasitic capacitance between the gate and the drain that depends on the drain-source voltage Vds disappears (generally in the case of SiC-MOSFET, the Miller period is very short). After the Miller period ends, the gate voltage Vgs starts to drop again, reaching a deep cutoff bias Vneg, and the disconnection action ends. Here, there are major differences between the gate drive circuit involved in Implementation 1 and the comparative example (here, the structure according to Patent Document 1).

[0083] The biggest difference is whether there is a deep cutoff bias Vneg.

[0084] The gate drive circuit 100 according to the first embodiment has a function of applying a deep off-bias Vneg to the gate, so that the power semiconductor element 10 is turned off faster than the comparative example which does not have the deep off-bias application function. In the interval from time t0 to the start of the Miller period and from the end of the Miller period to the end of the turn-off operation, the absolute value of the change rate dVgs / dt of the gate voltage Vgs is larger in the structure according to the first embodiment than in the structure of the comparative example.

[0085] This effect can improve the turn-off loss of the power semiconductor element 10, thereby achieving advantages such as suppression of heat generation in the power conversion device and miniaturization of the cooler.

[0086] On the other hand, in the structure according to the comparative example, since the turn-off operation is based on the shallow off bias Vs, there is a concern that the turn-off loss of the power semiconductor element 10 may not be sufficiently reduced. Furthermore, there are also differences in the characteristics of the gate voltage Vgs after the turn-off operation.

[0087] Since the structure according to the first embodiment includes the deep off bias Vneg, the gate voltage Vgs drops from the shallow off bias Vs to the deep off bias Vneg.

[0088] In the gate drive circuit 100 according to the first embodiment, at time t1 when the gate voltage Vgs reaches the deep off bias Vneg, the turn-off operation of the power semiconductor element 10 is completed.

[0089] According to the structure of the gate drive circuit 100 involved in the first embodiment, a deep cut-off bias Vneg is applied to the gate of the power semiconductor element 10 from time t1. Therefore, although it may become a cause of characteristic degradation and failure due to the pressure on the gate oxide film, the period from time t1 to time t2 when the deep cut-off bias Vneg starts to return to the shallow cut-off bias Vs is sufficiently shorter than the dead time period Td set for the inverter circuit of the power conversion device (both the upper branch and the lower branch perform the cut-off operation). That is, the actual pressure on the gate oxide film is very small. Therefore, the high reliability of the power semiconductor element 10 can be ensured.

[0090] In this example, during the period from time t0 to time t2, a deep off bias Vneg is applied to the gate of the power semiconductor element 10. This period is defined as a first period. Next, the situation after time t2 will be described.

[0091] During the dead time period Td, the gate voltage Vgs of the power semiconductor element 10 is set to a shallow off bias Vs, and the external drive signal IN1 and the external drive signal IN2 are set to “0”.

[0092] Here, the external drive signal IN2 has a function of notifying the timing of erroneous triggering of the gate of the power semiconductor element 10 , that is, the timing of turning on the opposing branch element.

[0093] Therefore, at the end time point of the dead time period Td, the external drive signal IN2 changes from “0” to “1”.

[0094] The gate drive circuit 100 determines that it is the timing for the opposite branch element of the power semiconductor element 10 to turn on according to the change of the external drive signal IN2, and the gate voltage Vgs of the power semiconductor element 10 changes from the shallow off bias Vs to the deep off bias Vneg again. After that, the opposite branch element performs the turning-on operation, so that the gate voltage Vgs of the power semiconductor element 10 rises from the deep off bias Vneg. Here, by setting the value of the deep off bias Vneg to be greater than the voltage value of the rise of the gate voltage Vgs, the gate voltage Vgs does not exceed 0V. That is, it can be said that there is a sufficient margin for the gate threshold voltage of the power semiconductor element 10.

[0095] Here, the period ton during which the opposing branch element of the power semiconductor element 10 actually starts turning on from time t3 is consistent with the delay amount of the gate control signal to the opposing branch element. It takes time to establish the deep off bias Vneg of the gate voltage Vgs applied to the power semiconductor element 10, so the delay of the gate control signal to the opposing branch element is inserted. As a result, it is possible to prevent the gate of the power semiconductor element 10 from being erroneously triggered without any problems.

[0096] At time t4 after the opposite branch element of the power semiconductor element 10 is turned on, the gate voltage Vgs of the power semiconductor element 10 starts to return from the deep off bias Vneg to the shallow off bias Vs again. That is, the pressure applied to the gate oxide film of the power semiconductor element 10 is very small. That is, during the period from time t3 to time t4, the deep off bias Vneg is applied to the gate of the power semiconductor element 10. Here, the period from the end time point of the dead time period Td to the shallow off bias being applied to the gate of the power semiconductor element 10 is defined as the second period. That is, the period from time t3 to time t4 is included in the second period.

[0097] The gate drive circuit 100 according to the first embodiment improves the switching loss by applying a deep off-bias to the power semiconductor element 10, and can also suppress the application time of the deep off-bias to a limited interval such as the first period and the second period to improve the reliability of the power semiconductor element 10. Thus, the life of the power semiconductor element is prolonged, and an economical power converter system can be realized.

[0098] Implementation method 2.

[0099] In the second embodiment, the operation of the gate drive circuit 101 including the gate resistance control circuit 40 between the power semiconductor element 10 and the first switching circuit 22 will be described.

[0100] Figure 4This is a diagram for explaining the gate driving circuit 101 according to the second embodiment.

[0101] Reference Figure 4 The gate drive circuit 101 is different from the gate drive circuit 100 according to the first embodiment in that a gate resistance control circuit 40 is provided between the power semiconductor element 10 and the first switching circuit 22. The other structures are the same, and therefore the detailed description thereof will not be repeated.

[0102] The gate resistance control circuit 40 includes a gate resistance 41 and a bypass switching element 42 connected in parallel to both ends of the gate resistance 41 .

[0103] The gate resistor 41 adjusts the switching speed of the power semiconductor element 10 , specifically, adjusts the turning-on speed and the turning-off speed.

[0104] When the resistance value of the gate resistor 41 is large, the surge voltage and electromagnetic noise of the drain-source voltage Vds during switching can be reduced, but the switching loss increases. On the contrary, when the resistance value of the gate resistor 41 is small, the relationship between the surge voltage of the drain-source voltage Vds, electromagnetic noise and switching loss is opposite to the case where the resistance value is large.

[0105] The bypass switching element 42 performs an on-state operation and an off-state operation according to the ON / OFF command of the gate control signal. The bypass switching element 42 is connected in parallel with the gate resistor 41. After the bypass switching element 42 is turned on, the gate current flows through the bypass switching element 42, and after the off-state operation, the gate current flows through the gate resistor 41.

[0106] The timing for turning on the bypass switching element 42 and bypassing the gate resistor 41 according to the second embodiment is when the gate off bias level is switched between the deep off bias Vneg and the shallow off bias Vs.

[0107] Specifically, in the first period, until the turn-off action of the power semiconductor element 10 is completed, the bypass switching element 42 maintains the turn-off action, and from the time point when the turn-off action of the power semiconductor element 10 is completed and the deep turn-off bias Vneg is established until it is switched to the shallow turn-off bias Vs, the bypass switching element 42 is turned on.

[0108] As an example, during the period from time Tb1 to time Tb2, the bypass switching element 42 is turned on.

[0109] Similarly, the timing for causing the bypass switching element 42 involved in embodiment 2 to perform the off action and switch to the path via the gate resistor 41 is from the time when the dead time period Td ends and the shallow off bias Vs is switched to the deep off bias Vneg in preparation for the on action of the opposite branch element to the time when the on action of the opposite branch element starts.

[0110] Specifically, in the second period, the bypass switching element 42 is kept on during the period from the shallow off bias Vs to the establishment of the deep off bias Vneg, and is turned off before the opposing arm element is turned on.

[0111] As an example, during the period from time T3 to time Tb3, the bypass switching element 42 is turned on.

[0112] By performing the above-described operation of the bypass switching element 42 , the bypass path not passing through the gate resistor 41 is utilized only in switching between the deep off bias Vneg and the shallow off bias Vs applied to the gate of the power semiconductor element 10 .

[0113] As described above, in the first embodiment, the second switching circuit 32 also operates in conjunction with the first switching circuit 22. That is, the switching speed of the deep cut-off bias Vneg and the shallow cut-off bias Vs depends on the circuit constant of the discharge path of the power semiconductor element 10. In short, if the value of the gate resistor 41 is large, the switching speed of the deep cut-off bias Vneg and the shallow cut-off bias Vs becomes slow according to the value. In the second embodiment, by providing a bypass path that does not pass through the gate resistor 41, the switching speed of the deep cut-off bias Vneg and the shallow cut-off bias Vs can be accelerated. In other words, the level and timing of the cut-off bias applied to the gate of the power semiconductor element 10 can be appropriately operated.

[0114] Furthermore, the gate resistor 41 is effective for false triggering of the gate. The reason is that if the gate resistor 41 is a small value (for example, 0 ohms), the floating inductance component of the gate wiring of the power semiconductor element 10 generates vibration, which may cause false triggering of the gate. In addition, since it is easily affected by electromagnetic noise, there is also the possibility of causing false triggering of the gate. As a countermeasure for these phenomena, when the gate is falsely triggered, that is, the opposite branch element is turned on, the bypass switch element 42 is turned off and set to a path through the gate resistor 41.

[0115] Next, a specific operation of the gate driving circuit 101 according to the second embodiment will be described.

[0116] Figure 5This is a diagram for explaining a timing chart when the gate driving circuit 101 according to the second embodiment controls the gate of the power semiconductor element.

[0117] Reference Figure 5 The basic operation of the gate driving circuit 101 according to the second embodiment is the same as that of the gate driving circuit 100 according to the first embodiment, and therefore the detailed description thereof will not be repeated.

[0118] At time t0, the turn-off operation of the power semiconductor element 10 starts. As shown in the figure, the gate voltage of the power semiconductor element 10 decreases to the deep cut-off bias Vneg, and the deep cut-off bias Vneg is established at time t1. Then, at time t2, in order to shorten the application time of the deep cut-off bias Vneg, the deep cut-off bias Vneg is switched to the shallow cut-off bias Vs.

[0119] Here, the difference from the gate drive circuit 100 involved in the first embodiment is that at the time tb1 within the interval between the time t1 and the time t2 included in the first period, the bypass switch element 42 performs the on action. By adding the action of this embodiment at the time tb1, the gate voltage of the power semiconductor element 10 changes at the time t2. Specifically, the switching speed from the deep cut-off bias Vneg to the shallow cut-off bias Vs becomes faster, and it is possible to quickly return to the shallow cut-off bias Vs as shown in the figure. Since it quickly returns to the shallow cut-off bias Vs, the application time of the deep cut-off bias Vneg can be reliably shortened compared with the first embodiment. In addition, at the time tb2, the bypass switch element 42 performs the off action.

[0120] Furthermore, after the dead time period Td has elapsed, the external drive signal IN2 notifying the timing of the turning-on operation of the opposing arm element changes from “0” to “1.” That is, at time t3, the dead time period Td ends.

[0121] At time t3 , the gate voltage of the power semiconductor element 10 is switched again from the shallow off bias Vs to the negative bias Vneg.

[0122] At this time t3, the bypass switching element 42 is turned on. As a result, the switching speed from the shallow off bias Vs to the deep off bias Vneg is faster than that of the first embodiment because the gate resistor 41 is bypassed, and as shown in the figure, the deep off bias Vneg can be quickly applied to the gate of the power semiconductor element 10.

[0123] Then, at time tb3, the bypass switching element 42 performs an opening operation.

[0124] At the subsequent time ton, the opposing arm element performs a turning-on operation, causing a gate erroneous triggering of the power semiconductor element 10. Here, at a time tb3 within the interval between the time t3 and the time ton included in the second period, the bypass switching element 42 performs a turning-off operation.

[0125] In this way, by adding the operation of the gate resistance control circuit 40 involved in the second embodiment at the time tb3, the gate false triggering of the power semiconductor element 10 caused by the above-mentioned floating inductance and electromagnetic noise can be prevented. Specifically, by setting the gate resistor 41 so that the bypass switching element 42 performs the cut-off operation, the gate false triggering tolerance equivalent to that of the first embodiment can be obtained as shown in the figure.

[0126] During the period after time tb2 in the dead time period Td, that is, during the off bias period of the power semiconductor element 10, the bypass switching element 42 is turned off in the gate resistance control circuit 40 to connect the gate resistance 41. By connecting the gate resistance 41 even during the off operation of the power semiconductor element 10, it is possible to suppress the vibration of the gate due to external factors. As a result, it is possible to prevent the gate of the power semiconductor element 10 from being erroneously triggered.

[0127] The conduction period (tb1-tb2, t3-tb3) of the bypass switch element 42 can be set by the components described in Embodiment 1. Specifically, it can be realized by combining an RC filter (delaying the period from time t0 to tb1) and a logic operation circuit (creating a single pulse using the external drive signal IN1 and the external drive signal IN2) described in Embodiment 1. In addition, the conduction period (bypass period) of the bypass switch element 42 can also be set arbitrarily, and switching between conduction and cutoff can be performed over multiple locations.

[0128] The gate resistor 41 is composed of circuit elements such as general lead resistors and chip resistors, and can be a circuit constant and power capacity in accordance with the switching operation conditions of the power semiconductor element 10. The number of circuit elements constituting the gate resistor 41 is not limited to single or multiple, and the circuit structure is not limited to series or parallel. As for the bypass switch element 42, as long as it can cope with the gate capacitance of the power semiconductor element 10, it is sufficient to use an inexpensive discrete circuit element. The higher the high-speed responsiveness of the bypass switch element 42, the better. There is such a contradiction: when the gate threshold voltage is high, the risk of malfunction is reduced and the high-speed responsiveness is reduced, and when the gate threshold voltage is low, the high-speed responsiveness is improved and the risk of malfunction is increased.

[0129] The gate drive circuit 101 according to the second embodiment can further shorten the period of the deep off bias Vneg applied to the gate of the power semiconductor element 10 by providing the gate resistance control circuit 40 between the power semiconductor element 10 and the first switching circuit 22. Furthermore, by making the switching from the shallow off bias Vs to the deep off bias Vneg faster, the reliability of the power semiconductor element 10 is further improved.

[0130] Therefore, the life of the power semiconductor element 10 can be further extended, and the use of an economical power converter system can be promoted.

[0131] Implementation method 3.

[0132] In Embodiment 3, a configuration of a switching circuit different from that of Embodiment 1 will be described.

[0133] Figure 6 This is a block diagram for explaining the function of gate drive circuit 100# of the power semiconductor device according to the third embodiment.

[0134] Reference Figure 6 The gate driving circuit 100# differs from the gate driving circuit 100 in that the gate voltage control circuit 20 is replaced by a gate voltage control circuit 20#, and the cut-off bias voltage control circuit 30 is replaced by a cut-off bias voltage control circuit 30#.

[0135] The other structures are the same as those of the gate driving circuit 100 according to the first embodiment, and therefore the detailed description thereof will not be repeated.

[0136] The gate voltage control circuit 20 # is different from the gate voltage control circuit 20 in that the first control circuit 21 is replaced by a first control circuit 21 #, and the first switching circuit 22 is replaced by a first switching circuit 22 #.

[0137] The off bias voltage control circuit 30 # is different from the off bias voltage control circuit 30 in that the second control circuit 31 is replaced by a second control circuit 31 #, and the second switching circuit 32 is replaced by a second switching circuit 32 #.

[0138] First switching circuit 22# includes a PMOSFET 22P on the high side and an NMOSFET 22N on the low side.

[0139] The PMOSFET 22P and the NMOSFET 22N are connected in series.

[0140] The PMOSFET 22P is connected to a positive voltage source Vdd and to an output node.

[0141] The NMOSFET 22N is connected to the output node and the output node of the second switching circuit 32 .

[0142] Second switching circuit 32# includes a PMOSFET 32P on the high side and an NMOSFET 32N on the low side.

[0143] The PMOSFET 32P and the NMOSFET 32N are connected in series.

[0144] PMOSFET 32P is connected to the source electrode of power semiconductor element 10 and to an output node. The output node is connected to first switching circuit 22#.

[0145] The NMOSFET 32N is connected to the output node and the negative voltage source Vneg.

[0146] The switching circuit according to the third embodiment uses, for example, a wide bandgap semiconductor, and is particularly effective for a power conversion device suitable for high-frequency drive applications.

[0147] A CMOS circuit including the PMOSFET 22P and the NMOSFET 22N and the PMOSFET 32P and the NMOSFET 32N according to the third embodiment will be described.

[0148] The upper and lower branch elements are all made of MOSFET, so the power consumption is lower than that of bipolar transistors. In addition, when the switching frequency of the power inverter increases, the number of switching times of the gate drive circuit also increases accordingly. That is, it is very useful for the above-mentioned high-frequency drive application.

[0149] The output lines of PMOSFET 22P and NMOSFET 22N swing between the high-side power supply voltage Vdd applied to PMOSFET 22P and the low-side potential (shallow cutoff bias Vs or deep cutoff bias Vneg). Furthermore, a constant driving capability can be obtained without depending on the difference between the input voltage from the power supply voltage and the output voltage of the output line. By achieving such a driving output, a gate driving circuit 100# with high driving capability and high stability can be realized.

[0150] On the other hand, in the case of a general push-pull circuit, the swing range of the output line narrows according to the gate threshold voltage of the transistor elements of the upper and lower branches. That is, when the output voltage is outside the swing range, the output of the push-pull circuit becomes a floating state, showing unstable operation.

[0151] The gate drive circuit 100# according to the third embodiment can achieve high drive capability and stable operation by implementing the switching circuit with a CMOS circuit. These effects can improve the characteristics of the power semiconductor element 10 and suppress oscillation caused by fluctuations in the gate potential.

[0152] The advantages of CMOS circuits are described above, but there are also disadvantages of CMOS circuits. When the upper and lower branch elements are switched, there is a possibility that a through current flows between the power supply voltage on the high side and the reference potential on the low side. Due to the flow of this through current, there is a possibility that the power consumption of the gate drive circuit 100 increases. The increase in power consumption can also be said to be disadvantageous to the operation of high-frequency driving, which goes against the above advantages.

[0153] Therefore, a dead time period between the upper and lower branches may be generated in the front stage of PMOSFET 22P, NMOSFET 22N and PMOSFET 32P, NMOSFET 32N. By setting an appropriate dead time period, the through current flowing into the CMOS circuit can be reduced. For example, the signals applied to the gates of PMOSFET 22P, NMOSFET 22N and PMOSFET 32P, NMOSFET 32N may be controlled independently.

[0154] Figure 7 1 and 2 are diagrams for explaining the specific configuration of first control circuit 21# and second control circuit 31# according to Embodiment 3. The configuration of basic elements and the like are similar to those of Figure 2 The first control circuit 21 and the second control circuit 31 shown are the same, so duplicate descriptions are omitted.

[0155] Reference Figure 7 , the first control circuit 21# includes a control unit 21A# and a delay circuit 21B#.

[0156] Second control circuit 31# includes delay circuits 31A# and 31B#, an inverter IV, an AND circuit AD, and an OR circuit OR.

[0157] AND circuit AD receives external drive signal IN2 via delay circuit 31B# and inverter IV and external drive signal IN2 not via elements, additional circuits, etc., and outputs an AND logic operation result to OR circuit OR.

[0158] The OR circuit OR receives the external drive signal IN1 via the delay circuit 31A# and the input of the AND circuit AD, and outputs an OR logical operation result.

[0159] Delay circuits 31A# and 31B# are delay circuits for generating delayed signals. For example, they can be composed of an RC filter as a general delay time adjustment circuit, and more preferably, they have a Schmitt trigger element for adjusting the transmission signal. In addition, the delay amounts of delay circuits 31A# and 31B# can be adjusted to different delay amounts.

[0160] The OR circuit OR outputs an off bias voltage control signal ("1") when the power semiconductor element 10 is stably turned on without switching, and outputs an off bias voltage control signal ("0") when it is stably turned off without switching.

[0161] Thus, PMOSFET 32P of second switching circuit 32# repeats an on operation and an off operation at a constant cycle.

[0162] On the other hand, at the timing of the transition of the switching operation, the output of the off bias voltage control signal changes in a complex manner. In response to the change of the external drive signal IN1 from "1" to "0", the OR circuit OR maintains the output of "1" for a "period proportional to the delay amount of the delay circuit 31A#". In response, the OR circuit OR turns on the NMOSFET 32N of the second switching circuit 32# in response to the output maintenance period of "1".

[0163] In addition, when the external drive signal IN2 changes from "0" to "1", the AND circuit AD outputs a one-shot pulse signal proportional to the delay amount of the delay circuit 31B#. In response, the OR circuit OR turns on the NMOSFET 32N of the second switching circuit 32# in response to the one-shot pulse signal.

[0164] According to the present embodiment, the PMOSFET 22P and the NMOSFET 22N are provided inside the first control circuit 21 included in the gate voltage control circuit 20, and the PMOSFET 32P and the NMOSFET 32N are provided inside the second control circuit 31 included in the off bias voltage control circuit 30. Thus, the power semiconductor element 10 can achieve suppression of gate oscillation, which is a problem in high-frequency applications, while obtaining high characteristics.

[0165] In addition, the structure of the gate resistance control circuit 40 according to the second embodiment can also be further applied.

[0166] Implementation method 4.

[0167] In the fourth embodiment, another aspect related to the control of the off bias level applied to the gate of the power semiconductor element 10 will be described.

[0168] Figure 81 is a diagram for explaining the waveform of the gate voltage Vgs of the SiC-MOSFET to which the gate drive circuit 100 of the present disclosure is applied.

[0169] Reference Figure 8 , showing the case where the period of applying the deep cut-off bias is adjusted.

[0170] Here, the gate on bias is set to +20 V, the shallow off bias Vs is set to 0 V, and the deep off bias Vneg is set to -5 V. Except for the period of the deep off bias Vneg, all driving conditions are the same.

[0171] The waveform LA shows a case where the application period of the off bias is shorter than that of the waveform LB.

[0172] That is, in these waveforms, the period of the deep off bias Vneg is different.

[0173] By adjusting the time constant of the RC filter constituting the delay circuit included in the off-bias voltage control circuit 30 , the period of the deep off-bias Vneg is adjusted.

[0174] Specifically, the capacitance of the capacitor is adjusted to adjust the delay amount of the delay circuit, thereby adjusting the application period of the off bias.

[0175] Specifically, when two types of capacitors of the delay circuit are provided, 470 pF and 680 pF, the period of the deep off bias Vneg can be set to a short period by setting the capacitor capacitance ("470 pF"), thereby further reducing the stress on the gate oxide film.

[0176] For example, by using a capacitor as a variable capacitance element, the capacitance of the capacitor can be set to an optimum value, and the period of the off bias Vneg can be adjusted to an optimum value.

[0177] Implementation method 5.

[0178] In the fifth embodiment, another mode related to the operation of the gate drive circuit 100 including the gate resistance control circuit 40 according to the second embodiment will be described.

[0179] Fig. 9 This is a diagram for explaining a timing chart when the gate driving circuit 101 according to the fifth embodiment controls the gate of the power semiconductor element.

[0180] Reference Fig. 9 The gate driving circuit 101 according to the fifth embodiment has the same basic operation as the gate driving circuit 100 according to the second embodiment, and therefore the detailed description thereof will not be repeated.

[0181] and Figure 5Compared with the timing diagram of Figure 3 The gate resistance control circuit 40 described above is bypassed by the switching element 42 for turning on.

[0182] Through this action, Fig. 9 As shown, the gate voltage Vgs of the power semiconductor element 10 is quickly switched from the deep off bias Vneg to the shallow off bias Vs. Thus, the application time of the deep off bias Vneg to the gate of the power semiconductor element 10 is reliably shortened.

[0183] The time tb4 at which the bypass switch element 42 performs the turning-on operation is set to the period from the turning-on operation completion point of the opposing branch element of the power semiconductor element 10 to the time t4. This setting can suppress the vibration of the gate of the power semiconductor element 10 during the turning-on period of the opposing branch element, thereby avoiding the possibility of causing false triggering. In addition, the application time of the deep off bias Vneg of the power semiconductor element 10 can be shortened.

[0184] This embodiment can be achieved by Figure 4 The additional element is provided with a function of controlling the gate resistance control circuit 40 so as to reduce the value of the gate resistance 41 and determining the time tb3 as the timing of the on-operation of the bypass switching element 42.

[0185] Specifically, the time tb4 is determined by effectively utilizing the timing information of the time ton which is the timing of the turning-on operation of the opposing arm element of the power semiconductor element 10 .

[0186] For example, the timing information of the time ton can be obtained by providing an overvoltage detection circuit or a voltage change rate dVds / dt detection circuit between the drain electrode and the source electrode of the power semiconductor element 10. Alternatively, the gate current detection circuit can be connected in series to the gate resistance control circuit 40 in an adjacent manner. By synchronizing the detection information of these detection circuits with the signal of the second control circuit 31 included in the off bias voltage control circuit 30, the appropriate timing of the time tb3 can be adjusted.

[0187] Alternatively, a state timer for which time setting has been completed in advance may be provided in the second control circuit 31 included in the cut-off bias voltage control circuit 30. The time tb4 may also be set by conducting experiments in advance and measuring the time taken for the opposite branch element of the power semiconductor element 10 to turn on.

[0188] In the fifth embodiment, the timing of turning on the bypass switching element 42 included in the gate resistance control circuit 40 is further added to the configuration of the second embodiment. This can more preferably shorten the application time of the deep off bias Vneg applied to the gate of the power semiconductor element 10.

[0189] Implementation method 6.

[0190] In the sixth embodiment, the structure of the integrated drive circuit 102 will be described.

[0191] Fig.10 This is a block diagram for explaining the functions of the integrated drive circuit 102 according to the sixth embodiment.

[0192] Reference Fig.10 The integrated drive circuit 102 according to the sixth embodiment is different from the gate drive circuit 100 in that it includes two drive circuits, namely a gate drive circuit 100P and a gate drive circuit 100N, and is an integrated circuit in which these two gate drive circuits are built.

[0193] The integrated type refers to, for example, the upper and lower branches of the power semiconductor elements are connected in series, such as Fig.10 As shown, it can be applied to the structure of a half-bridge circuit often seen in a power module in which power semiconductor elements are packaged in a 2-in-1 format.

[0194] Regarding the power semiconductor elements 10P and the power semiconductor elements 10N connected in series to each other, the power semiconductor elements of the upper and lower arms are driven by a single drive circuit such as the integrated drive circuit 102 .

[0195] The input signals are the external driving signal IN1 and the external driving signal IN2.

[0196] As described in Embodiment 1, it may be a logical pulse signal that sets the external drive signal IN to "1" during a period when the corresponding power semiconductor element should be turned on, and sets the external drive signal IN to "0" during a period when the corresponding power semiconductor element should be turned off.

[0197] Here, the external drive signal IN1 controls the gate of the power semiconductor device 10P of the upper arm element and is input to the gate voltage control circuit 20P. The external drive signal IN2 controls the gate of the power semiconductor device 10N of the lower arm element and is input to the gate voltage control circuit 20N.

[0198] As described in Embodiment 1, the external drive signal IN2 for notifying the timing of turning on the power semiconductor element 10N, which is the lower arm element of the opposing arm element, is input to the off bias voltage control circuit 30P. The external drive signal IN1 for notifying the timing of turning on the power semiconductor element 10P, which is the upper arm element of the opposing arm element, is input to the off bias voltage control circuit 30N.

[0199] With this configuration, the same operation as that of the gate driving circuit 100 described in the first embodiment is performed.

[0200] The circuit configurations of the gate drive circuit 100P and the gate drive circuit 100N included in the integrated drive circuit 102 are basically the same, but when there is a deviation in the element characteristics between the power semiconductor elements 10P and 10N of the upper and lower branch elements, fine adjustments can be made internally in the cut-off bias voltage control circuits 30P and 30N. For example, by adjusting the timing of the deep cut-off bias Vneg and the shallow cut-off bias Vs for the cut-off bias voltage control circuits 30P and 30N, a more appropriate operation of the power semiconductor element can be achieved.

[0201] In the sixth embodiment, regarding the external drive signal IN1 and the external drive signal IN2, for example, an isolation element such as a photocoupler or an isolation transformer, or an isolation element having sufficient insulation resistance is provided inside the gate voltage control circuit 20P and the gate voltage control circuit 20N and the off bias voltage control circuit 30P and the off bias voltage control circuit 30N. The isolation element may be a multi-input, multi-output isolator IC, and in such a structure, the insulation process of the gate voltage control circuit 20P and the off bias voltage control circuit 30P can be common.

[0202] The positive voltage source Vdd_P provided to the gate drive circuit 100P must be composed of an insulating power supply, and the potential of the positive voltage source Vdd_P is a floating potential relative to the ground potential. In addition, the deep cut-off bias Vneg_P and the shallow cut-off bias Vs_P set inside the gate drive circuit 100P are also floating potentials relative to the ground potential. The positive voltage source Vdd_P is a floating power supply, so it is also possible to form an arbitrary potential using, for example, a three-terminal regulator and generate a suitable deep cut-off bias Vneg_P and a shallow cut-off bias Vs_P.

[0203] By satisfying such a configuration, the gate drive circuit 100P included in the integrated drive circuit 102 can cause the power semiconductor element 10P corresponding to the upper arm in the half-bridge circuit to operate electrically safely.

[0204] In this example, the configuration of a half-bridge circuit is described, but the method according to the fifth embodiment can also be applied to a power module for a three-phase inverter in which power semiconductor elements are packaged in a 6-in-1 format, for example.

[0205] The structure according to the sixth embodiment includes an integrated drive circuit 102 that integrates the drive circuits of the upper and lower arms in order to drive the upper and lower arm elements in the half-bridge circuit of the power conversion device. As a result, it is possible to drive the power semiconductor element 10P of the upper arm element and the power semiconductor element 10N of the lower arm element with a simple circuit structure without unnecessary addition of external drive signals or complicated processing.

[0206] Implementation method 7.

[0207] Embodiment 7 is an example in which the power conversion device of the above-mentioned embodiment is applied to a power conversion system. The present disclosure is not limited to a specific power conversion device, and the case in which the present disclosure is applied to a three-phase inverter is described below as Embodiment 7.

[0208] Fig.11 This is a block diagram showing the configuration of a power conversion system according to the seventh embodiment.

[0209] Reference Fig.11 The power conversion system involved in Embodiment 7 includes a power supply 1000, a power conversion device 1001, and a load 1004. The power supply 1000 is a DC power supply, and supplies DC power to the power conversion device 1001. The power supply 1000 can be composed of various power supplies, for example, it can be composed of a DC system, a solar cell, a storage battery, or it can be composed of a rectifier circuit connected to an AC system, and an AC / DC converter. In addition, the power supply 1000 can also be composed of a DC / DC converter that converts the DC power output from the DC system into a predetermined power.

[0210] The power conversion device 1001 is a three-phase inverter connected between the power supply 1000 and the load 1004, and converts the DC power supplied from the power supply 1000 into AC power, and supplies the AC power to the load 1004. The power conversion device 1001 includes: a main conversion circuit 1002, which converts the DC power into AC power and outputs it; and a control circuit 1003, which outputs a control signal for controlling the main conversion circuit 1002 to the main conversion circuit 1002.

[0211] Load 1004 is a three-phase motor driven by AC power supplied from power converter 1001. Load 1004 is not limited to a specific use, and is a motor mounted on various electrical devices, such as a motor for hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioners.

[0212] The power conversion device 1001 will be described in detail below. The main conversion circuit 1002 includes a power semiconductor element and a freewheeling diode (not shown), and converts DC power supplied from the power source 1000 into AC power by switching the power semiconductor element, and supplies the AC power to the load 1004 .

[0213] There are various examples of the specific circuit structure of the main conversion circuit 1002, and the main conversion circuit 1002 of the embodiment is a 2-level three-phase full-bridge circuit, which can be composed of 6 power semiconductor elements and 6 freewheeling diodes connected in anti-parallel with each power semiconductor element. The 6 power semiconductor elements are connected in series with each 2 power semiconductor elements to form upper and lower branches, and each upper and lower branch constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. In addition, the output terminals of each upper and lower branch, that is, the three output terminals of the main conversion circuit 1002, are connected to the load 1004.

[0214] The gate drive circuit described in Embodiments 1 to 6 for driving each power semiconductor element can be applied to the main conversion circuit 1002 .

[0215] The gate drive circuit generates a gate control signal for driving the power semiconductor element of the main conversion circuit 1002, and provides it to the control electrode of the power semiconductor element of the main conversion circuit 1002. Specifically, the control circuit 1003 outputs an external drive signal for turning on the power semiconductor element and an external drive signal for turning off the power semiconductor element to the control electrode of each power semiconductor element. When the switch element is maintained in the on state, the external drive signal is a voltage signal (on signal) above the threshold voltage of the power semiconductor element, and when the switch element is maintained in the off state, the external drive signal is a voltage signal (off signal) below the threshold voltage of the power semiconductor element.

[0216] The control circuit 1003 controls the power semiconductor elements of the main conversion circuit 1002 in such a manner that the desired power is supplied to the load 1004. Specifically, the time (on-time) when each power semiconductor element of the main conversion circuit 1002 should be in the on state is calculated according to the power to be supplied to the load 1004. For example, the main conversion circuit 1002 can be controlled by PWM control that modulates the on-time of the power semiconductor element according to the voltage to be output. In addition, a control instruction (external drive signal) is output to the gate drive circuit of the main conversion circuit 1002 in such a manner that an on signal is output to the power semiconductor element that should be in the on state and an off signal is output to the power semiconductor element that should be in the off state at each time point.

[0217] In the power conversion device according to the embodiment, the gate drive circuit described above that constitutes the main conversion circuit 1002 is applied, so that reliability can be improved.

[0218] In this embodiment, an example of applying the present disclosure to a 2-level three-phase inverter is described, but the present disclosure is not limited thereto and can be applied to various power conversion devices. In this embodiment, a 2-level power conversion device is used, but a 3-level or multi-level power conversion device can also be used. When power is supplied to a single-phase load, the present disclosure can also be applied to a single-phase inverter. In addition, when power is supplied to a DC load, the present disclosure can also be applied to a DC / DC converter or an AC / DC converter.

[0219] In addition, the power conversion device disclosed in the present invention is not limited to the case where the above-mentioned load is an electric motor. For example, it can also be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0220] The embodiments disclosed herein are to be considered in all respects as illustrative and non-restrictive. Furthermore, it is of course possible to combine a plurality of embodiments as appropriate, and it is expected that the power conversion device can be effectively used efficiently and economically by further improving the effects of each embodiment.

[0221] The scope of the present disclosure is indicated by the claims rather than the above description, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0222] (Explanation of Reference Numerals)

[0223] 10, 10N, 10P: power semiconductor element; 20, 20N, 20P: gate voltage control circuit; 21: first control circuit; 22: first switching circuit; 30, 30N, 30P: cut-off bias voltage control circuit; 31: second control circuit; 32: second switching circuit; 40: gate resistance control circuit; 41: gate resistance; 42: bypass switching element; 100, 100N, 100P, 101: gate drive circuit; 102: integrated drive circuit; 1000: power supply; 1001: power conversion device; 1002: main conversion circuit; 1003: control circuit; 1004: load.

Claims

1. A semiconductor device comprising: a gate voltage control circuit that applies an on bias and an off bias to a gate terminal of the power semiconductor element in accordance with a first drive signal; and The off bias voltage control circuit changes the voltage level of the off bias according to the first drive signal and the second drive signal, and controls the application period of the changed off bias.

2. The semiconductor device according to claim 1, wherein The cutoff bias voltage control circuit changes the voltage level of the cutoff bias during a first period according to the first drive signal during the period of applying the cutoff bias, and changes the voltage level of the cutoff bias during a second period according to the second drive signal during the period of applying the cutoff bias.

3. The semiconductor device according to claim 2, wherein: The second drive signal is a control signal for applying an on bias and an off bias to a gate terminal of a power semiconductor element on an opposing arm side connected in series to the power semiconductor element. The second period includes a period after the dead time period during which the turning-on operation of the power semiconductor element on the opposing arm side is completed.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The off bias voltage control circuit sets the first off bias to a second off bias lower than the first off bias in accordance with the first drive signal and the second drive signal.

5. The semiconductor device according to any one of claims 1 to 4, wherein: Also available: The gate resistance control circuit is provided between the power semiconductor element and the gate voltage control circuit, and controls the gate resistance of the power semiconductor element.

6. The semiconductor device according to claim 5, wherein: The gate resistance control circuit controls the gate resistance when changing the voltage level of the off bias.

7. The semiconductor device according to claim 6, wherein: The gate resistance control circuit sets the gate resistance to be large before changing the voltage level of the off bias, and sets the gate resistance to be small when changing the voltage level of the off bias.

8. The semiconductor device according to any one of claims 5 to 7, wherein: The gate resistance control circuit comprises: a resistor element provided between the power semiconductor element and the gate voltage control circuit; and The bypass circuit bypasses the resistance element.

9. The semiconductor device according to any one of claims 1 to 8, wherein: The cut-off bias voltage control circuit comprises: a first delay circuit, delaying the first driving signal; a second delay circuit for delaying the second driving signal; a logic circuit that generates a switching signal based on a combination of a delay signal of the first delay circuit and a delay signal of the second delay circuit; and The switching circuit changes the voltage level of the cutoff bias according to the switching signal.

10. A power conversion device comprising: 1st power semiconductor element; a second power semiconductor element provided on the opposite branch side connected in series with the first power semiconductor element; as well as The first gate driving circuit and the second gate driving circuit are respectively provided corresponding to the first power semiconductor element and the second power semiconductor element, and drive the corresponding power semiconductor element according to the first driving signal and the second driving signal. Each of the gate drive circuits comprises: The gate voltage control circuit applies an on bias and an off bias to the gate terminal of the power semiconductor element according to a corresponding drive signal; as well as The off bias voltage control circuit changes the voltage level of the off bias according to the first drive signal and the second drive signal, and controls the application period of the changed off bias.

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