Device channel degradation monitoring circuit and chip

Abstract

The application relates to the field of integrated circuits and chip technologies, and provides a device channel degradation monitoring circuit and a chip.The circuit comprises a degradation ring oscillator, the degradation ring oscillator comprises an odd number of serially connected degradation inverters; a first transistor in the degradation inverter is a high-voltage power transistor, the drain of the first transistor is connected with the drain of a second transistor through an isolation voltage-resistant device, the gate of the second transistor is connected with a second input end, and the node between the drain of the second transistor and the isolation voltage-resistant device is connected with a second output end.The defects that the existing monitoring circuit is only applicable to monitoring low-voltage SOC chips and cannot monitor high-voltage circuits and chips are overcome, the application can support the degradation monitoring and early warning of high-voltage devices and circuits, can be embedded into a power supply and an isolation driving chip, and overcomes the problem that only the aging reliability prediction of the chip at the initial factory shipment can be made, and the high-voltage power supply and the isolation chip cannot be monitored in real time and dynamically with the working time.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit and chip technology, and more specifically to a device channel degradation monitoring circuit and chip. Background Technology

[0002] Industrial chips used in power, rail transit, and automotive industries are typically mounted outdoors with their terminals, making them highly susceptible to strong transient electromagnetic interference generated by the operation of surrounding power devices such as IGBTs, coupled with environmental factors such as high temperature and high humidity. Industrial chips need to operate stably 24 / 7 in high / low temperature, high humidity, and strong electromagnetic environments, with a lifespan of over 15 years. This poses a significant challenge to the reliability of chip pins that are vulnerable to environmental interference.

[0003] As VLSI manufacturing technology rapidly advances towards deeper submicron dimensions, while the channel length, junction depth, and gate oxide thickness of devices are proportionally reduced and the substrate concentration is increased, the power supply voltage has not decreased proportionally. This leads to a significant increase in the lateral and longitudinal electric fields in the channel region. Hot carriers, under high electric fields, gain sufficient energy to overcome the interface barrier (3.2 eV for electron injection and 4.5 eV for hole injection) and inject into the oxide layer, generating oxide layer trap charges or interface trap charges. This increases or destabilizes the oxide layer charge, exacerbating device degradation. Currently, it is generally believed that four types of charges exist on the SiO2 side of the Si-SiO2 interface: 1) fixed oxide layer charge Qf; 2) mobile charge Qm; 3) interface trap charge Qit; and 4) oxide layer trap charge Qot. When the energy of hot electrons exceeds the Si-SiO2 interface barrier, they may overcome the barrier and inject into the gate oxide layer. Some carriers eventually reach the gate electrode, forming part of the gate current. During the process of hot carriers passing through the gate oxide layer to the gate electrode, the hot carriers will use their energy to open the bonds at the interface, such as Si-H and Si-OH bonds, to generate acceptor interface states at the Si-SiO2 interface, or be captured by traps in the gate oxide layer to form trap charges. These generated interface states and trap charges will cause changes in the local electric field of the device, thereby leading to the degradation of device characteristics, causing the circuit performance to gradually degrade over time, and eventually causing the device and the circuit to fail, which is the channel degradation effect.

[0004] Power supply chips and isolation driver chips typically use high-voltage MOS devices, supporting power supplies of 40V and above. Traditional channel degradation monitoring circuits only support low-voltage devices of 5V, are only designed for SOC chips, and cannot support the monitoring of high-voltage devices and circuit systems above 40V. They are not suitable for power supply chips and isolation driver chips containing high-voltage devices. Summary of the Invention

[0005] To address the aforementioned technical deficiencies, this invention provides a device channel degradation monitoring circuit.

[0006] The present invention provides a device channel degradation monitoring circuit, comprising: a degradation ring oscillator, wherein the degradation ring oscillator includes an odd number of serially connected degradation inverters;

[0007] The degraded inverter has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal and the first output terminal operate at low voltage, while the second input terminal and the second output terminal operate at high voltage.

[0008] The degraded inverter includes: a first transistor, a second transistor, and an isolation voltage withstand device. The first transistor is a high-voltage power transistor with a withstand voltage of 12V to 750V. The drain of the first transistor is connected to the drain of the second transistor through the isolation voltage withstand device. The source of the first transistor is grounded. The source of the second transistor is connected to the high-voltage power supply terminal. The gate of the first transistor is connected to the first input terminal. The node between the drain of the first transistor and the isolation voltage withstand device is connected to the first output terminal. The gate of the second transistor is connected to the second input terminal. The node between the drain of the second transistor and the isolation voltage withstand device is connected to the second output terminal.

[0009] In this embodiment of the invention, the isolation withstand voltage device is a resistor.

[0010] In this embodiment of the invention, the isolation withstand voltage device is a diode-connected MOS device.

[0011] In this embodiment of the invention, the isolation withstand voltage device is composed of n NMOS transistors connected in a diode-like manner.

[0012] In this embodiment of the invention, the isolation withstand voltage device is composed of n PMOS transistors connected in a diode-like manner.

[0013] In this embodiment of the invention, the isolation withstand voltage device is composed of x PMOS transistors and y NMOS transistors connected in a diode-connected manner.

[0014] In this embodiment of the invention, the degraded inverter further includes a diode, the positive terminal of which is connected to the gate of the second transistor, and the negative terminal of which is connected to the high-voltage power supply terminal.

[0015] In this embodiment of the invention, a non-degenerate ring oscillator is also included;

[0016] The non-degenerate ring oscillator includes an odd number of serially connected non-degenerate inverters;

[0017] The non-degradable inverter has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal and the first output terminal operate at low voltage, while the second input terminal and the second output terminal operate at high voltage.

[0018] The non-degradable inverter includes: a third transistor, a fourth transistor, a fifth transistor, and an isolation voltage withstand device. The third transistor is a high-voltage power transistor. The drain of the third transistor is connected to the source of the fifth transistor. The drain of the fifth transistor is connected to the drain of the fourth transistor through the isolation voltage withstand device. The source of the third transistor is grounded. The source of the fourth transistor is connected to the high-voltage power supply terminal. The gate of the third transistor is connected to the first input terminal. The node between the drain of the fifth transistor and the isolation voltage withstand device is connected to the first output terminal. The gate of the fourth transistor is connected to the second input terminal. The node between the drain of the fourth transistor and the isolation voltage withstand device is connected to the second output terminal.

[0019] In this embodiment of the invention, the isolation withstand voltage device is a resistor or a diode-connected MOS device.

[0020] In this embodiment of the invention, a frequency attenuation detection circuit is also included;

[0021] The frequency decay detection circuit is used to detect the frequency decay of the degraded ring oscillator over time. In the corresponding period of the degraded ring oscillator, the number of periods of the non-degraded ring oscillator is counted to monitor the channel degradation of the first transistor in the degraded inverter.

[0022] In this embodiment of the invention, the frequency attenuation detection circuit includes: a frequency divider, a counter, a discriminator, and a latch;

[0023] The non-degenerate ring oscillator generates a non-degenerate oscillation signal and outputs it to the counter as the reference clock of the counter;

[0024] The degraded ring oscillator generates a degraded oscillation signal, which is output to the frequency divider for frequency division, to obtain the counter's counting signal and the latch's latching signal;

[0025] The counter counts the reference clock according to the counting signal and outputs the counting result to the discriminator;

[0026] The discriminator determines whether the counting result is greater than the threshold to obtain the discrimination result;

[0027] The latch latches the judgment result based on the latch signal and then outputs monitoring and early warning signals.

[0028] The present invention also provides a power chip including the above-described device channel degradation monitoring circuit.

[0029] The present invention also provides an isolation driver chip, which includes the above-described device channel degradation monitoring circuit.

[0030] This invention provides a corresponding monitoring circuit for channel degradation in high-voltage devices, enabling degradation monitoring and early warning for both the devices and the circuitry. The channel degradation monitoring circuit can be embedded into a power supply and isolation driver chip, forming a power supply and isolation driver chip with fault monitoring and early warning functions for high-voltage MOS devices.

[0031] Other features and advantages of the technical solution of the present invention will be described in detail in the following detailed embodiments section. Attached Figure Description

[0032] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0033] Figure 1 This is a schematic diagram of the high-voltage device channel degradation monitoring circuit provided in an embodiment of the present invention;

[0034] Figure 2 This is a circuit diagram of the degenerate inverter provided in the first embodiment of the present invention;

[0035] Figure 3 This is a circuit diagram of the degraded inverter provided in the second embodiment of the present invention;

[0036] Figure 4 This is a circuit diagram of the degenerate inverter provided in the third embodiment of the present invention;

[0037] Figure 5 This is a circuit diagram of a degraded inverter provided in the fourth embodiment of the present invention;

[0038] Figure 6 This is a circuit diagram of a non-degradable inverter provided in an embodiment of the present invention;

[0039] Figure 7 This is a schematic diagram of the ring oscillator provided in an embodiment of the present invention;

[0040] Figure 8 This is a schematic diagram of the frequency attenuation detection circuit provided in an embodiment of the present invention. Detailed Implementation

[0041] To make the technical solutions and advantages of the embodiments of the present invention clearer, the exemplary embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0042] In the description of this invention, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0043] In this invention, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to electrical connection or mutual communication; they can be directly connected or indirectly connected through an intermediate medium; they can refer to the internal connection of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0044] In the process of developing this invention, the inventors discovered that traditional channel degradation monitoring circuits are only designed for SOC chips and are not suitable for power chips or isolation driver chips. Moreover, traditional channel degradation monitoring solutions are only for monitoring low-voltage process defects and only support low-voltage devices at 5V, and cannot support the monitoring of high-voltage devices and circuit systems.

[0045] This invention provides a corresponding monitoring circuit for channel degradation in high-voltage devices, supporting degradation monitoring and failure early warning for 12V to 750V high-voltage devices and circuits. The channel degradation monitoring circuit of this invention can be embedded in power supply and isolation driver chips, and is suitable for channel degradation monitoring of power supply chips and isolation driver chips.

[0046] Figure 1 This is a schematic diagram of the high-voltage device channel degradation monitoring circuit provided in an embodiment of the present invention. Figure 1As shown, the high-voltage device channel degradation monitoring circuit provided in this embodiment includes: a non-degrading ring oscillator, a degrading ring oscillator, and a frequency attenuation detection circuit. The degrading ring oscillator includes an odd number of serially connected degrading inverters, and the non-degrading ring oscillator includes an odd number of serially connected non-degrading inverters. Both the degrading and non-degrading inverters contain high-voltage devices. The high-voltage devices in the degrading inverters are subjected to voltage stress, causing channel degradation and resulting in the frequency of the degrading ring oscillator decaying over time. The non-degrading ring oscillator generates a low-voltage non-degrading oscillation signal CLK_REF, which is output to the frequency attenuation detection circuit. The degrading ring oscillator generates a low-voltage degrading oscillation signal CLK_DEG, which is also output to the frequency attenuation detection circuit. The frequency attenuation detection circuit detects the amount of frequency attenuation of the degrading ring oscillator over time. Within the corresponding period of the degraded ring oscillator, it counts the number of periods of the non-degrading ring oscillator, thereby achieving monitoring and early warning of channel degradation of the high-voltage device. Among them, the frequency of the degenerate ring oscillator degrades (decays) over time, while the frequency of the non-degenerate ring oscillator degrades only slightly over time, and the frequency degradation of the non-degenerate ring oscillator is negligible compared to that of the degenerate ring oscillator.

[0047] In this embodiment of the invention, the degenerate ring oscillator includes an odd number of serially connected degenerate inverters. Each degenerate inverter has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal and the first output terminal operate at low voltage, while the second input terminal and the second output terminal operate at high voltage. Each degenerate inverter includes a first transistor, a second transistor, and an isolation voltage-resistant device. The first transistor is a high-voltage power transistor with a withstand voltage of 12V to 750V. The drain of the first transistor is connected to the drain of the second transistor through the isolation voltage-resistant device. The source of the first transistor is grounded. The source of the second transistor is connected to the high-voltage power supply terminal. The gate of the first transistor is connected to the first input terminal. The node between the drain of the first transistor and the isolation voltage-resistant device is connected to the first output terminal. The gate of the second transistor is connected to the second input terminal. The node between the drain of the second transistor and the isolation voltage-resistant device is connected to the second output terminal. Since the second input terminal of the degraded inverter (connected to the gate of the second transistor) operates at a high voltage, and the first input terminal (connected to the gate of the first transistor) operates at a low voltage, and the first transistor is a high-voltage power transistor, but the first output terminal (connected to the drain of the first transistor) needs to output a low voltage, the high voltage is carried by the isolation withstand voltage device. The current passes through the isolation withstand voltage device to generate a voltage drop, which changes the high level to a low level, thereby causing the first output terminal to output a low voltage signal.

[0048] In the first specific embodiment, such as Figure 2As shown, the degraded inverter includes: a first transistor M1, a second transistor M2, and a resistor R1. The first transistor M1 is a high-voltage power transistor. The drain of the first transistor M1 is connected to the drain of the second transistor M2 through the resistor R1. The source of the first transistor M1 is grounded to GND. The source of the second transistor M2 is connected to the high-voltage power supply terminal VDDH. The gate of the first transistor M1 is connected to the first input terminal IN_L. The node between the drain of the first transistor M1 and the resistor R1 is connected to the first output terminal OUT_L. The gate of the second transistor M2 is connected to the second input terminal IN_H. The node between the drain of the second transistor M2 and the resistor R1 is connected to the second output terminal OUT_H. The resistor R1 acts as an isolation voltage withstand device. The current flowing through the resistor R1 generates a voltage drop, causing the first output terminal OUT_L to output a low-voltage signal. Specifically, the first input terminal IN_L and the first output terminal OUT_L operate at a low voltage of 0-5V, while the second input terminal IN_H and the second output terminal OUT_H operate at a high voltage of 12V-750V. In a typical example, the operating voltage is 40V.

[0049] In the second specific embodiment, such as Figure 3 As shown, the degraded inverter includes: a first transistor M1, a second transistor M2, and a diode-connected MOS device as an isolation voltage withstand device. This diode-connected MOS device is composed of n PMOS transistors (MP1~MPn) connected in a diode-connected manner. The gate and source of each of the n PMOS transistors are connected as a MOS body diode. The first transistor M1 is a high-voltage power transistor. The drain of the first transistor M1 is connected to the drain of the second transistor M2 through the PMOS transistors (MP1~MPn). The source of the first transistor M1 is grounded to GND. The source of the second transistor M2 is connected to the high-voltage power supply terminal VDDH. The gate of the first transistor M1 is connected to the first input terminal IN_L. The node between the drain of the first transistor M1 and the drain of the PMOS transistor MPn is connected to the first output terminal OUT_L. The gate of the second transistor M2 is connected to the second input terminal IN_H. The node between the drain of the second transistor M2 and the source of the PMOS transistor MP1 is connected to the second output terminal OUT_H. The current flows through the PMOS transistors (MP1~MPn) and generates a voltage drop, causing the first output terminal OUT_L to output a low-voltage signal.

[0050] In the third specific embodiment, such as Figure 4As shown, the degraded inverter includes: a first transistor M1, a second transistor M2, and an isolated voltage-resistant device composed of n NMOS transistors (MN1~MNn) connected in a diode configuration. The gate and drain of each of the n NMOS transistors are connected as a MOS body diode. The first transistor M1 is a high-voltage power transistor. The drain of the first transistor M1 is connected to the drain of the second transistor M2 through the NMOS transistors (MN1~MNn). The source of the first transistor M1 is grounded to GND. The source of the second transistor M2 is connected to the high-voltage power supply terminal VDDH. The gate of the first transistor M1 is connected to the first input terminal IN_L. The node between the drain of the first transistor M1 and the source of the NMOS transistor MNn is connected to the first output terminal OUT_L. The gate of the second transistor M2 is connected to the second input terminal IN_H. The node between the drain of the second transistor M2 and the drain of the NMOS transistor MN1 is connected to the second output terminal OUT_H. Current flowing through the NMOS transistors (MN1~MNn) generates a voltage drop, causing the first output terminal OUT_L to output a low-voltage signal.

[0051] In the fourth specific embodiment, such as Figure 5 As shown, the degraded inverter includes: a first transistor M1, a second transistor M2, and an isolated voltage-resistant device composed of x PMOS transistors and y NMOS transistors connected in a diode configuration. The gate of each of the x PMOS transistors is connected to its source as a MOS body diode, and the gate of each of the y NMOS transistors is connected to its drain as a MOS body diode. The first transistor M1 is a high-voltage power transistor. The drain of the first transistor M1 is connected to the drain of the second transistor M2 through the x PMOS transistors and y NMOS transistors. The source of the first transistor M1 is grounded (GND), and the source of the second transistor M2 is connected to the high-voltage power supply terminal VDDH. The gate of the first transistor M1 is connected to the first input terminal IN_L. The node between the drain of the first transistor M1 and the source of the NMOS transistor MN1 is connected to the first output terminal OUT_L. The gate of the second transistor M2 is connected to the second input terminal IN_H, and the node between the drain of the second transistor M2 and the source of the PMOS transistor MP1 is connected to the second output terminal OUT_H. The current flows through x PMOS transistors and y NMOS transistors, generating a voltage drop that causes the first output terminal OUT_L to output a low-voltage signal.

[0052] In the above embodiment, the degraded inverter further includes a diode D1. The anode of diode D1 is connected to the gate of the second transistor M2, and the cathode of diode D1 is connected to the high-voltage power supply terminal VDDH. Diode D1 has a clamping function, which can protect the gate-source voltage VGS of the second transistor M2 and prevent the second transistor M2 from burning out.

[0053] In this embodiment of the invention, the non-degenerate ring oscillator includes an odd number of serially connected non-degenerate inverters. Each non-degenerate inverter has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal and the first output terminal operate at low voltage, while the second input terminal and the second output terminal operate at high voltage. The non-degenerate inverter includes a third transistor, a fourth transistor, a fifth transistor, and an isolation voltage-resistant device. The third transistor is a high-voltage power transistor. The drain of the third transistor is connected to the source of the fifth transistor. The drain of the fifth transistor is connected to the drain of the fourth transistor through the isolation voltage-resistant device. The source of the third transistor is grounded. The source of the fourth transistor is connected to the high-voltage power supply terminal. The gate of the third transistor is connected to the first input terminal. The node between the drain of the fifth transistor and the isolation voltage-resistant device is connected to the first output terminal. The gate of the fourth transistor is connected to the second input terminal. The node between the drain of the fourth transistor and the isolation voltage-resistant device is connected to the second output terminal.

[0054] In one specific embodiment, such as Figure 6 As shown, the non-degradable inverter includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a resistor R1. It also includes a diode D1, with the anode of D1 connected to the gate of the fourth transistor M4 and the cathode of D1 connected to the high-voltage power supply terminal VDDH. The third transistor M3 is a high-voltage power transistor. The drain of the third transistor M3 is connected to the source of the fifth transistor M5. The drain of the fifth transistor M5 is connected to the drain of the fourth transistor M4 through resistor R1. The source of the third transistor M3 is grounded. The source of the fourth transistor M4 is connected to the high-voltage power supply terminal VDDH. The gate of the third transistor M3 is connected to the first input terminal IN_L. The node between the drain of the fifth transistor M5 and resistor R1 is connected to the first output terminal OUT_L. The gate of the fourth transistor M4 is connected to the second input terminal IN_H, and the node between the drain of the fourth transistor M4 and resistor R1 is connected to the second output terminal OUT_H. The first input terminal IN_L and the first output terminal OUT_L operate at a low voltage of 0-5V, while the second input terminal IN_H and the second output terminal OUT_H operate at a high voltage of 12V-750V (e.g., 40V). A degraded inverter requires an overvoltage to the gate of the high-voltage device (first transistor M1) to accelerate its channel degradation, while a non-degraded inverter does not require an overvoltage to the high-voltage device (third transistor M3), and its degradation is very slow. A fifth transistor M5 is added between the third transistor M3 and the fourth transistor M4 in the non-degraded inverter. The fifth transistor M5 acts as isolation, further slowing down its degradation, which is negligible. Therefore, the output of the non-degraded inverter is used as a reference and compared with that of the degraded inverter to monitor the degree of degradation of the degraded inverter.

[0055] In other embodiments, the isolation voltage-degrading device in the non-degradable inverter can also be a diode-connected MOS device. This diode-connected MOS device is composed of n PMOS transistors connected in a diode-connected manner, or n NMOS transistors connected in a diode-connected manner, or x PMOS transistors and y NMOS transistors connected in a diode-connected manner.

[0056] In the above embodiments, the first transistor M1 and the third transistor M3 can be selected from high-voltage devices such as LDMOS (Laterally Diffused Metal Oxide Semiconductor), VDMOS (Vertical Double-Diffused Metal-Oxide-Semiconductor), and BJT (Bipolar Junction Transistor), with source-drain voltages (maximum withstand voltage) ranging from 12V to 750V. Under applied stress voltage, the first high-voltage transistor M1 undergoes channel degradation, and the frequency of the degraded ring oscillator composed of the degraded inverter decays over time. In typical power supply chips, the source-drain voltage of high-voltage devices such as LDMOS is 40V, supporting a 40V power supply.

[0057] like Figure 7 As shown, the ring oscillator consists of an odd number of inverters. The inverters are the inverters (degenerate inverters and non-degenerate inverters) provided in the above embodiments, and each inverter includes four pins: input high voltage IN_H, output high voltage OUT_H, input low voltage IN_L, and output low voltage OUT_L.

[0058] In this embodiment of the invention, the frequency decay detection circuit is used to detect the frequency decay of the degraded ring oscillator over time. Within the corresponding period of the degraded ring oscillator, the number of periods of the non-degraded ring oscillator is counted, thereby enabling monitoring and early warning of channel degradation of the high-voltage transistor in the degraded inverter. For example... Figure 8As shown, the frequency attenuation detection circuit includes a frequency divider, a counter, a discriminator, and a latch. A non-degenerate ring oscillator generates a low-voltage non-degenerate oscillation signal CLK_REF, which is output to the counter as its reference clock. A degenerate ring oscillator generates a low-voltage degenerate oscillation signal CLK_DEG, which is output to the frequency divider for frequency division, resulting in the counter's counting signal and the latch's latching signal. The counter counts the reference clock based on the counting signal and outputs the count result to the discriminator. The discriminator determines whether the count result is greater than a threshold to obtain the discrimination result. The latch latches the discrimination result based on the latching signal (rising edge of the CLK_DEG signal) and then outputs it. The frequency of CLK_DEG degrades over time, while the frequency of CLK_REF does not. As the degraded ring oscillator degrades, the period of the oscillation signal CLK_DEG becomes longer and the frequency becomes smaller (frequency decay). After frequency division, the period becomes even longer. The frequency-divided signal is used as a counting signal to count the number of reference clocks (non-degraded oscillation signals). As the degraded ring oscillator degrades, the count increases. If the count result is greater than the threshold, it indicates that the frequency of the CLK_DEG signal has decayed and the degraded ring oscillator has reached a certain degree of degradation. The latch outputs a channel degradation warning signal.

[0059] This invention designs a corresponding monitoring circuit for channel degradation in high-voltage devices, enabling degradation monitoring and early warning for both high-voltage devices and circuits. The channel degradation monitoring circuit of this invention can be embedded in power supply and isolation driver chips, forming a power supply and isolation driver chip with high-voltage MOS device fault monitoring and early warning functions. This invention fills the gap in current process monitoring modules that only monitor low-voltage processes and lack monitoring of high-voltage processes; it overcomes the current problem of only performing initial aging reliability predictions for chips at the time of shipment, and being unable to provide early warnings for the real-time dynamic aging monitoring of high-voltage power supplies and isolation chips over operating time.

[0060] This invention also provides a power supply chip that embeds the high-voltage device channel degradation monitoring circuit described in the above embodiments. This power supply chip can support degradation monitoring and failure early warning for 12V to 750V high-voltage devices and circuits.

[0061] This invention also provides an isolation driver chip that embeds the high-voltage device channel degradation monitoring circuit described in the above embodiments. This isolation driver chip can support degradation monitoring and failure early warning for 12V to 750V high-voltage devices and circuits.

[0062] The aforementioned power supply chip or isolation driver chip can be manufactured using ultra-high voltage bipolar CMOS-DMOS (BCD) process technology. Utilizing non-epitaxy ultra-high voltage BCD technology, MOS devices with withstand voltages up to 750V can be achieved, and these devices exhibit higher reliability. The high-voltage device channel degradation monitoring and early warning circuit of the above embodiment is compatible with the ultra-high voltage BCD process.

[0063] The optional embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the scope of the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all fall within the protection scope of the embodiments of the present invention. It should be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. As long as the combination does not violate the spirit of the embodiments of the present invention, it should also be regarded as the content disclosed by the embodiments of the present invention.

Claims

1. A device channel degradation monitoring circuit, comprising: The application relates to a degenerative ring oscillator, a non-degenerative ring oscillator and a frequency decay detection circuit. The degenerative ring oscillator comprises an odd number of serially connected degenerative inverters, and the non-degenerative ring oscillator comprises an odd number of serially connected non-degenerative inverters. The degenerative inverter has a first input end, a second input end, a first output end and a second output end, the working voltage of the first input end and the first output end is low voltage, and the working voltage of the second input end and the second output end is high voltage. The degenerative inverter comprises a first transistor, a second transistor and an isolation voltage-resistant device, the first transistor is a high-voltage power transistor with a voltage resistance of 12V-750V, the first transistor is subjected to a stress voltage to cause channel degeneration, and the frequency of the degenerative ring oscillator decays with time. The drain of the first transistor is connected to the drain of the second transistor through the isolation voltage-resistant device, the source of the first transistor is grounded, the source of the second transistor is connected to a high-voltage power supply end, the gate of the first transistor is connected to the first input end, the node between the drain of the first transistor and the isolation voltage-resistant device is connected to the first output end, the gate of the second transistor is connected to the second input end, and the node between the drain of the second transistor and the isolation voltage-resistant device is connected to the second output end. The frequency decay detection circuit is used for detecting the frequency decay amount of the degenerative ring oscillator with time, counting the number of cycles of the non-degenerative ring oscillator in the corresponding cycle of the degenerative ring oscillator, and monitoring the channel degeneration of the first transistor in the degenerative inverter.

2. The device channel degradation monitoring circuit of claim 1, wherein, The isolation voltage-resistant device is a resistor device.

3. The device channel degradation monitoring circuit of claim 1, wherein, The isolation voltage-resistant device is a diode-connected MOS device.

4. The device channel degradation monitoring circuit of claim 3, wherein, The isolation voltage-resistant device is connected by n NMOS transistors in a diode-connected mode.

5. The device channel degradation monitoring circuit of claim 3, wherein, The isolation voltage-resistant device is connected by n PMOS transistors in a diode-connected mode.

6. The device channel degradation monitoring circuit of claim 3, wherein, The isolation voltage-resistant device is connected by x PMOS transistors and y NMOS transistors in a diode-connected mode.

7. The device channel degradation monitoring circuit of claim 1, wherein, The degenerative inverter further comprises a diode, the anode of the diode is connected to the gate of the second transistor, and the cathode of the diode is connected to the high-voltage power supply end.

8. The device channel degradation monitoring circuit of claim 1, wherein, The non-degenerative inverter has a first input end, a second input end, a first output end and a second output end, the working voltage of the first input end and the first output end is low voltage, and the working voltage of the second input end and the second output end is high voltage. The non-degenerative inverter comprises a third transistor, a fourth transistor, a fifth transistor and an isolation voltage-resistant device, the third transistor is a high-voltage power transistor, the drain of the third transistor is connected to the source of the fifth transistor, the drain of the fifth transistor is connected to the drain of the fourth transistor through the isolation voltage-resistant device, the source of the third transistor is grounded, the source of the fourth transistor is connected to a high-voltage power supply end, the gate of the third transistor is connected to the first input end, the node between the drain of the fifth transistor and the isolation voltage-resistant device is connected to the first output end, the gate of the fourth transistor is connected to the second input end, and the node between the drain of the fourth transistor and the isolation voltage-resistant device is connected to the second output end.

9. The device channel degradation monitoring circuit of claim 8, wherein, The isolation voltage-resistant device is a resistor device or a diode-connected MOS device.

10. The device channel degradation monitoring circuit of claim 1, wherein, The frequency attenuation detection circuit comprises a frequency divider, a counter, a discriminator and a latch; The non-degenerate ring oscillator generates a non-degenerate oscillation signal output to the counter as a reference clock of the counter; The degenerate ring oscillator generates a degenerate oscillation signal output to the frequency divider for frequency division to obtain a counting signal of the counter and a latch signal of the latch; The counter counts the reference clock according to the counting signal and outputs a counting result to the discriminator; The discriminator judges whether the counting result is greater than a threshold to obtain a discrimination result; The latch outputs a monitoring and early warning signal after latching the discrimination result according to the latch signal.

11. A power supply chip, characterized by comprising: The power supply chip comprises the device channel degeneration monitoring circuit according to any one of claims 1-10.

12. An isolated driver chip, characterized by The isolation driving chip comprises the device channel degeneration monitoring circuit according to any one of claims 1-10.

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