Overlay measurement method for photoetching common plate
In the semiconductor chip manufacturing process, by using the different analytical capabilities of the first layer and the second layer lithography processes, the first mark is split into a second mark composed of multiple patterns, which solves the problem of the inability to measure the lithography erection accuracy, and realizes the measurement of alignment deviation and the improvement of product performance.
Patent Information
- Application Number
- CN202510099378.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2025-03-18
AI Technical Summary
During semiconductor chip manufacturing, when using the same photocopy mask for multi-layer lithography, the photolithography sleeve accuracy cannot be measured in real terms, resulting in the product yield and performance being affected.
By forming a first mark in the first layer lithography process and splitting the first mark into a second mark composed of a plurality of patterns of the same size in the second layer lithography process, the deviation value of the second mark nested in the first mark and the first mark is obtained to achieve the alignment deviation measurement of the first layer and the second layer.
It effectively avoids overlapping marks in the photolithography co-plate, realizes real measurement of the photolithography engraving accuracy, and improves the product yield and performance.
Smart Images
Figure CN119644680A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a method for measuring overlay of a photolithography common plate. Background Art
[0002] Photolithography is a process that transfers the mask pattern on the photomask to the wafer through a series of steps such as alignment and exposure. In the manufacturing process of semiconductor chips, the entire manufacturing process can only be completed through multi-layer photolithography processes. In order to achieve good product performance and high yield, how to control the position alignment of the current layer of photolithography pattern (pattern on the wafer) and the previous layer of photolithography pattern (pattern on the wafer) to meet the requirements of overlay accuracy is a crucial step in the multi-layer photolithography process. Overlay accuracy refers to the position alignment error of the photolithography patterns between layers of the wafer. Overlay accuracy will seriously affect the yield and performance of the product, and improving the overlay accuracy of the photoresist is also the key to determining the minimum unit size.
[0003] In the manufacturing process of semiconductor chips, the etching area and the ion implantation area may be the same area. In this case, a common photolithography plate (using the same mask) is required to reduce the mask cost. Because the overlay pattern will be imprinted on the wafer during etching, the overlay accuracy of the subsequent implantation layer cannot be truly measured. Summary of the invention
[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a method for measuring overlay of a common lithography plate, so as to solve the problem in the prior art that the lithography overlay accuracy cannot be truly measured when the same mask is used for different layers.
[0005] To achieve the above-mentioned purpose and other related purposes, the present application provides a method, comprising:
[0006] Step 1, forming a first mark on the wafer using a mask in a first layer photolithography process;
[0007] Step 2: using the mask in a second-layer photolithography process to form a second mark on the wafer, which is composed of a plurality of patterns of the same size split from the first mark, wherein the resolution capability of the machine and photoresist used in the second-layer photolithography process is stronger than that of the machine and photoresist used in the first-layer photolithography process;
[0008] Step three, obtaining the deviation value between the second mark nested in the first mark and the first mark to obtain the alignment deviation between the first layer and the second layer.
[0009] Preferably, the second mark has the same shape as the first mark.
[0010] Preferably, the first mark is a rectangle.
[0011] Preferably, the width of the rectangle is 1 μm-2 μm, and the length is 30 μm-50 μm.
[0012] Preferably, the multiple graphics of the same size split from the first mark are squares.
[0013] Preferably, the side length of the square is 150nm-200nm.
[0014] Preferably, a plurality of the squares are arranged in a matrix at equal intervals, and the intervals are 150 nm-200 nm.
[0015] Preferably, the first mark is used as an outer frame mark of the overlay alignment mark of the photolithography common plate, and the second mark is used as an inner frame mark of the overlay alignment mark of the photolithography common plate.
[0016] Preferably, the first layer and the second layer are located in the same area of the wafer, and the same photomask is used during photolithography.
[0017] Preferably, the first layer is a material layer that needs to be etched, and the second layer is a material layer that needs to be ion implanted.
[0018] As described above, the overlay measurement method for photolithography co-plate provided in the present application has the following beneficial effects: effectively avoiding the situation where the overlay mark overlaps when photolithography co-plate occurs, resulting in the inability to perform overlay measurement. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0020] Figure 1 A flow chart showing a method for measuring overlay of a photolithography common plate provided by an embodiment of the present application;
[0021] Figure 2A A schematic diagram showing an overlay alignment mark used for the first layer during photolithography of the same plate;
[0022] Figure 2B Schematic diagram showing the overlay alignment marks used for the second layer during photolithography co-planarization. DETAILED DESCRIPTION
[0023] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0024] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0025] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0026] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0027] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0028] In order to realize the monitoring of overlay accuracy, generally, an overlay mark is provided on the first layer of the mask, and a matching overlay mark is provided on the second layer of the mask. The first layer of the mask is used to perform the first layer of photolithography process to form a first layer of overlay mark pattern on the wafer. The second layer of the mask is used to perform the second layer of photolithography process to form a corresponding second layer of overlay mark pattern on the wafer. The overlay accuracy is obtained by measuring the position difference between the first layer of overlay mark pattern and the second layer of overlay mark pattern, or by measuring the diffraction light difference between the first layer of overlay mark pattern and the second layer of overlay mark pattern.
[0029] In the manufacturing process of semiconductor chips, the first layer and the second layer may be located in the same area of the wafer (for example, the etching area and the ion implantation area are the same area). When the same mask is used across the layers, if direct exposure is performed, the overlay marks of the front and rear layers will also be made at the same time. When the first layer and the second layer need to be directly aligned, direct exposure cannot perform overlay measurement because the overlay marks of the front and rear layers will overlap.
[0030] In order to solve this problem, the present application provides a method for measuring overlay of a photolithography plate.
[0031] See also Figure 1 , which shows a flow chart of a photolithography common plate overlay measurement method provided in an embodiment of the present application.
[0032] like Figure 1 As shown, the method comprises the following steps:
[0033] Step 1, forming a first mark on the wafer using a mask in a first layer photolithography process;
[0034] Step 2: using the mask in a second-layer photolithography process to form a second mark on the wafer, which is composed of a plurality of patterns of the same size split from the first mark, wherein the resolution capability of the machine and photoresist used in the second-layer photolithography process is stronger than that of the machine and photoresist used in the first-layer photolithography process;
[0035] Step three, obtaining the deviation value between the second mark nested in the first mark and the first mark to obtain the alignment deviation between the first layer and the second layer.
[0036] In step 1, preferably, the first marker is as follows Figure 2A The rectangle shown has a width of 1 μm-2 μm (micrometers) and a length of 30 μm-50 μm.
[0037] In step 2, when the first mark is a rectangle, the first mark is split into a plurality of squares, each of which has a side length of 150 nm to 200 nm. The plurality of squares are arranged in a matrix at equal intervals (eg Figure 2B As shown), the spacing is 150nm-200nm, and the matrix constitutes a second mark. The number of squares in each row of the matrix is determined according to the length of the rectangle, the side length of the square and the spacing between the squares, and the number of squares in each column of the matrix is determined according to the width of the rectangle, the side length of the square and the spacing between the squares.
[0038] A person skilled in the art may know that the first mark may also be a graphic with other shapes. After the first mark is split into multiple squares, the second mark formed by the graphic arrangement of the multiple squares has the same shape as the first mark, and the second mark can be nested in the first mark.
[0039] The first mark is used as the outer mark of the overlay alignment mark of the photolithography common plate, and the second mark is used as the inner mark of the overlay alignment mark of the photolithography common plate. The resolution capability of the machine and photoresist used in the first layer of photolithography is weaker than that of the machine and photoresist used in the second layer of photolithography, so only the first mark is formed on the cutting path of the wafer during the first layer of photolithography, and the second mark is formed on the cutting path of the wafer during the second layer of photolithography. The second mark can be nested in the first mark, so that overlay measurement can be performed.
[0040] Exemplarily, the machine used in the first layer photolithography process is an iline machine, and the machine used in the second layer photolithography process is a KRF machine. The photoresists used in the first layer photolithography process and the second layer photolithography process are usually different.
[0041] The first layer and the second layer are located in the same area of the wafer and use the same mask during photolithography. As an example, the first layer is a material layer that needs to be etched, and the second layer is a material layer that needs to be ion implanted.
[0042] In step three, Figure 2B For example, by measuring the position deviation between the side of the outermost square in each row of the matrix and the short side of the rectangle, the alignment deviation of the first layer and the second layer in the X direction (parallel to the long side of the rectangle) can be obtained; by measuring the position deviation between the side of the outermost square in each column of the matrix and the long side of the rectangle, the alignment deviation of the first layer and the second layer in the Y direction (parallel to the short side of the rectangle) can be obtained.
[0043] When the first mark adopts a graphic with other shapes, since the second mark has the same shape as the first mark and the second mark can be nested in the first mark, the alignment deviation between the first layer and the second layer can be obtained by obtaining the position deviation between the second mark and the first mark.
[0044] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0045] In summary, the overlay measurement method for photolithography co-plate provided by the present application can effectively avoid the situation where overlay measurement cannot be performed due to overlapping overlay marks during photolithography co-plate. Therefore, the present application effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
[0046] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present application.
Claims
1. A method for measuring overlay of a photolithography plate, characterized in that: The method comprises: Step 1, forming a first mark on the wafer using a mask in a first layer photolithography process; Step 2, using the mask to form a second mark on the wafer in a second-layer photolithography process, which is composed of a plurality of patterns of the same size split from the first mark, wherein the resolution capability of the machine and photoresist used in the second-layer photolithography process is stronger than that of the machine and photoresist used in the first-layer photolithography process; Step three, obtaining a deviation value between a second mark nested in the first mark and the first mark to obtain an alignment deviation between the first layer and the second layer.
2. The method according to claim 1, characterized in that The second mark has the same shape as the first mark.
3. The method according to claim 1, characterized in that The first mark is a rectangle.
4. The method according to claim 3, characterized in that The rectangle has a width of 1 μm-2 μm and a length of 30 μm-50 μm.
5. The method according to claim 1 or 3, characterized in that: The multiple figures of the same size formed by splitting the first mark are squares.
6. The method according to claim 5, characterized in that The side length of the square is 150nm-200nm.
7. The method according to claim 5, characterized in that The plurality of squares are arranged into a matrix at equal intervals, and the intervals are 150nm-200nm.
8. The method according to claim 1, characterized in that The first mark is used as an outer frame mark of an overlay alignment mark of a photolithography common plate, and the second mark is used as an inner frame mark of an overlay alignment mark of a photolithography common plate.
9. The method according to claim 1, characterized in that: The first layer and the second layer are located in the same area of the wafer and use the same photomask during photolithography.
10. The method according to claim 9, characterized in that The first layer is a material layer that needs to be etched, and the second layer is a material layer that needs to be ion implanted.