High-integration antenna control system
By using technologies such as the SOC chip XC7Z045-FFG900 and the RF agile transceiver and receiver chip AD9361, a high-integration antenna control system is built, which solves the shortcomings of antenna control units in the prior art in miniaturization and low power consumption, and achieves the effects of small size, low power consumption and high integration.
Patent Information
- Application Number
- CN202411507164.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-28
- Publication Date
- 2025-03-18
AI Technical Summary
The existing antenna control units have shortcomings in miniaturization and low power consumption, which is difficult to meet the needs of current engineering applications for small size and low power consumption.
The SOC chip XC7Z045-FFG900 is used as the core of receiver, motor drive and antenna control, and combines the RF agile transceiver and receiver chip AD9361 and a dedicated control core to achieve a highly integrated antenna control system.
It realizes a small size and low power consumption antenna control unit, improves the overall integration and flexibility of the hardware, reduces cost and power consumption, and is suitable for the needs of miniaturization and low power consumption in current engineering projects.
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Figure CN119644813A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a highly integrated antenna control system, belonging to the technical field of antennas. Background Art
[0002] In response to the demand for miniaturized, low-power antenna control units in current engineering applications, we developed a highly integrated antenna control unit, breaking through key technologies such as high-efficiency and miniaturized design of antenna control units.
[0003] Parabolic antennas are widely used in the fields of communication and measurement and control, and their control requirements are very strict. Not only must the servo system be able to operate safely, but the static control and dynamic response bandwidth of the servo system must also meet the requirements. The antenna control unit described in this patent includes three parts: antenna control, receiver and motor drive.
[0004] Traditional antenna control parts mostly use DSP+FPGA as the controller core. After the antenna receives the RF signal of Ka, Ku or C band, it is converted into the RF signal of L or S band through LNB. The down-conversion module mixes and filters the RF signal, and then converts it into a 70MHz intermediate frequency signal. After high-speed AD sampling, the analog signal is converted into a digital signal. The FPGA calculates the signal power, noise power, locking status, etc., and finally passes it to the DSP for tracking algorithm. Among them, DSP is the antenna control core, and FPGA completes the RF signal solution function.
[0005] The drive part mostly uses finished drivers from external manufacturers, which receive control instructions sent by DSP through the CAN bus, drive the motor to rotate, and complete the antenna star control. This design solution results in a large size and power consumption of the antenna control unit, which is difficult to apply to small antennas.
[0006] Therefore, it is necessary to improve the prior art to solve the above-mentioned shortcomings. Summary of the invention
[0007] The object of the present invention is to improve the above-mentioned deficiencies and provide an antenna control unit with small size and low power consumption.
[0008] In order to achieve the above object, the technical solution adopted by the present invention is:
[0009] A highly integrated antenna control system, comprising a receiver unit, a motor drive unit and an antenna control unit; the PL part of the SOC chip XC7Z045-FFG900 serves as the core of the receiver unit and the motor drive unit;
[0010] The RF agile transceiver chip AD9361 and the PL part form the receiver unit; the RF agile transceiver chip AD9361 integrates the zero intermediate frequency architecture into one chip. Each of its transceiver channels includes gain control, analog filtering and data converter functions, which are used to down-convert RF signals from 70MHz to 6GHz to zero frequency, and then cooperate with the PL part of the SOC chip XC7Z045-FFG900 to calculate the signal power;
[0011] The motor drive unit realizes position signal acquisition and processing through the corresponding dedicated control core, and realizes pulse distribution control of the six-channel PWM signal of the power inverter circuit;
[0012] The PS part of the SOC chip XC7Z045-FFG900 serves as the core of the antenna control unit; the PS part calculates the antenna tracking information according to the signal power, noise power, and locking status data information calculated by the PL part, and sends a motor drive instruction to the PL part to drive the antenna to rotate to the specified position to complete the antenna star control; at the same time, the PS part is responsible for communicating with the host computer, and the communication interfaces set include CAN, RS422 and network port.
[0013] The present invention has the following gain effects:
[0014] (1) The digital servo control solution of the SOC chip XC7Z045-FFG900 chip adopted in the present invention greatly improves the overall integration and flexibility of the hardware, makes up for the shortcoming that a single DSP cannot complete the PWM wave output of multiple motors, has a higher information acquisition rate, and is more accurate in sampling.
[0015] (2) The receiver unit design of PL end + AD9361 is adopted. Compared with the traditional tracking receiver unit, the new integrated tracking receiver system based on AD9361 has significant advantages in cost, volume, power consumption, heat generation, etc. It is very suitable for antenna products with high requirements on volume, power consumption, cost, etc. in current engineering projects.
[0016] (3) Using the PS end as the antenna control core greatly improves the system integration. Compared with the DSP+FPGA design, it has higher integration, smaller size, lower power consumption, and improved system reliability while effectively reducing the current hardware circuit cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 It is the overall structural block diagram of the present invention. DETAILED DESCRIPTION
[0018] The specific implementation of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the present invention, and is not used to limit the present invention.
[0019] This patent uses the SOC chip XC7Z045-FFG900 as the controller core.
[0020] 1. Receiver part.
[0021] The PL (programmable logic) part of the SOC chip XC7Z045-FFG900 serves as the receiver core.
[0022] The RF agile transceiver chip AD9361 and the PL end are selected to form the receiver unit. The AD9361 chip integrates the zero intermediate frequency architecture into one chip. Each transceiver channel includes gain control, analog filtering, data converter and other functions. It can down-convert the RF signal from 70MHz to 6GHz to near zero frequency, and then cooperate with PL to calculate the signal power. Since the chip has the functions of mixing and sampling, the down-conversion module and AD sampling chip are no longer needed.
[0023] 2. Motor drive part
[0024] The PL part of the SOC chip XC7Z045-FFG900 is used as the motor control core. In view of the high real-time characteristics of motor drive, a corresponding dedicated control core is developed to realize position signal acquisition and processing. The signal acquisition frequency is about 1MHz and the delay time is about 1us. The processing speed is much higher than the operation speed of the general DSP processor, which can better realize the pulse distribution control of the six-channel PWM signal of the power inverter circuit, thereby driving the motor to run continuously at high speed and smoothly.
[0025] 3. Antenna control part
[0026] The PS (processing system) part of the SOC chip XC7Z045-FFG900 serves as the antenna control core. The PS side calculates the antenna tracking information based on the signal power, noise power, locking status and other data information calculated by the PL side, and sends a motor drive instruction to the PL side to drive the antenna to rotate to the specified position to complete the antenna star control. At the same time, the PS side is responsible for communicating with the host computer, and the communication interfaces set include CAN, RS422 and network port.
[0027] Please refer to Figure 1 The PS side is responsible for task scheduling, completing and receiving host computer control instructions, real-time data upload, and antenna pointing control. The PL side is responsible for RF information collection and processing, and provides motor rotation control.
[0028] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that the present invention includes but is not limited to the contents described in the drawings and the above specific embodiments. Any modification that does not deviate from the functional and structural principles of the present invention will be included in the scope of the claims.
Claims
1. A highly integrated antenna control system, characterized in that: It includes a receiver unit, a motor drive unit and an antenna control unit; the PL part of the SOC chip XC7Z045-FFG900 serves as the core of the receiver unit and the motor drive unit; The RF agile transceiver chip AD9361 and the PL part form the receiver unit; The RF agile transceiver chip AD9361 integrates the zero-IF architecture into one chip. Each of its transceiver channels includes gain control, analog filtering, and data converter functions, which are used to down-convert RF signals from 70MHz to 6GHz to zero frequency, and then cooperate with the PL part of the SOC chip XC7Z045-FFG900 to calculate the signal power. The motor drive unit realizes position signal acquisition and processing through the corresponding dedicated control core, and realizes pulse distribution control of the six-channel PWM signal of the power inverter circuit; The PS part of the SOC chip XC7Z045-FFG900 serves as the core of the antenna control unit; the PS part calculates the antenna tracking information according to the signal power, noise power, and locking status data information calculated by the PL part, and sends a motor drive instruction to the PL part to drive the antenna to rotate to the specified position to complete the antenna star control; at the same time, the PS part is responsible for communicating with the host computer, and the communication interfaces set include CAN, RS422 and network port.