Low-dropout linear voltage stabilizing circuit, low-dropout linear voltage regulator and electronic equipment

Abstract

The invention belongs to the technical field of electronic circuits, and provides a low-dropout linear voltage stabilizing circuit, a low-dropout linear voltage regulator and electronic equipment. The low-dropout linear voltage stabilizing circuit comprises an error amplification module, a buffer module, a power module, a feedback module and a transient enhancement module, the buffer module is connected with the error amplification module, the power module and the transient enhancement module, the power module is connected with the transient enhancement module, the feedback module and a load, and the feedback module is connected with the error amplification module. When the current on the load changes, the transient enhancement module provides the first current for the power module according to the target voltage, so that the power module quickly adjusts the target voltage according to the first current and quickly responds to the change of the load; the feedback module outputs feedback voltage according to the target voltage; the error amplification module outputs an error signal according to the feedback voltage and the reference voltage; the buffer module outputs a driving signal to the power module according to the error signal, so that the power module maintains the target voltage stable according to the driving signal.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic circuits, and in particular relates to a low voltage dropout linear voltage regulator circuit, a low voltage dropout linear regulator and an electronic device. Background Art

[0002] Low Dropout Regulator (LDO) has good power pulse suppression and fast response speed, so it is widely used in low-noise circuits. In transient response, when the current on the load changes from small to large, the power tube cannot respond fast enough to provide the current required by the load, causing the output voltage to decrease rapidly and a downward voltage spike to appear, which is called undershoot. Similarly, when the current on the load changes from large to small, the power tube cannot respond fast enough, causing the output voltage to increase rapidly and an upward voltage spike to appear, which is called overshoot. Excessive voltage spikes may cause circuit damage.

[0003] Traditional LDO circuits use large capacitors at the microfarad level to achieve fast transient response to reduce damage to the circuit caused by voltage spikes. However, to drive large capacitors at the microfarad level, large-sized power tubes are required, which not only increases the area and cost of the circuit, but also affects the overall performance of the circuit. Summary of the invention

[0004] The embodiments of the present application provide a low voltage dropout linear voltage regulator circuit, a low voltage dropout linear regulator and an electronic device, which can solve the problems of large circuit area and high cost in traditional LDO circuits.

[0005] In a first aspect, an embodiment of the present application provides a low voltage difference linear voltage regulator circuit, comprising an error amplification module, a buffer module, a power module, a feedback module and a transient enhancement module, wherein the buffer module is respectively connected to the error amplification module, the power module and the transient enhancement module, the power module is respectively connected to the transient enhancement module, the feedback module and a load, and the feedback module is connected to the error amplification module;

[0006] When the current on the load changes, the transient enhancement module is used to provide a first current to the power module according to the target voltage, so that the power module quickly adjusts the target voltage according to the first current; the feedback module is used to output a feedback voltage according to the target voltage; the error amplification module is used to output an error signal according to the feedback voltage and a reference voltage; the buffer module is used to output a drive signal to the power module according to the error signal, so that the power module maintains the target voltage stable according to the drive signal; wherein the target voltage is the output voltage of the low voltage difference linear voltage regulator circuit.

[0007] In a possible implementation manner of the first aspect, the transient enhancement module includes a coupling unit, a first current mirror unit, and a second current mirror unit, the coupling unit is respectively connected to the power module, the first current mirror unit, and the second current mirror unit, the first current mirror unit is respectively connected to the power module and the second current mirror unit; the first current includes a second current and a third current;

[0008] When the current on the load changes from small to large, the coupling unit is used to output a first coupling signal according to the target voltage; the first current mirror unit is used to provide the second current to the power module according to the first coupling signal; the power module is used to quickly adjust the target voltage according to the second current to increase the target voltage; the second current mirror unit is used to enter a cut-off state according to the first coupling signal; when the current on the load changes from large to small, the coupling unit is used to output a second coupling signal according to the target voltage; the second current mirror unit is used to provide the third current to the power module according to the second coupling signal; the power module is used to quickly adjust the target voltage according to the third current to decrease the target voltage; the first current mirror unit is used to enter a cut-off state according to the second coupling signal.

[0009] In a possible implementation manner of the first aspect, the first current mirror unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a first current source, a source of the first transistor and a source of the second transistor both receive a power supply voltage, a gate of the first transistor is respectively connected to a drain of the first transistor, a first end of the first current source, a source of the fifth transistor and a source of the seventh transistor, a second end of the first current source is grounded, a drain of the fifth transistor is respectively connected to a drain of the sixth transistor, a gate of the fifth transistor and a gate of the sixth transistor, a source of the sixth transistor is respectively connected to a gate of the second transistor and a drain of the seventh transistor, a gate of the seventh transistor is respectively connected to the coupling unit and the second current mirror unit, a drain of the second transistor is respectively connected to a drain of the third transistor, a gate of the third transistor and a gate of the fourth transistor, a drain of the fourth transistor is respectively connected to the power module and the second current mirror unit, and a source of the third transistor and a source of the fourth transistor are both grounded.

[0010] In a possible implementation manner of the first aspect, the second current mirror unit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a second current source, a first end of the second current source, a source of the eighth transistor and a source of the ninth transistor all receive a power supply voltage, a gate of the eighth transistor is respectively connected to a gate of the ninth transistor, a drain of the ninth transistor and a drain of the thirteenth transistor, a drain of the eighth transistor is respectively connected to the power module and the first current mirror unit, a second end of the second current source is respectively connected to a drain of the tenth transistor, a gate of the tenth transistor, a drain of the fourteenth transistor and a source of the eleventh transistor, a gate of the eleventh transistor is respectively connected to a gate of the twelfth transistor, a drain of the eleventh transistor and a drain of the twelfth transistor, a source of the twelfth transistor is respectively connected to a source of the fourteenth transistor and a gate of the thirteenth transistor, a gate of the fourteenth transistor is respectively connected to the coupling unit and the first current mirror unit, and a source of the tenth transistor and a source of the thirteenth transistor are both grounded.

[0011] In a possible implementation manner of the first aspect, the coupling unit includes a coupling capacitor, a first end of the coupling capacitor is connected to the power module, and a second end of the coupling capacitor is connected to the first current mirror unit and the second current mirror unit respectively.

[0012] In a possible implementation of the first aspect, the buffer module includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor and an eighteenth transistor, the source of the fifteenth transistor receives a power supply voltage, the gate of the fifteenth transistor receives a bias voltage, the drain of the fifteenth transistor is respectively connected to the source of the sixteenth transistor, the collector of the eighteenth transistor, the power module and the transient enhancement module, the gate of the sixteenth transistor is connected to the error amplification module, the drain of the sixteenth transistor is respectively connected to the gate of the seventeenth transistor, the drain of the seventeenth transistor and the base of the eighteenth transistor, and the source of the seventeenth transistor and the emitter of the eighteenth transistor are both grounded.

[0013] In a possible implementation of the first aspect, the power module includes a power tube, a gate of the power tube is respectively connected to the buffer module and the transient enhancement module, a source of the power tube receives a power supply voltage, and a drain of the power tube is respectively connected to the feedback module, the transient enhancement module and the load.

[0014] In a possible implementation manner of the first aspect, the low voltage difference linear voltage regulator circuit further includes a Miller compensation module, and the Miller compensation module is respectively connected to the error amplification module, the buffer module, and the power module;

[0015] The Miller compensation module is used to perform phase compensation on the target voltage.

[0016] In a second aspect, an embodiment of the present application provides a low voltage dropout linear regulator, comprising the low voltage dropout linear regulator circuit described in any one of the first aspects.

[0017] In a third aspect, an embodiment of the present application provides an electronic device, comprising the low voltage difference linear voltage regulator circuit described in any one of the first aspects.

[0018] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0019] An embodiment of the present application provides a low voltage difference linear voltage stabilization circuit, including an error amplification module, a buffer module, a power module, a feedback module and a transient enhancement module, wherein the buffer module is respectively connected to the error amplification module, the power module and the transient enhancement module, the power module is respectively connected to the transient enhancement module, the feedback module and the load, and the feedback module is connected to the error amplification module.

[0020] When the current on the load changes: from small to large or from large to small, the transient enhancement module is used to provide a first current to the power module according to the target voltage, so that the power module can quickly adjust the target voltage according to the first current, so that the target voltage can quickly increase or decrease, and quickly respond to the change in the load. The feedback module is used to output a feedback voltage according to the target voltage. The error amplification module is used to output an error signal according to the feedback voltage and the reference voltage. The buffer module is used to output a drive signal to the power module according to the error signal, so that the power module maintains the target voltage stable according to the drive signal, wherein the target voltage is the output voltage of the low voltage difference linear voltage regulator circuit. The present application can not only quickly adjust the output voltage when the current on the load changes, but also maintain the stability and accuracy of the output voltage.

[0021] The transient enhancement module of the present application significantly improves the response speed of the power module during the transient response process, so that the target voltage can quickly respond to changes in the load, thereby effectively reducing the voltage spike and avoiding damage to the circuit caused by the voltage spike. Compared with the traditional LDO, the present application does not need to use large capacitors at the microfarad level, nor does it need to use large-sized power modules, which not only reduces the area and cost of the circuit, but also improves the overall performance of the circuit.

[0022] It can be understood that the beneficial effects of the second to third aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0024] Figure 1 It is a principle block diagram of a low voltage difference linear voltage regulator circuit provided in an embodiment of the present application;

[0025] Figure 2 is a principle block diagram of a low voltage difference linear voltage regulator circuit provided by another embodiment of the present application;

[0026] Figure 3 is a principle block diagram of a low voltage difference linear voltage regulator circuit provided by another embodiment of the present application;

[0027] Figure 4 1 is a circuit connection diagram of a low voltage difference linear voltage regulator circuit provided in an embodiment of the present application;

[0028] Figure 5 Schematic diagram of the circuit connection of the error amplifier in this application.

[0029] In the figure: 10, error amplification module; 20, buffer module; 30, power module; 40, feedback module; 50, transient enhancement module; 51, coupling unit; 52, first current mirror unit; 53, second current mirror unit; 60, load; 70, Miller compensation module. DETAILED DESCRIPTION

[0030] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0031] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0032] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0033] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0034] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0035] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0036] Traditional LDO circuits use large capacitors at the microfarad level to achieve fast transient response to reduce the damage caused by voltage spikes to the circuit. However, to drive large capacitors at the microfarad level, large-sized power tubes are required. Large-sized power tubes will produce large parasitic capacitance, which not only sacrifices the response speed of the circuit, but also affects the stability of the circuit. Therefore, the traditional LDO circuit uses large capacitors at the microfarad level to achieve fast transient response, which not only increases the area and cost of the circuit, but also affects the overall performance of the circuit.

[0037] In view of the above problems, the present application provides a low voltage drop linear voltage regulator circuit. Figure 1As shown, the low voltage difference linear voltage regulator circuit includes an error amplification module 10, a buffer module 20, a power module 30, a feedback module 40 and a transient enhancement module 50. The buffer module 20 is respectively connected to the error amplification module 10, the power module 30 and the transient enhancement module 50, the power module 30 is respectively connected to the transient enhancement module 50, the feedback module 40 and the load 60, and the feedback module 40 is connected to the error amplification module 10.

[0038] Specifically, when the current on the load 60 changes: from small to large or from large to small, the transient enhancement module 50 is used to provide a first current to the power module 30 according to the target voltage, so that the power module 30 quickly adjusts the target voltage according to the first current, so that the target voltage quickly increases or decreases, and quickly responds to changes in the load 60. The feedback module 40 is used to output a feedback voltage according to the target voltage. The error amplification module 10 is used to output an error signal according to the feedback voltage and the reference voltage. The buffer module 20 is used to output a drive signal to the power module 30 according to the error signal, so that the power module 30 maintains the target voltage stable according to the drive signal, wherein the target voltage is the output voltage of the low voltage difference linear voltage regulator circuit. The present application can not only quickly adjust the output voltage when the current on the load 60 changes, but also maintain the stability and accuracy of the output voltage.

[0039] The transient enhancement module 50 of the present application significantly improves the response speed of the power module 30 during the transient response process, so that the target voltage can quickly respond to the change of the load 60, thereby effectively reducing the voltage spike and avoiding the damage of the voltage spike to the circuit. Compared with the traditional LDO, the present application does not need to use a large capacitor of microfarad level, nor does it need to use a large-sized power module, which not only reduces the area and cost of the circuit, but also improves the overall performance of the circuit.

[0040] The low voltage difference linear voltage regulator circuit provided in the embodiment of the present application: when the current on the load 60 jumps from 0 to 50mA, the target voltage undershoots, and the voltage change is 3.59mV. When the current on the load 60 jumps from 50mA to 0, the target voltage overshoots, and the voltage change is 2.73mV. The transient response is good, and the voltage spike occurring in the transient response can be effectively reduced.

[0041] In some embodiments, Figure 2 As shown, the transient enhancement module 50 includes a coupling unit 51, a first current mirror unit 52 and a second current mirror unit 53. The coupling unit 51 is respectively connected to the power module 30, the first current mirror unit 52 and the second current mirror unit 53. The first current mirror unit 52 is respectively connected to the power module 30 and the second current mirror unit 53. The first current includes a second current and a third current, and the second current and the third current are two currents in opposite directions.

[0042] Specifically, when the current on the load 60 changes from small to large, the target voltage will become smaller and an undershoot phenomenon will occur. In order to reduce the voltage spike, the coupling unit 51 is used to output a first coupling signal according to the target voltage. The first current mirror unit 52 is used to provide a second current to the power module 30 according to the first coupling signal. The power module 30 is used to quickly adjust the target voltage according to the second current, so that the target voltage becomes larger, so as to quickly respond to changes in the load 60. The second current mirror unit 53 is used to enter a cut-off state according to the first coupling signal.

[0043] When the current on the load 60 changes from large to small, the target voltage will increase, and an overshoot phenomenon will occur. In order to reduce the voltage spike, the coupling unit 51 is used to output a second coupling signal according to the target voltage. The second current mirror unit 53 is used to provide a third current to the power module 30 according to the second coupling signal. The power module 30 is used to quickly adjust the target voltage according to the third current, so that the target voltage becomes smaller, so as to quickly respond to changes in the load 60. The first current mirror unit 52 is used to enter a cut-off state according to the second coupling signal.

[0044] In some embodiments, Figure 3 As shown, the low voltage difference linear voltage regulator circuit provided in the embodiment of the present application further includes a Miller compensation module 70, and the Miller compensation module 70 is connected to the error amplification module 10, the buffer module 20 and the power module 30 respectively.

[0045] Specifically, the Miller compensation module 70 is used to perform phase compensation on the target voltage to maintain the stability of the circuit.

[0046] In some embodiments, Figure 4 As shown, the power module 30 includes a power tube MP, a gate of the power tube MP is respectively connected to the buffer module 20 and the transient enhancement module 50, a source of the power tube MP receives the power supply voltage VDD, and a drain of the power tube MP is respectively connected to the feedback module 40, the transient enhancement module 50 and the load 60.

[0047] Specifically, the main function of the power tube MP is to provide a sufficiently large load current to ensure the stability of the output voltage VOUT (ie, the target voltage). In the present application, when the load 60 changes, the power tube MP adjusts its own voltage drop to cope with the change of the load 60, thereby maintaining the stability of the output voltage VOUT.

[0048] In some embodiments, Figure 4 As shown, the coupling unit 51 includes a coupling capacitor Cc, a first end of the coupling capacitor Cc is connected to the power module 30, and a second end of the coupling capacitor Cc is connected to the first current mirror unit 52 and the second current mirror unit 53 respectively.

[0049] Specifically, when the target voltage VOUT changes, the coupling capacitor Cc is used to output a corresponding coupling signal to the first current mirror unit 52 and the second current mirror unit 53. When the target voltage VOUT remains stable, the coupling capacitor Cc is equivalent to an open circuit.

[0050] In some embodiments, Figure 4 As shown, the first current mirror unit 52 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and a first current source Ib1. The source of the first transistor M1 and the source of the second transistor M2 both receive the power supply voltage VDD. The gate of the first transistor M1 is respectively connected to the drain of the first transistor M1, the first end of the first current source Ib1, the source of the fifth transistor M5 and the source of the seventh transistor M7. The second end of the first current source Ib1 is grounded. The drain of the fifth transistor M5 is respectively connected to the drain of the sixth transistor M6 and the drain of the sixth transistor M7. The drain of the transistor M6, the gate of the fifth transistor M5 and the gate of the sixth transistor M6 are connected, the source of the sixth transistor M6 is respectively connected to the gate of the second transistor M2 and the drain of the seventh transistor M7, the gate of the seventh transistor M7 is respectively connected to the coupling unit 51 and the second current mirror unit 53, the drain of the second transistor M2 is respectively connected to the drain of the third transistor M3, the gate of the third transistor M3 and the gate of the fourth transistor M4, the drain of the fourth transistor M4 is respectively connected to the power module 30 and the second current mirror unit 53, and the source of the third transistor M3 and the source of the fourth transistor M4 are both grounded. Among them, the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 constitute a current mirror, the first transistor M1 and the second transistor M2 constitute a PMOS current mirror, and the third transistor M3 and the fourth transistor M4 constitute an NMOS current mirror. The seventh transistor M7 is a switch tube for controlling the current path.

[0051] Specifically, when the current ILOAD on the load 60 changes from small to large, the target voltage VOUT will decrease, and an undershoot phenomenon will occur. The coupling capacitor Cc outputs a first coupling signal according to the changed target voltage VOUT. Since the target voltage VOUT decreases, the first coupling signal also decreases, so that the gate voltage of the seventh transistor M7 decreases, and the seventh transistor M7 is turned on. Since the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 constitute a current mirror, after the seventh transistor M7 is turned on, the current provided by the first current source Ib1 passes through the first transistor M1, the seventh transistor M7, the second transistor M2, the third transistor M3 and the fourth transistor M4 to provide a second current to the gate of the power tube MP, discharge the parasitic capacitance of the power tube MP, reduce the gate voltage of the power tube MP, and then increase the target voltage VOUT, quickly respond to the change of the load 60, and reduce the voltage spike. It should be noted that the current provided by the first current source Ib1 is a small current, which will be amplified in a certain ratio after passing through the current mirror composed of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4.

[0052] When the current ILOAD on the load 60 changes from large to small, the target voltage VOUT will increase, and an overshoot phenomenon will occur. The coupling capacitor Cc outputs a second coupling signal according to the changed target voltage VOUT. As the target voltage VOUT increases, the second coupling signal also increases, causing the gate voltage of the seventh transistor M7 to increase, and the seventh transistor M7 is disconnected. In addition, since the fifth transistor M5 and the sixth transistor M6 are connected back to back to form an ultra-large resistance circuit, the ultra-large resistance circuit hinders the flow of current, so that the first current mirror unit 52 is in a cut-off state.

[0053] In some embodiments, Figure 4As shown, the second current mirror unit 53 includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14 and a second current source Ib2, a first end of the second current source Ib2, a source of the eighth transistor M8 and a source of the ninth transistor M9 all receive a power supply voltage VDD, a gate of the eighth transistor M8 is respectively connected to a gate of the ninth transistor M9, a drain of the ninth transistor M9 and a drain of the thirteenth transistor M13, a drain of the eighth transistor M8 is respectively connected to the power module 30 and the first current mirror unit 52, and the second current source Ib2 is connected to a power module 30 and a first current mirror unit 52. The second end of 2 is respectively connected to the drain of the tenth transistor M10, the gate of the tenth transistor M10, the drain of the fourteenth transistor M14 and the source of the eleventh transistor M11, the gate of the eleventh transistor M11 is respectively connected to the gate of the twelfth transistor M12, the drain of the eleventh transistor M11 and the drain of the twelfth transistor M12, the source of the twelfth transistor M12 is respectively connected to the source of the fourteenth transistor M14 and the gate of the thirteenth transistor M13, the gate of the fourteenth transistor M14 is respectively connected to the coupling unit 51 and the first current mirror unit 52, and the source of the tenth transistor M10 and the source of the thirteenth transistor M13 are both grounded. Among them, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10 and the thirteenth transistor M13 constitute a current mirror, the eighth transistor M8 and the ninth transistor M9 constitute a PMOS current mirror, and the tenth transistor M10 and the thirteenth transistor M13 constitute an NMOS current mirror. The fourteenth transistor M14 is a switch tube for controlling the current path.

[0054] Specifically, when the current ILOAD on the load 60 changes from small to large, the target voltage VOUT will decrease, and an undershoot phenomenon will occur. The coupling capacitor Cc outputs a first coupling signal according to the changed target voltage VOUT. Since the target voltage VOUT decreases, the first coupling signal also decreases, so that the gate voltage of the fourteenth transistor M14 decreases, and the fourteenth transistor M14 is disconnected. Since the eleventh transistor M11 and the twelfth transistor M12 are connected back to back to form an ultra-large resistance circuit, the ultra-large resistance circuit hinders the flow of current, so that the second current mirror unit 53 is in a cut-off state.

[0055] When the current ILOAD on the load 60 changes from large to small, the target voltage VOUT will increase, and an overshoot phenomenon will occur. The coupling capacitor Cc outputs a second coupling signal according to the changed target voltage VOUT. Since the target voltage VOUT increases, the second coupling signal also increases, so that the gate voltage of the fourteenth transistor M14 increases, and the fourteenth transistor M14 is turned on. Since the eighth transistor M8, the ninth transistor M9, the tenth transistor M10 and the thirteenth transistor M13 constitute a current mirror, after the fourteenth transistor M14 is turned on, the current provided by the second current source Ib2 passes through the tenth transistor M10, the fourteenth transistor M14, the thirteenth transistor M13, the ninth transistor M9 and the eighth transistor M8, and then provides a third current to the gate of the power tube MP, charges the parasitic capacitance of the power tube MP, increases the gate voltage of the power tube MP, and then reduces the target voltage VOUT, quickly responds to the change of the load 60, and reduces the voltage spike. It should be noted that the current provided by the second current source Ib2 is a small current, which will be amplified in a certain ratio after passing through the tenth transistor M10, the fourteenth transistor M14, the thirteenth transistor M13, the ninth transistor M9 and the eighth transistor M8.

[0056] It should be noted that the first current source Ib1 and the second current source Ib2 are two identical current sources.

[0057] In summary, the overall structure of the transient enhancement module 50 in the present application is simple and easy to implement, and its size can be designed to be a minimum size of 220nm / 180nm; it adopts transistor back-to-back connection technology, and the equivalent resistance reaches hundreds of gigahertz. When the circuit is in a stable state, the first current mirror unit 52 and the second current mirror unit 53 are both in the cut-off state, achieving low power consumption, and there is no need to use large-area resistors, saving circuit area.

[0058] In some embodiments, Figure 4 As shown, the buffer module 20 includes a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17 and an eighteenth transistor M18, the source of the fifteenth transistor M15 receives the power supply voltage VDD, the gate of the fifteenth transistor M15 receives the bias voltage Vb, the drain of the fifteenth transistor M15 is respectively connected to the source of the sixteenth transistor M16, the collector of the eighteenth transistor M18, the power module 30 and the transient enhancement module 50, the gate of the sixteenth transistor M16 is connected to the error amplification module 10, the drain of the sixteenth transistor M16 is respectively connected to the gate of the seventeenth transistor M17, the drain of the seventeenth transistor M17 and the base of the eighteenth transistor M18, the source of the seventeenth transistor M17 and the emitter of the eighteenth transistor M18 are both grounded.

[0059] Specifically, the buffer module 20 is essentially an enhanced source follower, which has an additional eighteenth transistor M18, namely, an NPN transistor, compared to the traditional source follower. The enhanced source follower is characterized by low input capacitance and low output impedance, and can separate the pole of the output end of the error amplifier module 10 from the pole of the gate of the power tube MP to obtain better stability.

[0060] In some embodiments, Figure 4 As shown, the error amplifier module 10 includes an error amplifier EA, the output end of the error amplifier EA is respectively connected to the buffer module 20 and the Miller compensation module 70, the non-inverting input end of the error amplifier EA is connected to the feedback module 40, and the inverting input end of the error amplifier EA receives the reference voltage VREF.

[0061] Specifically, the main function of the error amplifier EA is to compare the reference voltage VREF with the feedback voltage VFB. The feedback voltage VFB is obtained by the target voltage VOUT through the feedback module 40, which represents the actual level of the current output voltage VOUT. By accurately comparing these two voltages, the error amplifier EA can sense the deviation of the output voltage VOUT. When the feedback voltage VFB is lower than the reference voltage VREF, the error amplifier EA will output a positive error signal; conversely, when the feedback voltage VFB is higher than the reference voltage VREF, it will output a negative error signal. The size of this error signal is proportional to the difference between the two, which achieves accurate amplification of the error. The error signal is then fed into the subsequent control loop to adjust the conduction degree of the power tube MP.

[0062] For example, Figure 5As shown, the error amplifier EA includes a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23, a twenty-fourth transistor M24, a twenty-fifth transistor M25, a twenty-sixth transistor M26, a twenty-seventh transistor M27, a twenty-eighth transistor M28 and a twenty-ninth transistor M29, the source of the nineteenth transistor M19, the source of the twenty-second transistor M22 and the source of the twenty-third transistor M23 all receive the power supply voltage VDD, the gate of the nineteenth transistor M19 receives the bias voltage Vb1, the drain of the nineteenth transistor M19 is respectively connected to the source of the twentieth transistor M20 and the source of the twenty-first transistor M21, the gate of the twentieth transistor M20 is connected to the feedback module 40 to receive the feedback voltage VFB, the gate of the twenty-first transistor M21 receives the reference voltage VREF, the drain of the twentieth transistor M20 is respectively connected to the source of the twenty-sixth transistor M26 and the drain of the twenty-eighth transistor M28, The drain of the twenty-first transistor M21 is connected to the source of the twenty-seventh transistor M27 and the drain of the twenty-ninth transistor M29 respectively, the gate of the twenty-second transistor M22 is connected to the gate of the twenty-third transistor M23, the drain of the twenty-fourth transistor M24 and the drain of the twenty-sixth transistor M26 respectively, the drain of the twenty-second transistor M22 is connected to the source of the twenty-fourth transistor M24, the drain of the twenty-third transistor M23 is connected to the source of the twenty-fifth transistor M25, the gate of the twenty-fourth transistor M24 and the gate of the twenty-fifth transistor M25 both receive the bias voltage Vb2, the drain of the twenty-fifth transistor M25 is connected to the drain of the twenty-seventh transistor M27 and the buffer module 20 respectively, the gate of the twenty-sixth transistor M26 and the gate of the twenty-seventh transistor M27 both receive the bias voltage Vb3, the gate of the twenty-eighth transistor M28 and the gate of the twenty-ninth transistor M29 both receive the bias voltage Vb4, and the source of the twenty-eighth transistor M28 and the source of the twenty-ninth transistor M29 are grounded.

[0063] Specifically, the error amplifier EA is a folded common source and common gate amplifier, wherein the twentieth transistor M20 and the twenty-first transistor M21 are a PMOS differential input pair, used to amplify the difference between the reference voltage VREF and the feedback voltage VFB; the nineteenth transistor M19 is a tail current source for providing a bias current; and the transistors M22 to M29 are the output electrodes of the common source and common gate structure.

[0064] In some embodiments, Figure 4As shown, the feedback module 40 includes a first resistor R1, a second resistor R2 and a load capacitor CL, the first end of the first resistor R1 is respectively connected to the first end of the load capacitor CL and the power module 30, the second end of the first resistor R1 is respectively connected to the first end of the second resistor R2 and the error amplification module 10, and the second end of the second resistor R2 and the second end of the load capacitor CL are both grounded.

[0065] Specifically, after the first resistor R1 and the second resistor R2 divide the output voltage VOUT, a feedback voltage VFB is output to the error amplification module 10, so that the error amplification module 10 outputs an error signal according to the feedback voltage VFB and the reference voltage VREF. The error signal is then sent to a subsequent control loop to adjust the conduction degree of the power tube MP to ensure the stability of the output voltage VOUT.

[0066] It should be noted that the load capacitor CL of the present application can use an ordinary capacitor, and there is no need to use a large capacitor of microfarad level, which saves circuit area and cost.

[0067] In some embodiments, Figure 4 As shown, the Miller compensation module 70 includes a Miller compensation capacitor Cm and a Miller compensation resistor Rm, the first end of the Miller compensation capacitor Cm is connected to the error amplification module 10 and the buffer module 20 respectively, the second end of the Miller compensation capacitor Cm is connected to the first end of the Miller compensation resistor Rm, and the second end of the Miller compensation resistor Rm is grounded.

[0068] Specifically, the Miller compensation capacitor Cm and the Miller compensation resistor Rm are used to compensate for the phase of the target voltage VOUT to ensure the stability of the circuit.

[0069] In summary, the present application adds a transient enhancement module 50 to the low voltage difference linear voltage regulator circuit, which can quickly charge and discharge the parasitic capacitance of the power tube MP when the power module 30 has a transient response, thereby improving the response speed of the power tube MP and reducing the voltage spike. When the current ILOAD on the load 60 changes drastically in a short period of time, the voltage spike of the output voltage VOUT can be controlled within 4mV. The small peak of the output voltage VOUT can be suitable for devices that are sensitive to voltage changes. Compared with the traditional LDO that uses large capacitors at the microfarad level to achieve better transient response, the load capacitor CL used in the present application is very small, saving circuit area and cost. The transient enhancement module 50 in the present application adopts transistor back-to-back connection technology, and the equivalent resistance reaches hundreds of gigahertz, which solves the problem of using large-area resistors to occupy circuit area.

[0070] The embodiment of the present application also provides a low voltage dropout linear regulator, including the low voltage dropout linear regulator circuit described above. Since the low voltage dropout linear regulator provided in the embodiment of the present application adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here one by one.

[0071] The embodiment of the present application also provides an electronic device, including the low voltage difference linear voltage regulator circuit described above. Since the electronic device provided by the embodiment of the present application adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0072] Exemplarily, the electronic device may be a switching power supply device.

[0073] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0074] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A low voltage drop linear voltage regulator circuit, characterized in that: It includes an error amplification module, a buffer module, a power module, a feedback module and a transient enhancement module, wherein the buffer module is respectively connected to the error amplification module, the power module and the transient enhancement module, the power module is respectively connected to the transient enhancement module, the feedback module and a load, and the feedback module is connected to the error amplification module; When the current on the load changes, the transient enhancement module is used to provide a first current to the power module according to the target voltage, so that the power module quickly adjusts the target voltage according to the first current; the feedback module is used to output a feedback voltage according to the target voltage; the error amplification module is used to output an error signal according to the feedback voltage and a reference voltage; the buffer module is used to output a drive signal to the power module according to the error signal, so that the power module maintains the target voltage stable according to the drive signal; wherein the target voltage is the output voltage of the low voltage difference linear voltage regulator circuit.

2. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The transient enhancement module includes a coupling unit, a first current mirror unit and a second current mirror unit, the coupling unit is connected to the power module, the first current mirror unit and the second current mirror unit respectively, the first current mirror unit is connected to the power module and the second current mirror unit respectively; the first current includes a second current and a third current; When the current on the load increases from small to large, the coupling unit is used to output a first coupling signal according to the target voltage; the first current mirror unit is used to provide the second current to the power module according to the first coupling signal; the power module is used to quickly adjust the target voltage according to the second current to increase the target voltage; The second current mirror unit is used to enter a cut-off state according to the first coupling signal; When the current on the load changes from large to small, the coupling unit is used to output a second coupling signal according to the target voltage; the second current mirror unit is used to provide the third current to the power module according to the second coupling signal; the power module is used to quickly adjust the target voltage according to the third current to make the target voltage smaller; the first current mirror unit is used to enter a cut-off state according to the second coupling signal.

3. The low voltage difference linear voltage regulator circuit according to claim 2, characterized in that: The first current mirror unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a first current source, the source of the first transistor and the source of the second transistor both receive a power supply voltage, the gate of the first transistor is respectively connected to the drain of the first transistor, the first end of the first current source, the source of the fifth transistor and the source of the seventh transistor, the second end of the first current source is grounded, the drain of the fifth transistor is respectively connected to the drain of the sixth transistor, the gate of the fifth transistor and the gate of the sixth transistor, the source of the sixth transistor is respectively connected to the gate of the second transistor and the drain of the seventh transistor, the gate of the seventh transistor is respectively connected to the coupling unit and the second current mirror unit, the drain of the second transistor is respectively connected to the drain of the third transistor, the gate of the third transistor and the gate of the fourth transistor, the drain of the fourth transistor is respectively connected to the power module and the second current mirror unit, and the source of the third transistor and the source of the fourth transistor are both grounded.

4. The low voltage difference linear voltage regulator circuit according to claim 2, characterized in that: The second current mirror unit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a second current source, a first end of the second current source, a source of the eighth transistor and a source of the ninth transistor all receive a power supply voltage, a gate of the eighth transistor is respectively connected to a gate of the ninth transistor, a drain of the ninth transistor and a drain of the thirteenth transistor, a drain of the eighth transistor is respectively connected to the power module and the first current mirror unit, a second end of the second current source is respectively connected to a drain of the tenth transistor, a gate of the tenth transistor, a drain of the fourteenth transistor and a source of the eleventh transistor, a gate of the eleventh transistor is respectively connected to a gate of the twelfth transistor, a drain of the eleventh transistor and a drain of the twelfth transistor, a source of the twelfth transistor is respectively connected to a source of the fourteenth transistor and a gate of the thirteenth transistor, a gate of the fourteenth transistor is respectively connected to the coupling unit and the first current mirror unit, and a source of the tenth transistor and a source of the thirteenth transistor are both grounded.

5. The low voltage difference linear voltage regulator circuit according to claim 2, characterized in that: The coupling unit includes a coupling capacitor, a first end of the coupling capacitor is connected to the power module, and a second end of the coupling capacitor is connected to the first current mirror unit and the second current mirror unit respectively.

6. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The buffer module includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor and an eighteenth transistor, the source of the fifteenth transistor receives a power supply voltage, the gate of the fifteenth transistor receives a bias voltage, the drain of the fifteenth transistor is respectively connected to the source of the sixteenth transistor, the collector of the eighteenth transistor, the power module and the transient enhancement module, the gate of the sixteenth transistor is connected to the error amplification module, the drain of the sixteenth transistor is respectively connected to the gate of the seventeenth transistor, the drain of the seventeenth transistor and the base of the eighteenth transistor, and the source of the seventeenth transistor and the emitter of the eighteenth transistor are both grounded.

7. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The power module includes a power tube, a gate of the power tube is respectively connected to the buffer module and the transient enhancement module, a source of the power tube receives a power supply voltage, and a drain of the power tube is respectively connected to the feedback module, the transient enhancement module and the load.

8. The low voltage difference linear voltage regulator circuit according to any one of claims 1 to 7, characterized in that: The low voltage difference linear voltage stabilization circuit further includes a Miller compensation module, and the Miller compensation module is respectively connected to the error amplification module, the buffer module and the power module; The Miller compensation module is used to perform phase compensation on the target voltage.

9. A low voltage dropout linear regulator, characterized in that: A low voltage difference linear voltage stabilizing circuit comprising any one of claims 1 to 8.

10. An electronic device, characterized in that: A low voltage difference linear voltage stabilizing circuit comprising any one of claims 1 to 8.

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