Data reading method and device, electronic equipment and computer readable storage medium

Abstract

The invention discloses a data reading method and device, electronic equipment and a computer readable storage medium. The data reading method is used for reading data in M storage units, each storage unit corresponds to a group of address memories, and each group of address memories comprises at least two address memories. The method comprises the following steps: receiving a reading request, wherein the reading request comprises N groups of reading addresses respectively corresponding to N storage units; respectively writing the N groups of read addresses into the corresponding N groups of address memories, and writing the first group of read addresses into the first group of address memories in parallel under the condition that the first group of read addresses comprises at least two read addresses and the address number of the first group of read addresses is not greater than the memory number of the first group of address memories; reading sub-data corresponding to the read addresses of the N groups of address memories from the N memory units to obtain N groups of sub-data; and merging the N groups of subdata to obtain target data corresponding to the reading request, and outputting the target data through the data transmission device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a data reading method, device, electronic device, and computer-readable storage medium. Background Art

[0002] As computing devices become more powerful and the amount of data that needs to be processed increases, central processing units (CPUs) and coprocessors continue to develop rapidly. The most common coprocessors are graphics processing units (GPUs), which mainly handle calculations related to graphics display; later, GPUs were used to handle general computing tasks, resulting in the emergence of general-purpose graphics processors (GPGPUs). General-purpose graphics processor chips can not only provide powerful graphics processing capabilities, but can also be used to perform highly parallel scientific computing, data analysis, machine learning, and other computationally intensive tasks. General-purpose graphics processor chips are usually equipped with high-speed video memory and have higher memory bandwidth than CPUs, which helps accelerate data-intensive applications. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a data reading method, the data reading method is used to read data in M ​​storage units, each of the storage units corresponds to a group of address memories, each group of address memories includes at least two address memories, wherein the method comprises: receiving a read request, wherein the read request comprises N groups of read addresses corresponding to N storage units in the M storage units, wherein each group of the N groups of read addresses comprises one or more read addresses; writing the N groups of read addresses into the N groups of address memories corresponding to the N storage units, wherein the N groups of read addresses comprise a first group of read addresses corresponding to a first storage unit in the N storage units; address, in the case where the first group of read addresses includes at least two read addresses and the address quantity of the first group of read addresses is not greater than the memory quantity of the first group of address memory corresponding to the first storage unit, the first group of read addresses are written into the first group of address memory in parallel; sub-data corresponding to the read addresses in the N group of address memory are read out from the N storage units to obtain N groups of sub-data corresponding to the N groups of read addresses respectively; the N groups of sub-data are merged to obtain target data corresponding to the read request, and the target data is transmitted to the target device through a data transmission device; wherein M is an integer greater than 1, and N is an integer greater than or equal to 1 and less than M.

[0004] For example, in the data reading method provided by at least one example of the above-mentioned embodiments of the present disclosure, the first group of read addresses includes k read addresses, k is an integer greater than or equal to 2; the N groups of read addresses are respectively written into the N groups of address memories corresponding to the N storage units, including: when the number of memories of the first group of address memories is greater than or equal to k, the k read addresses are written in parallel into the k address memories of the first group of address memories.

[0005] For example, in the data reading method provided by at least one example of the above-mentioned embodiments of the present disclosure, the N groups of read addresses are respectively written into the N groups of address memories corresponding to the N storage units, including: when the number of addresses included in each group of the N groups of read addresses is not greater than the number of memories included in the corresponding group of address memories, the N groups of read addresses are written into the N groups of address memories in parallel.

[0006] For example, in the data reading method provided by at least one example of the above-mentioned embodiments of the present disclosure, sub-data corresponding to the read address in the N groups of address memories are read out from the N storage units to obtain N groups of sub-data corresponding to the N groups of read addresses, including: in each clock cycle, based on the arbitration rule, selecting an address memory from the first group of address memories; reading out the sub-data corresponding to the read address in the selected address memory from the first storage unit.

[0007] For example, in the data reading method provided by at least one example of the above-mentioned embodiments of the present disclosure, each of the address memories includes multiple storage locations, and the width of each storage location in the multiple storage locations corresponds to the data bit width of one of the read addresses; wherein, in each clock cycle, based on the arbitration rule, an address memory is selected from the first group of address memories, including: based on the polling order of at least two address memories in the first group of address memories, one of the at least two address memories is selected; wherein, sub-data corresponding to the read address in the selected address memory is read out from the first storage unit, including: sub-data corresponding to the first read address in the selected address memory is read out from the first storage unit.

[0008] For example, in the data reading method provided by at least one example of the above-mentioned embodiments of the present disclosure, it also includes: recording the corresponding relationship between each read address in the read request and the N groups of address memories to form record information.

[0009] For example, in the data reading method provided by at least one example of the above-mentioned embodiments of the present disclosure, each of the storage units corresponds to a group of data storage devices, each group of data storage devices includes at least two data storage devices, and a group of address storage devices and a group of data storage devices of each of the storage units correspond to each other; wherein, sub-data corresponding to the read addresses in the N groups of address storage devices are read out from the N storage units to obtain N groups of sub-data corresponding to the N groups of read addresses, including: for each of the storage units, after reading out a sub-data corresponding to a read address each time, a data storage device is selected from the corresponding group of data storage devices, and the read sub-data is written into the selected data storage device; based on the record information, the sub-data corresponding to the read request is read out from the N groups of data storage devices to obtain the N groups of sub-data.

[0010] For example, in the data reading method provided by at least one example of the above-mentioned embodiments of the present disclosure, based on the record information, sub-data corresponding to the read request are read out from the N groups of data storage devices to obtain the N groups of sub-data, including: when the number of addresses included in each group of the N groups of read addresses is not greater than the number of memories included in a corresponding group of address memories, based on the record information, the sub-data corresponding to the read request are simultaneously read out from the N groups of data storage devices to obtain the N groups of sub-data.

[0011] For example, in the data reading method provided by at least one example of the above-mentioned embodiments of the present disclosure, the N groups of read addresses are respectively written into the N groups of address memories corresponding to the N storage units, including: when the number of addresses of the first group of read addresses is greater than the number of memories of the first group of address memories corresponding to the first storage unit, the first group of read addresses are written into the first group of read addresses in multiple times. Wherein, based on the record information, the sub-data corresponding to the read request is read out from the N groups of data memories, including: when there is at least one group of read addresses in the N groups of read addresses, the number of addresses included is greater than the number of memories included in the corresponding group of address memories, the sub-data corresponding to the read request is read out from the N groups of data memories in multiple times. Wherein, the N groups of sub-data are merged to obtain the target data corresponding to the read request, including: storing the sub-data read out from the N groups of data memories each time into the merge memory until the sub-data corresponding to the read request are all stored in the merge memory, and merging the sub-data in the merge memory to obtain the target data corresponding to the read request.

[0012] At least one embodiment of the present disclosure provides a data reading device, including M groups of address memories, an address processing unit, M reading units and a data processing unit. The M groups of address memories correspond to the M storage units, and each group of address memories includes at least two address memories. The address processing unit is connected to the M groups of address memories, and the M reading units correspond to the M storage units. The address processing unit is configured to: receive a read request, wherein the read request includes N groups of read addresses corresponding to N storage units of the M storage units, wherein each group of the N groups of read addresses includes one or more read addresses; write the N groups of read addresses into the N groups of address memories corresponding to the N storage units, wherein the N groups of read addresses include a first group of read addresses corresponding to a first storage unit of the N storage units, and when the first group of read addresses includes at least two read addresses and the number of addresses of the first group of read addresses is not greater than the number of memories of the first group of address memories corresponding to the first storage unit, the first group of read addresses is written into the first group of address memories in parallel. The M reading units are configured to read out sub-data corresponding to the read addresses in the N groups of address memories from the N storage units to obtain N groups of sub-data corresponding to the N groups of read addresses. The data processing unit is configured to merge the N groups of sub-data to obtain target data corresponding to the read request, and transmit the target data to the target device through the data transmission unit.

[0013] For example, in the data reading device provided by at least one example of the above-mentioned embodiments of the present disclosure, the M reading units include a first reading unit corresponding to the first storage unit, and the first reading unit is further configured to: in each clock cycle, based on the arbitration rule, select an address memory from the first group of address memories; and read out the sub-data corresponding to the read address in the selected address memory from the first storage unit.

[0014] For example, in the data reading device provided by at least one example of the above embodiments of the present disclosure, it also includes: a recording unit configured to record the correspondence between each read address in the read request and the N groups of address memories to form recording information.

[0015] For example, in the data reading device provided in at least one example of the above-mentioned embodiments of the present disclosure, it also includes M groups of data storage devices and a transmission unit, the M groups of data storage devices correspond to M storage units, and each group of data storage devices includes at least two data storage devices; the transmission unit is connected between the M groups of data storage devices and the data processing unit; wherein each of the reading units is further configured to: each time after reading out a sub-data corresponding to a read address from the corresponding storage unit, select a data storage device from a corresponding group of data storage devices, and write the read sub-data into the selected data storage device; wherein the transmission unit is configured to read out the sub-data corresponding to the read request from the N groups of data storage devices based on the record information, and send the sub-data to the data processing unit.

[0016] At least one embodiment of the present disclosure provides an electronic device, comprising a processor; a memory storing one or more computer program modules; wherein the one or more computer program modules are configured to be executed by the processor to implement the data reading method provided by any embodiment of the present disclosure.

[0017] At least one embodiment of the present disclosure provides a computer-readable storage medium storing non-transitory computer-readable instructions. When the non-transitory computer-readable instructions are executed by a computer, the data reading method provided by any embodiment of the present disclosure can be implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0019] Figure 1A A schematic diagram of a storage unit organization method;

[0020] Figure 1B A schematic diagram of another storage unit organization method;

[0021] Figure 2 A flow chart of a data reading method provided by at least one embodiment of the present disclosure is shown;

[0022] Figure 3 A schematic diagram showing a data reading process provided by at least one embodiment of the present disclosure is shown;

[0023] Figure 4 A flowchart of reading sub-data corresponding to N groups of read addresses provided by at least one embodiment of the present disclosure is shown;

[0024] Figure 5A and 5BAnother schematic diagram of a data reading process provided by at least one embodiment of the present disclosure is shown;

[0025] Figure 6 A schematic block diagram of a data reading device provided by at least one embodiment of the present disclosure is shown;

[0026] Figure 7 A schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown;

[0027] Figure 8 A schematic block diagram showing another electronic device provided by at least one embodiment of the present disclosure; and

[0028] Fig. 9 A schematic diagram of a computer-readable storage medium provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0030] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0031] The processor includes shared memory inside. Shared memory allows multiple processes to access the same memory area, so that data can be exchanged quickly between these processes. Shared memory can efficiently transmit large amounts of data. Because data does not need to be copied between different processes, as a very important storage unit in the processor (such as GPU), the efficiency of reading memory directly affects the data processing efficiency of the entire processor chip. Usually, in order to achieve high-bandwidth simultaneous access to memory, shared memory is divided into equal-sized storage units that can be accessed in parallel. For example, multiple independent storage units can be organized in a multi-banking manner, each storage unit can be a storage unit (bank), or can be a storage unit group (bank group) containing multiple storage units, where, for shared memory, the divided storage unit can also be called a memory block. When multiple addresses need to be accessed, access operations can be performed on multiple independent storage units at the same time. However, once the same storage unit is read at the same time, an access conflict will occur.

[0032] Figure 1A A schematic diagram of a storage unit organization method. Figure 1B A schematic diagram of another storage unit organization method.

[0033] For example, Figure 1A and Figure 1B As shown, the internal storage device 110 may be an internal storage device of a computing device (CPU, GPU, GPGPU or NPU, etc.), and the internal storage device 110 is interconnected and communicated with the request device 130 via a bus 120. For example, the internal storage device 110 may be various types of memory, cache, etc., and the request device 130 may be a processor, memory, etc., which is not limited in the embodiments of the present disclosure.

[0034] For example, Figure 1A As shown, taking a bank as a storage unit as an example, the internal storage device 110 includes N banks (bank 0, bank 1, ... bank N-1), where N is an integer greater than 1. For example, when the request device 130 in the computing device wants to read data from multiple banks, it will send a corresponding read request to the bus 120 to send the read request to the internal storage device 110 through the bus 120. The read request includes multiple read addresses, and the read addresses correspond to the banks to be accessed in the internal storage device 110; after reading data from the banks, the read data is transmitted to the request device through the bus.

[0035] For example, Figure 1BAs shown, taking a bank group as a storage unit as an example, the internal storage device 110 includes N bank groups (bank group 0, bank group 1, ... bank group N-1), each bank group includes n banks (bank 0, bank 1, ... bank n-1), where N and n are both integers greater than 1. For example, when a computing device needs to access or store data in multiple bank groups, Figure 1B and Figure 1A The difference between the memory access process and the memory access process is that the read address corresponds to the memory bank group to be accessed in the internal storage device 110.

[0036] For example, in Figure 1A and Figure 1B In the example, under normal circumstances, the read address corresponds one-to-one to the multiple storage banks / storage bank groups to be accessed; when two or more read addresses correspond to the same storage bank / storage bank group, a read conflict, or bank conflict (Bank Conflict), occurs, that is, the data corresponding to the two or more read addresses cannot be read from the same storage bank / storage bank group at the same time.

[0037] For example, when a read conflict occurs between read address 1 and read address 2 in one group of read addresses, in the current clock cycle, data of the corresponding storage body / storage body group can only be read in parallel based on read address 1 and other read addresses except read address 2, and data of the corresponding storage body / storage body group can only be read separately in the next clock cycle for read address 2. In this way, on the one hand, back pressure will be generated on bus 120, affecting the overall performance of the hardware device; on the other hand, since an extra clock cycle is added to read read address 2 separately, the bandwidth of the storage device is reduced by half, which will greatly reduce the bandwidth of the storage device in the case of frequent read conflicts.

[0038] Write conflicts often occur on the transmission link of computing devices. As the number of processing cores in computing devices increases, data access to storage units in storage devices also increases accordingly, which increases the possibility of write conflicts, reduces the bandwidth of storage devices, greatly increases data access time, and reduces the parallel processing efficiency of computing devices.

[0039] In some cases, a suitable swizzle algorithm can be used to deal with read conflicts. For example, different swizzle patterns are used for different read addresses, and the addresses corresponding to the storage units in the storage device are reallocated by hashing or other methods, so that multiple read addresses with read conflicts are re-mapped to multiple different storage units. This situation requires software participation, which greatly increases the complexity of the software.

[0040] In addition, for multiple read addresses with read conflicts, if they are processed over multiple clock cycles, the read data will also be transmitted back to the requesting device over multiple clock cycles. In this way, the bus needs to perform multiple data transmissions, which reduces efficiency and increases the bus load.

[0041] At least one embodiment of the present disclosure provides a data reading method, a data reading device, an electronic device, and a computer-readable storage medium. The data reading method comprises: receiving a read request, wherein the read request comprises N groups of read addresses corresponding to N storage units among the M storage units, wherein each group of the N groups of read addresses comprises one or more read addresses; writing the N groups of read addresses into N groups of address memories corresponding to the N storage units, wherein the N groups of read addresses comprise a first group of read addresses corresponding to a first storage unit among the N storage units, and in the case where the first group of read addresses comprises at least two read addresses and the number of addresses of the first group of read addresses is not greater than the number of memories of the first group of address memories corresponding to the first storage units, the first group of read addresses are written into the first group of address memories in parallel; reading out sub-data corresponding to the read addresses in the N groups of address memories from the N storage units to obtain N groups of sub-data corresponding to the N groups of read addresses; merging the N groups of sub-data to obtain target data corresponding to the read request, and transmitting the target data to a target device through a data transmission device; wherein M is an integer greater than 1, and N is an integer greater than or equal to 1 and less than M.

[0042] In the data reading method, by setting at least two address memories for each storage unit, multiple read addresses with read conflicts can be first written into the address memories of the corresponding storage units, thereby reducing the back pressure on the data input terminal, solving the problem of read conflicts at the hardware level, and improving the parallel processing efficiency of the computing device. In addition, by merging the returned data corresponding to the conflicting read addresses, the number of transmissions of the transmission device is reduced, and the utilization rate of the transmission device is improved.

[0043] Figure 2 A flow chart of a data reading method provided by at least one embodiment of the present disclosure is shown.

[0044] like Figure 2 As shown, the data reading method is used to read data in M ​​storage units, each storage unit corresponds to a group of address memories, each group of address memories includes at least two address memories, and the method may include steps S210~S240.

[0045] Step S210: receiving a read request, the read request including N groups of read addresses corresponding to N storage units among the M storage units, each of the N groups of read addresses including one or more read addresses.

[0046] Step S220: writing N groups of read addresses into N groups of address memories corresponding to the N storage units respectively, wherein the N groups of read addresses include a first group of read addresses corresponding to a first storage unit among the N storage units, and in the case where the first group of read addresses includes at least two read addresses and the number of addresses of the first group of read addresses is not greater than the number of memories of the first group of address memories corresponding to the first storage unit, the first group of read addresses are written into the first group of address memories in parallel;

[0047] Step S230: reading out sub-data corresponding to the read addresses in the N groups of address memories from the N storage units to obtain N groups of sub-data corresponding to the N groups of read addresses respectively;

[0048] Step S240: merge the N groups of sub-data to obtain target data corresponding to the read request, and transmit the target data to the target device through the data transmission device.

[0049] For example, M is an integer greater than 1, and N is an integer greater than or equal to 1 and less than M.

[0050] For example, the M storage units may be multiple storage units obtained by dividing the shared memory of the processor, and the storage unit may be the above-mentioned bank or bank group. The embodiments of the present disclosure do not limit the type and number of storage units.

[0051] Figure 3 A schematic diagram of a data reading process provided by at least one embodiment of the present disclosure is shown.

[0052] like Figure 3As shown, taking the storage unit as a storage body group (bank group) as an example, each storage unit includes multiple banks, for example, bank0~bank3 constitute bank group 0, bank4~bank7 constitute bank group 1, ..., bank28~bank31 constitute bank group 7. For each bank group, a group of address memories is provided. The embodiment of the present disclosure does not limit the number of address memories included in each group of address memories. Each group of address memories may include two or more address memories, and the following is an example of each group of address memories including two address memories. For example, for bank group 0, address memories A0~A1 are provided; for bank group 1, address memories A2~A3 are provided; for bank group 2, address memories A4~A5 are provided; for bank group 3, address memories A6~A7 are provided, ..., for bank group 7, address memories A14~A15 are provided. For example, each address memory can be implemented as a device for storage such as a register.

[0053] For example, in step S210, the address processing unit may receive a read request, and may parse and obtain multiple read addresses in the read request. After obtaining multiple read addresses, the address processing unit may send each read address to the corresponding address memory through a first selector (MUX). Each read address may correspond to a bank group, and in some cases, there are two or more read addresses corresponding to the same bank group. For example, the read request includes read addresses r0~r4 (only r0~r2 is shown in the figure), wherein read addresses r0 and r1 correspond to bank group 0, and read addresses r2~r4 correspond to bankgroup 1~ bank group 3, respectively. In this case, one or more read addresses corresponding to each bank group may be used as a group of read addresses, and each group of read addresses may include one or more read addresses. For example, read addresses r0 and r1 may be used as a group of read addresses, read address r2 may be regarded as a group of read addresses, read address r3 may be regarded as a group of read addresses, and read address r4 may be regarded as a group of read addresses.

[0054] For example, the first storage unit may be any storage unit corresponding to multiple (two or more) read addresses in the read request. In the above example, bank group 0 corresponds to two read addresses r0 and r1, and the first storage unit may be bank group 0. For any storage unit corresponding to multiple read addresses, the operation for the first storage unit may be referred to.

[0055] For example, a first group of address memories is provided for the first storage unit, the first storage unit corresponds to the first group of read addresses in the read request, and the first group of read addresses includes k read addresses, where k is an integer greater than or equal to 2. In step S220, when the number of memories in the first group of address memories is greater than or equal to k, the k read addresses are written in parallel to the k address memories of the first group of address memories. Writing the k read addresses in parallel to the k address memories can be understood as writing the k read addresses to the k address memories respectively in the same clock cycle. For example, the first storage unit is bank group0, the first group of address memories are address memories A0 and A1, and the first group of read addresses are read addresses r0 and r1. In this example, k is 2, and the number of address memories included in the first group of address memories is equal to k. Therefore, the read addresses r0 and r1 can be written in parallel to the address memories A0 and A1. For example, in the same clock cycle, the read address r0 is written to the address memory A0, and the read address r1 is written to the address memory A1. In this way, when there is a read conflict, the conflicting read addresses can be written into the address memory at the same time, ensuring that the read address in the read request will not back-pressure the input terminal.

[0056] For example, in step S220, when the number of addresses included in each group of N groups of read addresses is not greater than the number of memories included in a corresponding group of address memories, the N groups of read addresses are written into the N groups of address memories in parallel. For example, bank group 0 corresponds to read addresses r0 and r1, and the number of read addresses is not greater than the number of address memories A0 and A1 corresponding to bank group 0; bank group 1 corresponds to read address r2, and the number of read addresses is not greater than the number of address memories A2 and A3 corresponding to bank group 1; the same is true for other bank groups. When the number of read addresses corresponding to each bank group is not greater than the number of corresponding address memories, the read addresses corresponding to each bank group can be written into the corresponding address memory in the same clock cycle. For example, in the same clock cycle, read addresses r0 and r1 can be written into address memories A0 and A1 respectively, read address r2 can be written into address memory A2, read address r3 can be written into address memory A4, and read address r3 can be written into address memory A6.

[0057] For example, in step S230, data can be read from the corresponding bankgroup according to the read addresses written in each address memory, for example, sub-data d0 corresponding to read address r0 is read from bank group 0, and sub-data d1 corresponding to read address r1 is read from bank group 0, and sub-data d0 and d1 can be regarded as a group of sub-data; sub-data d2 corresponding to read address r2 is read from bank group 1, and sub-data d2 can be regarded as a group of sub-data; sub-data d3 corresponding to read address r3 is read from bank group 2 (not shown in the figure), and sub-data d3 can be regarded as a group of sub-data; sub-data d4 corresponding to read address r4 is read from bank group 3 (not shown in the figure), and sub-data d4 can be regarded as a group of sub-data. In this way, N groups of sub-data corresponding to N groups of read addresses are obtained.

[0058] For example, in step S240, N groups of sub-data corresponding to the same read request may be merged to obtain target data corresponding to the read request. For example, sub-data d0~d4 may be merged, and the merged data may be used as the target data to be read by the read request. Then, the target data is transmitted to the target device through a transmission device such as a bus. The target device may be an initiator of the read request (also referred to as a request device), or may be another device other than the initiator, such as a main memory or a processor of a computing device. By merging N groups of sub-data to obtain the target data corresponding to the read request, the bandwidth of the subsequent data bus may be aligned, and the data may be returned to the initiator through one transmission, thereby reducing the number of transmissions of the transmission device, improving the utilization rate of the transmission device, and reducing the number of accesses of the initiator, thereby improving the access bandwidth of the initiator.

[0059] According to the data reading method of the embodiment of the present disclosure, by setting at least two address memories for each storage unit, multiple read addresses with read conflicts can be first written into the address memory of the corresponding storage unit, thereby reducing the back pressure on the data input terminal, solving the problem of read conflicts at the hardware level, and improving the parallel processing efficiency of the computing device. In addition, by merging the returned data corresponding to the conflicting read addresses, the number of transmissions of the transmission device is reduced, and the utilization rate of the transmission device is improved.

[0060] For example, in step S230, sub-data corresponding to the read addresses in N groups of address memories are read out from N storage units to obtain N groups of sub-data corresponding to the N groups of read addresses, respectively, which may include: in each clock cycle, based on the arbitration rule, selecting an address memory from the first group of address memories; and reading out the sub-data corresponding to the read address in the selected address memory from the first storage unit.

[0061] For example, the arbitration rule may adopt a polling method, in which, in each clock cycle, based on the polling order of at least two address memories in the first group of address memories, one address memory in the at least two address memories is selected, and the sub-data corresponding to the read address in the address memory is read.

[0062] For example, refer to Figure 3 Taking bank group 0 as an example, within one clock cycle, sub-data d0 corresponding to the read address r0 stored in address memory A0 can be read from bank group 0. In the next clock cycle, sub-data d1 corresponding to the read address r1 stored in address memory A1 can be read from bank group 0. In the next cycle, sub-data corresponding to the next read address stored in address memory A0 can be read from bank group 0, and so on, and sub-data corresponding to the read addresses stored in the two address memories can be read cyclically. Based on this method, two read addresses stored in parallel can be read within adjacent clock cycles, avoiding the situation where the waiting time of some sub-data of the same read request is too long. For example, after reading out all the sub-data corresponding to the read request, these sub-data can be merged.

[0063] For example, each address memory includes multiple storage locations, and the width of each storage location in the multiple storage locations corresponds to the data bit width of a read address. Wherein, reading out the sub-data corresponding to the read address in the selected address memory from the first storage unit includes: reading out the sub-data corresponding to the first read address in the selected address memory from the first storage unit.

[0064] For example, Figure 3 As shown, taking two address memories A0 and A1 corresponding to bank group 0 as an example, each address memory may include 4 storage locations, and the width of each storage location is equal to or greater than the data bit width of each read address.

[0065] For example, if the read address r0 and the read address r1 both correspond to bank group 0, the read addresses r0 and r1 are written to the address memories A0 and A1 in parallel. If there are no other read addresses in the address memory A0 or A1, the read address r0 or r1 is written to the first storage location of the address memory A0 or A1 respectively; if there are still unwritten read addresses in the address memory A0 or A1, for example, there are other read addresses in the first storage location of the address memory A0, the read address r0 is written to the second storage location of the address memory A0.

[0066] For example, in each clock cycle, an address memory can be selected according to the polling scheduling strategy based on the polling order of address memories A0 and A1. After the address memory is selected, the read address can be selected according to the storage order of the read addresses in the selected address memory. Each time a read address is selected from the address memory, the read address stored in the first storage position can be selected. After the read address of the first storage position is read, the read addresses of other storage positions can be uniformly moved forward.

[0067] For example, in some embodiments, the data reading method may further include: recording a correspondence between each read address in a read request and N groups of address memories to form record information.

[0068] For example, Figure 3 As shown, the address processing unit can be connected to the recording unit, and the address processing unit can record the address memory to which each read address is assigned in the recording unit. Therefore, by querying the information in the recording unit, it can be known to which address memory each read address is assigned.

[0069] For example, each storage unit corresponds to a group of data memories, each group of data memories includes at least two data memories, and a group of address memories and a group of data memories of each storage unit correspond to each other.

[0070] For example, Figure 3 As shown, for each bank group, a group of data memories is provided. The embodiment of the present disclosure does not limit the number of data memories included in the data address memory. Each group of data memories may include two or more data memories, for example. The following description is made by taking each group of data memories including two data memories as an example. For example, for bank group 0, data memories B0~B1 are provided; for bank group 1, data memories B2~B3 are provided; for bank group 2, data memories B4~B5 are provided; for bank group 3, data memories B6~B7, ... are provided; for bank group 7, data memories B14~B15 are provided. For example, each data memory may be implemented as a device for storage such as a register. The number of address memories corresponding to each storage unit may be the same as the number of corresponding data memories, and the multiple address memories corresponding to each storage unit may correspond one-to-one to the corresponding multiple data memories.

[0071] Figure 4 A flowchart for reading out sub-data corresponding to N groups of read addresses provided by at least one embodiment of the present disclosure is shown.

[0072] like Figure 4As shown, in step S230, sub-data corresponding to the read addresses in the N groups of address memories are read out from N storage units to obtain N groups of sub-data corresponding to the N groups of read addresses respectively, which may include steps S231 and S232.

[0073] Step S231: for each storage unit, after reading out a sub-data corresponding to a read address each time, select a data storage from a corresponding group of data storages, and write the read sub-data into the selected data storage;

[0074] Step S232: Based on the record information, sub-data corresponding to the read request is read from N groups of data storage devices to obtain N groups of sub-data.

[0075] For example, for each storage unit, after reading out a sub-data corresponding to a read address each time, the sub-data can be stored in the corresponding multiple data storages ("multiple" means two or more) in turn in a polling manner. In each clock cycle, based on the polling order of multiple data storages, one of the data storages is selected, and the read sub-data is stored in the data storage selected by the polling. Taking bank group 0 as an example, bank group 0 corresponds to data storages B0 and B1. In one clock cycle, the sub-data d0 corresponding to the read address r0 is read out. The read address r0 was once stored in the address storage A0. Therefore, the sub-data d0 can be stored in the data storage B0 corresponding to the address storage A0. In the next clock cycle, the sub-data d1 corresponding to the read address r1 is read out. The sub-data d1 can be stored in the data storage B1. After reading out the next sub-data, the sub-data is stored in the data storage B0. By analogy, the read sub-data are stored in the two data storages cyclically. In this way, the corresponding relationship between the read address in the address storage and the sub-data in the data storage is also realized.

[0076] For example, each data memory includes a plurality of storage locations, and the width of each storage location in the plurality of storage locations corresponds to the bit width of one sub-data. Figure 3 As shown, taking two data memories B0 and B1 corresponding to bank group 0 as an example, each data memory may include 4 storage locations, and the width of each storage location is equal to or greater than the bit width of each sub-data.

[0077] For example, after reading out sub-data d0 from bank group 0, if there is no other sub-data in the data memory B0, the sub-data d0 is written to the first storage position of the data memory B0; if there is still unwritten sub-data in the data memory B0, for example, there is other sub-data in the first storage position of the data memory B0, the sub-data d0 is written to the second storage position of the data memory B0.

[0078] For example, in each clock cycle, a data memory may be selected according to the polling scheduling strategy based on the polling order of the data memories B0 and B1. After the data memory is selected, the sub-data may be stored according to the storage order of the read addresses in the selected data memory.

[0079] For example, the data processing unit can obtain sub-data from the recorded data storage device according to the recorded information. Each time the sub-data is obtained from the data storage device, the sub-data stored in the first storage position can be selected. After reading the sub-data in the first storage position, the sub-data in other storage positions can be moved forward uniformly.

[0080] For example, in step S232, based on the record information, sub-data corresponding to the read request are read out from N groups of data storage devices to obtain N groups of sub-data, which may include: when the number of addresses included in each group of N groups of read addresses is not greater than the number of memories included in a corresponding group of address memories, based on the record information, sub-data corresponding to the read request are simultaneously read out from N groups of data storage devices to obtain N groups of sub-data.

[0081] For example, when the number of addresses included in each of the N groups of read addresses is not greater than the number of memories included in the corresponding group of address memories, the N groups of read addresses can be written into the address memories in parallel, and the recording unit records which address memory each read address is stored in. After reading out the sub-data corresponding to each read address from the N storage units, the sub-data can be stored in the corresponding data memory, so the multiple sub-data corresponding to the multiple read addresses stored in parallel can also be stored in the same storage position of the multiple data memories. Since there is a corresponding relationship between the address memory and the data memory, it can be determined according to the recording information that the sub-data corresponding to the read request is stored in which data memories, based on which, the multiple sub-data corresponding to the read request can be read out from these data memories at one time at the same time.

[0082] For example, read addresses r0, r1, r2, r3 and r4 are written in parallel to address memories A0, A1, A2, A4 and A6, and this information can be recorded in the recording unit. The sub-data d0, d1, d2, d3 and d4 corresponding to the read addresses r0, r1, r2, r3 and r4 are written into data memories B0, B1, B2, B4 and B6 respectively. According to the information recorded by the recording unit, the data processing unit can select the data memories B0, B1, B2, B4 and B6 through the second selector (MUX), and read the sub-data in these data memories at the same time, so as to obtain all the sub-data corresponding to the read request. After reading these sub-data, the data processing unit can merge these sub-data to obtain the target data. Based on this method, the read sub-data can be stored in the expected data memory, and by recording information, all the sub-data of the read request can be read out from these expected data memories at the same time, thereby improving the processing efficiency.

[0083] For example, in some other embodiments, in step S220, when the number of addresses in the first group of read addresses is greater than the number of memories in the first group of address memories corresponding to the first storage unit, the first group of read addresses is written into the first group of read addresses in multiple times. In step S232, when there is at least one group of read addresses in the N groups of read addresses that includes a number of addresses greater than the number of memories in the corresponding group of address memories, the sub-data corresponding to the read request is read out from the N groups of data memories in multiple times. In step S240, the sub-data read out from the N groups of data memories each time are stored in the merge memory until the sub-data corresponding to the read request are all stored in the merge memory, and the sub-data in the merge memory are merged to obtain the target data corresponding to the read request.

[0084] Figure 5A and 5B Another schematic diagram of a data reading process provided by at least one embodiment of the present disclosure is shown.

[0085] like Figure 5A and 5BAs shown, taking bank group 0 as an example, bank group 0 corresponds to two address memories A0 and A1, and there are more than two read addresses corresponding to bank group 0 in the read request, for example, in addition to read addresses r0 and r1, there are also read addresses r5 and r6 corresponding to bank group 0. In this case, the read addresses r0, r1, r5 and r6 can be written into the address memories A0 and A1 twice. For example, in one clock cycle, the read addresses r0 and r1 are first written into the address memories A0 and A1 in parallel, and the read addresses r2, r3 and r4 are written into the address memories A2, A4 and A6 respectively, and in the next clock cycle, the read addresses r5 and r6 are written into the address memories A0 and A1 in parallel. In the data reading stage, in a certain clock cycle, sub-data d0, d1, d2, d3 and d4 are stored in data storages B0, B1, B2, B4 and B6 respectively, and the data processing unit can read out these sub-data according to the record information, and store these sub-data in the merge memory in the data processing unit. After two clock cycles, for example, the sub-data d0 and d1 corresponding to the read addresses r5 and r6 are stored in the data storages B0 and B1 respectively, and the data processing unit can read out the sub-data d0 and d1 according to the record information, and store the sub-data d0 and d1 in the merge memory. After receiving all the sub-data corresponding to the read request, the merge memory can merge these sub-data to obtain the target data. Based on this method, when the number of read addresses corresponding to a storage unit is greater than the number of corresponding address memories, the sub-data can be read and merged simply and efficiently using the record information and N groups of data memories.

[0086] For example, in other embodiments, when the number of addresses of the first group of read addresses is greater than the number of memories of the first group of address memories corresponding to the first storage unit, in addition to the above-mentioned writing of the first group of read addresses into the address memory in multiple times, and reading the data in multiple times and merging based on the record information, other processing methods can also be used. For example, if the number of addresses of the first group of read addresses is greater than the number of memories of the first group of address memories corresponding to the first storage unit, multiple read addresses in the first group of read addresses can be reallocated, and the extra read addresses can be reallocated to other storage units, so that multiple read addresses can be written in parallel to the address memory. For example, the first group of address memories corresponding to the first storage unit includes 2 address memories, and the first group of read addresses includes 3 read addresses, and 2 of the read addresses can be written in parallel to the 2 address memories, and the other read address can be reallocated to other idle storage units (storage units with idle address memories in the current cycle). For example, when setting the number of address memories corresponding to each storage unit, the number of read addresses that each storage unit usually corresponds to within a cycle will be considered. Therefore, under normal circumstances, the number of address memories corresponding to each storage unit can meet the storage requirements of the corresponding read addresses. When the number of read addresses is greater than the number of address memories, it can be processed in batches or reallocated, so that the data reading method of the embodiment of the present application can cope with a variety of situations.

[0087] Figure 6 A schematic block diagram of a data reading device 600 provided by at least one embodiment of the present disclosure is shown.

[0088] For example, Figure 6 As shown, the data reading device 600 includes an address processing unit 610, M groups of address memories 620, M reading units 630 and a data processing unit 640. These components are interconnected via a bus system and / or other forms of connection mechanisms (not shown). For example, these modules / units / devices can be implemented by hardware (e.g., circuit) modules, software modules, or any combination of the two. The following embodiments are the same and will not be repeated. For example, these units can be implemented by a processing unit with data processing capabilities and / or instruction execution capabilities and corresponding computer instructions. It should be noted that Figure 6 The components and structures of the data reading device 600 shown are merely exemplary and non-limiting. The data reading device 600 may also have other components and structures as required.

[0089] The M groups of address memories 620 correspond to the M storage units respectively, and each group of address memories includes at least two address memories.

[0090] The address processing unit 610 is connected to the M group address memory 620, and the address processing unit 610 is configured to: receive a read request, wherein the read request includes N groups of read addresses corresponding to N storage cells among the M storage cells, respectively, wherein each group of the N groups of read addresses includes one or more read addresses; write the N groups of read addresses into the N groups of address memories corresponding to the N storage cells, respectively, wherein the N groups of read addresses include a first group of read addresses corresponding to a first storage cell among the N storage cells, and when the first group of read addresses includes at least two read addresses and the number of addresses of the first group of read addresses is not greater than the number of memories of the first group of address memories corresponding to the first storage cell, the first group of read addresses are written in parallel into the first group of address memories.

[0091] The M read units 630 correspond to the M storage units respectively, and the M read units are configured to read out sub-data corresponding to the read addresses in the N groups of address memories from the N storage units to obtain N groups of sub-data corresponding to the N groups of read addresses respectively.

[0092] The data processing unit 640 is configured to merge the N groups of sub-data to obtain target data corresponding to the read request, and transmit the target data to the target device through the data transmission unit.

[0093] For example, the M group address memory 620 can refer to Figure 3 or Figure 5A The address processing unit 610 can refer to Figure 3 or Figure 5A The M read units 630 may include Figure 3 or Figure 5A The arbiter arb connected to the address memory shown in the figure can select an address memory from at least two connected address memories, and then the reading unit can read the sub-data corresponding to the read address in the selected address memory from the storage unit. The data processing unit 640 can refer to Figure 3 or Figure 5A The data processing unit shown.

[0094] For example, the M read units include a first read unit corresponding to the first storage unit, and the first read unit is further configured to: in each clock cycle, based on the arbitration rule, select an address memory from the first group of address memories; read out the sub-data corresponding to the read address in the selected address memory from the first storage unit.

[0095] For example, the data reading device further comprises a recording unit, see Figure 3 or Figure 5AThe recording unit shown is configured to record the correspondence between each read address in the read request and N groups of address memories to form recording information.

[0096] For example, the data reading device further includes M groups of data storage devices and a transmission unit, wherein the M groups of data storage devices correspond to the M storage units respectively, each group of data storage devices includes at least two data storage devices, and the transmission unit is connected between the M groups of data storage devices and the data processing unit. The M groups of data storage devices can be referred to as Figure 3 or Figure 5A The multiple groups of data storage shown, the transmission unit can refer to Figure 3 or Figure 5A A data selector (MUX) is shown connected to multiple groups of data memories.

[0097] For example, the M reading units 630 may also include Figure 3 or Figure 5A As shown in the arbiter arb connected to the data storage, each reading unit can be further configured as follows: each time a sub-data corresponding to a read address is read out from the corresponding storage unit, a data storage is selected from a corresponding group of data storages, and the read sub-data is written into the selected data storage.

[0098] For example, the transmission unit is configured to read out sub-data corresponding to the read request from the N groups of data storages based on the record information, and send the sub-data to the data processing unit.

[0099] For example, the above-mentioned units / modules / devices may be hardware, software, firmware, and any feasible combination thereof. For example, the above-mentioned units / modules / devices may be dedicated or general-purpose circuits, chips, or devices, etc., or may be a combination of a processor and a memory. The embodiments of the present disclosure do not limit the specific implementation forms of the above-mentioned units.

[0100] For example, the above-mentioned unit / module / device may include codes and programs stored in a memory; the processor may execute the codes and programs to implement some or all functions of the above-mentioned unit / module / device. For example, the above-mentioned unit / module / device may be a dedicated hardware device used to implement some or all functions of the above-mentioned unit / module / device. For example, the above-mentioned unit / module / device may be a circuit board or a combination of multiple circuit boards used to implement the above-mentioned functions. In an embodiment of the present disclosure, the one circuit board or the combination of multiple circuit boards may include: (1) one or more processors; (2) one or more non-temporary memories connected to the processor; and (3) firmware stored in the memory that can be executed by the processor.

[0101] It should be noted that in the embodiment of the present disclosure, each unit of the data reading device 600 corresponds to each step of the aforementioned data reading method. For the specific functions of the data reading device 600, reference can be made to the relevant description of the data reading method, which will not be repeated here. Figure 7 The components and structures of the data reading device 600 shown are only exemplary and non-restrictive. The data reading device 600 may also include other components and structures as needed. The data reading device 600 may include more or fewer circuits or units, and the connection relationship between the various circuits or units is not limited and can be determined according to actual needs. The specific configuration of each circuit or unit is not limited and can be composed of analog devices according to circuit principles, or can be composed of digital chips, or can be composed in other applicable ways.

[0102] At least one embodiment of the present disclosure further provides an electronic device, the electronic device comprising a processor and a memory, wherein the memory stores one or more computer program modules. The one or more computer program modules are configured to be executed by the processor to implement the above-mentioned data reading method.

[0103] Figure 7 A schematic block diagram of an electronic device provided in some embodiments of the present disclosure. Figure 7 As shown, the electronic device 700 includes a processor 710 and a memory 720. The memory 720 stores non-temporary computer-readable instructions (e.g., one or more computer program modules). The processor 710 is used to run non-temporary computer-readable instructions, and the non-temporary computer-readable instructions are executed by the processor 710 to execute one or more steps in the data reading method described above. The memory 720 and the processor 710 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown). For the specific implementation of each step of the data reading method and the related explanation content, please refer to the embodiment of the above-mentioned data reading method, and the repetitions will not be repeated here.

[0104] It should be noted that Figure 7 The components of the electronic device 700 shown are merely exemplary and non-limiting. The electronic device 700 may also have other components according to actual application requirements.

[0105] For example, the processor 710 and the memory 720 may communicate with each other directly or indirectly.

[0106] For example, the processor 710 and the memory 720 may communicate via a network. The network may include a wireless network, a wired network, and / or any combination of a wireless network and a wired network. The processor 710 and the memory 720 may also communicate with each other via a system bus, which is not limited in the present disclosure.

[0107] For example, the processor 710 and the memory 720 may be arranged on a server side (or a cloud side).

[0108] For example, the processor 710 can control other components in the electronic device 700 to perform desired functions. For example, the processor 710 can be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units with data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) can be an X86 or ARM architecture, etc. The processor 710 can be a general-purpose processor or a special-purpose processor, and can control other components in the electronic device 700 to perform desired functions.

[0109] For example, the memory 720 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and the processor 710 may run one or more computer program modules to implement various functions of the electronic device 700. Various applications and various data, as well as various data used and / or generated by the application, etc. may also be stored in the computer-readable storage medium.

[0110] It should be noted that, in the embodiment of the present disclosure, the specific functions and technical effects of the electronic device 700 can refer to the above description of the data reading method, which will not be repeated here.

[0111] Figure 8 This is a schematic block diagram of another electronic device provided in some embodiments of the present disclosure. The electronic device 800 is suitable for implementing the data reading method provided in the embodiments of the present disclosure. The electronic device 800 may be a terminal device, etc. It should be noted that: Figure 8 The electronic device 800 shown is merely an example and does not impose any limitation on the functions and scope of use of the embodiments of the present disclosure.

[0112] like Figure 8As shown, the electronic device 800 may include a processing device (e.g., a central processing unit, a graphics processor, etc.) 810, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 820 or a program loaded from a storage device 880 to a random access memory (RAM) 830. In the RAM 830, various programs and data required for the operation of the electronic device 800 are also stored. The processing device 810, the ROM 820, and the RAM 830 are connected to each other via a bus 840. An input / output (I / O) interface 850 is also connected to the bus 840.

[0113] Typically, the following devices may be connected to the I / O interface 850: an input device 860 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 870 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 880 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 890. The communication device 890 may allow the electronic device 800 to communicate with other electronic devices wirelessly or by wire to exchange data. Although Figure 8 The electronic device 800 is shown to have various devices, but it should be understood that it is not required to implement or possess all of the devices shown, and the electronic device 800 may alternatively implement or possess more or fewer devices.

[0114] For example, according to an embodiment of the present disclosure, the above-mentioned data reading method can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes a program code for executing the above-mentioned data reading method. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device 890, or installed from a storage device 880, or installed from a ROM 820. When the computer program is executed by the processing device 810, the functions defined in the data reading method provided in the embodiment of the present disclosure can be implemented.

[0115] At least one embodiment of the present disclosure further provides a computer-readable storage medium, which stores non-transitory computer-readable instructions. When the non-transitory computer-readable instructions are executed by a computer, the above-mentioned data reading method can be implemented.

[0116] Fig. 9 A schematic diagram of a storage medium provided in some embodiments of the present disclosure. Fig. 9 As shown, the storage medium 900 stores non-transitory computer-readable instructions 910. For example, when the non-transitory computer-readable instructions 910 are executed by a computer, one or more steps in the data reading method described above are performed.

[0117] For example, the storage medium 900 may be applied to the electronic device 700. Figure 7 The memory 720 in the electronic device 700 is shown. For example, the description of the storage medium 900 can refer to Figure 7 The corresponding description of the memory 720 in the electronic device 700 is shown and will not be repeated here.

[0118] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present disclosure is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other to form a technical solution.

[0119] In addition, although each operation is described in a specific order, this should not be understood as requiring these operations to be performed in the specific order shown or in a sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments individually or in any suitable sub-combination mode.

[0120] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.

[0121] There are a few points to note about this disclosure:

[0122] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to the general design.

[0123] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0124] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A data reading method for reading data in M ​​storage units, each of which corresponds to a group of address memories, each group of address memories including at least two address memories, wherein: The method comprises: Receiving a read request, wherein the read request includes N groups of read addresses corresponding to N storage units in the M storage units, respectively, wherein each group of the N groups of read addresses includes one or more read addresses; writing the N groups of read addresses into N groups of address memories corresponding to the N storage units respectively, wherein the N groups of read addresses include a first group of read addresses corresponding to a first storage unit among the N storage units, and in a case where the first group of read addresses includes at least two read addresses and the number of addresses of the first group of read addresses is not greater than the number of memories of the first group of address memories corresponding to the first storage unit, the first group of read addresses are written into the first group of address memories in parallel; Reading out sub-data corresponding to the read addresses in the N groups of address memories from the N storage units to obtain N groups of sub-data corresponding to the N groups of read addresses respectively; Merging the N groups of sub-data to obtain target data corresponding to the read request, and transmitting the target data to a target device through a data transmission device; Wherein, M is an integer greater than 1, and N is an integer greater than or equal to 1 and less than M.

2. The data reading method according to claim 1, wherein: The first group of read addresses includes k read addresses, where k is an integer greater than or equal to 2; Writing the N groups of read addresses into N groups of address memories corresponding to the N storage units respectively includes: When the number of memories in the first group of address memories is greater than or equal to k, the k read addresses are written in parallel into the k address memories in the first group of address memories.

3. The data reading method according to claim 1, wherein: Writing the N groups of read addresses into N groups of address memories corresponding to the N storage units respectively includes: In a case where the number of addresses included in each group of the N groups of read addresses is not greater than the number of memories included in a corresponding group of address memories, the N groups of read addresses are written into the N groups of address memories in parallel.

4. The data reading method according to claim 1, wherein: Reading out sub-data corresponding to the read addresses in the N groups of address memories from the N storage units to obtain N groups of sub-data respectively corresponding to the N groups of read addresses includes: In each clock cycle, based on an arbitration rule, selecting an address memory from the first group of address memories; The sub-data corresponding to the read address in the selected address memory is read out from the first storage unit.

5. The data reading method according to claim 4, wherein: Each of the address memories comprises a plurality of storage locations, and a width of each storage location in the plurality of storage locations corresponds to a data bit width of one of the read addresses; Wherein, in each clock cycle, based on the arbitration rule, selecting an address memory from the first group of address memories comprises: selecting one of the at least two address memories based on the polling order of at least two address memories in the first group of address memories; Among them, reading out the sub-data corresponding to the read address in the selected address memory from the first storage unit includes: reading out the sub-data corresponding to the first read address in the selected address memory from the first storage unit.

6. The data reading method according to any one of claims 1 to 5, further comprising: The correspondence between each read address in the read request and the N groups of address memories is recorded to form record information.

7. The data reading method according to claim 6, wherein: Each of the storage units corresponds to a group of data storages, each group of data storages includes at least two data storages, and a group of address storages and a group of data storages of each of the storage units correspond to each other; Wherein, reading out the sub-data corresponding to the read addresses in the N groups of address memories from the N storage units to obtain N groups of sub-data respectively corresponding to the N groups of read addresses includes: For each of the storage units, after reading out a sub-data corresponding to a read address each time, a data storage is selected from a corresponding group of data storages, and the read sub-data is written into the selected data storage; Based on the record information, sub-data corresponding to the read request are read out from the N groups of data storage devices to obtain the N groups of sub-data.

8. The data reading method according to claim 7, wherein: Based on the record information, reading out the sub-data corresponding to the read request from the N groups of data storage to obtain the N groups of sub-data includes: When the number of addresses included in each of the N groups of read addresses is not greater than the number of memories included in a corresponding group of address memories, based on the record information, sub-data corresponding to the read request are simultaneously read out from the N groups of data memories to obtain the N groups of sub-data.

9. The data reading method according to claim 7, wherein: Writing the N groups of read addresses into N groups of address memories corresponding to the N storage units respectively includes: When the number of addresses of the first group of read addresses is greater than the number of memories of the first group of address memories corresponding to the first storage unit, writing the first group of read addresses into the first group of read addresses in multiple times; Wherein, based on the record information, reading out the sub-data corresponding to the read request from the N groups of data storage devices includes: In the case that at least one of the N groups of read addresses includes a larger number of addresses than a corresponding group of address memories, reading out sub-data corresponding to the read request from the N groups of data memories in multiple times; The step of merging the N groups of sub-data to obtain target data corresponding to the read request includes: The sub-data read out from the N groups of data storage devices each time are stored in a merge memory until all the sub-data corresponding to the read request are stored in the merge memory, and the sub-data in the merge memory are merged to obtain target data corresponding to the read request.

10. A data reading device, comprising: M groups of address memories corresponding to the M storage units, each group of address memories including at least two address memories; An address processing unit connected to the M groups of address memories; M read units, corresponding to the M storage units; and Data processing unit; Wherein, the address processing unit is configured as follows: Receiving a read request, wherein the read request includes N groups of read addresses corresponding to N storage units in the M storage units, respectively, wherein each group of the N groups of read addresses includes one or more read addresses; writing the N groups of read addresses into N groups of address memories corresponding to the N storage units respectively, wherein the N groups of read addresses include a first group of read addresses corresponding to a first storage unit among the N storage units, and in a case where the first group of read addresses includes at least two read addresses and the number of addresses of the first group of read addresses is not greater than the number of memories of the first group of address memories corresponding to the first storage unit, the first group of read addresses are written into the first group of address memories in parallel; The M reading units are configured to read out sub-data corresponding to the read addresses in the N groups of address memories from the N storage units to obtain N groups of sub-data corresponding to the N groups of read addresses respectively; The data processing unit is configured to merge the N groups of sub-data to obtain target data corresponding to the read request, and transmit the target data to the target device through the data transmission unit.

11. The data reading device according to claim 10, wherein: The M reading units include a first reading unit corresponding to the first storage unit, The first reading unit is further configured as: In each clock cycle, based on an arbitration rule, selecting an address memory from the first group of address memories; The sub-data corresponding to the read address in the selected address memory is read out from the first storage unit.

12. The data reading device according to claim 10, further comprising: The recording unit is configured to record the corresponding relationship between each read address in the read request and the N groups of address memories to form recording information.

13. The data reading device according to claim 12, further comprising: M groups of data storage devices, corresponding to the M storage units, each group of data storage devices including at least two data storage devices; as well as A transmission unit connected between the M groups of data storage devices and the data processing unit; Each of the reading units is further configured to: after reading a sub-data corresponding to a read address from the corresponding storage unit each time, select a data storage from a corresponding group of data storages, and write the read sub-data into the selected data storage; The transmission unit is configured to read out the sub-data corresponding to the read request from the N groups of data storage devices based on the record information, and send the sub-data to the data processing unit.

14. An electronic device comprising: processor; a memory storing one or more computer program modules; The one or more computer program modules are configured to be executed by the processor to implement the data reading method according to any one of claims 1 to 9.

15. A computer-readable storage medium storing non-transitory computer-readable instructions, which, when executed by a computer, can implement the data reading method according to any one of claims 1 to 9.

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