An implementation method for an approximate multiplier for neural networks and the approximate multiplier itself.

Abstract

This invention discloses an approximate multiplier implementation method and an approximate multiplier for neural networks. The key technical points include: inputting a first operand and a second operand; splitting the first operand into a low-order part and a high-order part; performing a first encoding on the low-order part to obtain multiple sets of first-coded numbers, and performing a second encoding on the high-order part to obtain multiple sets of second-coded numbers; assembling the multiple sets of first-coded numbers and the multiple sets of second-coded numbers to form an assembled operand; generating a partial product matrix and a truncation error compensation value for the corresponding partial product matrix based on the assembled operand and the second operand; and generating an approximate multiplication result of the first operand and the second operand based on the partial product matrix and the truncation error compensation value. This invention combines approximate high-radix encoding with truncation compensation, significantly improving the performance of the approximate multiplier while ensuring computational accuracy and final network inference accuracy.

Description

Technical Field

[0001] This invention relates to the field of approximate multiplication calculation technology, and more specifically to an approximate multiplier implementation method and an approximate multiplier for neural networks. Background Technology

[0002] The high computational demands of neural networks pose a significant performance bottleneck and critical power consumption issue for embedded systems. The core of the inference process in neural networks is the MAC (multiply-accumulate) operation; advanced neural networks integrate thousands of MACs, resulting in enormous energy consumption. However, neural networks also possess strong fault tolerance, allowing for approximate calculations to reduce energy consumption.

[0003] Most existing approximate multipliers are based on ASIC design. For example, Chinese invention patent CN111488133B provides a high-performance approximate Booth multiplier and calculation method, which significantly improves accuracy while reducing the power consumption and area overhead of the approximate Booth multiplier.

[0004] However, compared with FPGA-based computing units, ASIC design is based on logic gate level, while FPGA design is based on lookup table 6-LUT and carry chain. Since the internal logic resources of FPGA are not considered during the design, the performance of common ASIC-based multipliers is greatly reduced when applied to FPGA. Therefore, the existing technology has shortcomings. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide an approximate multiplier implementation method and an approximate multiplier for neural networks. By designing the approximate multiplier using an FPGA architecture and combining approximate high-radix encoding and truncation compensation, the performance of the approximate multiplier is significantly improved without affecting inference accuracy.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] This invention provides a method for implementing an approximate multiplier for neural networks, comprising:

[0008] Input the first operand and the second operand, and split the first operand into a low-order part and a high-order part;

[0009] The lower-order part is first encoded to obtain multiple sets of first-coded numbers, and the higher-order part is second encoded to obtain multiple sets of second-coded numbers;

[0010] The plurality of first code numbers and the plurality of second code numbers are assembled to form an assembly operand;

[0011] Based on the assembly operand and the second operand, a partial product matrix and a truncation error compensation value corresponding to the partial product matrix are generated;

[0012] Based on the partial product matrix and the truncation error compensation value, an approximate multiplication result of the first operand and the second operand is generated.

[0013] As a further improvement of the present invention, the step of splitting the first operand into a low-order part and a high-order part includes splitting the first operand into a low-order part and a high-order part according to a preset weight, wherein the low-order part is the part with a lower weight and the high-order part is the part with a higher weight.

[0014] As a further improvement of the present invention, the high-radix approximate Booth coding is radix-8 approximate Booth coding, the low-radix Booth coding is radix-4 Booth coding, and the radix-8 approximate Booth coding is such that the odd-number multiple operation in the radix-8 Booth coding is approximated as the even-number multiple operation, and the approximation error is positive.

[0015] As a further improvement of the present invention, generating a partial product matrix based on the assembly operand and the second operand includes:

[0016] By grouping two digits together and taking a step of one digit, the second operand is traversed from the least significant digit to the most significant digit to obtain multiple groups of suboperands.

[0017] Following the order from least significant bit to most significant bit, each group of the first encoded number and each group of the second encoded number are input into the corresponding lookup table with each group of suboperands for logical operation to generate multiple partial product bits;

[0018] The partial product elements are arranged in the order of the lookup table to form the partial product matrix.

[0019] As a further improvement of the present invention, the step of generating the truncation error compensation value corresponding to the partial product matrix includes:

[0020] The lower-order part of the partial product matrix is ​​truncated to obtain an approximate partial product matrix and a truncated partial product matrix.

[0021] The truncation error compensation value is generated based on the truncated partial product matrix and the Karnaugh map.

[0022] As a further improvement of the present invention, the step of generating an approximate multiplication result of the first operand and the second operand based on the partial product matrix and the truncation error compensation value includes:

[0023] For two adjacent partial product positions in the partial product matrix, if the carry chain corresponding to the next partial product position receives the corresponding truncation error compensation value, then one of the output results of the previous partial product position and the corresponding carry chain is input to the carry chain corresponding to the next partial product position, and the truncation error compensation value is input to the carry chain corresponding to the next partial product position for addition logic operation to obtain the first carry output result of the carry chain corresponding to the next partial product position; otherwise, one of the output results of the previous partial product position and the corresponding carry chain is input to the carry chain corresponding to the next partial product position for addition logic operation to obtain the second carry output result of the carry chain corresponding to the next partial product position.

[0024] The last carry output of each column in the partial product matrix is ​​combined sequentially to obtain an approximate multiplication result of the first operand and the second operand.

[0025] This invention provides an approximate multiplier applied to the above-described implementation method. The approximate multiplier is composed of a lookup table and a carry chain arranged in a pipelined architecture.

[0026] The lookup table is used to generate partial product values;

[0027] The carry chain is used to implement the addition of the partial product with the corresponding previous partial product or carry output result.

[0028] The present invention provides an FPGA chip including the above-described approximate multiplier.

[0029] The present invention provides an FPGA system, including the above-mentioned FPGA chip.

[0030] This invention designs lookup tables and carry chains in FPGAs to pipeline the generation and accumulation of partial products. Compared to multiplier designs for ASICs, this significantly reduces the number of lookup tables required. Furthermore, by using approximate encoding to reduce the number of partial products, latency and the number of lookup tables are further reduced. Simultaneously, the low-weight bits in the partial product matrix are truncated, and Karnaugh maps are used for simplification. Error compensation values ​​are generated based on specific bits of the partial product matrix to compensate for truncation errors and ensure computational accuracy. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the method steps of the present invention;

[0032] Figure 2 This is a schematic diagram of the approximate multiplier structure of the present invention;

[0033] Figure 3 This refers to the grouping method of the first operand in this invention;

[0034] Figure 4 Karnaugh maps used to generate truncation compensation;

[0035] Figure 5 This is a schematic diagram of a 6-LUT structure;

[0036] Figure 6 This is a schematic diagram of the carry chain structure;

[0037] Figure 7 This is a schematic diagram of the internal logic of six types of LUTs. Detailed Implementation

[0038] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations thereof.

[0039] The term "and / or" in the following text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Additionally, the character " / " generally indicates that the preceding and following related objects have an "or" relationship. The terms "before," "after," "left," "right," "up," and "down" used in the following description refer to the directions in the accompanying diagram.

[0040] This application provides an approximate multiplier, which consists of a lookup table and a carry chain arranged in a pipelined architecture. The lookup table is used to generate partial products, and the carry chain is used to add the partial product to the corresponding previous partial product or carry output.

[0041] The approximate multiplier provided in this embodiment is based on the approximate multiplier for ASIC (Application-Specific Integrated Circuit) and incorporates the 6-LUT (Look-Up Table) and carry chain resources used in FPGA (Field-Programmable Gate Array). This addresses the performance degradation issue that occurs when ASIC-based designs are applied to FPGAs. It fully utilizes the 6-LUT, currently the most commonly used FPGA, to achieve approximate calculations, thereby reducing area and power consumption.

[0042] Most existing FPGA-based multiplier designs employ pipelined architectures, sacrificing some latency for smaller area, but do not combine classic approximation techniques such as approximate high-radix encoding and truncation compensation. This embodiment combines these two techniques during approximate multiplication, which can reduce the number of product rows through approximate high-radix encoding and sacrifice some accuracy for lower latency through truncation error compensation, while ensuring computational accuracy and final network inference accuracy. This significantly improves the performance of the approximate multiplier.

[0043] The following section further explains the method and steps for implementing approximate multiplication using the aforementioned approximate multiplier.

[0044] like Figure 1 As shown, this application provides a method for implementing an approximate multiplier for a neural network, characterized by comprising:

[0045] Input the first operand and the second operand, and split the first operand into the low-order part and the high-order part;

[0046] The lower-order part is first encoded to obtain multiple sets of first-coded numbers, and the higher-order part is second encoded to obtain multiple sets of second-coded numbers;

[0047] Multiple sets of first-coded numbers and multiple sets of second-coded numbers are assembled to form an assembly operand;

[0048] Based on the assembly operand and the second operand, generate the partial product matrix and the corresponding truncation error compensation value of the partial product matrix;

[0049] Based on the partial product matrix and the truncation error compensation value, an approximate multiplication result of the first operand and the second operand is generated.

[0050] Specifically, splitting the first operand into a low-order part and a high-order part includes splitting the first operand into a low-order part and a high-order part according to a preset weight, wherein the low-order part is the part with a lower weight and the high-order part is the part with a higher weight.

[0051] The first encoding is a high-radix approximate Booth code, and the second encoding is a low-radix Booth code.

[0052] The method provided in this embodiment is suitable for fault-tolerant high-digit multiplication. By using high-radix approximate Booth coding, it can reduce the number of partial product rows, thereby improving the performance of the multiplier.

[0053] Specifically, high-radix approximate Booth coding is radix-8 approximate Booth coding, low-radix Booth coding is radix-4 Booth coding, and radix-8 approximate Booth coding is used to approximate the odd-multiplication operation in radix-8 Booth coding as the even-multiplication operation, with the approximation error being positive.

[0054] In traditional radix-8 Buss coding, generating each partial product bit requires 4 bits of the multiplier and 3 bits of the multiplicand, which exceeds the input limit of a 6-LUT, resulting in the generation of each partial product requiring two 6-LUTs.

[0055] The approximate encoding method provided in this embodiment is designed for the 6-LUT's 6-input, 1-output characteristics. It can implement the radix-8 approximate Booth encoding algorithm using only 3 bits of the multiplier and 2 bits of the multiplicand. It reduces the number of partial product rows by using high radix approximate Booth encoding and limits the number of input bits required to generate one partial product to the input range of the 6-LUT by using an appropriate encoding method. This allows the generation of each partial product and its accumulation with the result bits of the previous row to still be achieved by a single 6-LUT after approximate high radix encoding. This minimizes the size of the partial product matrix, thereby reducing the number of LUTs and carry chains after synthesis.

[0056] Furthermore, this embodiment provides a step for generating a partial product matrix, including:

[0057] Divide the two digits into a group, and traverse the second operand from the least significant digit to the most significant digit, using one digit as the step size, to obtain multiple groups of suboperands;

[0058] Following the order from least significant bit to most significant bit, each group of first coded numbers and each group of second coded numbers are input into the corresponding lookup table along with each group of suboperands for logical operations to generate multiple partial product bits;

[0059] Arrange the multiple partial product bits in the order of the lookup table to form a partial product matrix.

[0060] Furthermore, this embodiment provides a step for generating a truncation error compensation value for the corresponding partial product matrix, including:

[0061] The lower-order part of the partial product matrix is ​​truncated to obtain the approximate partial product matrix and the truncated partial product matrix.

[0062] The truncation error compensation value is generated based on the truncated partial product matrix and Karnaugh map.

[0063] This embodiment generates a truncation error compensation value by simplifying the Karnaugh map and inputs it into the carry chain to participate in the subsequent partial accumulation process. This compensates for the error caused by truncation to a certain extent, further reduces the number of LUTs, and offsets the latency increase brought about by the pipeline architecture.

[0064] Furthermore, this embodiment provides a step for generating an approximate multiplication result of the first operand and the second operand based on the partial product matrix and the truncation error compensation value, including:

[0065] For two adjacent partial product units in a partial product matrix, if the carry-in chain of the next relative partial product unit receives the corresponding truncation error compensation value, then one of the outputs of the previous relative partial product unit and its corresponding carry-in chain is input into the carry-in chain of the next relative partial product unit, and the truncation error compensation value is input into the carry-in chain of the next relative partial product unit for addition logic operation, to obtain the first carry-in output result of the carry-in chain of the next relative partial product unit; otherwise, one of the outputs of the previous relative partial product unit and its corresponding carry-in chain is input into the carry-in chain of the next relative partial product unit for addition logic operation, to obtain the second carry-in output result of the carry-in chain of the next relative partial product unit.

[0066] By sequentially combining the last carry output of each column in the partial product matrix, we obtain an approximate multiplication result of the first and second operands.

[0067] For example, such as Figure 2 As shown, the above implementation method is illustrated using a 16×16 approximate multiplier structure as an example. To reduce the number of LUTs required for the multiplier unit, a pipelined structure is adopted. The generation of the partial product of each row and its addition with the result of the previous row are integrated into a one-bit LUT and a one-bit carry chain. The boxes marked with letters represent LUTs, CC represents the carry chain, and the bottom row pp i These represent the individual digits of the calculation result.

[0068] For 16-bit signed number multiplication, the bits with lower weights in the multiplier are first encoded using radix-8 approximate Booth encoding, while the bits with higher weights are encoded using radix-4 Booth encoding. The specific multiplier encoding grouping method is as follows: Figure 3 As shown, after padding the least significant bit with 0, the lower bits are grouped into four groups of four, resulting in four groups of radix-8 encoding (i.e., four groups of first encoding numbers). The higher bits are grouped into three groups of three, resulting in two groups of radix-4 encoding (i.e., two groups of second encoding numbers). In the partial product matrix, the first four rows of partial products corresponding to the lower bits of the multiplier are obtained by radix-8 approximate Booth encoding, while the last two rows of partial products corresponding to the higher bits of the multiplier are obtained by radix-4 Booth encoding. Radix-8 approximate Booth encoding reduces the number of rows of partial products from 8 to 6.

[0069] Table 1 shows the specific approximate encoding methods and their comparison with the exact encoding methods. The leftmost column is the four-bit multiplier being encoded, and the second, third, and fourth columns are the exact encoding result, the approximate encoding result, and the relative error value, respectively. It can be seen that in all the exact encodings, the operations ×1 and ×3 are approximated as ×2, ×4, or zeroing operations in the table. It is easy to see that 2A and 4A can be generated by shifting the multiplicand A to the left by one or two bits, respectively. The negative operation is achieved by inverting each bit and then adding one to the least significant bit of the partial product. Therefore, the logic for generating the partial product is relatively simple. Furthermore, it can be observed from Table 1 that the encoded partial product value is only related to the three highest bits of the encoded bits and is independent of the least significant bit. At the same time, the value of each bit can only be the corresponding bit of the multiplicand shifted to the left by one bit, shifted to the left by two bits (and inverted), or 0.

[0070] Table 1

[0071]

[0072] Therefore, for the LUT corresponding to the m-th bit of the partial product, where m = 1, ..., 16, the only required input bits are the multiplicand shifted left by one bit, A. m-1 And left shift two A's m-2 And the three B's of each group of multipliers n B n+1 and B n+2 , where n is the number of groups, n = 0, ..., 5, plus the partial product pp generated in the previous row. In this way, the input required for each LUT is limited to the range of 6 bits, ensuring that the generation of each partial product bit and its addition with the partial product of the previous row can be implemented by only one LUT, saving LUT resources.

[0073] Furthermore, considering the fault tolerance of neural networks, for the lower 12 columns with lower weights in the partial product matrix ( Figure 2 The solid and dashed bounding boxes are directly ignored, further reducing the amount of LUT used and offsetting the increased latency caused by the pipelined architecture; to partially compensate for the error caused by low-order truncation, the 8 partial products of columns 11 and 12 (such as...) are... Figure 2 The solid-lined portion is divided into two groups. Two compensation bits are generated using a Karnaugh map, which are then added to the carry input bits of the carry chains of the second and fourth row partial products, respectively. The Karnaugh map is shown below. Figure 4 As shown, for each group of four LUTs, I'1, I1, I'2, and I2 are the partial products generated by the LUTs in the 11th, 12th, 11th, and 12th columns of the top row, respectively.

[0074] The specific compensation generation method is as follows: for the four values ​​I'1, I1, I'2, and I2 in a set, when there is a high-order value (column 12) and a low-order value (column 11), or both high-order values ​​are 1, the compensation value is 1; otherwise, the compensation value is 0. In this way, the compensation value is approximately the value of columns 11 and 12 after considering the weights and adding them together. Since the calculation result is smaller after the low-order value is truncated, a positive error is introduced into the Karnaugh map of the compensation position, which also reduces the complexity of the Karnaugh map implementation logic.

[0075] Next, the calculation is performed using a 6-LUT and carry chain within the FPGA, where the structure of the 6-LUT is as follows: Figure 5 As shown, it can be configured as a 6-input 1-output or 5-input 2-output mode. Its internal logic is implemented using a lookup table. I0-I5 in the diagram represent the six inputs of the LUT. The carry chain structure is as follows... Figure 6 As shown, generally four bits are grouped together, including a one-bit carry input Cin, a four-bit selector input O5, a four-bit selection control input O6, four-bit outputs S0, S1, S2, S3, and a one-bit carry output Cout. When configuring the carry chain to implement addition logic, such as implementing x+y, O5 needs to input each bit of x (or y), and O6 needs to input the result of the bitwise XOR of x and y.

[0076] like Figure 7 These are six main LUT designs in approximate multipliers, with LUTA being the most commonly used. It has 6-bit input and 1-bit output. BE in the diagram is the encoded logic block, which is based on the three bits B of the multiplier b. n B n+1 and B n+2 The system controls the generation of a shift flag s, an invert flag c, and a zero flag z. These three flags, along with the two bits A of the multiplicand, are used to generate the shift flag s. m-1 A m-2 A partial product bit t is generated through selector logic. Then, through XOR logic, the bit result pp generated in the previous row is XORed with the newly generated partial product bit t to obtain a bit output cout. pp and cout are input to the O5 and O6 terminals of the carry chain respectively to add the result pp of the previous row to the partial product bit t generated in the current row.

[0077] LUTA2 is located at the highest bit of each row's partial product, summing the "1" from the previous row, the carry output pp from the previous row's carry chain, and the current partial product bit t. BE is similar to LUTA, being an encoded logic block, but because it's in the highest bit of each row, the input only contains the highest bit A of the multiplicand A. 15 Therefore, there is no shift flag s, and the three-digit multiplier B n B n+1 and B n+2The control encoding logic block obtains a partial product bit t, and the carry output pp from the previous row is added to "1". The result is ~pp and the carry is pp. Therefore, inside the LUT, pp is inverted and XORed with the generated partial product bit t. The result cout is input to the O6 end of the carry chain, and ~pp is input to the O5 end of the carry chain, realizing the addition of ~pp and t.

[0078] LUTB is used for the sign extension bit before the most significant bit of the partial product in each row, and the most significant bit A of the input multiplicand A is... 15 Three-digit multiplier B n B n+1 and B n+2 And the carry output pp from the previous line, SE is the sign extension bit generation logic, based on the input three-bit multiplier B. n B n+1 and B n+2 Decide whether to input A 15 Inverting the bit gives the inverted value of the highest bit of the partial product, s. Since the highest bit of the partial product on the right is added to "1", the resulting carry is the output pp of the carry chain of the previous row. Therefore, the sign extension bit also needs to be added to pp. The inverted value of the highest bit of the partial product, S, is XORed with the carry output pp of the carry chain of the previous row to get the result cout. This result is input to the O6 terminal of the carry chain of this row, and pp is input to the O5 terminal of the carry chain, thus realizing the addition of pp and s.

[0079] LUTA1 is located at the least significant bit of each row's partial product, generating the sign correction bit i and adding it to the result pp of the previous row, and adding the partial product bits t generated in this row. BE is the same as LUTA, serving as the encoded logic block used to generate the partial product bits t. The input includes the least significant bits A0 and 0 of the multiplicand, and the three bits B of the multiplier. n B n+1 and B n+2 The output includes the current bit pout and the carry cout, and no carry chain is needed below it. Since the partial product obtained after encoding may be the original partial product or the partial product shifted left by one bit, and for the rightmost LUT bit of each row, the partial product is shifted left by one bit, so the bit becomes 0. Therefore, the input in the multiplicand position is the least significant bit A0 and 0 of the multiplier. When the encoding result of the multiplier bit corresponding to this row is negative, the corresponding sign correction bit i is 1, otherwise it is zero. In order to achieve the addition of the three, the LUT internally implements the logical expressions pout=pp∧t∧i and cout=i&&(t∧pp)||(t&&pp).

[0080] LUTAF is applied in the first row and the stage error compensation section. Its function is to calculate the multiplier B based on the three digits B. n B n+1 and B n+2 and the two A's of the multiplicandm-1 A m-2 This yields a partial product cout and outputs it directly, effectively eliminating the need for the XOR operation between t and pp in LUTA.

[0081] LUTA2F is used to generate the sign extension bit ~s of the first row and add it to "1". The bit obtained by adding ~s to 1 is s, and the carry is ~s. However, it needs to be added to "1" through the carry chain in the next higher bit. Therefore, "1" can be XORed with ~s, i.e., s. Thus, the two results generated by LUTA2F are equal to the result after encoding the highest bit of the multiplicand. Aout is passed to the LUTA of the next row as input, and Bout is passed to the carry chain in the next higher bit as input.

[0082] In summary, this design is performed at the LUT level. For a LUT, a partial product bit is first generated based on the two bits of the multiplicand and the three bits of the multiplier through selector logic. Then, the bit result generated in the previous row is XORed with the newly generated partial product bit through XOR logic. The bit result of the previous row and the result of the XOR operation are input into the carry chain, thereby realizing simultaneous encoding and addition. This process is repeated row by row to obtain the final result of the multiplication operation.

[0083] To verify the hardware performance of the approximate multiplier, this invention utilizes Vivado 2018.3 for experimentation, employing an XC7K325TFBG FPGA. The designed multiplier was synthesized and implemented to obtain its area (represented by the number of LUTs), critical path delay, total power consumption, and dynamic power consumption. A comparison was then made with the Vivado multiplier IP, and the results are shown in Table 2. The data demonstrates that compared to the Vivado IP, this invention increases delay by 17%, but reduces area by 67% and dynamic power consumption by 34%, resulting in a significant improvement in overall performance.

[0084] Table 2

[0085]

[0086] To verify the software accuracy of the aforementioned approximate multiplier, this invention first uses C++ to test the mean relative error distance (MRED) and normalized mean error distance (NMED) of this invention for all possible input combinations within a 16-bit range. The specific calculation formulas are as follows:

[0087]

[0088] Where ED is the difference between the approximate calculation result and the exact calculation result, S is the exact calculation result, and N is the number of inputs, 2 2N The number of all possible input combinations is shown in Table 3.

[0089] Table 3

[0090]

[0091] The designed multiplier was then applied to neural network inference for handwritten digit recognition. This invention selected a small-scale neural network AlexNet and a large-scale network VGG16 for testing, recorded the probability of correct inference, and compared them with an accurate 16-bit input signed multiplier. The experimental results are shown in Table 4. The data shows that the inference result of applying this invention is not significantly lower than that of using an accurate multiplier.

[0092] Table 4

[0093]

[0094] The approximate multiplier implementation method for neural networks provided in this embodiment improves the performance of the approximate multiplier by combining approximate encoding and error compensation, while ensuring computational accuracy and final network inference accuracy.

[0095] Furthermore, embodiments of this application provide an FPGA chip including the aforementioned approximate multiplier.

[0096] Furthermore, embodiments of this application provide an FPGA system including the aforementioned FPGA chip.

[0097] This application provides an approximate multiplier implementation method and approximate multiplier for neural networks. Based on ASIC, it modifies the 6-LUT and carry chain resources used in FPGA to make the approximate multiplier suitable for the logic resources inside the FPGA. It solves the problem of performance degradation when ASIC-based designs are applied to FPGA. The approximation is achieved through three methods: pipelined architecture, radix-8 approximate Booth encoding, and low-bit truncation compensation, which saves logic resource consumption. It can effectively reduce the power consumption, area, and latency of the computing units in the neural network without significantly reducing accuracy, and has good practical application value.

[0098] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0099] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0100] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0101] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0102] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A method for implementing an approximate multiplier for a neural network, characterized in that, The approximate multiplier is composed of a lookup table and a carry chain arranged in a pipelined architecture. The implementation method of the approximate multiplier includes: Input the first operand and the second operand, and split the first operand into a low-order part and a high-order part; The lower-order part is first encoded to obtain multiple sets of first-coded numbers, and the higher-order part is second encoded to obtain multiple sets of second-coded numbers; The plurality of first code numbers and the plurality of second code numbers are assembled to form an assembly operand; Based on the assembly operand and the second operand, a partial product matrix and a truncation error compensation value corresponding to the partial product matrix are generated; Based on the partial product matrix and the truncation error compensation value, an approximate multiplication result of the first operand and the second operand is generated; The step of generating a partial product matrix based on the assembly operand and the second operand includes: Divide the two digits into a group, and traverse the second operand from the least significant digit to the most significant digit, using one digit as the step size, to obtain multiple groups of suboperands; Following the order from least significant bit to most significant bit, each group of the first encoded number and each group of the second encoded number are input into the corresponding lookup table with each group of suboperands for logical operation to generate multiple partial product bits; The plurality of partial product bits are arranged in the order of the lookup table to form the partial product matrix; The step of generating an approximate multiplication result of the first operand and the second operand based on the partial product matrix and the truncation error compensation value includes: For two adjacent partial product positions in the partial product matrix, if the carry chain corresponding to the next partial product position receives the corresponding truncation error compensation value, then one of the output results of the previous partial product position and the corresponding carry chain is input to the carry chain corresponding to the next partial product position, and the truncation error compensation value is input to the carry chain corresponding to the next partial product position for addition logic operation to obtain the first carry output result of the carry chain corresponding to the next partial product position; otherwise, one of the output results of the previous partial product position and the corresponding carry chain is input to the carry chain corresponding to the next partial product position for addition logic operation to obtain the second carry output result of the carry chain corresponding to the next partial product position. The last carry output of each column in the partial product matrix is ​​combined sequentially to obtain an approximate multiplication result of the first operand and the second operand.

2. The method for implementing an approximate multiplier for a neural network according to claim 1, characterized in that, The step of splitting the first operand into a low-order part and a high-order part includes splitting the first operand into a low-order part and a high-order part according to a preset weight, wherein the low-order part is the part with a lower weight and the high-order part is the part with a higher weight.

3. The method for implementing an approximate multiplier for a neural network according to claim 1, characterized in that, The first encoding is a high-radix approximate Booz code, and the second encoding is a low-radix Booz code.

4. The method for implementing an approximate multiplier for a neural network according to claim 3, characterized in that, The high-radix approximate Booth code is a radix-8 approximate Booth code, the low-radix Booth code is a radix-4 Booth code, and the radix-8 approximate Booth code is used to approximate the odd-multiplication operation in the radix-8 Booth code as the even-multiplication operation, and the approximation error is positive.

5. The method for implementing an approximate multiplier for a neural network according to claim 1, characterized in that, The step of generating the truncation error compensation value corresponding to the partial product matrix includes: The lower-order part of the partial product matrix is ​​truncated to obtain an approximate partial product matrix and a truncated partial product matrix. The truncation error compensation value is generated based on the truncated partial product matrix and the Karnaugh map.

6. An approximate multiplier, applied to the method as described in any one of claims 1-5, characterized in that, The approximate multiplier consists of a lookup table and a carry chain arranged in a pipelined architecture. The lookup table is used to generate partial product values; The carry chain is used to implement the addition of the partial product with the corresponding previous partial product or carry output result.

7. An FPGA chip, characterized in that, Including an approximate multiplier as described in claim 6.

8. An FPGA system, characterized in that, Including an FPGA chip as described in claim 7.

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