Assembly line type instruction execution method and device

Abstract

The embodiment of the invention provides a pipelined instruction execution method and device, in the pipelined instruction execution process, at least one to-be-executed instruction is pre-cached by setting an instruction cache unit, conflict detection is performed on the currently executed instruction and the pre-cached next instruction, and under the condition that a conflict condition is met, the instruction to be executed is executed by the instruction cache unit. According to the method, the next instruction is subjected to delay control, so that when the calculation result of the next instruction is output, the calculation result of the current instruction is output completely, and the cache resource conflict of the pipelined calculation instruction is effectively avoided.

Description

Technical Field

[0001] One or more embodiments of the present specification relate to the field of computer technology, and more particularly, to a pipelined instruction execution method and apparatus. Background Art

[0002] When using computers to process business, you will usually encounter multiple similar instructions that are executed serially. Here, similar instructions can be instructions for processing different data under the same computing type. For similar computing instructions, the same hardware computing resources on the computer or device can be used for computing.

[0003] For example, the fast number theoretic transform (NTT) is an important algorithm in the field of public key cryptography. It can be used to calculate the point value representation of polynomials on a ring to accelerate the multiplication of polynomials on a ring. The NTT algorithm may be involved in lattice-based post-quantum encryption algorithms, hash functions, digital signatures, and fully homomorphic encryption and zero-knowledge proofs in privacy computing technologies. The NTT algorithm can use hardware computing resources such as matrix computing cores and numerical computing cores (computing cores are usually integrated on GPUs, etc.) for calculations. After the NTT computing structure is determined, the corresponding hardware computing resources and cache resources can usually be determined and do not change with changes in real-time computing tasks.

[0004] In this way, a pipelined instruction execution process can be generated. That is, when there are enough computing resources available, the subsequent instructions can be received for execution. However, for different data, different instruction parameters will lead to different calculation pipeline depths between adjacent instructions. Changes in pipeline depth will lead to conflicts in the execution of adjacent instructions, such as computing resource conflicts and conflicts in on-chip data caches. Specifically, when the NTT specifications (number of points) in adjacent NTT calculation instructions are different, such as before the previous NTT calculation instruction is calculated, the subsequent NTT calculation instruction is calculated, resulting in a conflict in storage instructions.

[0005] Therefore, how to avoid computational conflicts between adjacent instructions is an important technical problem that needs to be solved in the pipeline instruction execution process. Summary of the invention

[0006] One or more embodiments of this specification describe a pipeline instruction execution method and device to solve one or more problems mentioned in the background technology.

[0007] According to a first aspect, a pipeline instruction execution device is provided, comprising:

[0008] An instruction cache unit, configured to cache at least one instruction to be executed, wherein the at least one instruction to be executed is obtained from the instruction queue;

[0009] A conflict determination unit, configured to determine whether adjacent instructions satisfy a predetermined conflict condition;

[0010] An instruction delay unit is configured to determine a delay time for a subsequent instruction that satisfies the predetermined conflict condition and perform delayed execution control, wherein the delay time makes the calculation result of the subsequent instruction be output no earlier than the calculation result of the previous instruction is fully output;

[0011] A real-time computing unit, wherein the unit computing module is configured to perform pipeline computing operations on the instructions;

[0012] A result output enabling unit, configured to enable output of a calculation result obtained by a calculation module of a calculation unit of the real-time calculation unit;

[0013] The result cache unit is configured to cache the calculation result.

[0014] In one embodiment, the pipelined instructions are vector transformation instructions in different domains, a single instruction contains multiple vectors with consistent dimensions, and the predetermined conflict condition is: the dimension of a single vector in the latter instruction is smaller than the dimension of a single vector in the previous instruction.

[0015] In one embodiment, the transformation includes one of the following transformations or its inverse transformation: discrete Fourier transform DFT, fast Fourier transform FFT, number theoretic transform NTT, discrete cosine transform DCT, discrete sine transform DST, discrete wavelet transform DWT.

[0016] In a further embodiment, the number of instructions cached in the instruction cache unit is determined by dividing the maximum vector dimension in each transformation instruction of the current business by the minimum number of vectors contained in a single instruction.

[0017] In one embodiment, the delay length of the subsequent instruction is calculated from the start time of execution of the previous instruction, which is: the difference in the calculation pipeline delay of a single vector of the previous instruction and the subsequent instruction, plus the sum of the output pipeline delays corresponding to each vector in the previous instruction. The pipeline delay of a single vector is determined by the number of butterfly computing units it contains.

[0018] In one embodiment, the real-time computing unit includes a plurality of unit computing modules, and the plurality of unit computing modules are connected in sequence to successively perform pipeline processing on the instructions.

[0019] According to a second aspect, a pipeline instruction execution method is provided, comprising: obtaining a first instruction from an instruction cache unit and executing it in a pipeline manner using a real-time computing unit, wherein the instruction cache unit stores at least one instruction to be executed obtained from an instruction queue; detecting whether the first instruction and a second instruction arranged thereafter satisfy a predetermined conflict condition; if the predetermined conflict condition is satisfied, determining an execution delay of the second instruction, so that when the execution delay arrives, the second instruction is pipelinedly executed via the real-time computing unit, thereby avoiding that a calculation result of the second instruction is output before the calculation result of the first instruction is outputted, and the calculation results of the first and second instructions are outputted from corresponding unit computing modules to a result cache unit.

[0020] In one embodiment, the pipelined instruction is a vector transformation instruction in different domains, a single instruction contains multiple vectors with the same dimension, and the predetermined conflict condition is: the dimension of a single vector in the second instruction is smaller than the dimension of a single vector in the first instruction.

[0021] In one embodiment, the number of instructions cached in the instruction cache unit is determined by dividing the maximum vector dimension in each transformation instruction of the current service by the minimum number of vectors included in a single instruction.

[0022] In one embodiment, the predetermined conflict condition is: the dimension of the single vector included in the second instruction is smaller than the dimension of the single vector included in the first instruction.

[0023] In one embodiment, the delay duration of the second instruction from the actual execution time of the previous instruction is calculated from the start time of the execution of the first instruction, which is: the difference in the computational pipeline delays of a single vector of the first instruction and the second instruction, plus the sum of the output pipeline delays corresponding to each vector in the first instruction, and the pipeline delay of a single vector of a single instruction is determined by the number of butterfly computing units it contains.

[0024] According to a third aspect, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed in a computer, the computer is caused to execute the method of the second aspect.

[0025] According to a fourth aspect, a computing device is provided, comprising a memory and a processor, wherein executable code is stored in the memory, and when the processor executes the executable code, the method of the second aspect is implemented.

[0026] Through the method and device provided in the embodiments of this specification, during the pipeline instruction execution process, an instruction cache unit is set to pre-cache at least one instruction, and conflict detection is performed on the current instruction and the next pre-cached instruction. When the conflict condition is met, the calculation delay control is performed on the next instruction, thereby ensuring that when the calculation result of the next instruction is output, the calculation result of the current instruction has been output, thereby effectively avoiding cache resource conflicts of pipeline calculation instructions. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0028] Figure 1 A schematic diagram showing a specific example of a 32-point NTT transformation;

[0029] Figure 2 A schematic diagram of a pipeline instruction processing architecture in conventional technology is shown;

[0030] Figure 3 A schematic diagram showing the connection of various unit computing modules for pipeline computing of butterfly transformation;

[0031] Figure 4 A schematic diagram showing pipeline instruction conflicts during actual execution is shown;

[0032] Figure 5 is a schematic diagram of a pipeline instruction execution architecture according to an embodiment of the present specification;

[0033] Figure 6 is an execution timing diagram of delayed execution of instructions among adjacent instructions according to a specific example;

[0034] Figure 7 It is a schematic diagram of a pipeline instruction execution flow according to an embodiment of the present specification. DETAILED DESCRIPTION

[0035] The solution provided in this specification is described below in conjunction with the accompanying drawings.

[0036] First, some professional terms that may be involved in this manual are clarified:

[0037] Computing core: A computing core is a microarchitecture component integrated into a processor or hardware accelerator that is used to execute a predetermined class of workloads. Common computing cores include: tensor computing cores, integer computing cores, floating-point computing cores, and so on. A single core may also have an instruction set, optimized data path, and storage structure to achieve corresponding business goals. Commonly used computing cores include tensor computing cores (such as Tensor Core, TPU Core, Matrix Core, etc.) and numerical computing cores (used to process numerical operations such as addition, multiplication, division, bit operations, and other related arithmetic or logical operations).

[0038] Fully Homomorphic Encryption (FHE): refers to an encryption scheme that allows any number of addition and multiplication operations to be performed in an encrypted state, and the same result as the plaintext data can be obtained. This means that complex calculations can be performed on encrypted data without decrypting the data. FHE provides greater computing power and privacy protection, but also has a complex and intensive computing form.

[0039] Zero-Knowledge Proof (ZKP): refers to a cryptographic tool that allows two communicating parties who do not trust each other to prove the validity of a proposition without revealing any additional information. The prover can convince the verifier that a certain assertion is correct without providing any useful information to the verifier. Zero-knowledge proof is essentially a protocol involving two or more parties, that is, a series of steps required for two or more parties to complete a task. The prover proves to the verifier and makes him believe that he knows or has a certain message, but the proof process cannot leak any information about the proven message to the verifier.

[0040] NTT (Number Theoretic Transform): NTT is a similar form of the Fast Fourier Transform in the field of number theory, which is calculated on a finite field modulo a prime number. Number Theoretic Transform is a variant of the Discrete Fourier Transform that uses modular arithmetic instead of traditional real or complex arithmetic. NTT is particularly suitable for situations where modular operations are required, such as large integer multiplication and homomorphic encryption in cryptography. NTT can be used for polynomial multiplication, and its process is similar to FFT (Fast Fourier Transform), the difference is that the operation object of FFT is the complex field, while the operation object of NTT is the prime field. NTT can also reduce the complexity of polynomial multiplication from O(N2) to O(NlogN), thus providing significant acceleration in fields such as cryptography. The NTT algorithm has very wide applications in lattice post-quantum cryptography, fully homomorphic encryption, zero-knowledge proof and other fields, and is one of the important algorithms in the field of modern cryptography.

[0041] Butterfly calculation: The core operation in NTT, also called butterfly transformation in this manual, it weights and multiplies two input data respectively, and then outputs the results to two different locations. Different NTT algorithms can usually be implemented through different combinations of butterfly operations, such as radix 2-butterfly, radix 4-butterfly, etc. Usually, the butterfly operation in the NTT algorithm is a recursive process, which divides the original N data points into two parts of N / 2 data points, each of which is subjected to complex operations and then merged. Recursive iterations at different levels can be integrated through butterfly operations.

[0042] Based on the knowledge provided by the above term explanations, in scenarios involving business processing such as secure computing (such as homomorphic encryption) and image processing (such as conversion from spatial domain to frequency domain), the data processing process usually involves vector transformation (such as FFT or NTT, etc.), and the dimension of the vector targeted by the vector transformation is the number of points corresponding to the vector transformation. For example, homomorphic encryption in secure computing usually involves polynomial operations. In polynomial multiplication operations, the coefficients of the polynomials constitute N-dimensional vectors. It is necessary to transform the N-dimensional vectors into N-dimensional vectors of another expression domain (such as a finite field), that is, to calculate the NTT transformation of N points to speed up the polynomial processing. Image processing is usually the processing of feature maps, which are usually in matrix form. Since FFT or NTT are usually vector transformations, the matrix corresponding to the feature map can be regarded as multiple groups (such as one row as a group or one column as a group) of vector transformations, or expressed as a tensor in vector form by equalization and then transformed. In this way, for vectors or matrices in actual business, FFT or NTT and other transformations can be performed.

[0043] In this specification, the execution process of pipeline instructions is described by taking the calculation instruction of NTT transformation as an example. In practice, discrete Fourier transform DFT, fast Fourier transform FFT, number theory transform NTT, discrete cosine transform DCT, discrete sine transform DST, discrete wavelet transform DWT, and their inverse transforms similar to NTT can all be included in the scope of pipeline instructions referred to in this specification. The various transformations listed above can also include multiple butterfly transformations as calculation units.

[0044] like Figure 1 As shown in the figure, a schematic diagram of 32-point NTT transformation is given. Represents the rotation factor in NTT transformation, where N=16, n=0, 1, 2...15. Figure 1 This is just an example of the point specification of NTT calculation. The butterfly transformation included in the NTT transformation of different points (corresponding to Figure 1 The number of adjacent columns in ) is different. Figure 1The transformation in can be understood as containing 16 2-point butterfly transformations. The NTT transformation of the 32-point vector can contain a 5-order butterfly transformation. The actual calculation structure can support NTT calculation instructions of different point specifications, and the number of butterfly transformations can be much larger than Figure 1 5 are shown. Those skilled in the art will appreciate that the number of points of the NTT transformation can be the specification of the NTT transformation, the dimension of the vector targeted by the transformation, and in homomorphic encryption calculations, the number of polynomial terms or coefficients contained in a single polynomial.

[0045] In the actual business execution process, multiple points of NTT transformations can be included. A single point of NTT transformation can be executed in the same instruction. For example, one instruction can include multiple 32-point NTT transformations, another instruction can include multiple 64-point NTT transformations, and so on. Usually, a large number of NTT calculation instructions can be used. Figure 2 The method shown is as follows. Figure 2 As shown, the computing unit can obtain instructions from the instruction queue one by one, perform corresponding calculations, and then store the calculation results in the result cache unit. After completing the result cache, the computing unit obtains the next instruction from the instruction queue.

[0046] The calculation unit may include a plurality of unit calculation modules, and the unit calculation modules may be used to perform corresponding calculations of a single step in the NTT transformation. Figure 1 As shown, for example, a single unit calculation module can be used to calculate a single butterfly transformation, that is, corresponding to a butterfly calculation (such as the multiplication calculation of a matrix of a single specification and a rotation factor matrix). After being processed in sequence by multiple unit calculation modules, the NTT transformation under the corresponding number of points can be completed. Figure 3 The sequential processing of 8 unit calculation modules is shown. Figure 3 In the example, a single unit computing module can process a single butterfly computing. Figure 1 The butterfly transformation between two adjacent columns in . Figure 1 The 32 shown (i.e. 2 5 ) points can be calculated using 5 unit calculation modules, while 128 (i.e. 2 7 ) point can be completed using 7 unit calculation modules, and so on. Figure 3 A single unit calculation unit in Figure 1 A butterfly transformation between two adjacent columns in the . A single unit computing module can perform a single butterfly operation in parallel. For example, 16 parallel 2-point butterfly transformations are performed for a 32-point NTT calculation.

[0047] It can be understood that in the NTT calculation process, the same instruction can contain multiple NTT transformations of the same specification, that is, corresponding to multiple polynomials with the same number of terms. The number of specifications of the butterfly transformation in the NTT transformation is called the order, and the order also corresponds to the number of unit calculation modules occupied. In this way, the calculation order of 32-point NTT can be 5 (i.e. log232), the calculation order of 64-point NTT can be 6 (i.e. log264), the calculation order of 128-point NTT can be 7 (i.e. log2128), and so on. Reference Figure 3 As shown, in the pipeline instruction execution process, a single NTT transformation can pass through each unit calculation module in sequence, and the calculation result of the NTT transformation can be output at the unit calculation module of the corresponding order. The unit calculation module, such as the 32-point 5th-order NTT calculation, outputs the calculation result in the 5th unit calculation module, the 64-point 6th-order NTT transformation outputs the calculation result in the 6th unit calculation module, and so on. Usually, a single NTT calculation in an instruction passes through each unit calculation module in sequence. After the last NTT calculation of the current instruction is processed by the first unit calculation module and passed to the second unit calculation module, the first unit calculation module meets the conditions for receiving the corresponding NTT calculation in the next instruction.

[0048] Contains instructions for NTT transformations of different orders, and the switching process is as follows Figure 4 shown. Figure 4 In the figure, a row represents a unit calculation module, and rectangles of different color depths represent NTT calculations under different points. Figure 4 As shown, in the 32-point 5-order NTT calculation instruction, the NTT calculation is passed to the next unit calculation module in turn. And after a single unit calculation module is used up, the NTT calculation of the next instruction can be passed on. Figure 4 In the example, when the 32-point 5-order NTT calculation is completed, the 128-point 7-order NTT calculation has not yet produced a result, so there is no result cache conflict. However, before the 128-point 7-order NTT calculation pipeline is completed, the 64-point 6-order NTT calculation has already started to produce calculation results and is preparing to start writing to the cache, so it may cause a result cache conflict. The calculation pipeline here can be understood as the calculation duration. In pipeline computing services, the calculation pipeline can be measured by the number of unit computing modules experienced, or the duration of the calculation process.

[0049] In practice, it is found that this kind of result cache conflict in NTT calculation usually does not exist when switching from small-point (low-order) NTT calculation to large-point (high-order) NTT calculation. It usually occurs when switching from large-point (high-order) NTT calculation to small-point (low-order) NTT calculation. This is especially the case when the NTT points decrease continuously. In other pipeline calculations besides NTT calculation, this kind of result cache conflict may also occur when switching from a calculation instruction with a longer calculation pipeline to a calculation instruction with a shorter calculation pipeline.

[0050] In view of this, the present specification provides a pipelined instruction execution architecture. The pipelined instruction execution architecture provided in the present specification can cache multiple instructions to be executed, and detect whether there is a result cache conflict between adjacent instructions before executing the instructions. If there is a conflict, the execution of the latter instruction is delayed, thereby avoiding the result cache conflict and improving the effectiveness of pipelined instruction execution.

[0051] Figure 5 A schematic diagram of a pipelined instruction execution architecture of a specific example is shown. The pipelined instruction execution architecture may include an instruction cache unit 501, a conflict judgment unit 502, an instruction delay unit 503, a real-time calculation unit 504, a result output enabling unit 505, and a result cache unit 506.

[0052] exist Figure 5 In the example, the instruction queue may store instructions to be executed, and these instructions to be executed may be various instructions that can be executed in a pipeline manner through multiple unit computing modules, such as instructions for various data transformations such as NTT, FFT, DFT, DCT, DST, DWT, or their inverse transformations. These instructions may be generated during the current business processing and written into the instruction queue in sequence. In the case where the instructions in the instruction queue are transformation instructions such as NTT, a single instruction may contain data transformations of the same number of points, and the transformation orders in different instructions are determined according to at least one of the actual business needs and the maximum capacity of the instructions.

[0053] The instruction cache unit 501 can obtain instructions to be executed from the instruction queue and pre-cache them. When the cache space in the instruction cache unit 501 is full, it stops obtaining instructions from the instruction queue. The cache space corresponding to the instruction cache unit 501 can be calculated according to the number of instructions or the number of bytes. For example, if the cache space can cache 3 instructions, then the instruction cache unit 501 is considered to be full when it pre-caches 3 instructions. The size of the cache space is 500 megabytes. Since the number of bytes of each instruction is not necessarily the same, the number of instructions to be obtained can be determined according to the number of bytes that can be accommodated. When the remaining cache space is insufficient to accommodate the next instruction, it is considered to be full.

[0054] According to a possible embodiment, the cache capacity of the instruction cache unit 501 is calculated by the number of instructions. The cache capacity may be positively correlated with the number of NTT calculation points and negatively correlated with the minimum number of NTT transformations in a single instruction (i.e., the number of polynomials, or the dimension of a single vector). For example, the cache capacity of the instruction cache unit 501 is denoted as BUF depth In a specific example, assuming that the maximum number of points in the current business polynomial is N, polyNum min The minimum number of NTT transformations (minimum number of vectors) that a single instruction may contain among all instructions of the current task, including: BUF depth =ceil(log2N×T clock / polyNum min ). Among them, ceil means rounding up, T clock is the number of computational execution cycles corresponding to a single butterfly transformation in the NTT transformation. It is also assumed here that a single execution cycle can process a single NTT transformation (such as a single polynomial in homomorphic encryption), so the number of execution cycles is equal to the number of NTT transformations. depth If they are equal, stop getting instructions from the instruction queue.

[0055] In an optional implementation, a sequence mark may be added to the instructions in all cache BUFs of the instruction cache unit 501 to indicate the order in which the instructions are executed. The sequence mark may be a numerical value describing the order, such as 1, 2, 3, etc., or a time mark, such as a mark consisting of a date and a specific time accurate to a predetermined time scale, such as 202410240933083125, etc.

[0056] The conflict determination unit 502 may determine whether there is a conflict of computing resources and / or cache resources between adjacent instructions. More specifically, it may determine whether there is a resource conflict between the current instruction and the next instruction.

[0057] Generally, when the number of NTT transformation points in the next instruction is less than the number of NTT transformation points in the current instruction (provided that the number of NTT transformation points in a single instruction is unique), it can be determined that there is a resource conflict between the current instruction and the next instruction, and a delay is required. Otherwise, when the number of NTT transformation points in the next instruction is greater than or equal to the number of NTT transformation points in the current instruction, it is determined that there is no resource conflict between the current instruction and the next instruction, and the pipeline computing unit can execute it normally without delay. As described above, the number of transformation points here can also be called the dimension of a single vector contained in the instruction.

[0058] The specific determination principle is as follows.

[0059] Use t nrepresents the current time, n is the number of the current instruction, N(t n ) represents the current t n The number of NTT transformation points (or the number of terms in a single polynomial, or the vector dimension of a single vector) in the nth instruction executed at time t, then the NTT calculation pipeline delay corresponding to the current instruction can be recorded as: PIPE(t n )=log2N(t n )×T clock Similarly, the next instruction (the n+1th instruction, corresponding to time t n+1 ) is denoted as N(t n+1 ), the NTT calculation pipeline delay can be recorded as: PIPE(t n+1 )=log2N(t n+1 )×T clock If there is a cache resource conflict, PIPE is required (t n+1 )<PIPE(t n ), then there must be N(t n+1 )<N(t n ). Therefore, in N(t n+1 ) is less than N(t n ) can be determined as PIPE(t n+1 )<PIPE(t n ), when a number of unit computing modules are vacated during the execution of the current nth instruction and the n+1th instruction is started to be executed, the execution result of the nth instruction may not be stored completely, and the n+1th instruction has already started to produce the result, that is, there is a cache resource conflict between the current nth instruction and the next n+1th instruction.

[0060] In order to avoid resource conflicts when executing instructions, this manual controls the delay through the instruction delay unit 503 so that the current instruction can complete the result cache before the next instruction is calculated. In other words, the calculation result of the next instruction is not output before the calculation result of the previous instruction is fully output. It can be understood that the delay of the next instruction should be the calculation pipeline delay of the current instruction more than the next instruction, plus the result output pipeline delay of the current instruction. For example: ΔPIPE = log2N(t n+1 )*T clock -log2N(t n )*T clock +PolyNum(t n )*T poly , where PolyNum(t n ) represents the number of vector transformations in the current instruction (corresponding to the number of vectors, and can also correspond to the number of polynomials under the transformation of homomorphic encryption polynomials), T polyIndicates the pipeline delay of a single vector transformation result output (usually one calculation execution cycle). The instruction delay unit 503 can determine a delay waiting time of ΔPIPE, or a delay time, for the next instruction that may cause a conflict. In an optional embodiment, the instruction delay unit 503 can also issue an enable signal for the execution of the next instruction when the delay ends.

[0061] The real-time calculation unit 504 can perform real-time calculation on the NTT transformation. Specifically, the real-time calculation unit can include multiple unit calculation modules (e.g. Figure 3 In the butterfly computing unit ButterFly shown in the figure, each unit computing module is connected in sequence to complete the relevant transformation calculation in a pipeline manner.

[0062] Result output enabling unit 505: enables the calculation result to be output to the result cache unit. The output enabling unit controls the time when the calculation result is output to the result cache unit, and controls which unit calculation module to obtain the calculation result from. Figure 3 As shown, the 32-point NTT calculation includes 5 butterfly transformations, which can be understood as using 5 unit calculation modules, and the 64-point NTT calculation uses 6 unit calculation modules, and so on. Each additional butterfly transformation can use one more unit calculation module. In this way, the result output enabling unit 505 can control the output of the calculation result of the corresponding NTT transformation from the last unit calculation module used when the calculation of the corresponding unit calculation module ends. Figure 3 The 32-point NTT shown taps from the 5th unit calculation module (i.e. obtains the output result), that is, it starts to output the calculation result data when the calculation of the 5th unit calculation module is completed. The 64-point NTT taps from the 6th unit calculation module, that is, it starts to output the calculation result data when the calculation of the 6th unit calculation module is completed, and so on.

[0063] Figure 5 In the example, the result output enabling unit 505 can control the calculation result of the real-time calculation unit 504 to be output to the result buffering unit 506. The result buffering unit 506 is used to buffer the calculation result.

[0064] The total pipeline delay of a single instruction includes the pipeline delay of the real-time computing unit 504 for the corresponding NTT transformation and the pipeline delay of the result output. The pipeline delay is the butterfly calculation time of the real-time computing unit 504 for the corresponding NTT transformation. In the case of cache resource conflicts between adjacent instructions, the instruction delay unit 503 can control the next instruction to enter the real-time computing unit 504 after a delay of ΔPIPE, thereby avoiding conflicts in computing resources or cache resources between adjacent instructions.

[0065] The following combination Figure 6 A specific example is given below. Figure 6 It shows a specific example of delay control of two adjacent instructions in the vector transformation corresponding to the polynomial (such as a single vector transformation corresponding to a single polynomial) in the homomorphic encryption scenario, namely 128-point (128-dimensional vector) NTT (including 7th-order butterfly calculation) corresponding to each of the 16 polynomials and 64-point (64-dimensional vector) NTT calculation (including 6th-order butterfly calculation) corresponding to each of the 16 polynomials.

[0066] like Figure 6 As shown, at the current time t0, the current instruction of 16 128-point NTT transformations begins to be executed. A single butterfly calculation (such as the corresponding Figure 1 The delay of the transformation of one column in the clock , then the time when the result output enable unit 505 controls the current instruction to start outputting the result should be t0+7×T clock , 7×T clock It is also the computation pipeline delay of a single polynomial (corresponding to the NTT transformation of a single vector) of the current instruction. Figure 3 The calculation results of each polynomial will be output at the corresponding time interval. Assume that the time to output the calculation result of a polynomial (output pipeline delay) is T poly , and the results of the two polynomial calculations cannot be output in parallel, then the end time (i.e., the emptying time) of the result output of the current instruction (containing 16 polynomials) is t0+7×T clock +16×T poly .

[0067] In order to avoid computing resource conflicts, it is necessary to clock +16×T poly After the time, the calculation result of the first polynomial corresponding to the NTT transformation in the next instruction (16 64-point NTT transformations) is output. The calculation pipeline delay of a polynomial corresponding to the NTT transformation of the next instruction is 6×T clock Therefore, the next instruction must be delayed at least until t1 = t0 + 7 × T clock +16×T poly -6×T clock =t0+T clock +16×T poly The delay time is the difference between the calculation flow of the current instruction and the next instruction (7×T clock -6×T clock ), plus the output pipeline of the current instruction (16×T poly ). In this way, it can be ensured that at t0+7×T clock +16×T poly At this moment, the calculation result of the current instruction is output, and the calculation result of the first polynomial corresponding to the NTT transformation of the next instruction begins to be output.

[0068] It is worth noting that the pipelined instruction execution architecture provided in this specification can be run on at least one of the following processor types including but not limited to: field programmable gate array (FPGA), CPU, GPU, application specific integrated circuit (ASIC), etc. In specific practice, Figure 5 The various units shown may be integrated into one processor or into multiple processors.

[0069] In an optional implementation, the instruction cache unit 501 may exist independently of other units in the pipeline instruction execution architecture. In this case, the overall control architecture may be implemented as follows: Figure 2 The back pressure method in the control instruction cache unit 501 delays the output of instructions to the real-time computing unit.

[0070] In another optional implementation, the instruction cache unit 501 and the conflict judgment unit 502 can exist independently of other units, and can operate at different main operating frequencies with the real-time calculation unit 503, the result output enabling unit 504, and the instruction delay unit 505.

[0071] In another optional implementation, the instruction cache unit 501 and the conflict judgment unit 502 can each simultaneously control different numbers of real-time computing units 503, result output enabling units 504, and instruction delay units 505, that is, one-to-many control can be achieved. The specific number of the controlled real-time computing units 503, result output enabling units 504, and instruction delay units 505 is related to hardware resources and specific services, and is not limited here.

[0072] based on Figure 5 The pipelined instruction execution architecture shown in the specification also provides a pipelined instruction execution process.

[0073] Figure 7 The pipeline instruction execution process according to an embodiment of the present specification is shown. The execution subject of the process can be various computers, devices, servers, etc. that integrate butterfly computing units, and can use Figure 5 The pipeline instruction execution device is used. Figure 7As shown, the pipeline instruction execution process may include: step 701, obtaining a first instruction from an instruction cache unit and executing it in a pipeline manner by a real-time computing unit, wherein the instruction cache unit stores at least one instruction to be executed obtained from an instruction queue; step 702, detecting whether the first instruction and a second instruction arranged thereafter satisfy a predetermined conflict condition; step 703, determining an execution delay of the second instruction when the predetermined conflict condition is satisfied, so that when the execution delay arrives, the second instruction is executed in a pipeline manner by the above-mentioned real-time computing unit, thereby avoiding that the calculation result of the second instruction is output before the calculation result of the first instruction is outputted, and the calculation results of the first instruction and the second instruction are outputted from the corresponding unit computing modules to the result cache unit.

[0074] First, in step 701, a first instruction is obtained from an instruction cache unit and executed in a pipeline manner using a real-time computing unit.

[0075] Among them, the instruction cache unit can store several instructions to be executed obtained from the instruction queue. The instructions here can be various instructions for pipeline execution by real-time computing units composed of multiple unit computing modules. For example, the pipeline instructions are vector transformation instructions in different domains, and a single instruction contains multiple vectors of the same dimension. The above transformation is one of the following transformations or its inverse transformation: discrete Fourier transform DFT, fast Fourier transform FFT, number theory transform NTT, discrete cosine transform DCT, discrete sine transform DST, discrete wavelet transform DWT, and so on.

[0076] Optionally, the instruction cache unit can store at most a first number of instructions. Here, the first number is determined according to the capacity of the instruction cache unit. It can be a pre-set number of cached instructions, or it can be a number of instructions determined according to the attributes of instructions in the current service. As a specific example, assuming that the maximum value of the current service NTT points is N, T clock is the number of computational execution cycles corresponding to a single butterfly transform unit in the NTT transform, polyNum min The minimum number of vectors that a single instruction may contain among all instructions of the current task. A single execution cycle processes a single polynomial. The first number can be determined by: BUF depth =ceil(log2N×T clock / polyNum min ), ceil means round up.

[0077] Next, in step 702 , it is detected whether the first instruction and the second instruction arranged thereafter satisfy a predetermined conflict condition.

[0078] Under the technical concept of this specification, instructions are executed in sequence, and whether a single instruction needs to be deferred depends on whether there will be a conflict in the use of computing resources and storage resources with the previous instruction. In other words, before the current instruction is stored, the next instruction can be calculated by the real-time computing unit, but storage cannot be started. Therefore, the calculation completion time for starting to execute the next instruction must meet the following requirements: not earlier than the storage of the current instruction. Here, the conflict condition can be: according to the pipeline instruction execution rules, the calculation completion time of the first polynomial of the next instruction is earlier than the time when the result cache of the current instruction is fully completed. Since the number of NTT calculation points corresponding to a single polynomial is consistent with the number of butterfly calculation specifications it contains, and a single butterfly calculation specification can be completed by a single unit calculation module, therefore, in one embodiment, the conflict condition can be simplified as follows: the number of NTT calculation points in the next instruction (the dimension of a single vector) is less than the number of NTT calculation points in the current instruction.

[0079] Here, it is detected whether the first instruction and the second instruction arranged thereafter meet the predetermined conflict condition, that is, the magnitude relationship of the NTT calculation points contained in the two is compared. Generally, when the NTT calculation points in the second instruction are less than the NTT calculation points in the first instruction, it is determined that the conflict condition is met.

[0080] Then, through step 703, when a predetermined conflict condition is met, the execution delay of the second instruction is determined, so that when the execution delay arrives, the second instruction is pipelinedly executed via the real-time computing unit.

[0081] In order to avoid conflicts between the computing resources and storage resources of the first instruction and the second instruction, the second instruction can be executed with a delay. That is, after the real-time computing unit completes the NTT calculation of the last vector in the first instruction, it does not receive the NTT calculation of the vector in the second instruction first, but starts processing the second instruction after the delay time of the second instruction arrives, so that the time when the NTT calculation result of the first vector of the second instruction is obtained is not earlier than the time when the NTT calculation result of the last vector of the first instruction is output.

[0082] To this end, according to one embodiment, the processing delay of the second instruction may be:

[0083] ΔPIPE=log2N(t n+1 )*T clock -log2N(t n )*T clock +PolyNum(t n )*T poly , where PolyNum(t n ) represents the number of vectors in the first instruction, N(t n+1) is the number of NTT calculation points of a single vector corresponding to the second instruction, N(t n ) is the number of NTT calculation points of a single vector corresponding to the first instruction, T poly Indicates the pipeline delay of the NTT calculation result output of a single vector (usually one calculation execution cycle). Assuming that the time when the first instruction starts to be executed is t0, the second instruction can be started at t0+ΔPIPE.

[0084] It can be understood that each instruction can be executed in a pipeline form, and the computing unit forming the pipeline is a plurality of sequentially connected unit computing modules. Figure 3 As shown, a single unit computing module can complete a single specification of butterfly transformation. The second instruction enters the computing unit when the delay arrives.

[0085] Since the start processing time of the second instruction is delayed in the steps described above, the corresponding calculation results are output when each instruction is completed, which will not cause result cache conflicts. It is worth noting that when obtaining the calculation results, it is necessary to consider the order of NTT calculation, so as to obtain the calculation results from the corresponding unit calculation module and output them (i.e. Figure 3 The output result corresponding to a single instruction is obtained from the log2Nth unit calculation module, where N is the NTT calculation order in the single instruction.

[0086] It is worth noting that the above embodiments describe the technical concept of this specification by taking NTT transformation as an example. In practice, various pipeline-executed instructions may adopt the above technical concept and belong to the protection scope of this specification. For example, various data transformations such as NTT, FFT, DFT, DCT, DST, DWT or their inverse transformations can be processed by pipeline-executed instructions. In addition, NTT, FFT, DFT, DCT, DST, DWT and their inverse transformations all include butterfly transformation, and the relevant contents of the butterfly transformation described in the previous text can be applied.

[0087] Looking back at the above process, during the pipeline instruction execution process, by setting the instruction cache unit, at least one instruction is pre-cached, and conflict detection is performed on the current instruction and the next pre-cached instruction. When the predetermined conflict condition is met, the next instruction is delayed to ensure that when the calculation result of the next instruction is output, the calculation result of the current instruction has been output, thereby effectively avoiding cache resource conflicts of pipeline calculation instructions.

[0088] According to another embodiment, there is also provided a computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, causes the computer to execute a combination of Figure 7 The method described by et al.

[0089] According to another embodiment of the present invention, a computing device is provided, including a memory and a processor, wherein the memory stores executable code, and when the processor executes the executable code, the Figure 7 The method described by et al.

[0090] Those skilled in the art should be aware that in one or more of the above examples, the functions described in the embodiments of this specification can be implemented by hardware, software, firmware, or any combination thereof. When implemented by software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium.

[0091] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of the technical concept of this specification. It should be understood that the above description is only the specific implementation method of the technical concept of this specification, and is not used to limit the protection scope of the technical concept of this specification. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solutions of the embodiments of this specification should be included in the protection scope of the technical concept of this specification.

Claims

1. A pipeline instruction execution device, comprising: An instruction cache unit, configured to cache at least one instruction to be executed, wherein the at least one instruction to be executed is obtained from the instruction queue; A conflict determination unit, configured to determine whether adjacent instructions satisfy a predetermined conflict condition; An instruction delay unit is configured to determine a delay time for a subsequent instruction that satisfies the predetermined conflict condition and perform delayed execution control, wherein the delay time makes the calculation result of the subsequent instruction be output no earlier than the calculation result of the previous instruction is fully output; A real-time computing unit, wherein the unit computing module is configured to perform pipeline computing operations on the instructions; A result output enabling unit, configured to enable output of a calculation result obtained by a calculation module of a calculation unit of the real-time calculation unit; The result cache unit is configured to cache the calculation result.

2. The device according to claim 1, wherein: The pipeline instructions are vector transformation instructions in different domains, a single instruction contains at least one vector with the same dimension, and the predetermined conflict condition is: the dimension of the single vector in the latter instruction is smaller than the dimension of the single vector in the former instruction.

3. The device as claimed in claim 2, wherein: The transformation includes one of the following transformations or its inverse transformation: discrete Fourier transform DFT, fast Fourier transform FFT, number theoretic transform NTT, discrete cosine transform DCT, discrete sine transform DST, discrete wavelet transform DWT.

4. The device according to claim 2, wherein: The number of instructions cached in the instruction cache unit is determined by: rounding up the quotient of the maximum vector dimension in each transformation instruction of the current service divided by the minimum number of vectors included in a single instruction.

5. The device according to claim 1, wherein: The delay of the subsequent instruction is calculated from the start time of the execution of the previous instruction, which is: the difference in the calculation pipeline delay of a single vector between the previous instruction and the subsequent instruction, plus the sum of the output pipeline delays corresponding to each vector in the previous instruction. The pipeline delay of a single vector is determined by the number of butterfly computing units it contains.

6. The device according to claim 1, wherein: The real-time computing unit includes a plurality of unit computing modules, and the plurality of unit computing modules are connected in sequence to continuously perform pipeline processing on the instructions.

7. A pipeline instruction execution method, comprising: Obtaining a first instruction from an instruction cache unit and executing it in a pipeline manner using a real-time computing unit, wherein the instruction cache unit stores at least one instruction to be executed obtained from an instruction queue; detecting whether the first instruction and a second instruction arranged thereafter satisfy a predetermined conflict condition; When the predetermined conflict condition is met, the execution delay of the second instruction is determined, so that when the execution delay is reached, the second instruction is executed in a pipeline manner via the real-time computing unit, thereby avoiding the calculation result of the second instruction being output before the calculation result of the first instruction is output, and the calculation results of the first instruction and the second instruction are output from the corresponding unit computing modules to the result cache unit.

8. The method of claim 7, wherein: The pipeline instructions are instructions for transforming vectors in different domains, a single instruction contains multiple vectors with the same dimension, and the predetermined conflict condition is: the dimension of a single vector in the second instruction is smaller than the dimension of a single vector in the first instruction.

9. The method of claim 7, wherein: The number of instructions cached in the instruction cache unit is determined by dividing the maximum vector dimension in each transformation instruction of the current service by the minimum number of vectors contained in a single instruction.

10. The method of claim 7, wherein: The predetermined conflict condition is: the dimension of the single vector included in the second instruction is smaller than the dimension of the single vector included in the first instruction.

11. The method of claim 7, wherein: The delay length of the second instruction is calculated from the start time of execution of the first instruction, which is: the difference between the calculation pipeline delays of a single vector of the first instruction and the second instruction, plus the sum of the output pipeline delays corresponding to each vector in the first instruction, and the pipeline delay of a single vector is determined by the number of butterfly computing units it contains.

12. A computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, causes the computer to execute the method according to any one of claims 7 to 11.

13. A computing device comprising a memory and a processor, characterized in that: The memory stores executable codes, and when the processor executes the executable codes, the method according to any one of claims 7 to 11 is implemented.

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