Simulation test system and data board simulation test method

Abstract

The invention discloses a simulation test system which comprises an upper computer, a CPU (central processing unit) processing module and an FPGA (field programmable gate array) processing module, the upper computer is connected with the CPU processing module through Ethernet, the CPU processing module is connected with the FPGA processing module through PCIe (peripheral component interface express), and the FPGA processing module is connected with a tested data board card through a communication expansion interface; the upper computer is used for issuing an instruction and controlling the sending of data, generating corresponding data by controlling the CPU processing module and sending the data to the tested data board card; the CPU processing module is connected with the upper computer and is used for generating test data, managing and initiating a test task; and the FPGA processing module is used for processing the test data generated by the CPU, performing data transmission with the tested data board card, and counting performance parameters of the tested data board card in the data transmission process. The invention further discloses a data board card simulation test method. According to the simulation test system, the data transmission speed is increased, the test efficiency is improved, and the simulation test system is suitable for more test scenes.

Description

Technical Field

[0001] The present application relates to the technical field of computer simulation testing, and more specifically, to a simulation testing system and a data board simulation testing method. Background Art

[0002] In the process of developing and applying data boards, it is necessary to test the data boards to obtain the data transmission rate, packet loss rate, etc. of the data boards. When the existing data board simulation platform test system performs FPGA self-test, due to the large number of system calls in the kernel driver, each transmission needs to copy data from user state to kernel state. The smaller the packet length, the more calls are made. The time is mainly consumed in system calls, and the PCIe transmission bandwidth cannot be fully utilized. Since the packet length of the transmission under test is mainly between 64-2048 bytes, the transmission rate of the kernel driver under this condition is about 30Mbps, which is far from meeting the requirements of performance testing, limiting the current testing capabilities of the simulation platform. Summary of the invention

[0003] In view of at least one defect or improvement demand in the prior art, the present invention provides a simulation test system and a data board simulation test method, which can solve at least one of the problems existing in the above-mentioned background technology.

[0004] To achieve the above-mentioned object, according to a first aspect of the present invention, a simulation test system is provided, comprising a host computer, a CPU processing module and an FPGA processing module, wherein the host computer is deployed on a general-purpose computer terminal and is connected to the CPU processing module via Ethernet, the CPU processing module and the FPGA processing module are connected via PCIe, and the FPGA processing module is connected to a data board under test via a communication expansion interface;

[0005] The host computer is used to issue instructions and control the sending of data, specify the amount of data to be sent and the sending rate parameters, and generate corresponding data by controlling the CPU processing module to send to the data board under test;

[0006] The CPU processing module is connected to the host computer to generate test data, manage and initiate test tasks;

[0007] The FPGA processing module is used to process the test data generated by the CPU, perform data transmission with the data board under test, and count the performance parameters of the data board under test during the data transmission process.

[0008] Furthermore, in the above-mentioned simulation test system, the CPU processing module includes a user-mode driver, a kernel-mode driver and a hardware driver.

[0009] Furthermore, in the above-mentioned simulation test system, the kernel-mode driver includes uio_xdma, which is used for device enumeration, initialization and interrupt processing tasks.

[0010] Furthermore, in the above-mentioned simulation test system, the user-mode driver specifically includes DPDK and pmd_xdma, wherein DPDK is a data plane development kit for processing packet sending and receiving based on the data plane library provided by itself, and pmd_xdma is a polling mode driver for sending and receiving data frames based on a non-interrupt manner and a zero-copy mechanism for entering and exiting the reference buffer memory.

[0011] Furthermore, in the above-mentioned simulation test system, the FPGA processing module includes a PCIe_XDMA IP core, a RISC-VIP core and a communication extension IP core; the PCIe_XDMA IP core is used to connect to the CPU through PCIe; the RISC-VIP core is used to connect to the data board under test through the communication extension IP core, and provide a universal protocol forwarding program.

[0012] Furthermore, in the above simulation test system, the PCIe_XDMA IP core and the RISC-V IP core are connected via an AIX4 bus, and the RISC-V IP core and the communication extension IP are connected via an AIX4 bus.

[0013] Furthermore, in the above simulation test system, the AXI4-Master Port on the PCIe_XDMA IP core is connected to the AXI4-Slave Port on the RISC-V IP core via an AIX4 bus.

[0014] Furthermore, in the above-mentioned simulation test system, when the RISC-V IP core is connected to data boards of different protocols, the RISC-V IP core is recompiled by downloading the corresponding protocol to provide a universal protocol forwarding program.

[0015] According to a second aspect of the present invention, a data board simulation test method is also provided, based on the above-mentioned simulation test system, comprising:

[0016] The host computer configures the test parameters, including the amount of data sent and the transmission rate, and starts the test;

[0017] The CPU processing module obtains the start test instruction sent by the host computer, obtains the test parameters, and generates corresponding test data;

[0018] The test data is transmitted to the FPGA processing module through the PCIe bus. The FPGA processing module filters and processes the test data and sends the processed data to the data board under test through the service interface.

[0019] The data board under test processes the received data and returns it to the FPGA processing module through the business interface;

[0020] The FPGA processing module counts the amount of data sent and received, and transmits the statistical results to the CPU processing module through the PCIe bus. The CPU processing module reports the statistical results to the host computer to complete the test.

[0021] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects compared with the prior art:

[0022] The simulation test system provided by the present invention can reduce the process of copying data from user state to kernel state during transmission by resetting the test path, fully utilize the PCIe transmission bandwidth, increase the transmission speed, and improve the test efficiency. At the same time, it can also quickly switch the transmission protocol through FPGA, which is suitable for more test scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A schematic diagram of the structure of a simulation test system provided in an embodiment of the present application;

[0025] Figure 2 A schematic diagram of the RISC-V workflow provided for an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0027] The terms "first", "second", "third", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0028] Figure 1 A structural diagram of a simulation test system provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the simulation test system provided in the embodiment of the present application includes a host computer, a CPU processing module and an FPGA processing module. The host computer is deployed on a general-purpose computer terminal and is connected to the CPU processing module via Ethernet. The CPU processing module and the FPGA processing module are connected via PCIe. The FPGA processing module is connected to the data board under test via a communication expansion interface.

[0029] The host computer is used to send instructions and control the sending of data, specify the amount of data to be sent and the sending rate parameters, and generate corresponding data by controlling the CPU processing module to send it to the data board under test;

[0030] The CPU processing module is connected to the host computer to generate test data, manage and initiate test tasks;

[0031] The FPGA processing module is used to process the test data generated by the CPU, transmit data with the data board under test, and count the performance parameters of the data board under test during the data transmission process.

[0032] Specifically, Figure 1 As shown, the simulation test system provided in the embodiment of the present application includes a host computer, a CPU processing module and a FPGA processing module.

[0033] The host computer is deployed on a general-purpose computer terminal and is mainly responsible for issuing instructions and controlling the transmission of data. Specifically, the host computer specifies the amount of data to be sent and the transmission rate and other parameters. By cooperating with the program of the CPU processing module, it generates corresponding data and sends it to the data card under test through the test platform. Optionally, the host computer can also be used to receive and display test results, such as test time, transmission rate, packet loss rate and other information.

[0034] The CPU processing module is physically connected to the FPGA processing module through PCIe. The CPU processing module can use, but is not limited to, the domestic RK3399 chip, and can be expanded to any processor chip with a PCIe interface. The CPU is used to connect to the host computer through Ethernet to generate specific data sent by the host computer, including data of a specific rate and length, which is used to test the function or performance of the data card under test.

[0035] The FPGA processing module is used to connect to the data card under test, select and transmit the test data generated by the CPU processing module, and obtain statistics and performance parameters of the data card under test during the data transmission process. Specifically, the FPGA contains several IP cores, such as the XDMA IP core and another IP core for expansion. These IP cores are responsible for processing data flow and communication with the CPU. In addition, the FPGA also integrates the RISK-V IP core, which can realize faster changes in protocol judgment logic, thereby improving test efficiency.

[0036] The simulation test system provided in the embodiment of the present application can reduce the process of copying data from user state to kernel state during transmission by resetting the test path, fully utilize the PCIe transmission bandwidth, increase the transmission speed, and improve the test efficiency. At the same time, it can also quickly switch the transmission protocol through FPGA, which is suitable for more test scenarios.

[0037] Optionally, in the simulation test system provided in an embodiment of the present application, the CPU processing module includes a user-mode driver, a kernel-mode driver and a hardware driver.

[0038] Optionally, in the simulation test system provided by the embodiment of the present application, the kernel-mode driver includes uio_xdma, which is used for device enumeration, initialization and interrupt processing tasks.

[0039] Optionally, the simulation test system provided in the embodiment of the present application is user-mode driven, specifically including DPDK and pmd_xdma, wherein DPDK is a data plane development kit for processing packet sending and receiving based on the data plane library provided by itself, and pmd_xdma is a polling mode driver for sending and receiving data frames based on a non-interrupt manner and a zero-copy mechanism for entering and exiting the reference buffer memory.

[0040] Specifically, DPDK (Data Plane Development Kit) is a collection of lib libraries and toolkits. The application runs in the user state of the operating system and can use the data plane library provided by itself to process packet sending and receiving, bypassing the Linux kernel-state protocol stack and improving the efficiency of message processing.

[0041] pmd (Pool Mode Driver) improves the efficiency of sending / receiving data frames through non-interrupt and zero-copy mechanism of data frames entering and exiting application buffer memory.

[0042] Optionally, in the simulation test system provided in the embodiment of the present application, the FPGA processing module includes a PCIe_XDMA IP core, a RISC-V IP core and a communication extension IP core; the PCIe_XDMA IP core is used to connect to the CPU through PCIe; the RISC-VIP core is used to connect to the data board under test through the communication extension IP core, and provide a universal protocol forwarding program.

[0043] Optionally, in the simulation test system provided by the embodiment of the present application, the PCIe_XDMA IP core and the RISC-V IP core are connected via an AIX4 bus, and the RISC-V IP core and the communication extension IP are connected via an AIX4 bus.

[0044] Optionally, in the simulation test system provided by the embodiment of the present application, the AXI4-MasterPort on the PCIe_XDMA IP core is connected to the AXI4-Slave Port on the RISC-V IP core through an AIX4 bus.

[0045] Optionally, in the simulation test system provided in the embodiment of the present application, when the RISC-V IP core is connected to a data board of a different protocol, the RISC-V IP core is recompiled by downloading the corresponding protocol to provide a universal protocol forwarding program.

[0046] Specifically, RISC-V uses an event loop to process data. The minimum unit of data transmission and reception is a complete data frame, which can simplify the complexity of the code in terms of packet number calculation and packet integrity verification. The RISC-V module can pre-process data packets, such as header verification, counting, and routing functions, simplify the logic of the FPGA, and reduce the risk of FPGA engineering redesign and recompilation time caused by business changes.

[0047] By instantiating the RISC-V module inside the FPGA, the time overhead caused by the need to regenerate the FPAG project due to protocol changes is reduced. Taking 12700K (P5.0GHz, E3.7GHz) as an example, the existing method of changing the protocol takes about 1 hour to regenerate an FPGA project. This application adopts the method of recompiling the RISC-V IP core by downloading the corresponding protocol. It takes 5 seconds to compile a RISC-V program, which can meet the needs of real-time logic modification. RISC-V is connected to the device under test, and the scalability of the device is improved through the RISC-V module, reducing the modification of the FPGA project logic.

[0048] Figure 2 This is a schematic diagram of the RISC-V workflow provided by this application, such as Figure 2 As shown in the figure, the A and B interfaces of RISC-V are connected to the data board under test through the communication expansion IP. The communication expansion IP is Figure 2 By judging the communication status of RapidIO, the communication status with the data board under test can be obtained.

[0049] After obtaining the CPU instruction, the total number of packets n is obtained by processing the CPU test data. The PCIe port Recv data is obtained to determine whether the Send end of RapidIO A port is idle. If not, the blocking value of port A is increased by 1. If idle, the test data is sent to port A for encryption. It is determined whether there is data in RapidIO B port Recv. If there is no data, proceed directly to the next step. If there is, obtain the B port Recv data and proceed to the next step; determine whether RapidIO B port Send is idle. If not, the blocking value of port B is increased by 1. If idle, the test data is sent to port B for decryption. It is determined whether there is data in RapidIO A port Recv. If there is data, proceed to the next step. It is determined whether the data has been circulated n times. If not, repeat the above steps. If n cycles have been completed, the number of packets n and the blocking amount of ports A and B are counted, so as to calculate the packet loss rate and accuracy, and end the test.

[0050] The embodiment of the present application also provides a data board simulation test method, based on the above simulation test system, including:

[0051] The host computer configures the test parameters, including the amount of data sent and the transmission rate, and starts the test;

[0052] The CPU processing module obtains the start test instruction sent by the host computer, obtains the test parameters, and generates corresponding test data;

[0053] The test data is transmitted to the FPGA processing module through the PCIe bus. The FPGA processing module filters and processes the test data and sends the processed data to the data board under test through the service interface.

[0054] The data board under test processes the received data and returns it to the FPGA processing module through the business interface;

[0055] The FPGA processing module counts the amount of data sent and received, and transmits the statistical results to the CPU processing module through the PCIe bus. The CPU processing module reports the statistical results to the host computer to complete the test.

[0056] By using the existing technology to pass the FPGA self-loop test, data is sent and received between 3399 and FPGA. The transmission rate is approximately 12Mbps when the packet length is 512 bytes, 30Mbps when the packet length is 1024 bytes, and reaches a steady state of 400Mbps after the packet length is increased to 8K. Using the data board simulation test method provided by the application, the transmission rate is approximately 600Mbps when the packet length is 512 bytes, 1000Mbps when the packet length is 1024 bytes, and maintains 1000Mbps after the packet length is increased to 8K.

[0057] Since the packet length of the transmission being tested is mainly between 64 and 2048 bytes, the transmission rate driven by the existing kernel technology under this working condition is around 30Mbps, which is far from meeting the requirements of performance testing, limiting the current testing capabilities of the simulation platform. The data board simulation test method provided in this application has obvious and effective improvements.

[0058] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0059] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0060] In the several embodiments provided in the present application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0061] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0062] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0063] A person of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable memory, which can include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0064] The above is only an exemplary embodiment of the present disclosure, and the scope of the present disclosure cannot be limited thereto. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the specification and practicing the disclosure here, those skilled in the art will easily think of the implementation scheme of the present disclosure. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the technical field not recorded in the present disclosure. The description and examples are regarded as exemplary only, and the scope and spirit of the present disclosure are defined by the claims.

[0065] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0066] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A simulation test system, characterized in that: It includes a host computer, a CPU processing module and an FPGA processing module, wherein the host computer is deployed on a general-purpose computer terminal and is connected to the CPU processing module via Ethernet, the CPU processing module and the FPGA processing module are connected via PCIe, and the FPGA processing module is connected to the data board under test via a communication expansion interface; The host computer is used to issue instructions and control the sending of data, specify the amount of data to be sent and the sending rate parameters, and generate corresponding data by controlling the CPU processing module to send to the data board under test; The CPU processing module is connected to the host computer to generate test data, manage and initiate test tasks; The FPGA processing module is used to process the test data generated by the CPU, perform data transmission with the data board under test, and count the performance parameters of the data board under test during the data transmission process.

2. The simulation test system according to claim 1, characterized in that: The CPU processing module includes a user state driver, a kernel state driver and a hardware driver.

3. The simulation test system as claimed in claim 2, characterized in that: The kernel mode driver includes uio_xdma, which is used for device enumeration, initialization and interrupt processing tasks.

4. The simulation test system as claimed in claim 2, characterized in that: The user-mode driver specifically includes DPDK and pmd_xdma, wherein DPDK is a data plane development kit for processing packet sending and receiving based on the data plane library provided by itself, and pmd_xdma is a polling mode driver for sending and receiving data frames based on a non-interrupt manner and a zero-copy mechanism for entering and exiting the reference buffer memory.

5. The simulation test system according to claim 1, characterized in that: The FPGA processing module includes a PCIe_XDMA IP core, a RISC-V IP core and a communication extension IP core; the PCIe_XDMA IP core is used to connect to the CPU through PCIe; the RISC-V IP core is used to connect to the data board under test through the communication extension IP core, and provide a universal protocol forwarding program.

6. The simulation test system according to claim 5, characterized in that: The PCIe_XDMA IP core and the RISC-V IP core are connected via an AIX4 bus, and the RISC-V IP core and the communication extension IP are connected via an AIX4 bus.

7. The simulation test system according to claim 6, characterized in that: The AXI4-Master Port on the PCIe_XDMA IP core is connected to the AXI4-Slave Port on the RISC-V IP core via the AIX4 bus.

8. The simulation test system according to claim 5, characterized in that: When the RISC-V IP core is connected to data boards with different protocols, the RISC-V IP core is recompiled by downloading the corresponding protocol to provide a universal protocol forwarding program.

9. A data board simulation test method, based on the simulation test system as claimed in claim 1, characterized in that: include: The host computer configures the test parameters, including the amount of data sent and the transmission rate, and starts the test; The CPU processing module obtains the start test instruction sent by the host computer, obtains the test parameters, and generates corresponding test data; The test data is transmitted to the FPGA processing module through the PCIe bus. The FPGA processing module filters and processes the test data and sends the processed data to the data board under test through the service interface. The data board under test processes the received data and returns it to the FPGA processing module through the business interface; The FPGA processing module counts the amount of data sent and received, and transmits the statistical results to the CPU processing module through the PCIe bus. The CPU processing module reports the statistical results to the host computer to complete the test.

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