SSD garbage recycling available logic address block comparison hardware acceleration method

Abstract

The invention provides an SSD garbage collection available logical address block comparison hardware acceleration method, which comprises the following steps of: 1, recording a write available data count of each physical block when the physical block is normally written; 2, when garbage is recycled, the physical block with the minimum available data size is searched for, and garbage recycling is conducted on the physical block; and 3, the step 2 is repeated till garbage recycling is completed. According to the method, hardware acceleration is carried out through the available logic address for garbage collection, when firmware is normally written into the physical blocks, the write-in available data count of each physical block can be recorded, so that garbage treatment can be carried out on the physical block with the minimum available data size in the garbage collection process, and after the garbage treatment is carried out on the physical block, the write-in available data count of each physical block can be recorded. And sequentially and continuously carrying out garbage collection on the physical blocks with the minimum available data volume. Therefore, an available logic address comparison acceleration function is realized, and the SSD power consumption is reduced while the garbage collection efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of solid state disk storage, and more specifically to a hardware acceleration method for comparing available logical address blocks of SSD garbage collection. Background Art

[0002] During the data reading and writing process, the SSD needs to store the mapping relationship between the logical address and the physical address (L2P) in the internal DRAM (dynamic random access memory). At the same time, when the data is written to NAND, the mapping relationship between the physical address and the logical address (P2L) will be written to a fixed position in the current block. When the SSD is doing garbage collection, it is necessary to find out the available physical addresses in the current physical block, read the data therein and write them into the new physical block. The existing approach requires the firmware to traverse and read all P2L pages, and then find out whether each logical address is available in the L2P table, and then perform subsequent garbage collection processing. Therefore, each data processing needs to be read and looked up by the firmware, which requires a lot of data processing time, has high requirements on the processing power of the SSD master CPU, and will also increase the power consumption of the SSD. Summary of the invention

[0003] The object of the present invention is to provide a hardware acceleration method for comparing available logical address blocks of SSD garbage collection, which can improve the garbage collection efficiency and reduce the power consumption of SSD.

[0004] According to one aspect of the present invention, a hardware acceleration method for comparing available logical address blocks for SSD garbage collection is provided, comprising:

[0005] Step 1: When writing a physical block normally, record the write available data count of each physical block;

[0006] Step 2: When garbage collection is performed, find the physical block with the smallest amount of available data and perform garbage collection on it;

[0007] Step 3: Repeat step 2 until garbage collection is completed.

[0008] In some embodiments, when garbage collection occurs:

[0009] Read each P2L page data of the physical block with the smallest available data amount into the SRAM cache;

[0010] Writing the SRAM cache address where the read P2L page data is stored into the hardware acceleration module;

[0011] The hardware acceleration module traverses and reads the logical addresses in the P2L page and compares them with the L2P table;

[0012] Through comparison, if the read logical address is unavailable, the data in the corresponding physical address is discarded; if the read logical address is available, the corresponding physical address data is read, and the data and mapping relationship are written into a new physical block, and the current physical block is erased.

[0013] In some implementations, the L2P table is stored in DRAM.

[0014] In some implementations, the hardware acceleration module compares, via an independent bus, whether the logical address in the P2L page is available in the L2P table.

[0015] In some implementations, if the logical address is unavailable, it indicates that the physical address data corresponding to the logical address has been overwritten, and the data in the physical address is discarded.

[0016] In some implementations, the data in the physical address in the available identification register of the hardware acceleration module is read, and the read data and the mapping relationship are written into a new physical block.

[0017] In some implementations, data in a physical address in an available identification register of the hardware acceleration module is read, and the read data and a mapping relationship are written into a new physical block until the available identification register indicates that all physical location comparison processing of the physical block currently garbage collected is completed.

[0018] The beneficial effect is that the present invention accelerates the hardware of available logical addresses for garbage collection. When the firmware writes physical blocks normally, the write available data count of each physical block will be recorded, so that during garbage collection, the physical block with the smallest available data volume can be garbage processed first, and then the physical block with the smallest available data volume can be garbage processed in sequence. In this way, the available logical address comparison acceleration function is realized, the garbage collection efficiency is accelerated, and the power consumption of the SSD is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A garbage collection flow chart of an SSD garbage collection hardware acceleration method using logical address block comparison according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The present invention will be further described below in conjunction with the accompanying drawings.

[0021] A hardware acceleration method for comparing available logical address blocks for SSD garbage collection includes: when the firmware of the SSD writes physical blocks normally, the write available data count of each physical block is recorded; when the garbage collection start condition is triggered, the firmware searches for the physical block with the smallest available data amount, performs garbage collection on it, reads all available data of the current physical block, writes a new physical block, and erases the current physical block. Repeat the above steps until the garbage collection is completed.

[0022] When garbage collection is performed: the physical block address with the smallest available physical block is selected and input into the hardware acceleration module. Specifically, each P2L page address of the physical block with the smallest amount of available data is read into the SRAM cache; the SRAM cache address where the read P2L page data is stored is written into the hardware acceleration module. The P2L page reading of the physical block is realized through the hardware acceleration module, and the logical address in the P2L mapping table is checked to see whether it is available, and then the available position information of the current physical block is output, and the firmware performs subsequent garbage collection processing on the data of the output available position. Specifically, the hardware acceleration module traverses and reads the logical address in the P2L page, and compares it with the L2P table stored in the DRAM; the hardware acceleration module compares the logical address in the P2L page in the L2P table through an independent bus to see whether it is available. Through the comparison, if the read logical address is not available, the corresponding physical address data is discarded. If the logical address is not available, it indicates that the physical address data corresponding to the logical address has been overwritten, and the data in the physical address is discarded. If the read logical address is available, the corresponding physical address data is read, and the data and mapping relationship are written into a new physical block.

[0023] When the firmware starts garbage collection, it finds the physical block with the least amount of available data, calculates each P2L page address of the physical block, reads each P2L page into the SRAM cache, and writes the SRAM cache address where each P2L page data is stored into the hardware acceleration module designed by the present invention. The hardware acceleration module traverses this P2L cache page and compares it with the L2P table of the DRAM in the system. The firmware traverses and reads the output results of the hardware acceleration module, reads the data page of the available physical location, writes the old data and the corresponding logical address to the new physical address, and erases the current physical block, and then continues to perform garbage collection on the physical block with the smallest amount of available data until the garbage collection is completed.

[0024] like Figure 1 As shown, garbage collection includes:

[0025] Calculate and find all P2L page addresses of the current physical block;

[0026] Read all P2L page data into SRAM cache in sequence;

[0027] Write the SRAM cache address to the hardware acceleration calculation module, and then trigger the hardware acceleration module;

[0028] The hardware acceleration module traverses and reads the logical address in the current P2L page, and compares whether this logical address is available in the L2P table through the hardware independent bus; if this logical address is not available, it indicates that the physical address data has been overwritten and the address data is discarded. If this logical address is available, then read this physical address data, and obtain the corresponding logical address through the extended metadata of the data, and write the data and mapping relationship into the new physical block. Specifically, the firmware reads the available identification register information of the hardware acceleration module, thereby obtaining which physical addresses in the physical block that is currently undergoing garbage collection have valid data. For the physical address indicated in the available identification register, read the data in this physical address, and write the data and mapping relationship into the new physical block. The above operation is repeated until the available identification register indicates that all physical locations of the physical block currently undergoing garbage collection have been compared and processed.

[0029] The above are only some embodiments of the present invention, which are only used to illustrate the technical solutions of the present invention, but not to limit them. For ordinary technicians in this field, without departing from the creative concept of the present invention, the technical solutions recorded in the above embodiments are modified, or some or all of the technical features are replaced by equivalents, which all belong to the protection scope of the present invention.

Claims

1. A hardware acceleration method for comparing available logical address blocks for SSD garbage collection, characterized in that: include: Step 1: When writing a physical block normally, record the write available data count of each physical block; Step 2: When garbage collection is performed, find the physical block with the smallest amount of available data and perform garbage collection on it; Step 3: Repeat step 2 until garbage collection is completed.

2. The SSD garbage collection available logical address block comparison hardware acceleration method according to claim 1, characterized in that: When garbage collection occurs: Read each P2L page data of the physical block with the smallest available data amount into the SRAM cache; Writing the SRAM cache address where the read P2L page data is stored into the hardware acceleration module; The hardware acceleration module traverses and reads the logical addresses in the P2L page and compares them with the L2P table; Through comparison, if the read logical address is unavailable, the data in the corresponding physical address is discarded; if the read logical address is available, the corresponding physical address data is read, and the data and mapping relationship are written into a new physical block, and the current physical block is erased.

3. The hardware acceleration method for comparing available logical address blocks for SSD garbage collection according to claim 1, characterized in that: The L2P table is stored in DRAM.

4. The hardware acceleration method for comparing available logical address blocks for SSD garbage collection according to claim 1, characterized in that: The hardware acceleration module compares whether the logical address in the P2L page is available in the L2P table through an independent bus.

5. The SSD garbage collection available logical address table comparison hardware acceleration method according to claim 2, characterized in that: If the logical address is unavailable, it indicates that the physical address data corresponding to the logical address has been overwritten, and the data in the physical address is discarded.

6. The SSD garbage collection available logical address comparison hardware acceleration method according to claim 2, characterized in that: The data in the physical address in the available identification register of the hardware acceleration module is read, and the read data and the mapping relationship are written into a new physical block.

7. The SSD garbage collection available logical address comparison hardware acceleration method according to claim 6, characterized in that: The data in the physical address in the available identification register of the hardware acceleration module is read, and the read data and the mapping relationship are written into the new physical block until the available identification register indicates that all physical position comparison processing of the physical block currently garbage collected is completed.

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