Memory management method and device of security chip and electronic equipment

Abstract

The embodiment of the invention relates to a memory management method and device of a security chip and electronic equipment, a plurality of cards are integrated on the security chip, the plurality of cards share the physical space of a non-volatile memory (NVM) of the security chip, and the NVM virtual space corresponding to each card is isolated through a firewall. The NVM virtual space and the NVM physical space correspond to each other and are the same in size; the method comprises the following steps: in response to a received request for writing data into a target virtual address, writing the data into a cache region corresponding to a currently running target card; the data in the cache region is written into the NVM physical space in response to the fact that NVM writing conditions are met, and the NVM writing conditions include receiving of a transaction submission request, page crossing and active submission of a user. By adopting the technical scheme, the multi-card memory management of the security chip is realized, the erasing frequency is reduced, the read-write speed is increased, the read-write performance is improved, and the service life is prolonged.

Description

Technical Field

[0001] The present disclosure relates to the technical field of memory management, and in particular to a memory management method, device and electronic device for a security chip. Background Art

[0002] At present, with the increasing integration of chips, it is a general trend to integrate SE (Subscriber Entity) and ESIM (Embedded Subscriber Identity Module) into the same security chip. The security chip has only one NVM (Non-Volatile Memory) memory, and the internal resources are relatively scarce. If multiple cards are to be integrated into the security chip, the operating performance of the chip and the service life of the underlying Flash need to be guaranteed. In this scenario, it is very necessary to provide a memory management system that supports multiple cards, has good read and write performance, and has a long service life. Summary of the invention

[0003] In order to solve the above technical problem or at least partially solve the above technical problem, the present disclosure provides a memory management method, device and electronic device for a security chip.

[0004] In a first aspect, an embodiment of the present disclosure provides a memory management method for a security chip, wherein a plurality of cards are integrated on the security chip, and the plurality of cards share a non-volatile memory NVM physical space of the security chip, the NVM physical space corresponds to an NVM virtual space, the NVM virtual space corresponds to the NVM physical space and has the same size, the NVM virtual space includes a rotation area space and a non-rotation area space, the rotation area space includes a user area space and a transaction backup area space corresponding to each card, the rotation area spaces of different cards are isolated by a system firewall, the system firewall is used to ensure that data of different cards will not be accessed by each other, the non-rotation area space includes a log area space corresponding to each card, the rotation area space and the non-rotation area space are isolated by a rotation area firewall, and the rotation area firewall is used to ensure that addresses outside the rotation area space do not participate in the rotation; the method comprises:

[0005] In response to receiving a request to write data to a target virtual address, writing the data into a buffer area corresponding to a currently running target card;

[0006] In response to satisfying a write NVM condition, the data in the cache area is written into the NVM physical space, wherein the write NVM condition includes receiving a transaction commit request, cross-page, and user-initiated commit.

[0007] In a second aspect, an embodiment of the present disclosure provides a memory management device for a security chip, wherein a plurality of cards are integrated on the security chip, wherein the plurality of cards share a non-volatile memory NVM physical space of the security chip, wherein the NVM physical space corresponds to the NVM virtual space, wherein the NVM virtual space corresponds to and has the same size as the NVM physical space, wherein the NVM virtual space includes a rotation area space and a non-rotation area space, wherein the rotation area space includes a user area space and a transaction backup area space corresponding to each card, wherein the rotation area spaces of different cards are isolated by a system firewall, wherein the system firewall is used to ensure that data of different cards are not accessed by each other, wherein the non-rotation area space includes a log area space corresponding to each card, wherein the rotation area space is isolated from the non-rotation area space by a rotation area firewall, wherein the rotation area firewall is used to ensure that addresses outside the rotation area space do not participate in the rotation; the device comprises:

[0008] A first writing module, configured to write the data into a buffer area corresponding to a currently running target card in response to receiving a request to write data to a target virtual address;

[0009] The second writing module is used to write the data in the cache area into the NVM physical space in response to satisfying the writing NVM condition, wherein the writing NVM condition includes receiving a transaction commit request, cross-page and user active commit.

[0010] In a third aspect, an embodiment of the present disclosure provides an electronic device, comprising: a processor; a memory for storing executable instructions of the processor; the processor is used to read the executable instructions from the memory and execute the executable instructions to implement the memory management method of the security chip as described in the first aspect.

[0011] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium, wherein the storage medium stores a computer program, and the computer program is used to implement the memory management method of the security chip as described in the first aspect.

[0012] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0013] The memory management scheme of the security chip provided by the embodiment of the present disclosure is as follows: the security chip is integrated with multiple cards, the multiple cards share the non-volatile memory NVM physical space of the security chip, the NVM physical space corresponds to the NVM virtual space, the NVM virtual space corresponds to the NVM physical space and has the same size, the NVM virtual space includes a rotation area space and a non-rotation area space, the rotation area space includes a user area space and a transaction backup area space corresponding to each card, the rotation area spaces of different cards are isolated by a system firewall, the system firewall is used to ensure that data of different cards will not be accessed by each other, the non-rotation area space includes a log area space corresponding to each card, the rotation area space and the non-rotation area space are isolated by a rotation area firewall, and the rotation area firewall is used to ensure that addresses outside the rotation area space do not participate in rotation; in response to receiving a request to write data to a target virtual address, the data is written to a cache area corresponding to the currently running target card; in response to satisfying a write NVM condition, the data in the cache area is written to the NVM physical space, wherein the write NVM condition includes receiving a transaction commit request, cross-page, and user active commit. By adopting the solution disclosed in the present invention, although there is only one NVM on a security chip, the NVM virtual space between different cards is isolated by the system firewall, so that the data of different cards will not be accessed by each other, and the compatibility of multiple cards is achieved, thereby realizing the multi-card memory management of the security chip; and when data is written, the cache area is first used to cache the data first, and the NVM is not written directly. The data is written to the NVM only when the conditions for writing to the NVM are met, which reduces the number of erase and write times while increasing the read and write speed, improves the read and write performance, and also helps to extend the service life. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0015] Figure 1 A schematic diagram of a flow chart of a memory management method of a security chip provided by an exemplary embodiment of the present disclosure;

[0016] Figure 2 A schematic diagram of a MAP-based workflow of an exemplary embodiment of the present disclosure is shown;

[0017] Figure 3 A schematic diagram of a WB-based workflow of an exemplary embodiment of the present disclosure is shown;

[0018] Figure 4 A schematic flow chart of a memory management method of a security chip provided by another exemplary embodiment of the present disclosure;

[0019] Figure 5 A schematic diagram showing a storage format of a hardware HE according to an exemplary embodiment of the present disclosure is shown;

[0020] Figure 6 A schematic diagram showing NVM space allocation and mapping relationship under multiple OSs according to an exemplary embodiment of the present disclosure is shown;

[0021] Figure 7 A transaction LOG workflow diagram of an exemplary embodiment of the present disclosure is shown;

[0022] FIG. 8( a ) shows a schematic diagram of a standard writing process based on a rotation mechanism according to an exemplary embodiment of the present disclosure. Figure 1 ;

[0023] FIG. 8( b ) shows a schematic diagram of a standard writing process based on a rotation mechanism according to an exemplary embodiment of the present disclosure. Figure 2 ;

[0024] FIG. 8( c ) shows a schematic diagram of a standard writing process based on a rotation mechanism according to an exemplary embodiment of the present disclosure. Figure 3 ;

[0025] FIG9(a) shows a schematic diagram of a transaction write process based on a rotation mechanism according to an exemplary embodiment of the present disclosure. Figure 1 ;

[0026] FIG. 9( b ) shows a schematic diagram of a transaction write process based on a rotation mechanism according to an exemplary embodiment of the present disclosure. Figure 2 ;

[0027] FIG9(c) shows a schematic diagram of a transaction write process based on a rotation mechanism according to an exemplary embodiment of the present disclosure. Figure 3 ;

[0028] FIG. 9( d ) shows a schematic diagram of a transaction write process based on a rotation mechanism according to an exemplary embodiment of the present disclosure. Figure 4 ;

[0029] FIG. 10( a ) shows a context management relationship diagram of an SE card according to an exemplary embodiment of the present disclosure;

[0030] FIG10( b ) shows a context management relationship diagram of an ESIM card according to an exemplary embodiment of the present disclosure;

[0031] FIG10( c ) shows a schematic diagram of a common interface of an exemplary embodiment of the present disclosure;

[0032] Fig.11 A schematic diagram of NVM read and write logic of SE and ESIM according to an exemplary embodiment of the present disclosure is shown;

[0033] Fig.12 A schematic diagram of the structure of a memory management device of a security chip provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0035] It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0036] The term "including" and its variations used herein are open inclusions, i.e., "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

[0037] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0038] It should be noted that the modifications of "one" and "plurality" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0039] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0040] As long as the security chip involves flash erasing and writing, the read-write performance and service life issues must be considered, and the flash needs to be simulated as an electrically erasable programmable read-only memory (EEPROM, also known as E2PROM). In addition, as the integration of multiple cards into the same security chip becomes a general trend, the integration of multiple cards requires solving the compatibility issues of multiple memory systems on a single chip, such as the coexistence of SE and ESIM, and spatial scalability.

[0041] In response to the above problems, the present invention provides a multi-OS high-performance and long-life security chip memory management system, which can realize an analog E2PROM management system that combines software and hardware in multiple dimensions, can significantly improve the reading and writing speed of Java objects, balance Flash erase and write, and make full use of its life. Multiple cards can coexist on one chip, such as SE and ESIM, which reduces costs, has a fast response speed, and can dynamically adjust the space.

[0042] The memory management method, device and electronic device of the security chip provided by the present disclosure are explained in detail below with reference to the accompanying drawings.

[0043] Figure 1 A flow chart of a memory management method for a security chip provided by an exemplary embodiment of the present disclosure is provided. The method can be executed by a memory management device for a security chip provided by an embodiment of the present disclosure. The device can be implemented by software and / or hardware and can be integrated in an electronic device. The electronic device is a device integrated with a security chip, wherein a plurality of cards are integrated on the security chip, and the plurality of cards share a non-volatile memory NVM physical space of the security chip. The NVM physical space corresponds to an NVM virtual space. The NVM virtual space includes a rotation area space and a non-rotation area space. The rotation area space includes a user area space and a transaction backup area space corresponding to each card. Different The rotation area space of the card is isolated by a system firewall. The system firewall is used to ensure that the data of different cards will not be accessed by each other. The non-rotation area space includes the log area space corresponding to each card. The rotation area space and the non-rotation area space are isolated by the rotation area firewall. The rotation area firewall is used to ensure that the addresses outside the rotation area space do not participate in the rotation. In addition, the system firewall and the rotation area firewall can be adjusted dynamically. The size of the NVM virtual space of each card can be dynamically adjusted according to the product and demand. The firewall is set. The NVM virtual space corresponds to the NVM physical space and has the same size. One card is an operating system OS (Operation System).

[0044] like Figure 1 As shown, the memory management method of the security chip may include the following steps:

[0045] Step 101, in response to receiving a request to write data to a target virtual address, write the data into a buffer area corresponding to a currently running target card.

[0046] In the disclosed embodiment, all cards on the security chip share a piece of NVM memory, and the NVM physical space is divided into multiple parts from the virtual address. Each part is isolated by a firewall. The firewall boundary is dynamically adjustable and used by different cards. The NVM size of each card can be adjusted by sending instructions according to different product models. Based on the real-time operating system RTOS (Real Time Operate System), each card belongs to a different task. Each card integrated on the security chip is integrated on the security chip in the form of an independent context. Card switching can be achieved by switching contexts. Although all cards on the security chip use the same set of NVM read and write logic, the data is independent, thereby realizing the coexistence of multiple cards on a security chip and its firewall isolation. As long as the Flash space is sufficient, more cards can be accommodated. For the public resources on the security chip, critical areas are used for protection. That is to say, when a card on the security chip uses public resources, the public resources will be protected by critical areas, so that other cards cannot use the public resources. When the public resources are released from the critical area, other cards can use the public resources.

[0047] In this embodiment, the virtual address of the NVM virtual space and the physical address of the NVM physical space are mapped to each other. For example, the NVM physical address can be directly mapped to the specified virtual address through the hardware MAP module, so that the upper-level user can directly obtain the NVM data by accessing the virtual address when reading the data, which greatly improves the read performance. Data reading and writing operations can be performed without converting the virtual address to the physical address, which speeds up the data reading speed. For the virtual address used by the user, there is no need to erase it, it can be written repeatedly and read directly, and all addresses are continuous and can be written directly.

[0048] For example, Figure 2 A schematic diagram of a MAP-based workflow of an exemplary embodiment of the present disclosure is shown. Figure 2 As shown, the NVM physical address can be mapped to the virtual address through the hardware MAP module. The upper-level user directly uses the virtual address 0x022bd000 to write the data 0x1234. Through MAP mapping, the physical address mapped by the virtual address is 0x0c100000, that is, the data 0x1234 can be written to the physical address 0x0c100000 through 0x022bd000, and the data 0x1234 can also be read from the physical address 0x0c100000 through the virtual address 0x022bd000.

[0049] In this embodiment, each card corresponds to a buffer area. When receiving data written by an upper user through a certain virtual address (referred to as a target virtual address for ease of description and distinction), the received data is first written into the buffer area corresponding to the currently running card (referred to as a target card for ease of description and distinction). For example, a hardware WB (Write Buffer) can be used as a buffer area, wherein the hardware WB is a special random access memory (Random Access Memory, RAM) space designed and developed by itself, which can cache 2 pages of non-continuous NVM data and specify the mutual mapping of NVM data. When the upper layer uses the write data, it is written to the buffer area first, thereby reducing the number of NVM erases and writes, and reading data from the buffer area will also be faster. The hardware WB can map the NVM physical address and the buffer area to each other, so that the upper user can access the latest data stored in the WB through the virtual address, rather than the old data of the NVM. In the case where the data in the WB is not submitted to the physical space, the data in the hardware WB is lost when the power is off, and the NVM data will not be changed. The old data will still be on again when the power is on. Hardware WB has the characteristics of fast reading and writing, and does not consume the internal resources of the security chip, which makes up for the deficiency of the current traditional ordinary cache solution that occupies chip resources during operation.

[0050] For example, Figure 3 A schematic diagram of a WB-based workflow of an exemplary embodiment of the present disclosure is shown. Figure 3 As shown in the figure, the hardware WB is mapped to the physical address of the NVM physical space. The data 0x1234 written through the virtual address 0x022bd000 is first written to the cache WB, and then the data in the WB is written to the physical space. Before the data in the WB is written to the physical space, when the data is read through the virtual address 0x022bd000, the data in the WB is read. For the physical address mapped by the WB, whether viewing the data of the virtual address or the physical address, the latest WB data is read. Compared with reading data from the NVM physical space, reading and writing the cache WB will be much faster than reading and writing the NVM physical space.

[0051] Step 102, in response to satisfying a write NVM condition, writing the data in the cache area into the NVM physical space, wherein the write NVM condition includes receiving a transaction commit request, cross-page, and user active commit.

[0052] In this embodiment, when a transaction commit request is received, or when a page is crossed, or when a user actively commits a cache area, it is determined that the write NVM condition is met, and the data in the cache area is written to the NVM physical space. As a result, it is not necessary to write to the NVM every time data is written, thereby reducing the number of read and write times of the NVM and helping to extend the service life.

[0053] The memory management method of the security chip provided by the embodiment of the present disclosure is as follows: a plurality of cards are integrated on the security chip, and the plurality of cards share the non-volatile memory NVM physical space of the security chip; the NVM physical space corresponds to the NVM virtual space; the NVM virtual space corresponds to the NVM physical space and has the same size; the NVM virtual space includes a rotation area space and a non-rotation area space; the rotation area space includes a user area space and a transaction backup area space corresponding to each card; the rotation area spaces of different cards are isolated by a system firewall, and the system firewall is used to ensure that data of different cards will not be accessed by each other; the non-rotation area space includes a log area space corresponding to each card; the rotation area space and the non-rotation area space are isolated by a rotation area firewall, and the rotation area firewall is used to ensure that addresses outside the rotation area space do not participate in rotation; in response to receiving a request to write data to a target virtual address, the data is written to a cache area corresponding to the currently running target card; in response to satisfying a write NVM condition, the data in the cache area is written to the NVM physical space, wherein the write NVM condition includes receiving a transaction commit request, cross-page, and user active commit. By adopting the solution disclosed in the present invention, although there is only one NVM on a security chip, the NVM virtual space between different cards is isolated by the system firewall, so that the data of different cards will not be accessed by each other, and the compatibility of multiple cards is achieved, thereby realizing the multi-card memory management of the security chip; and when data is written, the cache area is first used to cache the data first, and the NVM is not written directly. The data is written to the NVM only when the conditions for writing to the NVM are met, which reduces the number of erase and write times while increasing the read and write speed, improves the read and write performance, and also helps to extend the service life.

[0054] In an optional implementation of the present disclosure, in order to balance the erasing and writing of NVM, the present disclosure provides a rotation mechanism, which includes a physical page index PID (Physical Sector Id) and a virtual page index VID (Virtual Sector Id), which represent the physical NVM page and the virtual NVM page respectively. The corresponding page can be found through the index, and one index uniquely corresponds to one NVM page; VID and PID are mapped to each other through a hardware MAP module. The mechanism also includes an index table, which records the mapping relationship between VID and PID. Each time data is filled into the VID page, an idle PID page will be found, and the data will be written to the hardware WB first, and the WB will be associated with the physical address data. If the VID page is written repeatedly, it is an operation on the WB, and no NVM write will actually be generated. This reduces the number of NVM read and write times and greatly improves its service life. If a cross-page or transaction is submitted, the current WB data is submitted to NVM, and the index indicating idleness is increased by 1 to find a new idle PID mapping. For example, the index of the idle page found last time is VID5. After the cross-page or transaction is submitted, the index of the idle page found next is VID6 through index +1. After power failure, it can be rolled back to the state before power failure. Non-atomic writes can be written normally regardless of whether the transaction is enabled. Through abnormal interrupt management, the data can be restored to the state before power failure when power is restored after power failure.

[0055] Figure 4 A flowchart of a memory management method for a security chip provided by another exemplary embodiment of the present disclosure is shown in FIG. Figure 4 As shown, in Figure 1 Based on the illustrated embodiment, step 101 may include the following sub-steps:

[0056] Step 201 , in response to receiving a request to write data to a target virtual address, determining a target virtual page index corresponding to the target virtual address according to a correspondence between the virtual address and the virtual page index.

[0057] In this embodiment, one virtual address corresponds to one virtual page index, that is, one virtual address corresponds to one virtual NVM page, and one virtual NVM page (represented by the virtual page index) maps to one physical NVM page (represented by the physical page index). When a request to write data to the target virtual address is received, it can be determined that the upper-layer user requests VID write. At this time, the virtual page index corresponding to the target virtual address can be determined based on the correspondence between the virtual address and the virtual page index (referred to as the target virtual page index for ease of description and distinction).

[0058] For example, hardware HE (a special separate Flash) can be used to record important information such as PID, VID, transaction version number, sector version number, etc. The rotation mechanism implements rotation based on the information recorded by HE. The advantage is that it is in a specific hardware address segment, is not mixed with the data area, and does not occupy NVM space. Figure 5 A schematic diagram showing the storage format of a hardware HE according to an exemplary embodiment of the present disclosure is shown. Figure 5 As shown, the hardware HE can record the mapping relationship between PID and VID, as well as the version number of the page, PID inversion, VID inversion, version number inversion and other information. The HE page can be erased by erasing the corresponding NVM page, where the version number is used to record the new and old states of the page. The version number is initialized to 1, and the version number increases by 1 each time the page is written.

[0059] Step 202: determine a free virtual page index.

[0060] It can be understood that when writing data to the target virtual address, the virtual NVM page represented by the target virtual page index corresponding to the target virtual address is not necessarily free. In order to ensure that the data can be written successfully and balance the erasing of the NVM, in this embodiment, the written data can be written to a free NVM page. In this scenario, it is necessary to first determine a free virtual page index.

[0061] As an example, each VID can mark a corresponding status, for example, "0" indicates that the corresponding page has data and is not idle, and "1" indicates that the corresponding page is idle. Then, based on the status marked by each VID, the VIDs of all idle pages can be determined, and then a VID can be randomly selected from the VIDs of all idle pages as the determined idle virtual page index.

[0062] As an example, the status of different VIDs can be recorded by setting a bitmap table. The value of a bitmap is hexadecimal and is used to record the status of 8 VIDs. "0" means that the corresponding page has data and is not idle, and "1" means that the corresponding page is idle. According to the value of the bitmap, it can be determined which VIDs correspond to idle pages, and the smallest VID is selected as the idle virtual page index. For example, if the value of the bitmap is 0xE0, the status of VID7 to VID0 is "11100000" in turn, so it can be determined that vid0 to vid4 all have user data, vid5 to vid7 are idle, and vid5 is preferentially found as the idle page.

[0063] Since multiple cards are integrated on the security chip, when determining the free virtual page index, it is necessary to select from the space corresponding to the currently running target card. Therefore, in an optional implementation of the present disclosure, when determining a free virtual page index, the target user area space, target transaction backup area space and target log area space corresponding to the target card can be determined according to the NVM virtual space corresponding to each card; when the user starts a transaction, the first virtual page index set corresponding to the virtual address of the target transaction backup area space is determined according to the correspondence between the virtual address and the virtual page index, and a free virtual page index is determined from the first virtual page index set; when the user does not start a transaction, the second virtual page index set corresponding to the virtual address of the target user area space is determined according to the correspondence between the virtual address and the virtual page index, and a free virtual page index is determined from the second virtual page index set.

[0064] That is to say, in the disclosed embodiment, the NVM virtual space corresponding to each card includes user area space, transaction backup area space and log area space, the log area space belongs to the non-rotation area space, the user area space and the transaction backup area space belong to the rotation area space, the user area space and the transaction backup area space of the same card do not need to be isolated by a firewall, the user area space and the transaction backup area space of different cards are isolated by a system firewall (OS firewall), the rotation area space and the non-rotation area space are isolated by a rotation area firewall, and the log area spaces of different cards do not need to be isolated by a firewall, wherein the system firewall prevents data between two OSs from accessing each other, and the position of the OS firewall can be adjusted by instructions; the rotation area firewall is a NVM mapping and non-mapping firewall, which prevents the mapping address and the non-mapping address from accessing each other, and the position of the rotation firewall can also be adjusted by instructions to achieve the purpose of adjusting the size of the mapping area. The rotation areas of different cards, the rotation areas and the non-rotation areas are not visible to each other, and a security alarm is triggered if they cross the boundary.

[0065] For example, taking the example of integrating SE and ESIM on a security chip, Figure 6 FIG. 4 shows a schematic diagram of NVM space allocation and mapping relationship under multiple OSs according to an exemplary embodiment of the present disclosure. Figure 6 As shown in the figure, the NVM management of multiple OSes is as follows: the NVM space is divided into three parts: SE, ESIM, and LOG using OS firewalls and rotation zone firewalls. Taking the SE zone as an example, SE consists of the user zone + transaction backup zone. Both SE and ESIM spaces participate in the rotation. The SE_LOG and ESIM_LOG that are separated do not participate in the rotation. LOG is outside the rotation firewall. Figure 6It can be seen that although the space is logically divided into multiple blocks, there is a physical space of the same size corresponding to the logical space, which is connected through MAP mapping; the firewall can modify its position through instructions to meet the product requirements of various scenarios; the life of each sector in the rotation area is the same, which is the sum of the number of erase and write times of all sectors of the current chip, rather than the life of a single sector. The LOG area does not participate in the rotation, and its life is the maximum number of erase and write times of a single sector.

[0066] In this embodiment, the log area space is used to record the processing information of the transaction and implement the power-off support function, such as Figure 7 As shown, a complete set of LOG (log message) is 16 bytes, consisting of an 8-byte transaction version number and an 8-byte version number inverted. After the transaction is started, the 8-byte transaction version number is written in the LOG area, and the 8-byte version number is inverted after the transaction is submitted / terminated. If there is a power outage in the middle, the transaction version number will be incomplete. Therefore, in an optional implementation of the present disclosure, the scheme of the present disclosure also includes: when the user starts the transaction, the transaction version number of the transaction is written into the target log area space; after the transaction is submitted or terminated, the result of the transaction version number inverted is written into the target log area space, wherein the transaction version number and the result of the transaction version number inverted constitute a set of log messages. Based on this, the LOG area is scanned each time the power is turned on, and further processing is performed based on whether the LOG is complete. When the LOG data is incomplete (the inverted result of the transaction version number is missing), the transaction can be rolled back according to the recorded transaction version number to restore to the state before the power outage.

[0067] Step 203 : Determine a first physical page index corresponding to the idle virtual page index and a second physical page index corresponding to the target virtual page index according to a mapping relationship between the virtual page index and the physical page index.

[0068] In this embodiment, there is a mapping relationship between the virtual page index and the physical page index. After the free virtual page index is determined, the physical page index corresponding to the free virtual page index (referred to as the first physical page index for ease of description and distinction) and the physical page index corresponding to the target virtual page index (referred to as the second physical page index for ease of description and distinction) can be determined based on the mapping relationship between VID and PID.

[0069] Step 204 , swap the first physical page index with the second physical page index, and map the first physical page index with the cache area.

[0070] In this embodiment, for the determined first physical page index and the second physical page index, the first physical page index and the second physical page index are exchanged, so that the idle virtual page index is mapped to the second physical page index, and the target virtual page index is mapped to the first physical page index, so that the target virtual address of the written data is mapped to the physical page corresponding to the idle first physical page index, and the data is written to the idle physical page. After the exchange is completed, the first physical page index is mapped to the cache area, so that the data written to the cache area can be submitted to the first physical page.

[0071] Step 205 , write the data and the source data in the physical page corresponding to the second physical page index into the cache area.

[0072] In this embodiment, the source data in the physical page corresponding to the second physical page index and the data newly written through the target virtual address are all written into the cache area.

[0073] Further, in an optional embodiment of the present disclosure, if Figure 4 As shown, step 102 may include the following sub-steps:

[0074] Step 206: In response to receiving a transaction commit request or the cache being full, write the data in the cache into the physical page corresponding to the first physical page index.

[0075] In this embodiment, in response to receiving a transaction commit request or the cache area is full, the data in the cache area is written to the physical page corresponding to the first physical page index, thereby making the source data and the newly written data in the physical page corresponding to the second physical page index both committed to the free physical page.

[0076] Further, in an optional embodiment of the present disclosure, if Figure 4 As shown, the method of the present disclosure may also include the following steps:

[0077] Step 207 : after writing the data in the buffer area into the physical page corresponding to the first physical page index, erasing the source data in the physical page corresponding to the second physical page index.

[0078] In this embodiment, since the source data in the physical page corresponding to the second physical page index has been written into the cache area together with the newly written data, after the data in the cache area is written into the physical page corresponding to the first physical page index, the previous source data is also written into the physical page, so the source data in the physical page corresponding to the second physical page index can be erased, and the writing using this NVM is completed.

[0079] Further, in an optional embodiment of the present disclosure, if Figure 4 As shown, the method of the present disclosure may also include the following steps:

[0080] Step 208 , in response to receiving the transaction termination request, writing the data in the cache area into the physical page corresponding to the first physical page index.

[0081] Step 209 , restore the first physical page index and the second physical page index to restore the mapping relationship between the idle virtual page index and the first physical page index, and restore the mapping relationship between the target virtual page index and the second physical page index.

[0082] In this embodiment, when a user starts a transaction, if a transaction termination request is received, the data in the cache area is written to the physical page corresponding to the first physical page index, and the first physical page index and the second physical page index are restored, so that the idle virtual page index is re-mapped to the first physical page index, and the target virtual page index is re-mapped to the second physical page index, thereby restoring the mapping relationship between the idle virtual page index and the first physical page index, and restoring the mapping relationship between the target virtual page index and the second physical page index.

[0083] The memory management method of the security chip of the present embodiment provides a rotation mechanism to find free pages to write data when data is written, so that the erasing and writing of the NVM is balanced. By adopting the rotation scheme disclosed in the present invention, data is written faster (writing to the cache area) and read faster (reading from the cache area), which greatly improves the performance of the Java virtual machine and supports the recovery of old data (old data is erased only after the new data is actually submitted from the cache area to the physical page). There is no problem of data being in an intermediate state, the number of NVM erasures is reduced, and the erasing and writing of NVM pages will be evenly rotated. On the premise of improving the overall read and write performance of the Java virtual machine, the overall life of the security chip can be fully utilized and the service life is longer.

[0084] Figure 8(a) to Figure 8(c) FIG. 4 shows a schematic diagram of a standard write process based on a rotation mechanism according to an exemplary embodiment of the present disclosure. Figure 8(a) to Figure 8(c)As shown in FIG8(a), the standard write process includes: (1) assuming that the upper-level user writes data to virtual page 0 (VID0); (2) searching for a free page through the bitmap table, where a bit of 0 represents that the page has data and is not free, and a bit of 1 represents that the page is free. The lowest bit of the bitmap corresponds to the minimum value of the VID, that is, bit 0 of the bitmap corresponds to VID0, and so on. From the bitmap 0xE0 in FIG8(a), it can be seen that vid0 to vid4 all have user data, and vid5 to vid7 are free; vid5 is preferentially found as a free page; (3) mapping PID5 corresponding to the free VID5 to the cache WB0, as shown in the left figure of FIG8(b), the new data will be written to WB0; (4) exchanging VID0 and the PID mapped by VID5, that is, VID0 maps to PID5, and VID5 maps to PID10, to achieve a rotation, as shown in the right figure of Figure 8(b). As long as the WB0 data is not written into PID5, the subsequent reading and writing of VID0 are all reading and writing WB0, which will greatly improve the reading and writing speed, because reading and writing WB0 does not cause the Flash to be erased; (5) When the data needs to be written to the Flash, such as when the data has crossed pages or the transaction is committed, the WB0 data is submitted to PID5, and then the PID10 page corresponding to VID5 is erased. The PID10 page becomes free, and WB0 is cleared after the submission is completed, as shown in Figure 8(c); wait for the next mapping request, at which time only one erase occurs. It can be seen from the above process that no matter how many times the data in a page is changed, only one Flash erase actually occurs. Compared with the traditional one-erase-one-write method, the rotation scheme not only greatly improves the reading and writing performance, but also has a qualitative leap in life.

[0085] Figure 9(a) to Figure 9(d) A transaction write process diagram based on a rotation mechanism according to an exemplary embodiment of the present disclosure is shown. Figure 9(a) to Figure 9(d)As shown in FIG9(a), the transaction write process includes: (1) Assuming that the upper-level user starts a transaction and starts atomically writing VID0, in this scenario, the idle page will no longer be found in the idle user area, but in the transaction backup area; (2) Find an idle transaction backup page VID28 from the transaction backup area of ​​the current context (i.e., the currently running card), and mark VID28 as occupied in the backup area bitmap (0XFF becomes 0XEF), as shown in FIG9(a); (3) Map the idle VID28 corresponding to PID28 and WB0, as shown in the left figure of FIG9(b), and the new data will be written to WB0; (4) Exchange the mapping of VID0 and VID28 PID, that is, VID0 is mapped to PID28, and VID28 is mapped to PID10, to achieve a rotation, as shown in the right figure of Figure 9(b); (5) If the user commits the transaction, the data in WB0 is committed to VID0 (PID28), VID28 (PID10) is erased, WB0 is cleared, and the submission is completed, as shown in Figure 9(c); (6) If the user terminates the transaction, the data in WB0 is committed to VID0 (PID28), WB0 is cleared, the VID mapping relationship is restored, VID0 is remapped to PID10, VID28 is remapped to PID28, and the transaction restoration is completed, as shown in Figure 9(d).

[0086] In an optional implementation of the present disclosure, before writing the data in the cache area to the NVM physical space, if a write operation to the target virtual address is received, the data newly written by this write operation is written to the cache area; if a read operation to the target virtual address is received, the data is read from the cache area, thereby making the read and write operations faster and reducing the number of read and write times of the NVM.

[0087] Taking the two cards SE and ESIM integrated in the security chip as an example, SE (se) and ESIM (esim) each have a context, as shown in Figure 10 (a) and Figure 10 (b) respectively. The memory and variables of se and esim do not interfere with each other, and the switching speed is at the task level. They use the public interface provided by the virtual mmu (Memory Management Unit) to achieve the coexistence of SE and ESIM, and respond to request instruction actions at the speed of the task level. The schematic diagram of the public interface is shown in Figure 10 (c).

[0088] Fig.11 The schematic diagram of the NVM read and write logic of the SE and ESIM of an exemplary embodiment of the present disclosure is shown. The SE and ESIM exist in the security chip in the form of independent contexts, and the card is switched by switching the context. Fig.11As shown, when receiving an Application Protocol Data Unit (APDU) message from the upper layer, according to whether the current running card is an SE card or an ESIM card, the APDU message is stored in the task stack of the corresponding card, and the function of reading and writing the NVM of the corresponding card is completed by parsing the virtual address. When writing data, atomic write, non-atomic write and transaction write can be performed, wherein, for transactions, it includes transaction start (Begin), transaction commit (Commit) and transaction termination (Abort). The atomic write / non-atomic write interface implements atomic write / non-atomic write, and the underlying Java virtual machine uses the provided atomic / non-atomic write, transaction and other interfaces, that is, it can use virtual addresses to read and write data, and there is no need to convert addresses for reading and writing; after the atomic write of the transaction is turned on, it can roll back to the state before power failure after power failure and power on again, and non-atomic write can be written normally regardless of whether the transaction is turned on or not, and the abnormal interrupt manager can restore the data to the state before power failure after powering on again. The abnormal interrupt manager consists of two parts: Scan module, which is used to roll back transactions after power-on. The abnormal interrupt caused by power failure during transactions and atomic write processes can be restored to the state before power failure after scanning; Log software module, used in conjunction with Scan module, is used to record transactions and interrupt rollback. Under the rotation mechanism, the erasure and writing of NVM are balanced, and the chip life is extended to the maximum extent; WB caches data first and does not write directly to NVM, which reduces the number of erasures and improves the read and write speed while hardware HE records PID / VID information. The rotation mechanism manages the relationship between blocks based on this information; Therefore, on a security chip, although there is only one NVM, SE / ESIM compatibility is achieved, and more security units can be expanded in the future. Compared with ordinary single SE products, this solution can not only access SE and ESIM data independently, but also dynamically adjust the size of the product space (dynamic firewall), because the two OS have independent contexts, and the switching and response speed of SE and ESIM is at the task level; In addition, the data reading and writing speed is faster, the chip life is longer, and the provided read and write interface also supports transactions and atomic non-atomic operations. The entire system supports power failure and transaction rollback throughout the process.

[0089] According to the above process, the read and write verification performance can be tested on the same security chip; data can be continuously written to the chip with different capacities to verify its lifespan; data integrity and reliability can be verified after abnormal interruption; SE / ESIM compatibility and card cutting real-time performance can be verified through concurrent instructions. If based on the existing common solution, a security chip either supports SIM or ESIM. Even if it supports dual cards, the switching speed may not reach the task level; in terms of lifespan, it is very likely that a page will be erased and written at a high frequency, resulting in bad blocks, affecting normal business, and there is a time loss from virtual to physical address in read and write performance, etc. After testing, using the disclosed solution to manage the NVM space of multiple OSes, both the read and write performance and lifespan have been greatly improved, and the switching between SE and ESIM is task-level response; the read performance is improved by 5-10 times, and the number of erases and writes is reduced by more than 2 times; in terms of lifespan, the common solution is 10w times, and the service life of the disclosed solution is determined by the number of log pages, the number of log pages (taking 2 pages of log as an example) * 10w * (2048 / 32) = 12.80w transactions, and the lifespan is longer if no transaction is opened.

[0090] In summary, the memory allocation and management solution provided by the present disclosure allocates corresponding space and context to SE and ESIM according to the set firewall after power-on initialization, and the card switching function is realized through task and context switching, and the corresponding speed is task level rather than instruction level; when SE services such as wallets and access control are used, the corresponding object data will be read and written at the Java layer, and NVM management has mapping, caching, rotation, interrupt recovery, transactions and atoms, which improves the read and write performance of the Java virtual machine and the service life of the chip. When the security chip uses this memory management solution, in terms of function, when SE / ESIM coexists, the card response is at the task level, the data does not interfere with each other, and the space size of the two products is dynamically adjustable; in terms of performance, the data reading speed is 5 to 8 times that of the traditional solution, and the number of erases and writes is half or even less than that of the traditional solution; in terms of life, the chip will be scrapped only when the life of each page is exhausted to the greatest extent.

[0091] Fig.12A schematic diagram of the structure of a memory management device of a security chip provided by an embodiment of the present disclosure, wherein the device is implemented in software and / or hardware and can be integrated in an electronic device, wherein the electronic device is a device integrated with a security chip, wherein a plurality of cards are integrated on the security chip, and the plurality of cards share the NVM physical space of the security chip, the NVM physical space corresponds to the NVM virtual space, the NVM virtual space corresponds to the NVM physical space and has the same size, the NVM virtual space includes a rotation area space and a non-rotation area space, the rotation area space includes a user area space and a transaction backup area space corresponding to each card, the rotation area spaces of different cards are isolated by a system firewall, the system firewall is used to ensure that data of different cards will not be accessed by each other, the non-rotation area space includes a log area space corresponding to each card, the rotation area space and the non-rotation area space are isolated by a rotation area firewall, and the rotation area firewall is used to ensure that addresses outside the rotation area space do not participate in the rotation.

[0092] like Fig.12 As shown, the memory management device 50 of the security chip may include: a first writing module 510 and a second writing module 520 .

[0093] The first writing module 510 is used to write the data to the target virtual address in response to receiving a request to write the data to the target virtual address, and write the data to the buffer area corresponding to the currently running target card;

[0094] The second writing module 520 is used to write the data in the cache area into the NVM physical space in response to satisfying the write NVM condition, wherein the write NVM condition includes receiving a transaction commit request, cross-page, and user active commit.

[0095] Optionally, the first writing module 510 includes:

[0096] A first determining unit, configured to determine a target virtual page index corresponding to the target virtual address according to a correspondence between the virtual address and the virtual page index;

[0097] A second determining unit, used to determine a free virtual page index;

[0098] A third determining unit, configured to determine a first physical page index corresponding to the idle virtual page index and a second physical page index corresponding to the target virtual page index according to a mapping relationship between the virtual page index and the physical page index;

[0099] A mapping unit, configured to exchange the first physical page index with the second physical page index, and map the first physical page index with the cache area;

[0100] A first writing unit, configured to write the data and source data in a physical page corresponding to the second physical page index into the cache area;

[0101] The second writing module 520 is further used for:

[0102] The data in the cache area is written into the physical page corresponding to the first physical page index.

[0103] Further optionally, the memory management device 50 of the security chip further includes:

[0104] The erasing module is used to erase the source data in the physical page corresponding to the second physical page index after writing the data in the cache area into the physical page corresponding to the first physical page index.

[0105] Optionally, the second determining unit is further configured to:

[0106] Determine the target user area space, target transaction backup area space and target log area space corresponding to the target card according to the NVM virtual space corresponding to each card;

[0107] When a user starts a transaction, a first virtual page index set corresponding to the virtual address of the target transaction backup area space is determined according to the correspondence between the virtual address and the virtual page index, and a free virtual page index is determined from the first virtual page index set;

[0108] When the user does not open a transaction, a second virtual page index set corresponding to the virtual address of the target user area space is determined according to the correspondence between the virtual address and the virtual page index, and a free virtual page index is determined from the second virtual page index set.

[0109] Further optionally, the memory management device 50 of the security chip further includes:

[0110] The log recording module is used to write the transaction version number of the transaction into the target log area space when the user starts the transaction; after the transaction is committed or terminated, the result of negating the transaction version number is written into the target log area space, wherein the transaction version number and the result of negating the transaction version number constitute a group of log messages.

[0111] Optionally, the memory management device 50 of the security chip further includes:

[0112] a third writing module, configured to write the data in the buffer area into a physical page corresponding to the first physical page index in response to receiving a transaction termination request;

[0113] The restoration module is used to restore the first physical page index and the second physical page index to restore the mapping relationship between the free virtual page index and the first physical page index, and to restore the mapping relationship between the target virtual page index and the second physical page index.

[0114] Optionally, the first writing module 510 is further configured to: write data into the cache area in response to receiving a write operation to the target virtual address;

[0115] The memory management device 50 of the security chip further includes:

[0116] The reading module is used to read data from the cache area in response to receiving a read operation on the target virtual address.

[0117] Optionally, each card is integrated on the security chip in the form of an independent context, and the card is switched by switching the context.

[0118] The memory management device of the security chip applied to the electronic device provided in the embodiment of the present disclosure can execute the memory management method of the security chip provided in the embodiment of the present disclosure, and has the functional modules and beneficial effects corresponding to the execution method. The contents not described in detail in the embodiment of the device of the present disclosure can refer to the description in any method embodiment of the present disclosure.

[0119] The embodiments of the present disclosure also provide a computer program product, including a computer program / instruction, which, when executed by a processor, implements the memory management method of the security chip provided by any embodiment of the present disclosure.

[0120] According to one or more embodiments of the present disclosure, the present disclosure provides an electronic device, including:

[0121] processor;

[0122] a memory for storing instructions executable by the processor;

[0123] The processor is used to read the executable instructions from the memory and execute the executable instructions to implement the memory management method of the security chip provided in any embodiment of the present disclosure.

[0124] According to one or more embodiments of the present disclosure, the present disclosure provides a computer-readable storage medium, wherein the storage medium stores a computer program, and the computer program is used to implement the memory management method of the security chip provided in any embodiment of the present disclosure.

[0125] It should be noted that the computer-readable medium disclosed above may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0126] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0127] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0128] The units involved in the embodiments described in the present disclosure may be implemented by software or hardware, wherein the name of a unit does not, in some cases, constitute a limitation on the unit itself.

[0129] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0130] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0131] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present disclosure is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other.

[0132] In addition, although each operation is described in a specific order, this should not be understood as requiring these operations to be performed in the specific order shown or in a sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments individually or in any suitable sub-combination mode.

[0133] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.

Claims

1. A memory management method for a security chip, characterized in that: The security chip is integrated with multiple cards, and the multiple cards share the non-volatile memory NVM physical space of the security chip. The NVM physical space corresponds to the NVM virtual space. The NVM virtual space corresponds to the NVM physical space and has the same size as the NVM physical space. The NVM virtual space includes a rotation area space and a non-rotation area space. The rotation area space includes a user area space and a transaction backup area space corresponding to each card. The rotation area spaces of different cards are isolated by a system firewall. The system firewall is used to ensure that data of different cards will not be accessed by each other. The non-rotation area space includes a log area space corresponding to each card. The rotation area space and the non-rotation area space are isolated by a rotation area firewall. The rotation area firewall is used to ensure that addresses outside the rotation area space do not participate in the rotation. The method comprises: In response to receiving a request to write data to a target virtual address, writing the data into a buffer area corresponding to a currently running target card; In response to satisfying a write NVM condition, the data in the cache area is written into the NVM physical space, wherein the write NVM condition includes receiving a transaction commit request, cross-page, and user-initiated commit.

2. The method according to claim 1, characterized in that The step of writing the data into a buffer area corresponding to the currently running target card includes: Determining a target virtual page index corresponding to the target virtual address according to a correspondence between a virtual address and a virtual page index; Determine a free virtual page index; Determine, according to a mapping relationship between a virtual page index and a physical page index, a first physical page index corresponding to the idle virtual page index and a second physical page index corresponding to the target virtual page index; Exchanging the first physical page index with the second physical page index, and mapping the first physical page index with the cache area; Writing the data and source data in the physical page corresponding to the second physical page index into the cache area; Writing the data in the cache area into the NVM physical space includes: The data in the cache area is written into the physical page corresponding to the first physical page index.

3. The method according to claim 2, characterized in that The method further comprises: After writing the data in the buffer area into the physical page corresponding to the first physical page index, erasing the source data in the physical page corresponding to the second physical page index.

4. The method according to claim 2, characterized in that: The step of determining a free virtual page index includes: Determine the target user area space, target transaction backup area space and target log area space corresponding to the target card according to the NVM virtual space corresponding to each card; When a user starts a transaction, a first virtual page index set corresponding to the virtual address of the target transaction backup area space is determined according to the correspondence between the virtual address and the virtual page index, and a free virtual page index is determined from the first virtual page index set; When the user does not open a transaction, a second virtual page index set corresponding to the virtual address of the target user area space is determined according to the correspondence between the virtual address and the virtual page index, and a free virtual page index is determined from the second virtual page index set.

5. The method according to claim 4, characterized in that The method further comprises: When a user starts a transaction, the transaction version number of the transaction is written into the target log area space; After the transaction is committed or terminated, the result of negating the transaction version number is written into the target log area space, wherein the transaction version number and the result of negating the transaction version number constitute a group of log messages.

6. The method according to claim 2, characterized in that The method further comprises: In response to receiving the transaction termination request, writing the data in the buffer area into the physical page corresponding to the first physical page index; The first physical page index and the second physical page index are restored to restore a mapping relationship between the free virtual page index and the first physical page index, and to restore a mapping relationship between the target virtual page index and the second physical page index.

7. The method according to any one of claims 1 to 6, characterized in that: Before writing the data in the cache area into the NVM physical space, the method further includes: In response to receiving a write operation to the target virtual address, writing data to the cache area; In response to receiving a read operation to the target virtual address, data is read from the cache area.

8. The method according to any one of claims 1 to 6, characterized in that: Each card is integrated on the security chip in the form of an independent context, and the card is switched by switching the context.

9. A memory management device for a security chip, characterized in that: The security chip is integrated with multiple cards, and the multiple cards share the non-volatile memory NVM physical space of the security chip. The NVM physical space corresponds to the NVM virtual space. The NVM virtual space corresponds to the NVM physical space and has the same size as the NVM physical space. The NVM virtual space includes a rotation area space and a non-rotation area space. The rotation area space includes a user area space and a transaction backup area space corresponding to each card. The rotation area spaces of different cards are isolated by a system firewall. The system firewall is used to ensure that data of different cards will not be accessed by each other. The non-rotation area space includes a log area space corresponding to each card. The rotation area space and the non-rotation area space are isolated by a rotation area firewall. The rotation area firewall is used to ensure that addresses outside the rotation area space do not participate in the rotation. The device comprises: A first writing module, configured to write the data into a buffer area corresponding to a currently running target card in response to receiving a request to write data to a target virtual address; The second writing module is used to meet the NVM writing condition and write the data in the cache area into the NVM physical space, wherein the NVM writing condition includes receiving a transaction commit request, cross-page and user active commit.

10. An electronic device, characterized in that: The electronic device comprises: processor; a memory for storing instructions executable by the processor; The processor is used to read the executable instructions from the memory and execute the executable instructions to implement the memory management method of the security chip according to any one of claims 1 to 8.

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