Chain mapping with compression

Abstract

The invention relates to chained mapping with compression. Various applications may include a memory device having a chain mapping with compression of received data. The memory device may include a mapping table having entry locations that associate a virtual page with a physical address of a first stripe of compressed data for the virtual page. A controller of the memory device, in response to the data of the virtual page being compressed data, may load information about a second stripe of the compressed data into an additional position in the first stripe that is different from a position of the compressed data of the virtual page in the first stripe. Additional apparatus, systems, and methods are disclosed.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to electronic devices, and more particularly, to storage memory devices and operations thereof. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices in various manufactured products. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data, and examples of volatile memory include random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), or synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory can retain stored data when power is not supplied, and examples of non-volatile memory include flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory (such as phase change random access memory (PCRAM)), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), and three-dimensional (3D) XPoint TM Memory, etc.

[0003] Various types of memory may be used in applications where manufacturers of consumer products use a memory device architecture that may include one or more memory subsystems with multiple individual storage memory media, where the memory device interacts with a host device to store user data in the one or more memory subsystems of the memory device. The host device and the memory device may operate using one or more protocols that may include standardized protocols. The operation and properties of the memory devices and other electronic devices in the system may be improved by enhancing the programming and design of these electronic devices for their introduction into the system where the electronic devices are desired. Summary of the invention

[0004] In one aspect, the present disclosure relates to a memory device comprising: a mapping table having entry locations associating a virtual page with a physical address of a first stripe of data of the virtual page, the data being arranged in a physical memory of the memory device in multiple stripes; and a controller, responsive to the data of the virtual page being compressed data, loading information about a second stripe of compressed data into an additional location in the first stripe, the additional location being a location in the first stripe different from a location of the compressed data of the virtual page.

[0005] In another aspect, the present disclosure relates to a method of operating a memory device, the method comprising: accessing an indirection table based on a virtual address received in a read request to the memory device from a host device; reading a first stripe of a plurality of stripes of compressed data from a physical memory of the memory device, the plurality of stripes of compressed data corresponding to the read request, reading the first stripe from the physical memory at a physical address listed in the indirection table corresponding to the virtual address; reading a physical address of a next stripe of the plurality of stripes of compressed data from the first stripe; reading the next stripe of compressed data from the physical memory corresponding to the physical address of the next stripe, including reading a physical address of a subsequent stripe of the plurality of stripes of compressed data; sequentially reading remaining stripes of the plurality of stripes except the next stripe, reading each of the remaining stripes from the physical memory at a physical address obtained when a previous stripe was read in the sequential read; and decompressing the compressed data read from the plurality of stripes.

[0006] In another aspect, the present disclosure relates to a method of operating a memory device, the method comprising: accessing an indirection table based on a virtual address received in a write request to the memory device from a host device; compressing data corresponding to a user page size of the write request to generate compressed data; obtaining a physical address of a physical memory from a free space manager of the memory device based on the size of the compressed data, the physical address defining locations of a plurality of stripes to store the compressed data in the physical memory; updating the indirection table with a first physical address of the physical address, the first physical address corresponding to a first stripe of the compressed data; writing a second physical address of the physical address to the first stripe in the physical memory, the second physical address corresponding to a second stripe of the compressed data; sequentially writing remaining stripes of the plurality of stripes except the second stripe to the physical memory, each of the remaining stripes containing a physical address, writing subsequent stripes at the physical address in the sequential writing until a last stripe of the compressed data of a virtual page corresponding to the virtual address is written. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The drawings, which are not necessarily drawn to scale, generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0008] Figure 1 is a representation of the relationship between mapping tables that translate virtual pages from a host to data stripes of a memory device that may be implemented with compressed virtual pages, according to various embodiments.

[0009] Figure 2Representations of data of virtual pages stored in a number of stripes of a storage medium of a memory device are illustrated according to various embodiments, where the data is compressed data.

[0010] Figure 3 A representation of a chained mapping scheme implemented by a linear table having a single entry for compressed data of a given virtual page in a temporary storage device of a memory device, wherein the single entry contains an index to a physical address of a first stripe of compressed data for the given virtual page, according to various embodiments is illustrated.

[0011] Figure 4 is a flow diagram of features of an example method of reading data from a memory device, wherein the data is stored in the memory device as compressed data, according to various embodiments.

[0012] Figure 5 is a flow diagram of features of an example method of writing data to a memory device, wherein the data is stored in the memory device as compressed data, in accordance with various embodiments.

[0013] Figure 6 A block diagram illustrating example component features of a compute fast link system including a chained mapping scheme with compression of user data in accordance with various embodiments.

[0014] Figure 7 Description of various embodiments Figure 6 An instance of a compression zone manager for a computationally fast link controller.

[0015] Figure 8 Description of various embodiments Figure 7 An embodiment of an instance of a table manager of a compression zone manager.

[0016] Fig. 9 is a block diagram of an example system including a host operating with a memory device having one or more memory media, wherein the memory device can implement a chained mapping scheme with compression of user data, according to various embodiments. DETAILED DESCRIPTION

[0017] The following detailed description refers to the accompanying drawings, which show various embodiments in which the present invention can be practiced by way of illustration and not limitation. These embodiments are described in sufficient detail to enable those skilled in the art to practice these and other embodiments. Other embodiments may be utilized, and structural, logical, mechanical and electrical changes may be made to these embodiments. The various embodiments are not necessarily mutually exclusive, because some embodiments may be combined with one or more other embodiments to form new embodiments. Therefore, the following detailed description should not be understood in a limiting sense.

[0018] In order to improve the utilization of physical space in the memory device, a data compression feature may be implemented in the memory device to compress data received from the host. The memory device may include one or more memory media for storing user data. This feature may be structured to compress the data when writing host data and decompress the compressed data when reading in response to a host read request. Compared to a memory device without compression, the compression of user data may change the target capacity of the memory device and provide better physical capacity utilization. Compression may be characterized by a compression ratio, which may depend on the properties of the data blocks used as the basis for storing data in the memory device. Compression may be used to change the data block size of the stored data. For an example unit block size of 4096 bytes, referred to as 4K bytes (4KB), compression may result in storing data in units between a few bytes and 4KB. In conventional methods, additional indirection will be used to locate the data blocks in the memory medium of the memory device after compression.

[0019] The memory devices may be implemented in a number of different memory device architectures. For example, compression may be performed in, but not limited to, a compute express link (CXL) memory device, a solid state drive (SSD), or other memory device. One or more memory devices may be coupled to a host (for example, a host computing device) to store data, commands, and / or instructions for use by the host when the computer or electronic system is operating. Data, commands, or instructions may be transferred between the host and the one or more memory devices during operation of the computing or other electronic system.

[0020] Various protocols or standards may be applied to facilitate communication between a host and one or more other devices (e.g., memory devices, memory buffers, accelerators, or other input / output devices). For example, an out-of-order protocol such as CXL may be used to provide high bandwidth and low latency connectivity. Other protocols may be used in place of or in conjunction with CXL.

[0021] CXL is an open standard interconnect configured for high-bandwidth, low-latency connectivity between host devices and other devices, such as accelerators, memory buffers, and other I / O devices. CXL is designed to facilitate high-performance computing workloads by supporting heterogeneous processing and memory systems. CXL implements coherency and memory semantics on top of Peripheral Component Interconnect Express (PCIe)-based I / O semantics to optimize performance.

[0022] CXL can be used in applications such as artificial intelligence, machine learning, analytics, cloud infrastructure, edge computing devices, communication systems, and elsewhere. Data processing in such applications can use various scalar, vector, matrix, and spatial architectures that can be deployed in central processing units (CPUs), graphics processing units (GPUs), field programmable gate arrays (FPGAs), digital signal processors (DSPs), application specific integrated circuits (ASICs), other programmable logic devices, intelligent network interface cards (NICs), or other accelerators that can be coupled using CXL links. Processing modules such as CPUs can be implemented as host devices or host processors in the architecture of structured CPUs.

[0023] CXL supports dynamic multiplexing using a set of protocols including input / output (CXL.io, based on PCIe), cache (CXL.cache), and memory (CXL.memory) semantics. CXL can be used to maintain a unified, consistent memory space between the CPU and any memory on an attached CXL device. This configuration allows the CPU and CXL devices to share resources and operate on the same memory region to improve performance, reduce data movement, and reduce software stack complexity. In an example, the CPU may be primarily responsible for maintaining or managing consistency in a CXL environment. Therefore, CXL can be utilized to help reduce device cost and complexity, as well as the overhead traditionally associated with consistency across I / O links.

[0024] CXL runs on top of the PCIe physical layer (PHY) and provides full interoperability with PCIe. CXL devices can start link training from PCIe Gen 1 data rates and can negotiate CXL as their operating protocol if their link partner supports CXL. CXL can be used as an operating protocol, for example, using the alternative protocol negotiation mechanism defined in the PCIe 5.0 specification. As a result, devices and platforms can more easily adopt CXL by leveraging the PCIe infrastructure without having to design and validate PHYs, channels, channel extension devices, or other upper layers of PCIe.

[0025] CXL technology can maintain memory consistency between the CPU memory space and the memory on the attached device, which enables resource sharing to improve performance, reduce software stack complexity and reduce overall system cost. Three main types of devices can adopt the CXL interconnect protocol. Type 1 devices may include accelerators, such as smart NICs that typically lack local memory. Via CXL, these type 1 devices can communicate with the memory of the host processor to which they are coupled. Type 1 devices can use CXL.io+CXL.cache protocols. Type 2 devices may include GPUs, ASICs, and FPGAs, which are equipped with tools such as but not limited to double data rate (DDR) memory or high bandwidth memory (HBM) and can use CXL to make the host processor's memory locally available to the accelerator and the accelerator's memory locally available to the host processor. Type 2 devices can also be co-located in the same cache coherent domain and help improve heterogeneous workloads. Type 2 devices can use CXL.io+CXL.cache+CXL.memory protocols. Type 3 devices may include memory devices that can be attached via CXL to provide additional bandwidth and capacity to the host processor. The type of memory is independent of the host's main memory. Type 3 devices can use CXL.io+CXL.memory protocols.

[0026] Compression in a memory device, such as but not limited to a CXL memory device, may be implemented with a mechanism for locating a block of data in a storage medium after compression. The ability to reference data using a reference other than the value of the data itself (for example, to operate on the data by its memory address) is an indirection mechanism. An indirection table may contain entries that are pointers to the location or locations of the data in the storage medium. A linear indirection table may be used for address translation of compressed data. A linear indirection table of a memory device may be arranged to have an entry for each address of a page of data provided by a host device. Such addresses and pages of data are provided by the host device and are independent of the management of the data in the memory device. With respect to the memory device, the host supplied address and page are a virtual address (VA) and a virtual page (VP), which are mapped by the memory device to a physical address (PA). The PA is an address used by the memory device to point to a memory medium (for example, a memory die or a packaged memory die), a row, and a column to store one or more bits of data, wherein the pointing mechanism may include calculations that depend on the type of memory used for the memory medium.

[0027] In a memory device, the user page size may be set equal to 4KB, where the VP is structured to be equal to 64 consecutive PAs of the memory device (64B*64=4096B(4KB)). A media unit of a memory device may be defined as the minimum amount of data that may be written to the memory device. A media unit may be set to 256B. A media unit may be referred to as a stripe. For a user page size of 4KB user data, 16 stripes may be used to store the user data. Other sizes of user pages and sizes of stripes may be used.

[0028] In a first conventional method (first option) of managing data compression in a memory device, a mapping table in the memory device may be implemented as a linear indirect table structured with one entry (e.g., 4K) for each user block. The entry may include a starting PA of a data stripe in a storage medium of the memory device and a count (specified number) of consecutive PAs storing compressed data after the starting PA. Optionally, the entry of the starting PA may be an index, where the count identifies the next specified index. The index may be a pointer to a location in a table with a stripe of PAs. This first option may provide a relatively small mapping table, but may result in the implementation of defragmentation. Defragmentation is a process of freeing up storage space. In this first option, defragmentation in the memory device may be challenging and complex. For example, in the first option, defragmentation may be used to create free consecutive data stripes, which may introduce complexity to the compression procedure.

[0029] In a second conventional option, the use of defragmentation may be avoided by having an entry for each VA in a linear indirection table that contains the PA for each entry corresponding to data written by a given VA. Optionally, the entry for the PA associated with a given VA may be a set of indexes, where each index may point to a location in a table that has a stripe with a different PA for each index. However, in this second option, this indirection table is a mapping table that may be significantly increased in size compared to the first option. For a user page size of 4KB and a stripe size of 256B, the mapping table size for the second option may be 16 times the mapping table size for the first option.

[0030] In various embodiments, a chain mapping scheme that translates VA to PA in a memory storage device may be implemented for data that can be compressed. The mapping table size may depend on the compression ratio of the data to be written to the memory storage device. Depending on the compression ratio of the selected compression program, a compressible page may be compressed into a number of stripes that is less than the number of stripes in which the data of the page is stored in an uncompressed format. If the page can be compressed, the mapping table may have a PA for the first stripe to store the compressed data of the page in the memory medium of the memory device. For the compressed data of the VP in the chain mapping scheme, the mapping table for the VA of the VP may have a single entry, where the PAs of the stripes other than the first stripe are stored in the physical memory of the memory medium. By storing the compressed data of the VP in a series of stripes, the PAs of subsequent stripes of the series are stored in additional locations of the previous stripes of the series. The additional locations may be reserved bits of the physical memory of the memory medium. The chain mapping scheme may be viewed as a chain mechanism with a linear table of the PAs of the first stripe of the compressed data of the VP and where the next stripe information is stored in additional bits of the current stripe.

[0031] Figure 1 1 is a representation 100 of a relationship between mapping tables 105 that translate VPs from a host to data stripes of a memory device that may be implemented with compressed VPs. Representation 100 shows an entry 107 of mapping table 105 corresponding to data entry 104 of a VP for a VA. Entry 107 includes a PA for a first stripe 125 of data corresponding to compressed data for the VP. First stripe 125 may contain a PA for a next stripe 126 of compressed data for the VP. Next stripe 126 may contain a PA for a subsequent stripe 127 of compressed data for the VP. Thus, when defining a stripe containing compressed data for a VP for a VA that corresponds to a PA in entry 107 of mapping table 105, the stripe may be accessed from a chain of PAs for stripes within the chain of stripes. Although for Figure 1 The chained representation 100 shows three stripes, but the number of stripes used to store compressed data for the VP may be more or less than three depending on the compression result of the VP, the size of the user data page of the VP, and the size of the stripes used by the memory device to store data in the memory medium of the memory device.

[0032] With the PA of the compressed data stripe associated with the VA of the VP from the single entry 107 of the mapping table 105, the mapping table 105 may be implemented as a linear indirect table and the size of the mapping table 105 may be approximately the same as the size of the linear table in the first conventional option mentioned above. However, the single entry 107 of the mapping table 105 does not include an additional bit to identify in the mapping table 105 a count of additional stripes to store compressed data structured as in the first option.

[0033] Figure 2200 illustrates data of a VP stored in a plurality of stripes of a memory medium of a memory device, wherein the data is compressed data. The VP from the host may be stored in one or more buffers (buffer(s)) 204 for writing to the memory medium of a memory cache. The buffer(s) 204 may be implemented in different structural formats that may hold or cache data for further processing. The VP has a VA that may be associated with a PA that may be stored in an entry of a mapping table 205, which may be similar to Figure 1 The linear indirect table of the mapping table 105 of FIG. 104 , wherein the PA may be the PA of the first stripe in the physical memory of the storage medium, the first stripe to store data after the storage device compresses the received VP. Figure 2 , the PA of the first stripe is stored in entry 207 of mapping table 205, and the PA of subsequent stripes is stored in additional locations in the physical memory of the storage medium of the memory device. The additional locations are additional data bits of the storage medium and may be reserved bits of the storage medium.

[0034] A memory device without compression support may include additional reserved bits in its memory media for storing metadata and key identification (key ID). Metadata is data about other data. Metadata may be structured to reference data that can be used to characterize and identify the attributes of the data it describes, which may be user data stored in a stripe of the memory media. Key IDs may be used for security to support data security. By writing data with key IDs at specific locations in the data, a scheme may be implemented to check specific locations when reading data in response to a read request from a host, the host passing the key of the read request to the memory device. If the key of the read request matches the key ID at the specific location of the requested storage data, the memory device may send the requested data to the host, or if a mismatch is determined in the comparison of the key and the key ID, the requested data will not be sent to the host, i.e., the requested data cannot be accessed. Key IDs may be used for encryption and decryption in the memory device. Key IDs may be an optional feature in the memory device. Stripes of data storing VPs may be structured with spare bits to store metadata, key IDs, and error correction codes (ECCs) as well as user data blocks (UDBs) in the stripe. Since the key ID and metadata are stored at the granularity of the entire user data block size of the VP, a stripe of compressed data containing the key ID and metadata can be implemented using a complete set of spare bits, typically formatted as extra reserved bits for storing metadata and key ID, without having the key ID and metadata in each stripe of compressed data. The extra reserved bits in a stripe of compressed data for a given VP can be used to store the PA of the next stripe in a series of stripes of compressed data for the given VP. Each stripe in a series of stripes of compressed data can contain the PA of the next stripe, except for the last stripe in the series. The last stripe in the series terminates the chain of PAs that defines the series of stripes.

[0035] Figure 2 A chain mapping scheme implemented by a linear table 205 is illustrated, the linear table 205 having a single entry for compressed data of a given VP, wherein the single entry contains the PA of the first stripe of the VP, and a chaining mechanism that stores the next stripe information in an extra bit of the current stripe in the set of stripes of compressed data of the VP. As discussed, the linear table 205 includes in entry 207 the PA of the first stripe 225 of compressed data of the VP at the buffer(s) 204. The first stripe 225 may include a segment 221-1 for UDB, a segment 222-1 for ECC, and a segment 223-1 in an extra position. Other information of the data of the VP may be located in the segment 222-1 or the segment 223-1, such as, but not limited to, a cyclic redundancy check (CRC) of the data. The segment 223-1 in an extra position of the first stripe 225 may include the next PA of the next stripe 226.

[0036] The next stripe 226 may include a section 221-2 for UDB, a section 222-2 for ECC, and a section 223-2 at an additional position. Other information of the data of the VP may be located in the section 222-2 or the section 223-2, such as but not limited to the CRC of the data. The section 223-2 at an additional position of the next stripe 226 may include a subsequent PA of the subsequent stripe 227.

[0037] Subsequent stripe 227 may include segment 221-3 for UDB, segment 222-3 for ECC, and segment 223-3 for additional position. Other information for the data of the VP may be located in segment 222-3 or segment 223-3, such as, but not limited to, a CRC of the data. If there is another subsequent stripe, segment 223-3 for additional position of subsequent stripe 227 may include the PA of the other subsequent stripe. If subsequent stripe 227 is the last stripe containing compressed data for a given VP, the additional position of subsequent stripe 227 does not include the PA of the other subsequent stripe. The absence of a PA in the reserved bits of a stripe, such as subsequent stripe 227, identifies the end of the PA chain for compressed data of a given VP. Alternatively, a fixed code in the bits of the additional position reserved for PA may identify the end of the PA chain for compressed data of a given VP.

[0038] Figure 3 A representation 300 illustrating a chain mapping scheme implemented by a linear table 305 having a single entry of compressed data for a given VP in a temporary storage device 304 of a memory device, wherein the single entry contains an index of the PA of the first stripe of compressed data for the given VP. The temporary storage device 304 may be a buffer(s) or other similar functional structure. The entry of the linear table 305 may contain an index that serves as a pointer to the location of a set 311 of PAs. In Figure 3 In this non-limiting example of , the VP in temporary storage 304 is one of set 303 of VPs and has a VA corresponding to index 4 in entry 307, where index 4 points to position 4 in set 311 of PAs. The PA at position 4 is the PA of stripe 325 of compressed data. Stripe 325 of compressed data may include an additional position of a pointer 309 that may hold the index position of the PA of the next stripe of compressed data. Figure 3 In this non-limiting example of , pointer 309 points to index position 14 of set of PAs 311. The PA at position 14 of set of PAs 311 identifies the next stripe of compressed data, which may include a pointer to the PA to determine the subsequent stripe. The chained structure uses an index or pointers to an index into the stripe of compressed data for a given VP until the last stripe in the series of stripes for a given VP is reached.

[0039] Figure 44 is a flow chart of features of an embodiment of an example method 400 for reading data from a memory device, wherein the data is stored in the memory device as compressed data. A controller of the memory device may be used to manage providing data from the compressed data and managing a read program. The read program may be managed by a processing circuit system of the controller that may execute instructions stored in the memory device. The controller may be implemented as one or more processing devices that may execute instructions stored in the memory device and control the circuit system of the memory device to execute the stored instructions. At 410, an indirect table is accessed based on a VA received in a read request from a host to the memory device. The read request may be a request for one or more blocks of a complete VP of data, wherein each block has the size of a data stripe in a memory medium of the memory device. If the indirect table is not cached, the indirect table may be accessed by loading the indirect table.

[0040] At 420, a first stripe of the plurality of stripes of compressed data is read from a physical memory of the memory device. The plurality of stripes of compressed data corresponds to a read request, wherein the first stripe is read from a PA listed in an indirection table corresponding to a VA. Each stripe of the plurality of stripes may have a size of, but is not limited to, 64 bytes.

[0041] At 430, a PA of a next stripe of the plurality of stripes of compressed data is read from the first stripe. At 440, a next stripe of compressed data is read from a physical memory corresponding to the PA of the next stripe, including reading a PA of a subsequent stripe of the plurality of stripes of compressed data. At 450, remaining stripes of the plurality of stripes except the next stripe are sequentially read. Each of the remaining stripes is read from a PA obtained when the previous stripe is read in the sequential read. At 460, compressed data read from the plurality of stripes is decompressed. Uncompressed data may be sent to a host.

[0042] Variations of method 400 or methods similar to method 400 may include several different embodiments that may be combined depending on the application of such methods and / or the architecture of the system including the electronic device implementing such methods. Such methods may include placing additional read requests for data corresponding to the VA in the progress list. Variations may include, while reading the first stripe of compressed data, reading the PA of the next stripe through pins of the memory subsystem of the memory device, where the pins are used for a function different from transmitting user data. These pins may be data mask inversion (DMI) pins of one or more memory media of the memory device. DMI is a dual-purpose bidirectional signal used to indicate data to be masked, and data to be inverted on the bus. For data bus inversion (DBI), depending on the architecture of the memory media, the DMI signal may be driven high when the data on the data bus is inverted, and the DMI signal may be driven low when the data is in its normal state, or vice versa. DBI may be disabled via a mode register setting of the memory media.

[0043] A variation of method 400 or a method similar to method 400 may include decompressing the compressed data after reading all of the compressed data of the plurality of stripes of compressed data from the physical memory of the memory device. A variation may include copying the uncompressed data generated after reading the plurality of stripes from the physical memory to one or more caches of the memory device or one or more read buffers of the memory device.

[0044] Figure 5 1 is a flow chart of features of an embodiment of an example method 500 for writing data to a memory device, wherein the data is stored in the memory device as compressed data. A controller of the memory device may be used to manage providing compressed data and a write procedure. The write procedure may be managed by a processing circuitry of the controller that may execute instructions stored in the memory device. The controller may be implemented as one or more processing devices that may execute instructions stored in the memory device and control the circuitry of the memory device to execute the stored instructions.

[0045] At 510, an indirection table is accessed based on a VA received in a write request from a host device to a memory device. The indirection table may be accessed by loading the indirection table for processing or may be accessed from a cache. The indirection table in the cache may include a first PA corresponding to the VA.

[0046] At 520, data corresponding to a user page size of a write request is compressed to generate compressed data. The user page size may be, but is not limited to, 4 KB. At 530, a PA of a physical memory is obtained from a free space manager of a memory device based on the size of the compressed data. The PA defines locations of multiple stripes to store the compressed data in the physical memory. At 540, an indirect table is updated with a first PA in the PA. The first PA corresponds to a first stripe of the compressed data.

[0047] At 550, a second PA among the PAs is written to the first stripe in the physical memory, the second PA corresponding to the second stripe of compressed data. At 560, the remaining stripes among the plurality of stripes, except the second stripe, are sequentially written to the physical memory. Each of the remaining stripes contains a PA at which a subsequent stripe is written in the sequential write until the last stripe of compressed data corresponding to the VP of the VA is written.

[0048] Variations of method 500 or methods similar to method 500 may include several different embodiments that may be combined depending on the application of such methods and / or the architecture of the system including the electronic device implementing such methods. Such methods may include writing the first stripe, the second stripe, and the remaining stripes into physical memory along with the PAs of subsequent stripes of compressed data by writing the PAs in each stripe to reserved bit locations in each stripe. Variations may include writing the PAs of subsequent stripes into the previous stripe using pins of a memory subsystem of a memory device, where the pins are used for a function different from transferring user data. These pins may be DMI pins of one or more memory media of the memory device.

[0049] A variation of method 500 or a method similar to method 500 may include performing an invalidation procedure to free up a PA for future use. Prior to compressing data corresponding to a write request, the PA of a VA mapped to an accessed indirect table may be passed to a free space manager. The PA of a stripe chain associated with the PA of the VA mapped to the accessed indirect table may be obtained by the free space manager traversing the chain and identifying the PA in each stripe in the chain except for the last stripe of the chain. In response to obtaining the PA, the free space manager may free up a storage location for use in a future write request.

[0050] The chain mapping scheme of memory devices as discussed herein can be implemented in several different applications of electronic devices. Electronic devices, such as mobile electronic devices (e.g., smart phones, tablet computers, etc.), electronic devices used in automotive applications (e.g., automotive sensors, control units, driver assistance systems, passenger safety or comfort systems, etc.), and Internet-connected equipment or devices (e.g., Internet of Things (IoT) devices, etc.) have storage requirements that vary depending on, among other things, the type of electronic device, the usage environment, performance expectations, etc. An electronic device can be divided into several main components: a processor (e.g., a central processing unit (CPU) or other main processor); a memory (e.g., one or more volatile or non-volatile random access memory (RAM) memory devices, such as DRAM, mobile or low-power double data rate synchronous DRAM (DDR SDRAM), etc.); and a storage device (e.g., a non-volatile memory (NVM) device, such as flash memory, ROM, SSD, MMC or other memory card structures or assemblies, etc.). Such electronic devices may be associated with a range of architectures, including CXL systems and managed memory systems, and SSDs, Universal Flash Storage (UFS) devices, and other devices that may be included in CXL systems or managed memory systems. TM ) and embedded multimedia card (eMMC TM) device. Such electronic devices may also include processing circuitry, such as one or more of a memory handling device, a direct memory access (DMA) controller, and a flash memory interface circuitry, to manage access to the physical memory media. Many such electronic devices may include a user interface (e.g., a display, a touch screen, a keyboard, one or more buttons, etc.), a graphics processing unit (GPU), power management circuitry, a baseband processor, or one or more transceiver circuits, etc.

[0051] Figure 6 is a block diagram of an embodiment of example component features of a CXL system 600 including a linked mapping with compression of user data. The CXL system 600 may include a CXL host 635 and a CXL memory device 640 that may operate according to the CXL protocol. The CXL memory device 640 may include a controller 645 that interfaces with the CXL host 635 and a medium 642 of the CXL memory device 640 to write user data directed from the CXL host 635 to the medium 642 using one or more write requests and read user data from the medium 642 for the CXL host 635 using one or more read requests. The execution of the write requests and the read requests may be performed using a linked page mapping scheme with compression of the user data.

[0052] The controller 645 may include a CXL front end (FE) 641 that interfaces with the CXL host 635 using the CXL protocol and a cache manager 643 that manages user data flows associated with read and write requests received from the CXL host 635. The user data may be stored in a medium 642, where the medium 642 may be structured as one or more memory structures arranged as channels for data storage. The user data may be processed with an Advanced Encryption Standard (AES) 647 and ECC 648. Processing the user data with the ECC 648 may be performed by a memory controller (MC) and an interface (INF) 649 that controls input and output of the user data with respect to the medium 642. The user data operated by the AES 647, the ECC 648, and the MC & INF 649 may be compressed data. Compressing the user data and decompressing the user data may be controlled by a compression region manager (CRM) 646.

[0053] Figure 7 illustrate Figure 66. The CRM 646 of the CXL controller 645 of FIG. 646 may include a read buffer 751 to handle user data for read requests and a write buffer 753 to handle user data for write requests. The read buffer 751 and the write buffer 753 may be first-in-first-out (FIFO) structures, which may be implemented in a number of formats including one or more registers or one or more other buffer structures that may cache user data. Data from the read buffer 751 and the write buffer 753 may be directed to the table manager 755 and the compression logic 759 through a multiplexer (MUX) 752. The CRM 646 also includes a decompression logic 758 to decompress received compressed read data using logic circuitry within the decompression logic 758, where the compressed read data is compressed data received from the media 642 in response to the read request. If the input user data meets the compression criteria, the compression logic 759 may use the received compression ratio data to compress the input user data using logic circuitry within the compression logic 759. The criteria may be provided in the compression ratio data or from the table manager 755. The compression logic 759 may provide the compressed data to the table manager 755, which may output the compressed data, or may output the compressed data alternatively or in conjunction with the table manager 755. The compression logic 759 may also provide the compression ratio data for subsequent operations associated with compression. The compression logic 759 may be structured to perform compression calculations. In addition to operating on the output of read / write compressed data, the table manager 755 may also operate on read / write mapping data to receive and output read / write mapping data. The table manager 755 may be operable to manage a chained mapping scheme with compressed data as taught herein.

[0054] Figure 8 illustrate Figure 7866. The table manager 755 may include a register 862. The register 862 may be a FIFO structure, which may be implemented in a number of formats including one or more register structures or one or more other buffer structures that may hold data. The table manager 755 may include one or more tables (table(s)) 867. The table(s) 867 may include tables for mapping and looking up information about cached data and updating mappings associated with read and write requests. The table(s) 867 may operate with the FSM 865 to make the PA available for invalidation processes, including evicting data pages from identified memory locations in response to write operations, as taught herein. The table(s) 867 may include an indirect table for mapping and updating information that translates received VAs with associated PAs as taught herein. Frequently read data may be cached and the table(s) 867 may be used to determine whether this data is currently part of a read or write (read / write) request. The current data of the cached read / write request is determined to be a hit and the current data of the uncached read / write request is determined to be a miss. Table(s) 867 may provide data from lookup hit data, data from lookup miss data, and data of page evictions associated with a mapping for a write operation.

[0055] Fig. 9 is a block diagram of an embodiment of an example system 900 including a host 935 operating with a memory device 940 having one or more memory media, wherein the memory device 940 may implement a chained page mapping scheme with compression of user data in an application implementing the memory device 940. Figure 1 Mapping procedures, Figure 2 and 3 The data structure of Figure 4 and 5 methods and those related to Figures 6 to 8 The chained page mapping scheme is implemented by techniques associated with the functionality of the structure of the system 900. The system 900 and its components can be structured in a number of different arrangements. For example, the system 900 can be arranged to have variations of the types of components including a host 935, an interface 950, a memory device 940, memory media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6, a processing device 945, one or more buffers (buffer(s)) 954, firmware 955, a storage device 944, and a bus 957.

[0056] The host 935 is coupled to the memory device 940 through an interface 950, wherein the host 935 is a host device that may include one or more processors that may vary in type compatible with the interface 950 and the memory device 940. The memory device 940 may include a processing device 945 coupled to memory media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6 through a bus 957, wherein each memory medium has one or more memory cell arrays. The memory media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6 may be implemented as a memory structure that may be selected from different types of memory. Although Fig. 9 , but memory device 940 may be implemented with more or less than six memory media, i.e., memory device 940 may include one or more memory media. The memory media may be implemented in a number of formats including, but not limited to, multiple memory dies or multiple packaged memory dies.

[0057] Processing device 945 may include processing circuitry or be structured as one or more processors. Processing device 945 may be structured as a memory system controller for memory device 940. Processing device 945 may be implemented in a number of different formats. Processing device 945 may include or be structured as one or more types of processors compatible with memory media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6. Processing device 945 may include processing circuitry that may be structured with a digital signal processor (DSP), an application specific integrated circuit (ASIC), other types of processing circuits (including groups of processors or multi-core devices), or a combination thereof.

[0058] The memory device 940 may include firmware 955 having code executable by the processing device 945 to manage at least the memory media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6. The firmware 955 may reside in a storage device of the memory device 940 coupled to the processing device 945. The firmware 955 may be coupled to the processing device 945 using a bus 957 or some other interface on the memory device 940. Alternatively, the firmware 955 may reside in the processing device 945 or may be distributed in the memory device 940 along with firmware components, such as, but not limited to, code, including one or more components in the processing device 945. The firmware 955 may include code having instructions executable by the processing device 945 to operate on the memory media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6. The instructions may include instructions that perform operations to store the user data as compressed data on one or more of the memory media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6 using a chained mapping scheme as taught herein.

[0059] Memory device 940 may include storage device 944 that may be implemented to provide data or parameters for maintaining memory device 940. Storage device 944 may include one or more of a non-volatile memory structure or RAM. Although storage device 944 is Fig. 9 940, but the storage device 944 may be integrated into the processing device 945. The storage device 944 may be coupled to the bus 957 to communicate with other components of the memory device 940. Alternatively, the storage device 944 may be coupled to the processing device 945, wherein the processing device 945 handles the communication between the storage device 944 and the other components of the memory device 940. The storage device 944 may be coupled to the bus 957 and the processing device 945.

[0060] Each of the memory media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6, firmware 955, storage device 944, and other memory structures of memory device 940 are implemented as machine-readable media. Non-limiting examples of machine-readable media may include solid-state memory, optical media, and magnetic media. Specific examples of non-transitory machine-readable media may include: non-volatile memory, such as semiconductor memory media (e.g., EPROM, EEPROM), and flash memory devices; magnetic disks, such as internal hard disks and removable magnetic disks; magneto-optical disks; and compact disc ROM (CD-ROM) and digital versatile disc-read only memory (DVD-ROM) disks.

[0061] Firmware 955, storage device 944, or other components of memory device 940 may include a mapping table with entry locations that associate a VP with the PA of the first stripe of compressed data for the VP. The mapping table may be similar to Figure 1 The processing device 945 may be implemented as a controller to write a second physical address from a set of physical addresses into a first stripe in a physical memory, wherein the second physical address corresponds to a second stripe of compressed data, and sequentially write remaining stripes of the plurality of stripes except the second stripe to the physical memory, wherein each of the remaining stripes contains a physical address at which subsequent stripes are written in the sequential writing until a last stripe of compressed data corresponding to a virtual page of the virtual address is written.

[0062] The firmware 955, storage device 944, or other components of the memory device 940 may have instructions executable by the processing device 945 to operate on user data to store the user data in a compressed format in one or more of the memory media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6. The firmware 955, storage device 944, or other components of the memory device 940 may have instructions executable by the processing device 945 to operate on compressed user data to read and generate uncompressed user data from one or more of the memory media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6.

[0063] Processing device 945 may execute instructions stored on one or more components in memory device 940 that, when executed by processing device 945, cause memory device 940 to perform operations. The operations may include method 400, method 500, methods similar to method 400 or method 500, methods associated with such methods, and methods associated with Figures 6 to 8 The operations may include operations to read data from physical memory of one or more of the storage media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6, where the data is stored in a compressed format.

[0064] The operation may include accessing the indirection table based on the VA received in the read request from the host 935 to the memory device 940. If the indirection table is not cached, the indirection table may be accessed by loading the indirection table. The indirection table may be located in one or more of the buffer(s) 954, firmware 955, storage device 944, or processing device 945.

[0065] The operation may include reading a first stripe of a plurality of stripes of compressed data from a physical memory of the memory device 940, wherein the plurality of stripes of compressed data corresponds to the read request. Each stripe of the plurality of stripes may have a size of, but is not limited to, 64 bytes. The first stripe may be read from a physical memory at a PA listed in an indirect table corresponding to a VA. The operation may include reading a PA of a next stripe of the plurality of stripes of compressed data from the first stripe and reading a next stripe of compressed data from a physical memory corresponding to the PA of the next stripe. The reading of the next stripe includes reading a PA of a subsequent stripe of the plurality of stripes of compressed data. The operation may include sequentially reading the remaining stripes of the plurality of stripes except the next stripe. Each of the remaining stripes is read from a PA obtained when the previous stripe is read in the sequential read. The compressed data read from the plurality of stripes is decompressed. Uncompressed data may be provided to the host 935.

[0066] Operations performed using processing device 945 may include placing additional read requests for data corresponding to the virtual address in a progress list. The progress list may be located in one or more of buffer(s) 954, firmware 955, storage device 944, or processing device 945.

[0067] Operations performed using processing device 945 may include, when reading a first stripe of compressed data, reading the PA of the next stripe through a pin of a memory subsystem of memory device 940. The pin may be a pin used for a function different from transferring user data. The pin may be, but is not limited to, a DMI pin. Operations may include decompressing compressed data after reading all compressed data of a plurality of stripes of compressed data from a physical memory of the memory device. Operations may include copying uncompressed data to one or more caches of the memory device or one or more read buffers of the memory device, the uncompressed data having been generated after reading all of the plurality of stripes from the physical memory. The one or more read buffers may be included in buffer(s) 954.

[0068] Processing device 945 may execute instructions stored on one or more components in memory device 940 that, when executed by processing device 945, cause memory device 940 to perform operations. The operations may include operations that write data in a compressed format to physical memory of one or more of storage media 942-1, 942-2, 942-3, 942-4, 942-5, and 942-6.

[0069] The operation may include accessing an indirection table based on a VA received in a write request from the host 935 to the memory device 940. The indirection table may be accessed by processing to load the indirection table. Alternatively, the indirection table may be accessed in a cache, wherein the indirection table includes a first PA corresponding to the VA.

[0070] The operations performed using the processing device 945 may include compressing data corresponding to a user page size of a write request. The user page size may be, but is not limited to, 4KB. The operations may include obtaining a PA of a physical memory from a FSM of the memory device 940 based on the size of the compressed data. The PA defines the location of multiple stripes to store the compressed data in the physical memory. The operations may include updating an indirect table with a first PA in the PA, wherein the first PA corresponds to a first stripe of the compressed data.

[0071] Operations performed using processing device 945 may include writing a second PA of the PAs to a first stripe in physical memory, wherein the second PA corresponds to a second stripe of compressed data. Operations include sequentially writing remaining stripes of the plurality of stripes, except the second stripe, to physical memory. Each of the remaining stripes contains a PA at which a subsequent stripe is written in a sequential write until a last stripe of compressed data corresponding to the VP of the VA is written.

[0072] Operations performed using the processing device 945 may include, before compressing data corresponding to a write request, passing the PA of the VA mapped to the accessed indirect table to the FSM and obtaining the PA of the stripe chain associated with the PA mapped to the VA in the accessed indirect table by the FSM. The FSM may traverse the stripe chain and identify the PA in each stripe in the chain except the last stripe of the chain. The operations may include the FSM freeing up a location for future write requests.

[0073] The operations performed using the processing device 945 may include writing the PA of the first stripe, the second stripe, and the remaining stripes and subsequent stripes of compressed data into reserved bit positions in each stripe. The operations may include writing the PA of the subsequent stripe into the previous stripe using a pin of the memory subsystem of the memory device 940. The pin may be a pin used for a function different from transmitting user data. The pin may be, but is not limited to, a DMI pin.

[0074] The following are example embodiments according to the systems, devices, and methods taught herein.

[0075] An example memory device 1 may include: a mapping table having an entry location that associates a VP with a PA of a first stripe of data of the VP, the data being arranged into multiple stripes in a physical memory of the memory device; and a controller that, in response to the data of the VP being compressed data, loads information about a second stripe of the compressed data into an additional location in the first stripe, the additional location being a location in the first stripe that is different from a location of the compressed data of the VP.

[0076] Example memory device 2 may include the features of example memory device 1 and may include the information about the second stripe, including the PA of the second stripe.

[0077] The example memory device 3 may include features of any of the aforementioned example memory devices and may include the controller arranged to load information about a third stripe of compressed data into additional locations in the second stripe, the additional locations in the second stripe being an allocation different from the allocation of the compressed data for the VP.

[0078] Example memory device 4 may include the features of example memory device 3 and any of the preceding example memory devices and may include the information about the third stripe, including the PA of the third stripe.

[0079] The example memory device 5 may include features of any of the aforementioned example memory devices and may include a free space manager to enable the PA to be used to write data from a host to a memory subsystem of the memory device.

[0080] Example memory device 6 may include features of any of the aforementioned example memory devices and may include a compute express link (CXL) type 3 memory device.

[0081] In example memory device 7, any of the memory devices described in example memory devices 1-6 may include a memory device incorporated into an electronic device further including a host processor and a communication bus extending between the host processor and the memory device.

[0082] In example memory device 8, any of the memory devices described in example memory devices 1-7 may be modified to include any structure presented in another of example memory devices 1-7.

[0083] In example memory device 9, any apparatus associated with the memory devices described in example memory devices 1-8 may further include a machine-readable storage device configured to store instructions as a physical state, wherein the instructions may be used to perform one or more operations of the apparatus.

[0084] In example memory device 10, any of the memory devices described in example memory devices 1-9 may be operated according to any of example methods 1-20 below.

[0085] An example method 1 for operating a memory device may include: accessing an indirection table based on a VA received in a read request from a host device to the memory device; reading a first stripe of a plurality of stripes of compressed data from a physical memory of the memory device, the plurality of stripes of compressed data corresponding to the read request, reading the first stripe from the physical memory at a PA listed in the indirection table corresponding to the VA; reading a PA of a next stripe of the plurality of stripes of compressed data from the first stripe; reading the next stripe of compressed data from the physical memory corresponding to the PA of the next stripe, including reading a PA of a subsequent stripe of the plurality of stripes of compressed data; sequentially reading remaining stripes of the plurality of stripes except the next stripe, reading each of the remaining stripes from the physical memory at a PA obtained when a previous stripe was read in the sequential read; and decompressing the compressed data read from the plurality of stripes.

[0086] Example method 2 of operating a memory device may include features of example method 1 of operating a memory device and may include placing an additional read request for data corresponding to the virtual address in a progress list.

[0087] Example method 3 of operating a memory device may include features of any of the foregoing example methods of operating a memory device and may include, while reading the first stripe of compressed data, reading the PA of the next stripe through a pin of a memory subsystem of the memory device, the pin being used for a function different from transmitting user data.

[0088] Example method 4 of operating a memory device may include features of any of the preceding example methods of operating a memory device and may include decompressing the compressed data after reading all of the compressed data for the plurality of stripes of compressed data from the physical memory of the memory device.

[0089] Example method 5 of operating a memory device may include features of any of the foregoing example methods of operating a memory device and may include copying uncompressed data generated after reading the plurality of stripes from the physical memory to one or more caches of the memory device or one or more read buffers of the memory device.

[0090] Example method 6 of operating a memory device may include features of any of the foregoing example methods of operating a memory device and may include accessing the indirection table, including loading the indirection table if the indirection table is not cached.

[0091] Example method 7 of operating a memory device may include the features of any of the preceding example methods of operating a memory device and may include each stripe of the plurality of stripes having a size of 64 bytes.

[0092] In example method 8 of operating a memory device, any of example methods 1-7 of operating a memory device may be performed while operating an electronic device further including a host processor and a communication bus extending between the host processor and the memory device.

[0093] In example method 9 of operating a memory device, any of example methods 1-8 of operating a memory device may be modified to include the operations set forth in any other of example methods 1-8.

[0094] In example method 10 of operating a memory device, any of example methods 1-9 of operating a memory device may be implemented at least in part by using instructions stored as a physical state in one or more machine-readable storage devices.

[0095] The example method 11 of operating a memory device may include features of any of the foregoing example methods 1-10 of operating a memory device and may include performing functions associated with any features of the example methods 1-11 of operating a memory device.

[0096] An example method 12 for operating a memory device may include: accessing an indirection table based on a virtual address received in a write request to the memory device from a host device; compressing data corresponding to a user page size of the write request to generate compressed data; obtaining a PA of a physical memory from a free space manager of the memory device based on the size of the compressed data, the PA defining locations of a plurality of stripes to store the compressed data in the physical memory; updating the indirection table with a first PA of the PA, the first PA corresponding to a first stripe of the compressed data; writing a second PA of the PA to the first stripe in the physical memory, the second PA corresponding to a second stripe of the compressed data; sequentially writing remaining stripes of the plurality of stripes except the second stripe to the physical memory, each of the remaining stripes containing a PA, writing subsequent stripes at the PA in the sequential writing until a last stripe of the compressed data corresponding to the VP of the virtual address is written.

[0097] An example method 13 of operating a memory device may include features of the example method 12 of operating a memory device and may include: before compressing the data corresponding to the write request, passing the PA mapped to the virtual address in the accessed indirect table to the free space manager; obtaining the PA of the chain by traversing the stripe chain associated with the PA mapped to the virtual address in the accessed indirect table by the free space manager and identifying the PA in each stripe of the chain except the last stripe of the chain; and releasing a location for future write requests.

[0098] An example method 14 of operating a memory device may include features of any of the aforementioned example methods 12 to 13 of operating a memory device and may include writing the PA of the first stripe, the second stripe, and the remaining stripes, and subsequent stripes of the compressed data written including writing the PA in each stripe into a reserved bit position in each stripe.

[0099] The example method 15 of operating a memory device may include features of any of the foregoing example methods 12-14 of operating a memory device and may include accessing the indirection table to include loading the indirection table for processing.

[0100] Example method 16 of operating a memory device may include features of any of the foregoing example methods 12-15 of operating a memory device and may include writing the PA of a subsequent stripe into a previous stripe using pins of a memory subsystem of the memory device that are used for a function other than transferring user data.

[0101] The example method 17 of operating a memory device may include features of any of the foregoing example methods 12-16 of operating a memory device and may include accessing the indirection table including accessing the indirection table in a cache, the indirection table including the first PA corresponding to the virtual address.

[0102] The example method 18 of operating a memory device may include the features of any of the foregoing example methods 12-17 of operating a memory device and may include that the user page size is 4KB.

[0103] In example method 19 of operating a memory device, any of example methods 12-18 of operating a memory device may be performed while operating an electronic device further including a host processor and a communication bus extending between the host processor and the memory device.

[0104] In example method 20 of operating a memory device, any of example methods 12-19 of operating a memory device may be modified to include the operations set forth in any other of example methods 12-19 of operating a memory device.

[0105] In example method 21 of operating a memory device, any of example methods 12-20 of operating a memory device may be implemented at least in part by using instructions stored as a physical state in one or more machine-readable storage devices.

[0106] The example method 22 of operating a memory device may include features of any of the foregoing example methods 12-21 of operating a memory device and may include performing functions associated with any features of the example memory devices 1-11.

[0107] Example method 23 of operating a memory device may include features of any of the foregoing example methods 1-11 and example methods 12-22 of operating a memory device and may include performing functions associated with any features of example memory devices 1-11.

[0108] An example machine-readable storage device storing instructions that, when executed by one or more processors, cause the machine to perform operations, may include instructions for performing functions associated with any features of example memory devices 1 to 11 or for performing methods associated with any features of example methods 1 to 11 of operating a memory device and example methods 12 to 23 of operating a memory device.

[0109] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. Various embodiments use permutations and / or combinations of the embodiments described herein. It should be understood that the above description is intended to be illustrative and not limiting, and that the phrases or terms employed herein are for descriptive purposes.

Claims

1. A memory device, comprising: a mapping table having an entry location associating a virtual page with a physical address of a first stripe of data for the virtual page, the data being arranged in a plurality of stripes in a physical memory of the memory device; and A controller that, in response to the data of the virtual page being compressed data, loads information about a second stripe of the compressed data into an additional location in the first stripe, the additional location being a location in the first stripe different from a location of the compressed data of the virtual page.

2. The memory device of claim 1, wherein the information about the second stripe includes the physical address of the second stripe.

3. The memory device of claim 1 , wherein the controller is arranged to load information about a third stripe of compressed data into an additional location in the second stripe, the additional location in the second stripe being a location different from a location of the compressed data of the virtual page. 4 . The memory device of claim 3 , wherein the information about the third stripe includes the physical address of the third stripe.

5. The memory device of claim 1, wherein the memory device includes a free space manager to make physical addresses available for writing data from a host to a memory subsystem of the memory device.

6. The memory device of claim 1, wherein the memory device is a Compute Express Link (CXL) Type 3 memory device.

7. A method of operating a memory device, the method comprising: accessing an indirection table based on a virtual address received in a read request from a host device to the memory device; reading a first stripe of a plurality of stripes of compressed data from a physical memory of the memory device, the plurality of stripes of compressed data corresponding to the read request, the first stripe being read from the physical memory at a physical address listed in the indirection table corresponding to the virtual address; reading a physical address of a next stripe of the plurality of stripes of compressed data from the first stripe; reading the next stripe of compressed data from the physical memory corresponding to the physical address of the next stripe, including reading a physical address of a subsequent stripe of the plurality of stripes of compressed data; sequentially reading remaining stripes of the plurality of stripes except the next stripe, reading each of the remaining stripes from the physical memory at a physical address obtained when a previous stripe was read in the sequential reading; and The compressed data read from the plurality of stripes is decompressed.

8. The method of claim 7, wherein the method includes placing additional read requests for data corresponding to the virtual address in a progress list.

9. The method of claim 7, wherein the method includes, while reading the first stripe of compressed data, reading the physical address of the next stripe through a pin of a memory subsystem of the memory device, the pin being used for a function other than transferring user data.

10. The method of claim 7, wherein the method includes decompressing the compressed data after reading all of the compressed data for the plurality of stripes of compressed data from the physical memory of the memory device.

11. The method of claim 7, wherein the method includes copying uncompressed data generated after reading the plurality of stripes from the physical memory to one or more caches of the memory device or one or more read buffers of the memory device.

12. The method of claim 7, wherein accessing the indirection table comprises loading the indirection table if the indirection table is not cached.

13. The method of claim 7, wherein each of the plurality of stripes has a size of 64 bytes.

14. A method of operating a memory device, the method comprising: accessing an indirection table based on a virtual address received in a write request from a host device to the memory device; compressing data corresponding to the user page size of the write request, thereby generating compressed data; obtaining a physical address of a physical memory from a free space manager of the memory device based on a size of the compressed data, the physical address defining a location of a plurality of stripes to store the compressed data in the physical memory; updating the indirection table with a first one of the physical addresses, the first physical address corresponding to a first stripe of the compressed data; writing a second physical address of the physical addresses into the first stripe in the physical memory, the second physical address corresponding to a second stripe of the compressed data; The remaining stripes of the plurality of stripes except the second stripe are sequentially written to the physical memory, each of the remaining stripes containing a physical address at which a subsequent stripe in the sequential writing is written until a last stripe of the compressed data corresponding to the virtual page of the virtual address is written.

15. The method according to claim 14, wherein the method comprises: prior to compressing the data corresponding to the write request, passing a physical address mapped to the virtual address in the accessed indirect table to the free space manager; obtaining, by the free space manager traversing a chain of stripes associated with the physical address mapped to the virtual address in the accessed indirect table and identifying a physical address in each stripe in the chain except the last stripe of the chain, a physical address of the chain; and Frees the location for future write requests.

16. The method of claim 14, wherein writing physical addresses of the first stripe, the second stripe, and the remaining stripes and subsequent stripes of the compressed data written comprises writing the physical addresses in each stripe in reserved bit positions in each stripe.

17. The method of claim 14, wherein accessing the indirection table comprises loading the indirection table for processing.

18. The method of claim 14, wherein the method includes writing the physical address of a subsequent stripe into a previous stripe using a pin of a memory subsystem of the memory device, the pin being used for a function other than transferring user data.

19. The method of claim 14, wherein accessing the indirection table comprises accessing the indirection table in a cache, the indirection table comprising a first physical address corresponding to the virtual address.

20. The method of claim 14, wherein the user page size is 4 KB.

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