Electronic device and related system management method

Abstract

The embodiment of the invention discloses an electronic device and a related system management method, the electronic device comprises a target processor core, and the target processor core is configured to manage M hardware resource sets in the electronic device according to a tree topology structure mode; the tree topological structure comprises M nodes, the M nodes form a topological structure of a first layer, a second layer,..., and a K layer from top to bottom, and each hardware resource set in the M hardware resource sets corresponds to one node in the M nodes; the hardware resource set corresponding to the child node in any pair of father node and child node in the tree topology structure is a subset of the hardware resource set corresponding to the father node. When the hardware resources of the electronic device are managed by adopting the embodiment of the invention, the security and the robustness of the electronic device system can be ensured, and the chip resources can be saved.

Description

Technical Field

[0001] The present application relates to the field of computers, and in particular to electronic devices and related system management methods. Background Art

[0002] The implementation of privilege levels on the processor is mainly to isolate different software entities and ensure that software running at different privilege levels can only use hardware resources within the scope of permission, thereby improving the security of the processor system. With the rapid development of processors, the application scenarios of processors are becoming more and more extensive, and the types of software running on processors are becoming more and more diverse. In order to ensure the robustness and security of the processor system, the existing privilege levels have to be expanded, resulting in increasingly complex hardware resource management solutions and a waste of more chip resources. Summary of the invention

[0003] The embodiments of the present application provide an electronic device and a related system management method, which can ensure the security and robustness of the electronic device system and save chip resources when managing the hardware resources of the electronic device.

[0004] In the first aspect, an embodiment of the present application provides an electronic device, which may include a processor, which may include N processor cores, and the target processor core among the N processor cores may be configured to manage the M hardware resource sets in the above-mentioned electronic device in a tree-like topological structure. The tree-like topological structure may include M nodes, and the M nodes constitute a topological structure of the 1st layer, the 2nd layer, ... the Kth layer from top to bottom, and each node in the i-th layer is connected to a node in the (i-1)th layer, and each node in the (i-1)th layer is connected to one or more nodes in the i-th layer, and any two nodes in the i-th layer and the (i-1)th layer that have a connection relationship constitute a pair of parent nodes and child nodes, and the (i-1)th layer corresponds to the parent node, and the i-th layer corresponds to the child node. Further, each of the above-mentioned M hardware resource sets corresponds to one of the M nodes, and the hardware resource set corresponding to the child node in any pair of parent nodes and child nodes in the tree-like topological structure is a subset of the hardware resource set corresponding to the parent node. The above L, N, and M can all be integers greater than 0; i is a positive integer greater than or equal to 2 and less than or equal to K.

[0005] In an embodiment of the present application, the hardware resources in the electronic device are managed in a tree topology structure, and the M nodes in the tree topology structure can constitute a multi-layer structure from top to bottom, and the node data contained in each layer can be different or the same. From another perspective, the tree topology structure can include one or more branches, each of the multiple branches can include at least one node, and different branches can include different nodes. Further, the hardware resources of the electronic device can be divided into M hardware resource sets, each hardware resource set corresponds to a node in the tree topology structure, and the hardware resource set corresponding to the child node in any pair of parent-child nodes is a subset of the hardware resource set corresponding to the parent node. In the actual application process, the hardware resource set corresponding to each node can be configured to support the operation of a software type of software (such as an application, or a system program, etc.) in a running state (such as a safe state, or an unsafe state, etc.). For a pair of parent and child nodes, the hardware resources that the parent node can use are more than those that the child node can use, that is, the control right of the parent node is greater than that of the child node, so as to isolate different types of software. When running a certain type of software, the target processor core can only use the hardware resources within the scope of authority and cannot use resources outside the authority, thereby ensuring the security of the system. At the same time, the number of nodes M included in the tree topology structure and the connection relationship between the nodes can be determined according to application requirements, thereby reducing the number of useless nodes and saving chip resources.

[0006] In some embodiments, each node in the i-th layer in the tree topology structure may correspond to a different set of hardware resources.

[0007] In the embodiment of the present application, the hardware resource sets corresponding to the nodes in the i-th layer in the tree topology are different, that is, the hardware resource sets corresponding to the nodes in the same layer are independent of each other. In the existing technology, the nodes at the same level reuse the same hardware resource set, but the operating status is different, so the same hardware resource set needs to be marked, and the hardware implementation is complicated. Compared with the existing technology, in the present application, since the hardware resources that the nodes at the same level can access are independent of each other, it is easier to perform hardware isolation when dividing hardware resources.

[0008] In some embodiments, the above hardware resource set may include, but is not limited to, one or more of memory resources, instruction resources, register resources, and interface resources.

[0009] In some embodiments, any parent node in the i-th layer in the tree topology structure can configure a hardware resource set corresponding to the corresponding child node.

[0010] In the embodiment of the present application, in any pair of parent-child nodes in the tree topology, the parent node can configure the hardware resource set corresponding to the child node, and the hardware resource set includes memory resources, instruction resources, register resources, interface resources, etc. that the child node can access, and the range of hardware resources that the child node can access is smaller than the range of hardware resources that the parent node can access. In actual application, a hardware resource set can be configured to support running one type of software in one operating state, thereby ensuring the security and stability of the system.

[0011] In some embodiments, the target processor core may further include a first register, which may be used to store a node identifier of the target node. The node identifier may be used to instruct the target processor core to enable a hardware resource set corresponding to the target node. The target node may be one of the M nodes.

[0012] In an embodiment of the present application, the first register may store in advance the mapping relationship between the hardware resource set corresponding to each of the multiple nodes included in the tree topology and the node identifier. After the node identifier of the target node is written into the first register, the first register may enable the hardware resource set corresponding to the target node based on the node identifier of the target node. Since the hardware resource sets are independent of each other for nodes in the same level, there is no need to reuse the same hardware resources between nodes. Therefore, in actual application, each node can be configured to support running a type of software in a running state, and then the processor core can determine the hardware resource set that can run the corresponding target task based on the target task, which simplifies the system model and software implementation.

[0013] In the second aspect, an embodiment of the present application provides an electronic device, which may include a processor, which may include N processor cores, and the target processor core among the N processor cores may be configured to manage the M hardware resource sets in the above-mentioned electronic device in a tree-like topological structure. The tree-like topological structure may include M nodes, and the M nodes constitute a topological structure of the 1st layer, the 2nd layer, ... the Kth layer from top to bottom, and each node in the i-th layer is connected to a node in the (i-1)th layer, and each node in the (i-1)th layer is connected to one or more nodes in the i-th layer, and any two nodes in the i-th layer and the (i-1)th layer that have a connection relationship constitute a pair of parent nodes and child nodes, and the (i-1)th layer corresponds to the parent node, and the i-th layer corresponds to the child node. Further, each of the above-mentioned M hardware resource sets corresponds to one of the M nodes, and the hardware resource set corresponding to the child node in any pair of parent nodes and child nodes in the tree-like topological structure is a subset of the hardware resource set corresponding to the parent node. The above L, N, and M can all be integers greater than 0; i is a positive integer greater than or equal to 2 and less than or equal to K. The target processor core can use the hardware resource set corresponding to the first node among the M nodes to determine the target task to be run, wherein the first node as a parent node can have at least one child node. Furthermore, the target processor core can also use the hardware resource set corresponding to the first node to determine the second node corresponding to the target task from the child nodes of the first node. Then, the target processor core can start the hardware resource set corresponding to the second node to run the target task.

[0014] In an embodiment of the present application, the hardware resources in the electronic device are managed in a tree topology structure, and the M nodes in the tree topology structure can constitute a multi-layer structure from top to bottom, and the node data contained in each layer can be different or the same. From another perspective, the tree topology structure can include one or more branches, each of the multiple branches can include at least one node, and different branches can include different nodes. Further, the hardware resources of the electronic device can be divided into M hardware resource sets, each hardware resource set corresponds to a node in the tree topology structure, and the hardware resource set corresponding to the child node in any pair of parent-child nodes is a subset of the hardware resource set corresponding to the parent node. In the actual application process, the hardware resource set corresponding to each node can be configured to support the operation of a software type of software (such as an application, or a system program, etc.) in a running state (such as a safe state, or an unsafe state, etc.). For a pair of parent and child nodes, it can be realized that the hardware resources that the parent node can use are more than the hardware resources that the child node can use, that is, the control right of the parent node is greater than the control right of the child node. For example, the parent node can assign the received running tasks to the child node for processing to isolate different types of software. When running a certain type of software, the target processor core can only use the hardware resources within the scope of authority and cannot use resources outside the authority to ensure the security of the system. At the same time, the number of nodes M included in the tree topology structure and the connection relationship between the nodes can be determined according to application requirements, thereby reducing the number of useless nodes and saving chip resources.

[0015] In some embodiments, the target processor core may further include a first register, which may be used to store a node identifier of the target node. The node identifier may be used to instruct the target processor core to enable a hardware resource set corresponding to the target node. The target node may be one of the M nodes.

[0016] In some embodiments, the target processor core is specifically used to update the node identifier of the second node into the first register. Further, the target processor core can enable the hardware resource set corresponding to the second node based on the node identifier of the second node in the first register.

[0017] In an embodiment of the present application, the first register may store in advance the mapping relationship between the hardware resource set and the node identifier corresponding to each node in the multiple nodes included in the tree topology. After the first node determines the second node that needs to run the target task next, the first node may update the node identifier of the second node to the first register, and then the target processor core can determine the corresponding hardware resource set based on the node identifier, thereby instructing the target processor core to enable the hardware resource set corresponding to the second node and run the target task. In the existing technology, since the nodes in the same level need to reuse the same hardware resource set, the processor core needs to determine the hardware resource set first, and in the configuration running state, the corresponding hardware resources can be used to run the target task. In the present application, for the nodes in the same level, the hardware resource sets are independent of each other, and there is no need to reuse the same hardware resources between nodes, so each node can be configured to support running a type of software in a running state, and then the processor core can determine the hardware resource set that can run the corresponding target task based on the target task, simplifying the system model and software implementation.

[0018] In some embodiments, the target processor core may be used to obtain first configuration information from a hardware resource set corresponding to the first node, wherein the first configuration information may include software entry information of the target task, service entry information provided by the first node, etc. Further, the target processor core may determine the target task to be currently executed based on the first configuration information.

[0019] In an embodiment of the present application, the first node can be configured to run a certain type of software in a certain operating state, and the first node can obtain the first configuration information during the software running process. The first configuration information may include, but is not limited to, information such as the software entry information of the target task to be run, the service entry information that the first node can provide, and the software type of the target task. Furthermore, the first node can determine the current target task to be run based on the first configuration information, and can match the software type of the target task with the software types that multiple nodes support running, and then can determine the second node that supports the target task type. In the present application, a set of hardware resources runs a type of software, ensuring the security and stability of the system.

[0020] In some embodiments, the target processor core is further configured to determine a useless node among the M nodes through a third node among the M nodes according to second configuration information, wherein the second configuration information includes information about the useless node. Further, the target processor core may configure a lower node of the useless node as a child node of an upper node of the useless node.

[0021] In the embodiment of the present application, the third node can be any node among the multiple nodes, and the hardware resource set corresponding to the third node can support running a type of software in a running state. In the process of running the software, if the second configuration information (which may include information of useless nodes) is obtained. Further, the third node can determine the useless nodes among the multiple nodes based on the second configuration information, and configure the lower nodes of the useless nodes as the child nodes of the upper nodes of the useless nodes, so as to delete the useless nodes in the tree topology structure composed of multiple nodes and improve the system efficiency.

[0022] In a third aspect, the present application provides a system management method, which can be applied to an electronic device, and the electronic device may include a processor, and the processor may include N processor cores, and the target processor core of the N processor cores may be configured to manage M hardware resource sets in the electronic device in a tree topology. The tree topology may include M nodes, and the M nodes constitute a topology of the 1st layer, the 2nd layer, ... the Kth layer from top to bottom, and each node in the i-th layer is connected to a node in the (i-1)th layer, and each node in the (i-1)th layer is connected to one or more nodes in the i-th layer, and any two nodes in the i-th layer and the (i-1)th layer that have a connection relationship constitute a pair of parent nodes and child nodes, and the (i-1)th layer corresponds to the parent node, and the i-th layer corresponds to the child node. Further, each of the above-mentioned M hardware resource sets corresponds to one of the M nodes, and the hardware resource set corresponding to the child node in any pair of parent nodes and child nodes in the tree topology is a subset of the hardware resource set corresponding to the parent node. The above L, N, and M can all be integers greater than 0; i is a positive integer greater than or equal to 2 and less than or equal to K. The method includes: the target task to be run can be determined by using the hardware resource set corresponding to the first node among the M nodes through the above target processor core, wherein the first node as a parent node can have at least one child node. Furthermore, the target processor core can also use the hardware resource set corresponding to the first node to determine the second node corresponding to the target task from the child nodes of the first node. Then, the target processor core can start the hardware resource set corresponding to the second node to run the target task.

[0023] In some embodiments, the target processor core may also include a first register, which may be used to store a node identifier of the target node. The node identifier may be used to instruct the target processor core to enable a hardware resource set corresponding to the target node. The target node may be one of the nodes in the tree topology structure.

[0024] In some embodiments, the above-mentioned starting the hardware resource set corresponding to the second node to run the target task can be understood as updating the node identifier of the second node to the first register, and then based on the node identifier of the second node in the first register, enabling the hardware resource set corresponding to the second node.

[0025] In some embodiments, determining the target task to be currently executed includes: acquiring first configuration information from a hardware resource set corresponding to the first node, wherein the first configuration information may include software entry information of the target task, service entry information provided by the first node, etc. Further, the target processor core may determine the target task to be currently executed based on the first configuration information.

[0026] In some embodiments, the method further includes: determining, by the target processor core, a useless node in the tree topology structure based on a third node among the M nodes according to the second configuration information, wherein the second configuration information may include information of the useless node. Further, the lower node of the useless node may be configured as a child node of the upper node of the useless node.

[0027] In a fourth aspect, an embodiment of the present application provides a chip system, which may include a processor, and the processor may include N processor cores, and the target processor core among the N processor cores may be configured to manage the M hardware resource sets in the above-mentioned chip system in a tree-like topological structure. The tree-like topological structure may include M nodes, and the M nodes constitute a topological structure of the 1st layer, the 2nd layer, ... the Kth layer from top to bottom, and each node in the i-th layer is connected to a node in the (i-1)th layer, and each node in the (i-1)th layer is connected to one or more nodes in the i-th layer, and any two nodes in the i-th layer and the (i-1)th layer that have a connection relationship constitute a pair of parent nodes and child nodes, and the (i-1)th layer corresponds to the parent node, and the i-th layer corresponds to the child node. Further, each of the above-mentioned M hardware resource sets corresponds to one of the M nodes, and the hardware resource set corresponding to the child node in any pair of parent nodes and child nodes in the tree-like topological structure is a subset of the hardware resource set corresponding to the parent node. The above L, N, and M can all be integers greater than 0; i is a positive integer greater than or equal to 2 and less than or equal to K.

[0028] In a fifth aspect, the present application provides a computer storage medium, characterized in that the computer storage medium stores a computer program, and when the computer program is executed by a processor, it implements the method described in any one of the third aspects above.

[0029] In a sixth aspect, the present application provides a chip system, which includes a processor for supporting an electronic device to implement the functions involved in the third aspect, for example, generating or processing the information involved in the system management method. In a possible design, the chip system also includes a memory, which is used to store program instructions and data necessary for the electronic device. The chip system can be composed of a chip, or it can include a chip and other discrete devices.

[0030] In a seventh aspect, the present application provides a computer program product, characterized in that the computer program includes instructions, and when the computer program is executed by a computer, the computer executes any one of the methods described in the third aspect above.

[0031] In an eighth aspect, a chip system is provided, wherein the chip system includes at least one processor for implementing the method of the third aspect or any one of the embodiments of the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of a chip system provided in an embodiment of the present application.

[0033] Figure 2 A schematic diagram of a processor provided in an embodiment of the present application.

[0034] Figure 3 A schematic diagram of a hierarchical structure of a tree topology structure provided in an embodiment of the present application.

[0035] Figure 4 A schematic diagram of a tree topology structure provided in an embodiment of the present application.

[0036] Figure 5 A schematic diagram of hardware resource division provided in an embodiment of the present application.

[0037] Figure 6 A schematic diagram of another tree topology structure provided in an embodiment of the present application.

[0038] Figure 7 A schematic diagram of another tree topology structure provided in an embodiment of the present application.

[0039] Figure 8 A schematic diagram of another tree topology structure provided in an embodiment of the present application.

[0040] Fig. 9 A schematic diagram of another processor provided in an embodiment of the present application.

[0041] Fig.10 A schematic diagram of an operation target task provided in an embodiment of the present application.

[0042] Fig.11 A flowchart of a system management method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0044] The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0045] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0046] The present application embodiment provides a chip system. Figure 1 , Figure 1 1 is a schematic diagram of a chip system provided by an embodiment of the present invention, and the chip system may include but is not limited to a system on chip 101 (System on chip, Soc), an internal memory 102, and an external memory 103. The chip system can be integrated in any electronic device, such as a computer, a mobile phone, a tablet, a personal digital assistant, a smart wearable device, a smart car or a smart home appliance, and the chip system can work under the necessary software driver.

[0047] System on chip 101 (System on chip, Soc) refers to a technology that integrates a complete system on a single chip and groups all or part of the necessary electronic circuits. The system on chip 101 may include multiple processing units and a controller 1014. Among them, the multiple processing units may include one or more of a central processing unit 1011 (Central Processing Unit, CPU), a modem processing unit, a graphics processing unit 1012 (graphics processing unit, GPU), an image signal processing unit (image signal processor, ISP), a video codec unit, a digital signal processing unit (digital signal processor, DSP), a baseband processing unit, and a neural network processing unit 1013 (neural-network processing unit, NPU). Optionally, different processing units can communicate with the controller 1014 through a primary bus.

[0048] The central processing unit 1011, which can also be called a central processing unit, or a processor, is a chip that integrates at least one processor core. The processor core is the abbreviation of the processor core, also known as the kernel, and is the most important component of the CPU. It is made of single crystal silicon using a certain production process. All CPU calculations, command reception or command storage, and data processing are performed by the processor core. The processor core can load instructions or data stored in the external memory 103 (such as a disk, etc.) into the internal memory 102, and call the instructions or data that need to be calculated to the processor core for calculation. After the calculation is completed, the processor core temporarily stores the result in the internal memory 102, and stores the instructions or data that need to be stored for a long time in the external memory 103 through the controller 1014. The processor core can run different types of software such as an operating system, a file system (such as a flash file system F2FS) or an application to control multiple hardware or software components connected to the processor, and can process various data and perform operations. In order to improve the security of the processor system, the hardware resources are divided so that the processor core can run in multiple modes (such as privileged levels) to isolate different software entities and ensure that software running at different privileged levels can only use hardware resources within the scope of authority and cannot use resources outside the authority, thereby ensuring the security of the system. In this application, in order to solve the problems of poor scalability and complex hardware implementation in the existing hardware resource division process, a flexible tree structure will be used to divide and manage the hardware resources of the system on chip 101. The hardware resources of the system on chip 101 can be divided into multiple hardware resource sets according to application requirements, and each hardware resource set can run a software entity, avoiding the use of complex status tags to support different software entities to reuse a certain hardware resource set, simplifying the system model and software implementation.

[0049] The graphics processing unit 1012 is a microprocessor for image processing. The graphics processing unit 1012 is used to perform mathematical and geometric calculations for graphics rendering. The system on chip 101 may include one or more graphics processing units 1012, which execute program instructions to generate or change display information. In some embodiments, the graphics processing unit 1012 is a hardware chip with a privileged level implementation, wherein the privileged level can also be designed using the tree-shaped privileged level provided by the present application, which can save more invalid nodes and simplify the system model and software implementation.

[0050] The neural network processing unit 1013 is a neural network computing processor. By drawing on the biological neural network structure, for example, drawing on the transmission mode between neurons in the human brain, it can quickly process input information and can also continuously self-learn. The neural network processing unit 1013 can realize applications such as intelligent cognition of electronic devices, such as: image recognition, face recognition, voice recognition, text understanding, etc. In some embodiments, the neural network processing unit 1013 is a hardware chip with privileged level implementation, wherein the privileged level can also be designed using the tree-shaped privileged level provided by the present application, which can save more invalid nodes and simplify the system model and software implementation.

[0051] Optionally, the memory of the central processing unit 1011 may be a cache memory (Cache). The cache may include one or more of a first-level cache (L1 Cache), a second-level cache (L2 Cache), a third-level cache (L3 Cache), etc. The cache may store instructions or data that the central processing unit 1011 has just used or cyclically used. If the central processing unit 1011 needs to use the instruction or data again, it may be directly called from the cache. This avoids repeated access, reduces the waiting time of the processor core, and thus improves the efficiency of the processor.

[0052] Internal memory 102 (Memory), referred to as memory, can be located outside the system on chip 101, usually a power-off volatile memory, which will lose the content stored on it when the power is off, and can also be called main memory. The internal memory 102 in this application includes a readable and writable running memory, which is used to temporarily store the calculation data in the processor core, and to exchange data with the external memory 103 or other external memories, and can be used as a storage medium for temporary data of the operating system or other running programs. At different privilege levels, the processing unit (such as a processor) can access different memory resources.

[0053] The internal memory 102 may include one or more of a dynamic random access memory (DRAM), a static random access memory (SRAM), a synchronous dynamic random access memory (SDRAM), etc. Among them, DRAM includes double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM), referred to as DDR, second generation double data rate synchronous dynamic random access memory (DDR2), third generation double data rate synchronous dynamic random access memory (DDR3), fourth generation low power double data rate synchronous dynamic random access memory (Low Power Double Data Rate 4, LPDDR4) and fifth generation low power double data rate synchronous dynamic random access memory (Low Power Double Data Rate 5, LPDDR5), etc.

[0054] The external memory 103 is a non-volatile memory, and its stored contents will not be lost after power failure. The external memory 103 can be used for long-term storage of instructions and data involved in the operation of the central processing unit 1011, such as startup programs, operating systems, applications and data. Since the central processing unit 1011 cannot directly read instructions and data in the external memory 103 or directly write instructions or data to the external memory 103, when the central processing unit 1011 executes a read (or load) instruction, it actually temporarily loads the contents to be read (including instructions and / or data) stored in the external memory 103 into the internal memory 102 through the controller 1014, and then the central processing unit 1011 reads it from the internal memory 102; and when executing a write (i.e. store) instruction, it actually temporarily writes the data to be stored (including instructions and / or data) into the internal memory 102 by the central processing unit 1011, and then stores it from the internal memory 102 to the external memory 103 through the controller 1014.

[0055] The external memory 103 may include one or more of Flash flash memory (for example, NAND flash memory, NOR flash memory, etc.), universal flash storage (UFS), embedded multimedia card eMMC, universal flash storage multi-chip package uMCP memory, embedded multimedia card multi-chip package eMCP memory, solid-state drive (SSD), etc.

[0056] Understandably, Figure 1 The chip systems in the embodiments are just some exemplary implementations provided by the embodiments of the present invention. The chip systems in the embodiments of the present invention include but are not limited to the above implementations.

[0057] Please see attached Figure 2 , an embodiment of the present application provides an electronic device, Figure 2 The electronic device 02 may include a processor 20, which may be the central processing unit 1011. The processor 20 may include N processor cores, where N is an integer greater than 0. When N is equal to 1, it is a single-core processor; when N is an integer greater than 1, it is a multi-core processor, and different processor cores may be isomorphic or heterogeneous, which is not specifically limited in this application. In this application, the electronic device 02 may also include more modules, such as Figure 2 The internal memory 21 is shown by way of example.

[0058] The target processor core 201 among the N processor cores is configured to manage the M hardware resource sets in the electronic device 02 in a tree topology structure. Each of the M hardware resource sets may include one or more of memory resources, instruction resources, register resources, and interface resources.

[0059] Optionally, the hardware resources of the electronic device 02 may be divided into multiple parts according to application requirements.

[0060] The tree-like topology structure includes M nodes, and the M nodes constitute a topology structure of the 1st layer, 2nd layer, ... K layers from top to bottom. Each node in the i-th layer is connected to a node in the (i-1)th layer, and each node in the (i-1)th layer is connected to one or more nodes in the i-th layer. Any two nodes in the i-th layer and the (i-1)th layer that are connected constitute a pair of parent nodes and child nodes, and the (i-1)th layer corresponds to the parent node and the i-th layer corresponds to the child node; each of the M hardware resource sets corresponds to one of the M nodes.

[0061] Specifically, Figure 3 As shown, Figure 3 A schematic diagram of a tree topology structure provided in an embodiment of the present application, Figure 3 The tree topology in may include M nodes, and these nodes form a topology of K layers from top to bottom, namely, the first layer, the second layer, ..., the Kth layer. For multiple nodes in the i-th layer, each node in the i-th layer can be connected to a node in the i-1th layer; for multiple nodes in the i-1th layer, each node in the i-1th layer can be connected to at least one node in the i-th layer. There can be one or more pairs of parent-child nodes in the tree topology, such as Figure 3, node1 is the parent node and node3 is the child node. Optionally, the number of nodes M included in the tree topology structure and the connection relationship between the nodes can be determined according to the needs of the application scenario. Furthermore, the hardware resources of the electronic device 02 can be divided into M hardware resource sets, each hardware resource set corresponding to a node in the tree topology structure, so that the hardware resources of the electronic device 02 can be divided and managed based on the tree topology structure, which can not only ensure the security and robustness of the electronic device 02 system, but also save chip resources.

[0062] The hardware resource set corresponding to the child node in any pair of parent nodes and child nodes in the tree topology structure is a subset of the hardware resource set corresponding to the parent node; L, N, M are integers greater than 0; i is a positive integer greater than or equal to 2 and less than or equal to K, i = 2, 3, ..., K.

[0063] Specifically, each node in the tree topology corresponds to a hardware resource set, and in any pair of parent-child nodes, the hardware resource set corresponding to the child node is a subset of the hardware resource set corresponding to the parent node. In actual application, it can be realized that the parent node can use more hardware resources than the child node, that is, the control right of the parent node is greater than the control right of the child node, so as to isolate different types of software. When running a certain type of software, the target processor core 201 can only use the hardware resources within the scope of authority and cannot use resources outside the authority, thereby ensuring the security of the system.

[0064] In some embodiments, each node in the i-th layer in the tree topology structure corresponds to a different set of hardware resources.

[0065] Specifically, the hardware resource sets corresponding to the nodes in the i-th layer in the tree topology are different, that is, the hardware resource sets corresponding to the nodes in the same layer are independent of each other. In the existing technology, the nodes at the same level reuse the same hardware resource set, but the operating status is different, so the same hardware resource set needs to be marked, and the hardware implementation is complicated. Compared with the existing technology, in this application, since the hardware resources that the nodes at the same level can access are independent of each other, it is easier to perform hardware isolation when dividing the hardware resources.

[0066] In summary, the number of nodes M included in the tree topology structure and the relationship between each node can be determined according to application requirements in this application. In the tree topology structure, multiple nodes can constitute a multi-layer structure from top to bottom, and the node data contained in each layer can be different or the same, which is not specifically limited in this application. From another perspective, the tree topology structure can include one or more branches, each branch in the multiple branches can include at least one node, and different branches can include different nodes. Further, the hardware resources of the electronic device 02 can be divided into M hardware resource sets, and each hardware resource set corresponds to a node in the tree topology structure. The hardware resource set corresponding to each node can be configured to support running a software type of software (such as an application program, or a system program, etc.) in a running state (such as a safe state, or an unsafe state, etc.). Compared with the existing technology, for nodes of the same level, there is no need to reuse the same hardware resources, so as to achieve a hardware resource set corresponding to a software entity (i.e., a software type), saving more invalid nodes and saving chip resources. At the same time, for different scenarios or needs, new nodes or branches can be opened at any node in the tree topology, which is more scalable than existing technologies. In addition, a single node (also called a tree node) among multiple nodes is exclusively used by a certain software entity. From a hardware perspective, it is easier to design hardware resource isolation for different tree nodes, that is, isolation of register resources, memory resources, instruction resources, interface resources, etc. Compared with existing technologies, in this application, since nodes at the same level do not need to reuse the same hardware resources, it avoids using complex status tags to support different software entities to reuse a certain set of hardware resources, thereby exchanging a more streamlined design for safer benefits.

[0067] It should be noted that the operating environment when the software runs on the processor can be called the running state. Generally, the hardware of the processor can be configured to enable the software to execute in different running states, which can be divided into safe state / non-safe state, virtual state / non-virtual state, normal state, etc.

[0068] Secure state and non-secure state are two operating states of the processor. In recent years, the increasing popularity of connected devices has forced device manufacturers to take the security issues of devices more seriously. To address these issues, experts have developed a new specification and defined a method to ensure the integrity and confidentiality of data running on the device that implements the method. Trusted Execution Environment (TEE) is a secure area within the processor that is considered secure and can also be called "secure world". It runs in an independent environment and runs in parallel with the operating system. By using both hardware and software to protect data and code, this parallel system is more secure than traditional systems. The processor is considered to be in a secure state when running in a trusted execution environment. The non-trusted execution environment is considered to be insecure and is called "non secure world". The processor is considered to be in a non-secure state when running in a non-trusted execution environment.

[0069] Virtual state and non-virtual state are two operating states of the processor. When the software runs on a virtual machine, the processor is in a virtual state; when the software runs in a non-virtual machine (such as a physical machine), the processor is in a non-virtual state. A virtual machine is a complete computing system that is simulated by software and has complete hardware system functions and runs in a completely isolated environment.

[0070] Software is a collection of computer data and instructions organized in a specific order. Generally speaking, software can be divided into many types, such as system software, application software, and middleware between the two. Software does not only include computer programs that can be run on computers (computers here refer to computers in a broad sense), but also documents related to these computer programs are generally considered part of the software. Simply put, software is a combination of programs and documents.

[0071] Assume that the electronic device 02 is a server, the processor 20 is a processor in the server, and the server has the need to run a host and a virtual machine. When the server runs a virtual machine, the processor 20 is in a virtual state, and when the server runs a host, the processor 20 is in a non-virtual state. Furthermore, in order to ensure the security and stability of the system, Figure 4As shown, according to the requirements, the tree topology structure can be designed to include 5 nodes, and the tree structure is divided into two branches, the first branch includes Node0, Node1, Node2; the second branch includes Node0, Node1, Node3, Node4. Further, the hardware resources of the server are divided into 5 hardware resource sets, and each node corresponds to a hardware resource set. Optionally, the hardware resource set corresponding to each node can be configured to support running a preset software in a running state. For example, Node0 can support running firmware (Firmware) in a normal state (a normal running environment in which the processor runs the software without configuring the processor); Node1 can support running a management program in a normal state, such as a host kernel (Host kernel) and a virtual machine monitor (hypervison); Node2 can support running a host user program (Host user) in a non-virtual state; Node3 can support running a virtual machine kernel (guest kernel) in a virtual state; Node4 can support running a virtual machine user program (guest user) in a virtual state.

[0072] For nodes on the same branch, the control right of the parent node is greater than that of the child node, that is, the hardware resource set corresponding to the child node is a subset of the hardware resource set corresponding to the parent node, such as Figure 5 As shown, since Node0 is the root node, Node0 has the most hardware resources that it can access, followed by Node1, the child node of Node0. For nodes at the same level, since the hardware resources that each node can access are independent, such as Node2 and Node3 are nodes at the same level, the hardware resources that the two nodes can access are independent of each other. In the existing technology, nodes at the same level reuse the same set of hardware resources, but the operating status is different, so it is necessary to mark the status of the hardware resource set, and the hardware implementation is complicated. Compared with the existing technology, in this application, since the hardware resources that nodes at the same level can access are independent of each other, it is easier to perform hardware isolation when dividing hardware resources.

[0073] When a new operating state requirement arises, Figure 4 A branch is added to the tree topology structure shown, and the number of nodes in the new branch can be determined according to demand, and then the hardware resources of the electronic device 02 can be divided according to the number of nodes in the current tree topology structure, so that each node corresponds to a hardware resource set. Figure 6As shown, the newly added operating state is the safe state, and the newly added third branch includes Node0, Node5, Node6, and Node7. Optionally, the hardware resource set corresponding to each node can be configured to support running a preset software in a certain operating state. For example, Node5 can support running secure virtualization software in a safe state; Node6 can support running a secure kernel in a safe state; Node7 can support running a secure user program in a safe state. After adding a branch, since the number of nodes in the newly added branch is determined by demand, more invalid nodes are saved and chip resources are saved. At the same time, since nodes at the same level do not need to reuse the same hardware resources, it is easier to use complex status tags to support different software entities to reuse a certain hardware resource set, and hardware implementation is easier.

[0074] Assume that the electronic device 02 is a smart meter, the processor 20 is a processor in the smart meter, and the smart meter only needs to display information such as power consumption. Figure 7 As shown, according to the requirements, the tree topology structure can be designed to include two nodes, namely Node0 and Node1, and Node0 is the parent node of Node1. Optionally, the hardware resource set corresponding to each node can be configured to support running a preset software in a running state. For example, Node0 can support running firmware (Firmware) in the normal state; Node1 can support running user programs (user) in the normal state.

[0075] Assume again that the electronic device 02 is a smart watch, the processor 20 is a processor in the smart watch, and the smart watch has the function of displaying multiple applications. Furthermore, to ensure the security and stability of the system, Figure 8 As shown, according to the requirements, the tree topology structure can be designed to include 3 nodes, and the tree structure includes a branch, which includes Node0, Node1 and Node2, and Node0 is the root node, and Node1 is the parent node of Node2. Optionally, the hardware resource set corresponding to each node can be configured to support running a preset software in a certain operating state. For example, Node0 can support running firmware (Firmware) in the normal state; Node1 can support running kernel programs (kernel) in the normal state; Node2 can support running user programs (user) in the normal state.

[0076] In some embodiments, any parent node in the i-th layer in the tree topology structure configures a set of hardware resources corresponding to the corresponding child node.

[0077] Specifically, in any pair of parent-child nodes in a tree topology, the parent node can configure a hardware resource set corresponding to the child node, which includes memory resources, instruction resources, register resources, interface resources, etc. that the child node can access, and the range of hardware resources that the child node can access is smaller than the range of hardware resources that the parent node can access. In actual application, the hardware resource set corresponding to a node can be configured to support running a type of software in a certain operating state. Compared with existing technologies, in this application, since the hardware resources that nodes at the same level can access are independent of each other, it is easier to perform hardware isolation when dividing hardware resources. At the same time, since a hardware resource set can be configured to support running a type of software in a certain operating state, the security and stability of the system are ensured.

[0078] In some embodiments, Fig. 9 As shown, the target processor core 201 also includes a first register 2011, which is used to store the node identifier of the target node. The node identifier is used to instruct the target processor core 201 to enable the hardware resource set corresponding to the target node, and the target node is one of the M nodes.

[0079] Specifically, the first register 2011 can store in advance the mapping relationship between the hardware resource set corresponding to each node in the multiple nodes included in the tree topology and the node identifier. After the node identifier of the target node is written into the first register 2011, the first register 2011 can enable the hardware resource set corresponding to the target node based on the node identifier of the target node. In the existing technology, since the nodes in the same level need to reuse the same hardware resource set, the processor core needs to first determine the hardware resource set, and in the configuration running state, the corresponding hardware resources can be used to run the target task. In the present application, the hardware resource sets are independent of each other for the nodes in the same level, and the same hardware resources do not need to be reused between nodes. Therefore, each node can be configured to support running a type of software in a running state, and then the processor core can determine the hardware resource set that can run the corresponding target task based on the target task, simplifying the system model and software implementation.

[0080] Optionally, each of the M nodes in the tree topology is configured to support running one type of software in one running state.

[0081] In some embodiments, the target processor core 201 is used to: use the hardware resource set corresponding to the first node among the M nodes to determine the target task to be run, wherein the first node as a parent node may have at least one child node. Further, the target processor core may also use the hardware resource set corresponding to the first node to determine the second node corresponding to the target task from the child nodes of the first node. Then, the target processor core may start the hardware resource set corresponding to the second node to run the target task.

[0082] Specifically, the target task to be run can be a system program, an application program, or other type of software. For a pair of parent and child nodes, it can be realized that the hardware resources that the parent node can use are more than the hardware resources that the child node can use, that is, the control right of the parent node is greater than the control right of the child node. For example, the parent node can assign the received running task to the child node for processing.

[0083] In some embodiments, the target processor core 201 is specifically used to: update the node identifier of the second node to the first register 2011; and enable the hardware resource set corresponding to the second node based on the node identifier of the second node in the first register 2011.

[0084] Specifically, the first register 2011 can store in advance the mapping relationship between the hardware resource set and the node identifier corresponding to each node in the multiple nodes included in the tree topology. After determining the second node that needs to run the target task next, the node identifier of the second node can be updated to the first register 2011, and then the target processor core 201 can determine the corresponding hardware resource set based on the node identifier, so that the target processor core 201 can be instructed to enable the hardware resource set corresponding to the second node and run the target task. In the existing technology, since the nodes in the same level need to reuse the same hardware resource set, the processor core needs to determine the hardware resource set first, and in the configuration running state, the corresponding hardware resource can be used to run the target task. In the present application, the hardware resource sets are independent of each other for the nodes in the same level, and the same hardware resources do not need to be reused between nodes, so each node can be configured to support running a type of software in a running state, and then the processor core can determine the hardware resource set that can run the corresponding target task based on the target task, simplifying the system model and software implementation.

[0085] In some embodiments, the target processor core 201 is further used to: obtain first configuration information from the hardware resource set corresponding to the first node, wherein the first configuration information may include software entry information of the target task, service entry information provided by the first node, etc. Further, the target processor core may determine the target task to be currently executed according to the first configuration information.

[0086] Specifically, the first node can be configured to run a certain type of software in a certain operating state, and the first node can obtain the first configuration information from the memory resources of the first hardware resource set during the software running process. The first configuration information may include, but is not limited to, the software entry information of the target task to be run, the service entry information that the first node can provide, the software type of the target task, and other information. Furthermore, the first node can determine the current target task to be run based on the first configuration information, and can match the software type of the target task with the software types supported by multiple nodes to determine the second node that supports the target task type, thereby realizing a hardware resource set running one type of software, ensuring the security and stability of the system.

[0087] Optionally, the first configuration information may also include a node identifier of a node running the target task. Further, the second node may be determined from child nodes of the first node based on the node identifier in the first configuration information.

[0088] For example, when the electronic device 02 equipped with the processor 20 is reset (for example, restarted), the first node can be the root node among the multiple nodes, and the target processor core 201 can start the root node according to the default settings, and run the software supported by the root node through the hardware resource set corresponding to the root node. When there is a need to run other types of software, the root node can obtain the first configuration information to determine the target task to be run, and then determine the second node from the multiple nodes based on the software type of the target task, and the root node can have the right to specify the second node to run the target task next, ensuring the security and stability of the system.

[0089] In some embodiments, the target processor core is also used to: determine a useless node among the M nodes through a third node among the M nodes according to second configuration information, where the second configuration information includes information about the useless node; and configure the lower node of the useless node as a child node of the upper node of the useless node.

[0090] Specifically, the third node can be any node among the multiple nodes, and the hardware resource set corresponding to the third node can support running a type of software in a running state. During the running of the software, if the second configuration information (which may include information of useless nodes) is obtained, the third node can further determine the useless nodes among the multiple nodes based on the second configuration information, and configure the lower nodes of the useless nodes as child nodes of the upper nodes of the useless nodes, so as to delete the useless nodes in the tree topology structure composed of multiple nodes and improve the system efficiency.

[0091] In some embodiments, the target processor core 201 runs the target task through the target hardware resources corresponding to the second node; sends a first service request to a fourth node among multiple nodes, the first service request is used to request the use of hardware resources other than the target hardware resources, and the fourth node is the parent node or ancestor node of the second node.

[0092] Specifically, the target processor core 201 can run tasks based on the hardware resource set corresponding to the second node, but has no authority to use hardware resources outside the hardware resource set. Therefore, the target processor core 201 can only use the hardware resources within the scope of authority to run the target task. During the operation process, if it is necessary to use hardware resources outside the scope of authority, the second node will send a service request to its parent node or ancestor node so that when running the target task, it can use hardware resources outside the hardware resource set corresponding to the second node, which ensures that the target task can run normally and also ensures the security and stability of the system.

[0093] For example, Fig. 9 As shown, it is assumed that the first node is Node0 (root node) and the second node is Node2. Among them, the memory segment address that Node0 can access can be 0x00-0x400, the memory address of the service entry provided by Node0 can be 0x100, and the memory address that Node2 can access can be 0x500. After the electronic device 02 equipped with the processor 20 is reset (for example, restarted), the target processor core 201 can start the root node according to the default settings, and the root node can obtain the software code from the 0x00-0x400 memory segment address to run the supported software. When there is a demand to run other software, the root node can obtain the first configuration information, and the first configuration information may include the memory address (such as 0x500) for storing the target task, the service entry (0x100) provided by the root node and other information. It can be understood that the service entry provided by the root node can be used by request of the descendant node. Further, Node2 can obtain the code of the target task from the 0x500 memory address and run the target task. When Node2 needs hardware resources outside the scope of access rights, it can send a service request to Node0 so that hardware resources outside the hardware resource set corresponding to Node2 can be used when running the target task.

[0094] In some embodiments, the target processor core 201 receives and responds to the first service request through the fourth node, obtains a response result corresponding to the first service request, and sends the response result to the second node.

[0095] Specifically, the fourth node is the parent node or ancestor node of the second node, and the range of hardware resources that the fourth node can access is larger than the range of hardware resources that the second node can access. After receiving the service request sent by the second node, the fourth node can use the hardware resources that the fourth node can access to respond to the service request to obtain a response result. Furthermore, the fourth node can send the response result to the second node, so that the hardware resources outside the authority scope of the second node can be used when running the target task, which ensures that the target task can run normally and also ensures the security and stability of the system.

[0096] For example, Fig.10 As shown, the fourth node can be Node0, and the memory address of the service entry provided by Node0 can be 0x100. When Node2 sends a service request to Node0, the service request can include the memory address 0x100 of the service entry provided by Node0 to instruct Node0 to read data from the address with the memory address 0x100 to respond to the service request initiated by Node2. Further, after receiving the service request, Node0 reads data from the address with the memory address 0x100 to respond to the service request initiated by Node2 to obtain a response result, and sends the response result to Node2, so that hardware resources outside the scope of Node2's authority can be used when running the target task, which ensures that the target task can run normally and also ensures the security and stability of the system.

[0097] In some embodiments, the target processor core 201 receives and responds to the first service request through the fourth node, obtains a response result corresponding to the first service request, and sends the response result to a fifth node among multiple nodes, where the fifth node is the parent node or ancestor node of the fourth node.

[0098] Specifically, the fourth node may be the parent node or ancestor node of the second node, and the range of hardware resources accessible to the fourth node is larger than the range of hardware resources accessible to the second node. After receiving the service request sent by the second node, the fourth node may use the hardware resources accessible to the fourth node to respond to the service request to obtain a response result. Furthermore, the fourth node may send the response result to the parent node or ancestor node of the fourth node, and the parent node or ancestor node of the fourth node may decide whether to return the response result to the second node, thereby ensuring the security and stability of the system and avoiding returning some important system information to the second node, causing system insecurity and other problems.

[0099] In some embodiments, the target processor core 201 receives the response result through the fifth node, and determines whether to send the response result to the second node based on the system configuration information; if so, sends the response result to the second node; or, notifies the fourth node to send the response result to the second node.

[0100] Specifically, the system configuration information may be information configured in advance by the user, or may be information agreed upon in advance by the standard. After receiving the response result, the parent node or ancestor node of the fourth node (i.e., the fifth node) may determine whether the response result is important system information based on the system configuration information, and if not, the response result may be returned to the second node. Furthermore, the parent node or ancestor node of the fourth node may directly return the response result to the second node, or the parent node or ancestor node of the fourth node may also notify the fourth node to allow the fourth node to return the response result to the second node, thereby enabling the use of hardware resources outside the authority of the second node when running the target task, thereby ensuring that the target task can run normally and also ensuring the security and stability of the system.

[0101] In summary, in order to solve the problems of poor scalability and complex hardware implementation in the existing hardware resource division process, a flexible tree structure will be used to divide and manage the hardware resources of electronic devices. The hardware resources of electronic devices can be divided into multiple hardware resource sets according to application requirements, and each hardware resource set can run a software entity, avoiding the use of complex status tags to support different software entities to reuse a hardware resource set, thereby simplifying the system model and software implementation.

[0102] See also Fig.11 The present application provides a system management method, which is applied to an electronic device. The electronic device includes a processor, and the processor includes N processor cores. The target processor core among the N processor cores is configured to manage M hardware resource sets in the electronic device in a tree topology structure; the tree topology structure includes M nodes, and the M nodes constitute a topology structure of the 1st layer, the 2nd layer, ... the Kth layer from top to bottom, each node in the i-th layer is connected to a node in the (i-1)th layer, and each node in the (i-1)th layer is connected to one or more nodes in the i-th layer, and any two nodes in the i-th layer and the (i-1)th layer that have a connection relationship constitute a pair of parent nodes and child nodes, and the (i-1)th layer corresponds to the parent node and the i-th layer corresponds to the child node; each hardware resource set in the M hardware resource sets corresponds to one node in the M nodes; the hardware resource set corresponding to the child node in any pair of parent nodes and child nodes in the tree topology structure is a subset of the hardware resource set corresponding to the parent node; L, N, M are integers greater than 0; i is a positive integer greater than or equal to 2 and less than or equal to K. The detailed description is as follows:

[0103] Step S301: Determine a target task to be executed by using a hardware resource set corresponding to a first node among M nodes.

[0104] Specifically, the first node as a parent node has at least one child node.

[0105] Step S302: using the hardware resource set corresponding to the first node, determine a second node corresponding to the target task from the child nodes of the first node.

[0106] Step S303: Start the hardware resource set corresponding to the second node to run the target task.

[0107] In some embodiments, the target processor core also includes a first register, which is used to store a node identifier of the target node. The node identifier is used to instruct the target processor core to enable a hardware resource set corresponding to the target node. The target node is one of the nodes in the tree topology structure.

[0108] In some embodiments, starting the hardware resource set corresponding to the second node to run the target task includes: updating the node identifier of the second node to the first register; and enabling the hardware resource set corresponding to the second node based on the node identifier of the second node in the first register.

[0109] In some embodiments, the method also includes: obtaining first configuration information from a hardware resource set corresponding to the first node; the first configuration information includes one or more of the software entry information of the target task and the service entry information provided by the first node; and determining the target task to be run currently based on the first configuration information.

[0110] In some embodiments, the method also includes: determining, through the target processor core, a useless node in the tree topology structure based on a third node among the M nodes and according to second configuration information, wherein the second configuration information includes information of the useless node; and configuring the lower node of the useless node as a child node of the upper node of the useless node.

[0111] In this application, in order to solve the problems of poor scalability and complex hardware implementation in the existing hardware resource division process, a flexible tree structure will be used to divide and manage the hardware resources of the electronic device. The hardware resources of the electronic device can be divided into multiple hardware resource sets according to application requirements, and each hardware resource set can run a software entity, avoiding the use of complex status tags to support different software entities to reuse a hardware resource set, thereby simplifying the system model and software implementation.

[0112] An embodiment of the present application provides a chip system, which may include a processor, which may include N processor cores, and the target processor core among the N processor cores may be configured to manage the M hardware resource sets in the above chip system in a tree-like topological structure. The tree-like topological structure may include M nodes, and the M nodes constitute a topological structure of the 1st layer, the 2nd layer, ... the Kth layer from top to bottom, and each node in the i-th layer is connected to a node in the (i-1)th layer, and each node in the (i-1)th layer is connected to one or more nodes in the i-th layer, and any two nodes in the i-th layer and the (i-1)th layer that have a connection relationship constitute a pair of parent nodes and child nodes, and the (i-1)th layer corresponds to the parent node, and the i-th layer corresponds to the child node. Furthermore, each of the above M hardware resource sets corresponds to one of the M nodes, and the hardware resource set corresponding to the child node in any pair of parent nodes and child nodes in the tree-like topological structure is a subset of the hardware resource set corresponding to the parent node. The above L, N, and M can all be integers greater than 0; i is a positive integer greater than or equal to 2 and less than or equal to K.

[0113] The present application provides a computer storage medium, characterized in that the computer storage medium stores a computer program, and when the computer program is executed by a processor, any one of the above-mentioned system management methods is implemented.

[0114] An embodiment of the present application provides an electronic device, the electronic device includes a processor, and the processor is configured to support the electronic device to implement the corresponding functions in any of the above-mentioned system management methods. The electronic device may also include a memory, which is coupled to the processor and stores program instructions and data necessary for the electronic device. The electronic device may also include a communication interface for the electronic device to communicate with other devices or a communication network.

[0115] The present application provides a chip system, which includes a processor for supporting an electronic device to implement the functions involved above, for example, generating or processing information involved in the above-mentioned system management method. In a possible design, the chip system also includes a memory, which is used to store program instructions and data necessary for the electronic device. The chip system can be composed of a chip, or it can include a chip and other discrete devices.

[0116] The present application provides a computer program product, characterized in that the computer program includes instructions, and when the computer program is executed by a computer, the computer is caused to execute the above-mentioned system management method.

[0117] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0118] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the order of the actions described, because according to the present application, some steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0119] In the several embodiments provided in the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the above-mentioned units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0120] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0121] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0122] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server or a network device, etc., specifically a processor in a computer device) to perform all or part of the steps of the above-mentioned methods of each embodiment of the present application. Among them, the aforementioned storage medium may include: U disk, mobile hard disk, magnetic disk, optical disk, read-only memory (Read-Only Memory, abbreviated: ROM) or random access memory (Random Access Memory, abbreviated: RAM) and other media that can store program codes.

[0123] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An electronic device, characterized in that: The electronic device includes a processor, which includes N processor cores. The target processor core among the N processor cores is configured to manage M hardware resource sets in the electronic device in a tree-like topology structure; the tree-like topology structure includes M nodes, and the M nodes constitute a topology structure of 1st layer, 2nd layer, ... K layers from top to bottom, each node in the i-th layer is connected to a node in the (i-1)th layer, each node in the (i-1)th layer is connected to one or more nodes in the i-th layer, and any two nodes in the i-th layer and the (i-1)th layer that are connected constitute a pair of parent nodes and child nodes, and the (i-1)th layer corresponds to the parent node and the i-th layer corresponds to the child node; each hardware resource set in the M hardware resource sets corresponds to one of the M nodes; the hardware resource set corresponding to the child node in any pair of parent nodes and child nodes in the tree-like topology structure is a subset of the hardware resource set corresponding to the parent node; L, N, M are integers greater than 0; i is a positive integer greater than or equal to 2 and less than or equal to K.

2. The electronic device according to claim 1, characterized in that: The hardware resource sets corresponding to the nodes in the i-th layer in the tree topology are different.

3. The electronic device according to claim 1 or 2, characterized in that: The hardware resource set includes one or more of memory resources, instruction resources, register resources, and interface resources.

4. The electronic device according to any one of claims 1 to 3, characterized in that: Any parent node in the i-th layer in the tree topology structure is configured with a set of hardware resources corresponding to the corresponding child node.

5. The electronic device according to any one of claims 1 to 4, characterized in that: The target processor core also includes a first register, which is used to store a node identifier of a target node. The node identifier is used to instruct the target processor core to enable a hardware resource set corresponding to the target node, and the target node is one of the M nodes.

6. An electronic device, characterized in that: The electronic device includes a processor, the processor includes N processor cores, and a target processor core among the N processor cores is configured to manage M hardware resource sets in the electronic device in a tree topology structure; the tree topology structure includes M nodes, and the M nodes constitute a topology structure of 1st layer, 2nd layer, ... K layers from top to bottom, each node in the i-th layer is connected to a node in the (i-1)th layer, each node in the (i-1)th layer is connected to one or more nodes in the i-th layer, and any two nodes in the i-th layer and the (i-1)th layer that have a connection relationship constitute a pair of parent nodes and child nodes, and the (i-1)th layer corresponds to the parent node and the i-th layer corresponds to the child node; each hardware resource set in the M hardware resource sets corresponds to one of the M nodes; the hardware resource set corresponding to the child node in any pair of parent nodes and child nodes in the tree topology structure is a subset of the hardware resource set corresponding to the parent node; L, N, M are integers greater than 0; i is a positive integer greater than or equal to 2 and less than or equal to K; wherein the target processor core is used to: Determine a target task to be executed by using a hardware resource set corresponding to a first node among the M nodes; the first node as a parent node has at least one child node; Determine, by using the hardware resource set corresponding to the first node, a second node corresponding to the target task from the at least one child node; Start the hardware resource set corresponding to the second node to run the target task.

7. The electronic device according to claim 6, characterized in that: The target processor core also includes a first register, which is used to store a node identifier of a target node. The node identifier is used to instruct the target processor core to enable a hardware resource set corresponding to the target node, and the target node is one of the M nodes.

8. The electronic device according to claim 7, characterized in that: The target processor core is specifically used for: updating the node identifier of the second node into the first register; Based on the node identifier of the second node in the first register, a hardware resource set corresponding to the second node is enabled.

9. The electronic device according to any one of claims 6 to 8, characterized in that: The target processor core is specifically used for: Acquire first configuration information from a hardware resource set corresponding to the first node; the first configuration information includes one or more of software entry information of the target task and service entry information provided by the first node; The target task to be currently executed is determined according to the first configuration information.

10. The electronic device according to any one of claims 6 to 9, characterized in that: The target processor core is further used for: Determine, by a third node among the M nodes, useless nodes among the M nodes according to second configuration information, where the second configuration information includes information about the useless nodes; The lower node of the useless node is configured as a child node of the upper node of the useless node.

11. A system management method, characterized in that: Applied to an electronic device, the electronic device includes a processor, the processor includes N processor cores, a target processor core among the N processor cores is configured to manage M hardware resource sets in the electronic device in a tree-like topology structure; the tree-like topology structure includes M nodes, the M nodes constitute a topology structure of 1st layer, 2nd layer, ... K layers from top to bottom, each node in the i-th layer is connected to a node in the (i-1)th layer, each node in the (i-1)th layer is connected to one or more nodes in the i-th layer, any two nodes in the i-th layer and the (i-1)th layer that are connected constitute a pair of parent nodes and child nodes, and the (i-1)th layer corresponds to the parent node and the i-th layer corresponds to the child node; each of the M hardware resource sets corresponds to one of the M nodes; the hardware resource set corresponding to the child node in any pair of parent nodes and child nodes in the tree-like topology structure is a subset of the hardware resource set corresponding to the parent node; L, N, M are integers greater than 0; i is a positive integer greater than or equal to 2 and less than or equal to K; the method comprises: Determine a target task to be executed by using a hardware resource set corresponding to a first node among the M nodes; the first node as a parent node has at least one child node; Determine, by using the hardware resource set corresponding to the first node, a second node corresponding to the target task from the at least one child node; Start the hardware resource set corresponding to the second node to run the target task.

12. The method according to claim 11, characterized in that The target processor core also includes a first register, which is used to store a node identifier of a target node. The node identifier is used to instruct the target processor core to enable a hardware resource set corresponding to the target node. The target node is one of the nodes in the tree topology structure.

13. The method according to claim 12, characterized in that The starting the hardware resource set corresponding to the second node to run the target task includes: updating the node identifier of the second node into the first register; Based on the node identifier of the second node in the first register, a hardware resource set corresponding to the second node is enabled.

14. The method according to any one of claims 11 to 13, characterized in that: The step of determining the target task to be executed includes: Acquire first configuration information from a hardware resource set corresponding to the first node; the first configuration information includes one or more of software entry information of the target task and service entry information provided by the first node; The target task to be currently executed is determined according to the first configuration information.

15. The method according to any one of claims 11 to 14, characterized in that: The method further comprises: Determining, by the target processor core, a useless node in the tree topology structure based on a third node among the M nodes and according to second configuration information, wherein the second configuration information includes information about the useless node; The lower node of the useless node is configured as a child node of the upper node of the useless node.

16. A chip system, characterized in that: The chip system includes a processor, which includes N processor cores. The target processor core among the N processor cores is configured to manage M hardware resource sets in the chip system in a tree-like topology structure; the tree-like topology structure includes M nodes, and the M nodes constitute a topology structure of 1st layer, 2nd layer, ... K layers from top to bottom, each node in the i-th layer is connected to a node in the (i-1)th layer, each node in the (i-1)th layer is connected to one or more nodes in the i-th layer, and any two nodes in the i-th layer and the (i-1)th layer that are connected constitute a pair of parent nodes and child nodes, and the (i-1)th layer corresponds to the parent node and the i-th layer corresponds to the child node; each hardware resource set in the M hardware resource sets corresponds to one of the M nodes; the hardware resource set corresponding to the child node in any pair of parent nodes and child nodes in the tree-like topology structure is a subset of the hardware resource set corresponding to the parent node; L, N, M are integers greater than 0; i is a positive integer greater than or equal to 2 and less than or equal to K.

17. A chip system, characterized in that: The chip system includes at least one processor, a memory and an interface circuit. The memory, the interface circuit and the at least one processor are interconnected by lines. Instructions are stored in the at least one memory. When the instructions are executed by the processor, the method described in any one of claims 11 to 15 is implemented.

18. A computer storage medium, characterized in that: The computer storage medium stores a computer program, which, when executed by a processor, implements the method described in any one of claims 11 to 15.

19. A computer program product, characterized in that The computer program comprises instructions, and when the computer program is executed by a computer or a processor, the computer or the processor executes the method according to any one of claims 11 to 15.

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