Method and device for extracting three-dimensional stray capacitance parameters of periodic structure and storage medium

Abstract

The invention discloses a method and device for extracting three-dimensional stray capacitance parameters of a periodic structure and a storage medium, and the method comprises the steps: extracting one or more periodic layout data from an integrated circuit layout, and recording periodic boundary information when the layout data is extracted, the integrated circuit layout is provided with a plurality of conductors and / or media, and the conductors and / or media are connected with the periodic layout data; the plurality of conductors and / or media are periodically distributed along one direction or multiple directions, and the periodic layout data comprises conductor description information and / or medium description information; based on the extracted conductor description information and / or medium description information, constructing a calculation model of a three-dimensional geometric structure corresponding to a single conductor and / or a single medium, and based on the recorded periodic boundary information, generating a periodic boundary condition corresponding to the calculation model; and based on the calculation model of the three-dimensional geometric structure, according to the periodic boundary condition, a three-dimensional field solver for the periodic structure optimization solving process is used to calculate and obtain the total capacitance of each conductor and the coupling capacitance between the conductors.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit automated design, and more specifically, the present invention relates to a method, device and storage medium for extracting three-dimensional parasitic capacitance parameters of a periodic structure. Background Art

[0002] One of the most notable features of integrated circuit design under the current advanced chip manufacturing process is the increasingly important parasitic parameter effect between interconnects in the chip, which has a significant impact on chip performance and circuit delay. With the development of very large scale integration (VLSI) technology, the electromagnetic parasitic effect of metal interconnects with a width of only nanometers and multi-layer distribution has become a key factor affecting circuit performance and even determining whether the circuit can work properly.

[0003] The task of parasitic parameter extraction is to use parasitic circuit parameters such as resistance, capacitance, and inductance to establish an electromagnetic model for subsequent process analysis and testing for the electromagnetic coupling effect between interconnects. Parasitic parameter extraction affects the evaluation of circuit performance indicators such as delay, power consumption, and reliability, and is crucial to solving signal integrity problems in complex circuits (such as digital / analog hybrid circuits, RF circuits, etc.). The core of parasitic parameter extraction is to calculate the parasitic resistance, capacitance, and inductance of interconnects through Maxwell's electromagnetic field equations. Compared with other parameters, resistance extraction is easier; when the signal frequency is not very high, the inductance effect is not prominent; therefore, capacitance is the most concerned of the three parameters. How to accurately and quickly extract capacitance is becoming increasingly important to ensure design quality, improve manufacturing yield, reduce costs, and shorten design cycles.

[0004] As the industry places increasingly higher demands on the computational accuracy of parasitic parameter extraction, research on parasitic capacitance parameter extraction has evolved from one-dimensional, two-dimensional, 2.5-dimensional to three-dimensional. Three-dimensional capacitance parameter extraction usually requires the establishment of a geometric structure model that reflects the three-dimensional interconnect structure, and then uses numerical methods to solve the electrostatic field equations, which is called a "three-dimensional field solver". The three-dimensional field solver has high computational accuracy, but the amount of calculation is relatively large.

[0005] In actual scenarios, complex layouts often contain a large number of structural elements. If a complete calculation is performed on the entire layout, it will require huge computing resources and time, which is not conducive to reducing costs and shortening the design cycle. Summary of the invention

[0006] Performing a complete calculation of the entire layout to extract parasitic capacitance parameters often requires huge computing resources and time. To solve the above problems, the present invention proposes a method, device and storage medium for extracting three-dimensional parasitic capacitance parameters of a periodic structure for a layout with a periodic structure. This method uses periodic boundary conditions to model a single basic unit through periodic simplification, thereby accurately simulating the entire periodic structure without sacrificing calculation accuracy, realizing rapid extraction of parasitic capacitance, saving computing resources, reducing time costs, and shortening the design cycle.

[0007] To achieve the above object, the present invention adopts the following technical solutions.

[0008] In a first aspect of the present invention, a method for extracting three-dimensional parasitic capacitance parameters of a periodic structure is proposed, and the method steps are specifically as follows:

[0009] S1, extracting one periodic or multiple periodic layout data from an integrated circuit layout, and recording periodic boundary information when extracting the layout data, wherein the integrated circuit layout has multiple conductors and / or media, and the multiple conductors and / or media are periodically distributed along one direction or multiple directions, and the periodic layout data includes conductor description information and / or medium description information;

[0010] S2, constructing a computational model of a three-dimensional geometric structure corresponding to a single conductor and / or a single medium based on the extracted conductor description information and / or medium description information, and generating periodic boundary conditions corresponding to the computational model based on the recorded periodic boundary information;

[0011] S3, based on the calculation model of the three-dimensional geometric structure and according to the periodic boundary conditions, a three-dimensional field solver for the periodic structure optimization solution process is used to calculate and obtain the total capacitance of each conductor and the coupling capacitance between the conductors.

[0012] Furthermore, in S1, the integrated circuit layout data includes conductor description information and medium description information.

[0013] Furthermore, the conductor description information includes the size and position information of the conductor; the medium description information includes the thickness, position and relative dielectric constant ε of the medium. r information.

[0014] Furthermore, the conductor includes a main conductor and an environmental conductor.

[0015] Furthermore, the periodic boundary condition satisfied by the main conductor is: Dirichlet boundary condition u=1, and the periodic boundary condition satisfied by the environmental conductor is: Dirichlet boundary condition u=0.

[0016] Furthermore, when extracting the periodic layout data, the conductor and the medium in the extraction area are truncated according to the position of the truncation window to determine the periodic boundary information.

[0017] Furthermore, after the conductor and medium in the extraction area are cut off, the periodic boundary information is determined according to the conductor and medium generated by the cut off at both sides before and after the period.

[0018] Furthermore, the determining of the periodic boundary information based on the conductor and medium generated by truncation on both sides of the period includes:

[0019] The conductor and medium generated by truncation are directly used as periodic boundary information;

[0020] Alternatively, the conductor and the medium generated by the truncation are identified to determine the periodic boundary information.

[0021] Further, the identifying of the conductor and the medium generated by the truncation to determine the periodic boundary information includes:

[0022] Setting labels at corresponding positions of the integrated circuit layout where the conductor and the medium generated by the truncation are located;

[0023] generating a new integrated circuit layout according to the integrated circuit layout and the label;

[0024] Based on the new integrated circuit layout, geometric shapes of conductors and dielectrics are identified according to the labels;

[0025] Unify geometric shapes with multiple labels into one label according to a given rule;

[0026] Determine geometric shapes with the same label to identify them as the same object, wherein the object is the conductor or the medium;

[0027] The identified object is used as the periodic boundary information.

[0028] Further, generating a new integrated circuit layout according to the integrated circuit layout and the label includes:

[0029] The integrated circuit layout together with the label is translated forward and backward along the periodic arrangement direction by a period length respectively, and forms a new integrated circuit layout with the integrated circuit layout.

[0030] Furthermore, when establishing a computational model of a three-dimensional geometric structure, based on the recorded periodic boundary information, the whole is expanded outward by a set distance on both sides of the periodic direction, and a completely consistent grid division method is used on both sides of the periodic boundary after expansion to generate corresponding periodic boundary conditions.

[0031] Furthermore, the method further comprises:

[0032] For the computational model of the three-dimensional geometric structure, a bias voltage is set for the conductor, a three-dimensional field solver based on the boundary element method is used to calculate the charge on each conductor boundary, and the charge on each conductor boundary is numerically integrated to extract the parasitic capacitance of each conductor.

[0033] Furthermore, the 3D field solver is optimized for periodic structures, including:

[0034] Determine the type of the units on both sides of the periodic direction after discretization, the type is a common unit or a periodic unit, and establish a mapping relationship between the units on both sides of the periodic direction after discretization to form a unit pair;

[0035] The matrix coefficients of the linear equations with the same degree of freedom of the periodic units are assembled according to the unit pairs, and the total capacitance of each conductor and the coupling capacitance between the conductors are calculated accordingly.

[0036] Furthermore, each unit pair has two degrees of freedom, the corresponding electric potential u is used as the first type of physical quantity, and the normal electric field strength q of the boundary surface is used as the second type of physical quantity. It is agreed that each periodic unit stores one degree of freedom, and the units on the front side of the periodic direction uniformly store one of the first type of physical quantity and the second type of physical quantity, and the units on the rear side of the periodic direction uniformly store the other type of physical quantity;

[0037] If the medium information of the two units of a unit pair is inconsistent, the unit attribute of the unit pair is changed from periodic boundary to medium interface, and the total capacitance of each conductor and the coupling capacitance between conductors are calculated as the interface connecting the media on both sides.

[0038] Furthermore, type information is additionally stored at the cell level to determine whether the cell in the cell pair is a periodic cell or a common cell; or by determining whether the geometric coordinates of the cell in the cell pair are equal to the maximum value or minimum value of the truncation window in the periodic direction. If so, it is a periodic cell, otherwise it is a common cell.

[0039] According to a second aspect of the present invention, a three-dimensional parasitic capacitance parameter extraction device for a periodic structure is proposed, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute any of the methods described in the first aspect of the present invention.

[0040] According to a third aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and the computer program can be loaded by a processor to execute any one of the methods according to the first aspect of the present invention.

[0041] The advantages of the present invention compared to the prior art are:

[0042] The present invention improves the performance of the three-dimensional field solver for a layout with a periodic structure. By applying periodic boundary conditions to one or more basic periods for modeling and calculation, instead of calculating the original complete layout, a large reduction in the number of calculation grids is achieved, thereby reducing the dimension of the equation and the number of integral calculations, saving computing resources, and ultimately achieving a significant improvement in computing performance, greatly accelerating the extraction speed of parasitic capacitance parameters of the periodic structure, reducing time costs, and shortening the design cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1A The present invention provides a flow chart of an embodiment of a method for extracting three-dimensional parasitic capacitance parameters of a periodic structure.

[0044] Figure 1B It is a schematic diagram of the periodic structure of an integrated circuit according to an embodiment of the present invention.

[0045] Figure 2 Schematic diagram of a geometric model of a basic period of an integrated circuit according to an embodiment of the present invention.

[0046] Figure 3 It is a schematic diagram of the steps of intelligently identifying periodic boundary information based on extracted layout data according to an embodiment of the present invention.

[0047] Figure 4 is a schematic diagram of a periodic unit pair according to an embodiment of the present invention.

[0048] Figure 5 It is a structural block diagram of an illustrative device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0050] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are usually of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and generally indicates that the objects associated with each other are in an "or" relationship.

[0051] Method Embodiment

[0052] like Figure 1A As shown, the present invention provides a flow chart of an embodiment of a method for extracting three-dimensional parasitic capacitance parameters of a periodic structure, which includes:

[0053] S1, extracting one periodic or multiple periodic layout data from an integrated circuit layout, and recording periodic boundary information when extracting the layout data, wherein the integrated circuit layout has multiple conductors and / or media, and the multiple conductors and / or media are periodically distributed along one direction or multiple directions, and the periodic layout data includes conductor description information and / or medium description information;

[0054] The layout data of integrated circuits can be stored in memory in a variety of storage formats (such as CFI, GDSⅡ, Oasis) in the industry. These layout information describes the relevant characteristics of conductors and media in detail, including the thickness, length, width, and position information of conductors, as well as the thickness, position, and relative dielectric constant ε of the media. r wait.

[0055] like Figure 1B and Figure 2 As shown in the figure, in the constructed integrated circuit geometric structure model, multiple conductors and several dielectrics are usually marked. These conductors are divided into two categories: main conductors, the periodic boundary conditions satisfied by the main conductors are: Dirichlet boundary conditions u = 1 (i.e., the potential is always kept at 1 volt); environmental conductors, the periodic boundary conditions satisfied by the environmental conductors are: Dirichlet boundary conditions u = 0 (i.e., the potential is always kept at 0 volt).

[0056] When extracting periodic layout data, the conductor and medium in the extraction area are truncated according to the position of the truncation window to determine the periodic boundary information. Figure 2As shown, a schematic diagram of a geometric model of a basic cycle obtained through extraction is given (this embodiment takes one cycle as an example, and it should be understood that it is also valid for multiple cycles and is not limited to one cycle). It can be seen that the conductors on the left and right sides are cut off, and the dielectric layer is also cut off in the surrounding directions.

[0057] Furthermore, after the conductors and media in the extraction area are cut off, the periodic boundary information is determined based on the conductors and media generated by the cut off on both sides of the period. That is, the conductors and media generated by the cut off are further identified and recorded as periodic boundary information.

[0058] To this end, further, determining the periodic boundary information according to the conductor and medium generated by truncation on both sides of the period includes:

[0059] The conductor and medium generated by truncation are directly used as periodic boundary information;

[0060] Alternatively, the conductor and the medium generated by the truncation are identified to determine the periodic boundary information.

[0061] The above method is equivalent to directly providing a description of periodic boundary information; or, intelligently identifying periodic boundary information based on extracted layout data.

[0062] Further, the identifying of the conductor and the medium generated by the truncation to determine the periodic boundary information includes:

[0063] Setting labels at corresponding positions of the integrated circuit layout where the conductor and the medium generated by the truncation are located;

[0064] generating a new integrated circuit layout according to the integrated circuit layout and the label;

[0065] Based on the new integrated circuit layout, geometric shapes of conductors and dielectrics are identified according to the labels;

[0066] Unify geometric shapes with multiple labels into one label according to a given rule;

[0067] Determine geometric shapes with the same label to identify them as the same object, wherein the object is the conductor or the medium;

[0068] The identified object is used as the periodic boundary information.

[0069] Further, generating a new integrated circuit layout according to the integrated circuit layout and the label includes:

[0070] The integrated circuit layout together with the label is translated forward and backward along the periodic arrangement direction by a period length respectively, and forms a new integrated circuit layout with the integrated circuit layout.

[0071] by Figure 3 Specifically demonstrated in a specific application scenario, the steps of intelligent identification of periodic boundary information based on extracted layout data are as follows: setting a label at the corresponding position of the layout of the object to be identified, such as Figure 3 a); the layout data together with the label data are shifted forward and backward along the periodic arrangement direction by one period length each, and a new layout is formed with the original data, as shown in Figure 3 b) as shown; Based on the new layout, the label data is subjected to geometric shape recognition, such as Figure 3 c); geometric shapes with multiple labels are unified into one label according to a given rule, such as lexicographic order, such as Figure 3 d); for geometric shapes with the same label, they are identified as the same object, the object information within the basic period is updated, and stored as periodic boundary information, such as Figure 3 e) as shown.

[0072] S2, constructing a computational model of a three-dimensional geometric structure corresponding to a single conductor and / or a single medium based on the extracted conductor description information and / or medium description information, and generating periodic boundary conditions corresponding to the computational model based on the recorded periodic boundary information;

[0073] In S2, whether the periodic boundary conditions can be accurately applied is an important guarantee for reducing the calculation scale by utilizing the periodicity of the structure. However, the basic period obtained by truncating the original layout often cannot guarantee that the two sides of the period have completely overlapping geometric structures due to the complexity of its graphics and the loss of precision of the calculated data. Therefore, it is necessary to load the medium information on both sides of the interface on the periodic boundary based on the recorded periodic boundary information, impose consistent constraints or condense degrees of freedom. On the other hand, in the implementation process of the solution, there is usually a need for encryption of the calculation grid. To solve this problem, the present invention proposes the following implementation method: When establishing a calculation model of a three-dimensional geometric structure, based on the recorded periodic boundary information, the overall expansion is a set distance on both sides of the periodic direction, and a completely consistent grid division method is used on the periodic boundaries on both sides after the expansion and the corresponding periodic boundary conditions are generated.

[0074] S3, based on the constructed computational model of the three-dimensional geometric structure, uses a three-dimensional field solver to calculate and obtain the total capacitance of each conductor and the coupling capacitance between the conductors.

[0075] Furthermore, the method may also include: for the calculation model of the three-dimensional geometric structure, setting a bias voltage for the conductor, using a three-dimensional field solver based on the boundary element method to calculate the amount of charge on each conductor boundary, and numerically integrating the amount of charge on each conductor boundary to extract the parasitic capacitance of each conductor.

[0076] The numerical simulation of interconnect capacitance extraction requires solving the electrostatic field equations, setting a specific bias voltage for the conductor, calculating the charge on each conductor boundary, and then numerically integrating the charge on each conductor boundary to extract the parasitic capacitance of each conductor. This can be done as follows:

[0077] 1) Establish the electrostatic field equation

[0078] From the Maxwell equations, it can be seen that the potential distribution of the interconnected parasitic capacitor with a certain bias voltage can be described by the Laplace equation with mixed boundary conditions:

[0079]

[0080]

[0081]

[0082]

[0083] u before =u after ,q before =-q after , onΓ cyclic (5)

[0084] Among them, the domain to be solved Ω=∪Ω k ,Ω k is the area occupied by medium k, m is the total number of media contained. u is the electric potential, Represents the normal electric field strength on the boundary surface, and n is the normal to the boundary unit. ε k is the dielectric constant of medium k. At the interface of the medium Γ I The subscripts a and b represent the two adjacent media. cyclic The subscripts before and after represent the front and back sides of the period direction respectively.

[0085] (a) Equation (1) shows that the potential u satisfies Laplace's equation in each dielectric region.

[0086] (b) Equation (2) indicates that the Dirichlet boundary condition is satisfied on each conductor surface, with u=1 on the main conductor surface and u=0 on the ambient conductor surface.

[0087] (c) Equation (3) indicates that the Neumann boundary condition is satisfied on the outer boundary of each dielectric region.

[0088] (d) Equation (4) represents the electric displacement at the dielectric interface and the potential continuity condition.

[0089] (e) Equation (5) represents the periodic boundary condition in the periodic direction.

[0090] 2) Calculation of parasitic capacitance

[0091] The capacitance C between two conductors i and j ij Defined as:

[0092] C ij =-Q i / V ji (6)

[0093] Among them, Q i is the induced charge on conductor i, V ji is the voltage between conductors j and i. Charge Q i It can be obtained by the following formula:

[0094]

[0095] Among them, Γ i is the outer surface of conductor i.

[0096] The calculation of parasitic capacitance can be reduced to solving the normal electric field strength on the conductor surface under a certain bias voltage. Apply 1 volt voltage to the main conductor and 0 volt voltage to the ambient conductor; then calculate the normal electric field strength on the conductor surface; by integrating the electric field strength, calculate the induced charge on the conductor. The absolute value of the charge on the ambient conductor is the coupling capacitance between it and the main conductor. The amount of charge on the main conductor represents the total capacitance between it and the ambient conductor.

[0097] In S3, for the calculation model of the three-dimensional structure of the integrated circuit, a three-dimensional field solver based on a direct boundary element method is used to extract the parasitic capacitance parameters of each conductor.

[0098] Using Green's formula and the basic solution of Laplace's equation u * The Laplace equation (1) with mixed boundary conditions under a certain bias voltage can be transformed into the following direct boundary integral equation:

[0099]

[0100] Among them, u s is the electric potential at the source point s, c s is the geometric shape constant at the source point s. In particular, when the boundary where the source point is located is a smooth surface, cs =0.5, is the boundary of medium k.

[0101] Basic solution of three-dimensional * for

[0102]

[0103] Where r is the distance between the source point s and the field point p(x,y,z)

[0104]

[0105] By discretizing the region boundary, we can obtain a series of discretized boundary integral equations:

[0106]

[0107] Substituting boundary conditions (2) to (5) into equation (10), we obtain the linear algebraic equation system:

[0108] Ax=b (12)

[0109] Solve equation group (12). Calculate the parasitic capacitance parameters (capacitance value) by equation (7).

[0110] In S3, the three-dimensional field solver optimization for periodic structures is implemented, including:

[0111] 1)Storing periodic unit pair information;

[0112] According to the periodic boundary information, a mapping relationship is established between the discretized units on both sides to form a unit pair. Figure 4 It shows three groups of unit pairs (A1 and A2, B1 and B2, C1 and C2) formed along the periodic direction after the boundary is discretized.

[0113] 2) Update the unit attributes of the unit pair;

[0114] If the media information of two units in a unit pair is inconsistent, it means that the truncation window is located at the interface of the media. Figure 4 As shown in the unit pair B in the figure, the unit attribute of the unit pair is changed from periodic boundary to medium interface, and the relevant interface data is updated. When calculating, it is processed as the interface connecting the media on both sides.

[0115] 2) Storage and access of physical quantities of periodic units;

[0116] Each unit pair has two degrees of freedom, corresponding to the electric potential u as the first-order physical quantity and the normal electric field strength on the boundary surface As a second-class physical quantity. Figure 4As shown, it is agreed that each periodic unit stores one degree of freedom, the units on the front side of the periodic direction uniformly store one of the first type of physical quantity and the second type of physical quantity (such as u), and the units on the back side of the periodic direction uniformly store another type of physical quantity (corresponding to the previous text, such as q). If you need to access the physical quantity of a periodic unit, you can do so by accessing the degree of freedom of the unit and the degree of freedom of the next unit to which it belongs.

[0117] 3) Rapid determination of periodic units;

[0118] It is necessary to distinguish between common cells and periodic cells during calculation. In addition to storing type information at the cell level, the present invention also proposes an implementation method that does not require additional storage. Considering the characteristic that the periodic cell is always on the boundary of the truncation window, when the geometric coordinates of the cell are equal to the maximum or minimum value of the truncation window in the period direction, it is a periodic cell, otherwise it is a common cell.

[0119] 4) Calculate the matrix coefficients of the linear equation system.

[0120] Traverse the units and calculate the matrix coefficients of the linear equation system: for ordinary units, the matrix coefficients are calculated and assembled in the usual way; for periodic units, after the coefficients are calculated, the coefficients with the same degree of freedom are assembled according to the unit pairs.

[0121] To this end, based on the above optimization of the three-dimensional field solver for periodic structures, it can be seen that it essentially includes:

[0122] Determine the type of the units on both sides of the periodic direction after discretization, the type is a common unit or a periodic unit, and establish a mapping relationship between the units on both sides of the periodic direction after discretization to form a unit pair;

[0123] The matrix coefficients of the linear equations with the same degree of freedom of the periodic units are assembled according to the unit pairs, and the total capacitance of each conductor and the coupling capacitance between the conductors are calculated accordingly.

[0124] Furthermore, each unit pair has two degrees of freedom, the corresponding electric potential u is used as the first type of physical quantity, and the normal electric field strength q of the boundary surface is used as the second type of physical quantity. It is agreed that each periodic unit stores one degree of freedom, and the units on the front side of the periodic direction uniformly store one of the first type of physical quantity and the second type of physical quantity, and the units on the rear side of the periodic direction uniformly store the other type of physical quantity;

[0125] If the medium information of the two units of a unit pair is inconsistent, the unit attribute of the unit pair is changed from periodic boundary to medium interface, and the total capacitance of each conductor and the coupling capacitance between conductors are calculated as the interface connecting the media on both sides.

[0126] Furthermore, type information is additionally stored at the cell level to determine whether the cell in the cell pair is a periodic cell or a normal cell; or by determining whether the geometric coordinates of the cell in the cell pair are equal to the maximum or minimum value of the truncation window in the periodic direction. If it is equal to the maximum or minimum value of the window, it is a periodic cell, otherwise it is a normal cell.

[0127] According to one aspect of an embodiment of the present invention, a three-dimensional parasitic capacitance parameter extraction device for a periodic structure is provided. The device can be implemented by a general computer or computer system, and the computer or computer system has an input device, a display device, an external I / F, a communication I / F, a processor, and a memory. These hardware are connected to each other in a manner that can communicate via a bus.

[0128] The processor is a computer's internal CPU, or a dedicated CPU, DSP or other processing unit. The memory device includes a computer-readable storage medium, such as a computer read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0129] The memory stores a program running on the processor, and the processor executes the process of the above-mentioned method for extracting three-dimensional parasitic capacitance parameters of a periodic structure when running the program.

[0130] Figure 5 Schematic diagram of the device structure according to one embodiment of the present invention. Figure 5 As shown, the device may include one or more ( Figure 5 Only one is shown) a processor and a memory for storing data. Figure 5 The structure shown is only for illustration and does not limit the structure of the above terminal device. Figure 5 More or less other functional components as shown in, or having the same Figure 5 Equivalent functions or comparisons shown Figure 5 The functions shown have more different configurations, and other functional components are determined according to the application scenarios. This application does not limit them to uniqueness.

[0131] According to one aspect of an embodiment of the present invention, the present invention also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the above-mentioned method embodiment are implemented and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0132] Based on the above-mentioned embodiments, the present application also provides a method for extracting parameters of three-dimensional parasitic capacitance of a periodic structure, which includes:

[0133] Extracting conductor and / or dielectric description information from integrated circuit layout;

[0134] Constructing a computational model of a three-dimensional geometric structure corresponding to a single conductor and / or a single medium based on the extracted conductor and / or medium description information, and generating periodic boundary conditions of the computational model in combination with the recorded periodic boundary information;

[0135] Based on the constructed three-dimensional geometric structure calculation model and in accordance with periodic boundary conditions, the total capacitance of each conductor and / or the coupling capacitance between the conductors are calculated.

[0136] The various steps mentioned in this embodiment are described exemplarily with reference to the records of the above specific embodiments, and will not be described in detail here.

[0137] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A method for extracting parameters of three-dimensional parasitic capacitance of a periodic structure, characterized in that: include: S1, extracting one periodic or multiple periodic layout data from an integrated circuit layout, and recording periodic boundary information when extracting the layout data, wherein the integrated circuit layout has multiple conductors and / or media, and the multiple conductors and / or media are periodically distributed along one direction or multiple directions, and the periodic layout data includes conductor description information and / or medium description information; S2, constructing a computational model of a three-dimensional geometric structure corresponding to a single conductor and / or a single medium based on the extracted conductor description information and / or medium description information, and generating periodic boundary conditions corresponding to the computational model based on the recorded periodic boundary information; S3, based on the calculation model of the three-dimensional geometric structure and according to the periodic boundary conditions, a three-dimensional field solver for the periodic structure optimization solution process is used to calculate and obtain the total capacitance of each conductor and the coupling capacitance between the conductors.

2. The method for extracting parameters of three-dimensional parasitic capacitance of a periodic structure according to claim 1, characterized in that: When extracting the periodic layout data, the conductor and the medium in the extraction area are truncated according to the position of the truncation window to determine the periodic boundary information.

3. The method for extracting parameters of three-dimensional parasitic capacitance of a periodic structure according to claim 2, characterized in that: Determining the periodic boundary information according to the conductor and medium generated by truncation on both sides of the period includes: The conductor and medium generated by truncation are directly used as periodic boundary information; Alternatively, the conductor and the medium generated by the truncation are identified to determine the periodic boundary information.

4. The method for extracting parameters of three-dimensional parasitic capacitance of a periodic structure according to claim 3, characterized in that: The step of identifying the conductor and the medium generated by the truncation to determine the periodic boundary information includes: Setting labels at corresponding positions of the integrated circuit layout where the conductor and the medium generated by the truncation are located; The integrated circuit layout together with the label is translated forward and backward along the period arrangement direction by a period length respectively, and a new integrated circuit layout is formed with the integrated circuit layout; Based on the new integrated circuit layout, geometric shapes of conductors and dielectrics are identified according to the labels; Unify geometric shapes with multiple labels into one label according to a given rule; The geometric shapes having the same label are determined to be identified as the same object, where the object is the conductor or the medium.

5. The method for extracting parameters of three-dimensional parasitic capacitance of a periodic structure according to claim 1, characterized in that: When establishing a computational model of a three-dimensional geometric structure, based on the recorded periodic boundary information, the entire structure is expanded outward by a set distance on both sides of the periodic direction, and a completely consistent grid division method is used on the periodic boundaries on both sides after expansion to generate corresponding periodic boundary conditions.

6. The method for extracting parameters of three-dimensional parasitic capacitance of a periodic structure according to claim 1, characterized in that: Also includes: For the computational model of the three-dimensional geometric structure, a bias voltage is set for the conductor, a three-dimensional field solver based on the boundary element method is used to calculate the charge on each conductor boundary, and the charge on each conductor boundary is numerically integrated to extract the parasitic capacitance of each conductor.

7. The method for extracting parameters of three-dimensional parasitic capacitance of a periodic structure according to claim 1, characterized in that: Optimized 3D field solvers for periodic structures, including: Determine the type of the units on both sides of the periodic direction after discretization, the type is a common unit or a periodic unit, and establish a mapping relationship between the units on both sides of the periodic direction after discretization to form a unit pair; The matrix coefficients of the linear equations with the same degree of freedom of the periodic units are assembled according to the unit pairs, and the total capacitance of each conductor and the coupling capacitance between the conductors are calculated accordingly.

8. The method for extracting parameters of three-dimensional parasitic capacitance of a periodic structure according to claim 7, characterized in that: Each unit pair has two degrees of freedom, the corresponding electric potential u is used as the first type of physical quantity, and the normal electric field strength q of the boundary surface is used as the second type of physical quantity. It is agreed that each periodic unit stores one degree of freedom, and the units on the front side of the periodic direction uniformly store one of the first type of physical quantity and the second type of physical quantity, and the units on the back side of the periodic direction uniformly store the other type of physical quantity; If the medium information of the two units of a unit pair is inconsistent, the unit attribute of the unit pair is changed from periodic boundary to medium interface, and the total capacitance of each conductor and the coupling capacitance between conductors are calculated as the interface connecting the media on both sides.

9. A three-dimensional parasitic capacitance parameter extraction device for a periodic structure, characterized in that: include: at least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which can be loaded by a processor to execute the method according to any one of claims 1 to 8.

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