Compression of analog content addressable memory

Abstract

The invention relates to compression of analog content addressable memory. Random input data is applied to the analog CAM array, and an average similarity measure is calculated for each output row of the analog CAM array. Rows in the analog CAM array having similarity metrics close to each other may be eliminated, such as by removing or merging similar rows together. Therefore, the size of the analog CAM array can be reduced without losing the accuracy of the model stored on the analog CAM array.

Description

Background Art

[0001] Content addressable memory (CAM) is a computational memory in which the stored data is accessed not by its location but by its content. Analog CAM can search for multi-level voltages and store analog ranges in non-volatile memory. Each analog CAM cell of the analog CAM can be programmed with a voltage range (e.g., variance range) limited by an upper and lower limit. Words or "tags" are input into the analog CAM, and the analog CAM searches for tags in its content, and when the value of the input data matches the storage voltage value range, the analog CAM returns the address of the location where the found content resides. CAM is powerful, efficient, and fast. However, CAM is also relatively large, consumes a lot of power, and is relatively expensive. These shortcomings limit their applicability, making the application of selecting their power, efficiency, and speed sufficient to offset their size, cost, and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures.

[0003] Figure 1 is a block diagram of a content addressable memory system according to some implementations.

[0004] Figure 2 A portion of an analog CAM array is illustrated in accordance with some implementations.

[0005] Figure 3A An example of a circuit configuration for simulating a CAM cell during a search operation according to some embodiments is illustrated.

[0006] Figure 3B An example of a circuit configuration for emulating a CAM cell during a compression operation is illustrated in accordance with some implementations.

[0007] Figure 4 Illustrated is a configuration for emulating a CAM cell during a compression operation according to some embodiments.

[0008] Figure 5 A flow chart of a method for performing compression on an analog CAM array is illustrated in accordance with some implementations.

[0009] Fig. 6A is a diagram illustrating, according to some embodiments, Figure 5 A conceptual diagram of the steps for removing rows of an analog CAM array in a compression method shown in FIG.

[0010] Figure 6B is a diagram illustrating, according to some embodiments, Figure 5A conceptual diagram of the steps in the compression method for merging two rows of an analog CAM array is shown in FIG.

[0011] Figure 7 is a block diagram of a computing system according to some implementations.

[0012] Figure 8 A flow chart of a method for performing compression on an analog CAM array is illustrated in accordance with some implementations.

[0013] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.The figures are drawn to clearly illustrate the relevant aspects of the disclosure and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0014] The following disclosure provides many different examples for implementing different features. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting.

[0015] Various embodiments described herein are directed to compression of analog content addressable memory (CAM) arrays that implement analog representations of sparse lookup tables (LUTs). Sparse LUTs can be generated by any acceptable technology. For example, sparse LUTs can be based on machine learning models (e.g., such as decision tree models). The analog CAM array includes a plurality of analog CAM cells arranged in rows and columns. The overall utilization of the analog CAM array may not be optimal because some rows of CAM cells in the analog CAM array may be filled with redundant data, or may not be filled at all. Therefore, it becomes advantageous to identify similar rows and perform compression methods to eliminate similar rows (e.g., by merging these similar rows or even removing some rows in similar rows completely).

[0016] A method for compressing an analog CAM array includes applying random input data to each row of the analog CAM array, and calculating an average similarity metric of the output of each row of the analog CAM array. The similarity metric of each row of the analog CAM cells is measured by sensing the discharge current flowing through the pull-down transistor of the CAM cell and entering the discharge line of the row. The discharge line of the CAM cell of each row is connected to a transimpedance amplifier (TIA) and an analog-to-digital converter (ADC). The TIA produces an analog output for each row, which can be sensed by the ADC and converted into a digital representation. This digital representation is a similarity metric of the row of the analog CAM array with the applied input. The average similarity metric of the row of the analog CAM array is then calculated by the number of elements of the random input data, and then this average similarity metric is compared with other digital representations of the average similarity metrics of other rows calculated. Then the rows in the analog CAM array with average similarity metrics close to each other (within a desired amount) can be merged together and / or one of these rows can be removed to compress them. In the case of using an analog CAM as a decision tree reasoning accelerator, the advantageous features of one or more embodiments disclosed herein can allow the size of the analog CAM array to be reduced by up to 15 percent without a significant loss in model reasoning accuracy. This allows the number of analog CAM rows that need to be programmed to be reduced, thereby saving time. Additionally, a reduction in footprint or memory size can be achieved. This results in lower power consumption, as a smaller memory array requires fewer active components and consumes less energy during search and write operations. Further, the use of compression allows larger models to be converted to analog representations using analog CAM arrays, as the models are not limited to the size that the physical array can encode.

[0017] Figure 1 is a block diagram of a content addressable memory device 50 according to some embodiments. The content addressable memory device 50 includes an analog CAM array 52 and a plurality of peripheral circuits for programming and operating the analog CAM array 52. ​​The peripheral circuits include a search / write circuit 54, a precharge circuit 56, a sense circuit 58, a mode selection circuit 60, and a controller 62. As mentioned above, the analog CAM array 52 can search multiple levels of voltage and store analog values ​​in a non-volatile memory such as a memristor (or programmable resistor). A voltage range (e.g., a variance range) can be programmed for each analog CAM cell of the analog CAM array 52, and the analog CAM array can be implemented using a circuit (described later) including, for example, a plurality of memristors.

[0018] In general, a CAM can be implemented with a technology that allows the CAM to store its contents even when power is off or otherwise removed. Thus, the CAM's data is more persistent, allowing the CAM to act as a non-volatile memory. For example, these technologies include resistive memory (i.e., memristor), phase change memory, magnetoresistive memory, ferroelectric memory, some other resistive random access memory device, or a combination of those technologies.

[0019] exist Figure 2 , the configuration of the analog CAM cells 55 within the analog CAM array 52 is shown. The analog CAM array 52 includes a plurality of analog CAM cells 55 arranged in rows (e.g., R1, R2, R3, etc.) and columns (e.g., C1, C2, C3, etc.). Each row of the analog CAM cells 55 stores a word. During a search operation, a search word of analog input data is transmitted to the analog CAM array 52 via data lines (e.g., DL0, DL1, DL2, etc.). Each row of the analog CAM cells 55 then indicates whether the value of the analog input data matches the storage voltage value range of the row. The storage voltage value range encoded in each analog CAM cell 55 is compared with the corresponding input data value of the search word. Each analog CAM cell 55 can match any value within its programmed variance range (wherein the range includes non-binary values). During a write operation, the storage word of the analog input data is transmitted to the row of the analog CAM cells 55 of the analog CAM array 52. ​​The storage range of each analog CAM cell 55 is encoded based on the corresponding input data value of the storage word.

[0020] Return to reference Figure 1 , the search / write circuit 54 is adapted to perform a search operation, a write operation, or a compression operation for the analog CAM array 52. ​​The search / write circuit 54 may include a digital-to-analog converter (DAC). The DAC is used to apply a write voltage to the analog CAM cells 55 of the analog CAM array 52 during a write operation, and to apply a search voltage to the analog CAM cells 55 of the analog CAM array 52 during a search operation. The search / write operation may involve setting an appropriate analog voltage level to represent a desired data pattern. For example, the DAC may apply a write voltage to program a voltage range (e.g., a variance range) for each analog CAM cell 55, or may apply a search voltage to test whether the search voltage is within a voltage range (e.g., a variance range) programmed in each analog CAM cell 55.

[0021] The precharge circuit 56 is configured to precharge the match line of each analog CAM row 53 to a voltage V before the search operation begins. ML, and is further configured to set the match line of each analog CAM row 53 to a constant voltage during a compression operation. During a search operation, if the row of input data applied to the analog CAM cells 55 of the analog CAM row 53 matches the range of stored voltage values ​​in the corresponding analog CAM cells 55, then the match line of the analog CAM row 53 is held high (e.g., held at a voltage V ML Alternatively, if the analog input data applied to analog CAM cell 55 of analog CAM row 53 does not match the range of stored voltage values ​​in analog CAM cell 55, the match line goes low (e.g., voltage V ML During the compression operation, the match line of the analog CAM row 53 is held at a constant voltage to induce a discharge current that can be measured to quantify the similarity of the analog CAM row 53 to the test word.

[0022] The sensing circuit 58 is adapted to sense the output of the analog CAM rows 53 of the analog CAM array 52. ​​The sensing circuit 58 may include a sense amplifier for each analog CAM row 53. Additionally, the sensing circuit 58 may include a transimpedance amplifier (TIA) and an analog-to-digital converter (ADC) (described later) for each analog CAM row 53. During the search operation, the discharge line of the analog CAM cell 55 of each analog CAM row 53 is connected to the reference voltage V NS . The match lines of the analog CAM cells 55 of each analog CAM row 53 are connected to a sense amplifier. The sense amplifier can be used during a search operation to detect whether the match line of the analog CAM row 53 is high (indicating a match with the search term) or low (indicating a non-match with the search term). As described in more detail later, the sense circuit 58 is also used to test the analog CAM rows 53 during a compression operation. During a compression operation, the discharge lines of the analog CAM cells 55 of each analog CAM row 53 are connected to the TIA and ADC. The TIA and ADC can be used during a compression operation to determine a similarity value of the analog CAM row 53 to a test term.

[0023] The mode selection circuit 60 is used to switch the analog CAM array 52 between different modes. For example, the mode selection circuit 60 can switch the analog CAM array 52 between a mode for performing a search operation and a mode for performing a write operation. The mode selection circuit 60 may include a multiplexer for each analog CAM row 53. The multiplexer is used to rewire the connection of the analog CAM array 52 to the sensing circuit 58.

[0024] The controller 62 is adapted to control the mode selection circuit 60, the sensing circuit 58, and the search / write circuit 54. The controller 62 may include a digital control circuit (e.g., a microcontroller), an application specific integrated circuit, or the like. The digital control circuit provides the necessary control signals and data to the mode selection circuit 60, the sensing circuit 58, and the search / write circuit 54. For example, the digital control circuit may be used to drive the DAC of the search / write circuit 54, and to control and coordinate the operation of the DAC. The controller 62 may include other components, such as a clock circuit for temporalizing operations in the content addressable memory device 50.

[0025] Figure 3A An example of a circuit configuration 80 for an analog CAM cell 55 during a search operation is illustrated. Specifically, one analog CAM cell 55 of a row is shown along with a sense amplifier 68 of a sense circuit 58 for the row. The circuit configuration 80 for the analog CAM cell 55 is shown as an example having a 6T2M circuit implementation. In other words, the circuit configuration 80 includes six transistors (e.g., T1 to T6) and two memristors (e.g., a first memristor M1 and a second memristor M2). Further, the circuit configuration 80 includes a match line ML, a data line DL, a first source line SL, and a second memristor M2. HI and the second source line SL LO . The first memristor M1 coupled in series with the transistor T1 can be considered as a memristor-transistor pair M1 / T1. The second memristor M2 coupled in series with the transistor T3 can be considered as a memristor-transistor pair M2 / T3. Memristors can be used as non-volatile electronic memory devices whose resistance can be programmed. Therefore, analog values ​​can be stored (or encoded on the analog CAM cell 55) by the analog CAM cell 55 using the conductance of the memristor of the corresponding cell. The variance range (also called storage range or width) of the analog CAM cell 55 is defined by the lower limit encoded by the conductance of the first memristor M1 and the upper limit encoded by the conductance of the second memristor M2.

[0026] During a write operation, a programming voltage is applied to the first memristor M1 and the second memristor M2 of the analog CAM cell 55 to program the storage voltage range (eg, variance range) of each analog CAM cell 55. This is done by applying a voltage to the first source line SL HI To increase the conductance of the first memristor M1 and / or the second memristor M2 and apply a voltage to the second source line SL LO This is done to reduce the conductance of the first memristor M1 and / or the second memristor M2. During a write operation, voltages may also be applied to the data line DL. The search / write circuit 54 may be used to apply these voltages to the data line DL, the first source line SL HI and the second source line SLLO .

[0027] During the search operation, a voltage is applied to the data line DL to provide analog input data for comparison with the range of stored voltage values ​​in the first memristor M1 and the second memristor M2. The search / write circuit 54 can be used to apply the voltage to the data line DL. The data line DL is electrically connected to the gate of the transistor T1 and is electrically connected to the gate of the transistor T3. Therefore, the circuit configuration 80 receives an input value via DL, which is used to set a target value associated with the searched input data. In operation, this desired search target value is input via DL, and the analog CAM unit 55 matches when the input target value is within the range of stored voltage values ​​defined by the conductance of the first memristor M1 and the second memristor M2. In the illustrated example, transistors T1 to T6 can be implemented as metal oxide semiconductor field effect transistors (MOSFETs) or the like.

[0028] The presence or absence of a match between the search input data received via the data line DL and the data in the storage voltage value range in the analog CAM cell 55 is indicated on the match line ML. The match line ML is precharged to a voltage V before the search operation begins (e.g., using precharge circuit 56). ML When performing a search operation, if the analog input data applied to the analog CAM cell 55 via the data line DL matches the range of stored voltage values ​​encoded in the analog CAM cell 55, the match line ML remains high (eg, at a voltage V ML Alternatively, if the analog input data applied to the analog CAM cell 55 via the data line DL does not match the range of stored voltage values ​​encoded in the analog CAM cell 55, the match line ML goes low (e.g., voltage V ML The voltage V ML The voltage V drops because the current in the match line ML is discharged through either the pull-down transistor T2 or the pull-down transistor T6 of the analog CAM cell 55. For example, when the target search value of the analog input data applied to the analog CAM cell 55 via the data line DL is lower than the lower limit of the variance range encoded by the conductance of the first memristor M1, the voltage V ML As the current in the match line ML is discharged through the pull-down transistor T2 and enters the discharge line 66, it decreases. Further, when the target search value of the analog input data applied to the analog CAM cell 55 via the data line DL is higher than the upper limit of the variance range encoded by the conductance of the second memristor M2, the voltage V ML As the current in the match line ML is discharged through the pull-down transistor T6 and into the discharge line 66, it decreases. Each row of analog CAM cells 55 is connected to a corresponding discharge line 66, which may be horizontally aligned with the analog CAM cells 55 to which it is connected.

[0029] During a search operation, the match line ML is connected in series to a sense amplifier 68 of the sense circuit. The sense amplifier 68 senses the voltage signal in the match line ML and distinguishes between a signal indicating a match (e.g., a high signal) and a signal indicating a mismatch (e.g., a low signal). In this manner, the sense circuit is used to determine whether a given analog CAM cell 55 matches the value of the search term.

[0030] Return to reference Figure 2 , the analog CAM cells 55 of each analog CAM row 53 are connected to and share corresponding match lines. Therefore, the corresponding match line of each analog CAM row 53 will only indicate a match if all target search values ​​of the analog input data applied to the corresponding analog CAM cells 55 of the analog CAM row 53 match the range of stored voltage values ​​encoded in the corresponding analog CAM cells 55. The corresponding match line of the analog CAM row 53 indicates a mismatch if one or more target search values ​​of the analog input data applied to the corresponding analog CAM cells 55 of the analog CAM row 53 do not match the range of stored voltage values ​​encoded in the corresponding analog CAM cells 55. The match lines of the analog CAM row 53 are coupled to the sense amplifiers 68 of the sense circuit of the row.

[0031] The analog CAM array 52 may include an implementation of a sparse lookup table (LUT), such as a sparse lookup table created as an analog representation of a machine learning model. The machine learning model may be based on a tree-based model, such as a decision tree model, a random forest model, a gradient boosting model, an XGboost model, and the like.

[0032] The decision tree model is a machine learning algorithm typically used for classification and regression tasks. It has a tree-like structure where each internal node represents a decision based on a specific feature and each leaf node represents a class label or predicted value. The machine learning algorithm makes decisions based on the features of the input data by following the path from the root node to the leaf node.

[0033] Thus, a decision tree model may be mapped to an analog CAM array 52, wherein the decision tree model suggests routing decisions and these routing decisions are converted into rules that may be stored in the analog CAM array 52. ​​A decision tree model typically consists of discrete branches with specific conditions at each node. These discrete conditions may be converted into an analog representation using the analog CAM array 52, wherein each analog CAM row 53 of the analog CAM array 52 may represent a different path or sequence of nodes in the decision tree. This would involve encoding the conditions and results along each of the different paths into the analog CAM cells 55 of each analog CAM row 53. For example, as previously described above in Figure 1As described in , this encoding can involve applying a programming voltage to the analog storage element (e.g., the first memristor M1 and the second memristor M2) of each analog CAM cell 55 to program a voltage range (e.g., a variance range) for each analog CAM cell 55. In addition, in the analog representation, each column (e.g., C1, C2, C3, etc.) can be a separate node in the decision tree. Each column can correspond to a corresponding feature vector (e.g., f1, f2, f3...) evaluated at the node. The storage voltage value range encoded in each analog CAM cell 55 of the analog CAM row 53 is compared with the input data, and an output indicates whether the value of the input data matches the storage voltage value range in the analog CAM row 53.

[0034] Further references Figure 2 , the example configuration shows that the analog CAM cells 55 of each column (e.g., C1, C2, C3, etc.) of the analog CAM array 52 can be searched individually on corresponding data lines (e.g., DL0, DL1, DL2, etc.). The data lines (e.g., DL0, DL1, DL2, etc.) each receive an analog value to be searched by the analog CAM array 52, which is applied to each of the data lines via a corresponding voltage (e.g., V DL0 、V DL1 、V DL2 etc.) to transmit. Figure 2 As can be seen in FIG. 5 , each data line can be vertically aligned with and coupled to a corresponding column of the analog CAM array 52. ​​Whether there is a match between the data stored in each analog CAM cell 55 within a particular analog CAM row 53 and the search input data received via the corresponding data line is indicated on the match line (e.g., ML0, ML1, ML2, ML3, etc.).

[0035] As previously described, the analog CAM cells 55 of each analog CAM row 53 are connected to and share a corresponding match line (e.g., ML0, ML1, ML2, ML3, etc.) that is precharged to a voltage V before the search operation begins. ML The corresponding match line may be horizontally aligned with the analog CAM cell 55 to which it is connected. When performing a search operation, if the analog input data applied to each analog CAM cell 55 of the analog CAM row 53 matches the range of stored voltage values ​​encoded in the corresponding analog CAM cell 55, the corresponding match line is held high (e.g., held at a voltage V ML Alternatively, if the analog input data applied to the analog CAM cell 55 of the analog CAM row 53 does not match the range of stored voltage values ​​encoded in the corresponding analog CAM cell 55, the corresponding match line goes low (e.g., voltage VML drops) to indicate a mismatch.

[0036] When the decision tree model is stored in the analog CAM array 52, it is desirable to compress the analog CAM array 52 by eliminating similar rows of the analog CAM array 52. ​​Due to the nonlinearities, the match lines of the rows of the analog CAM array 52 may not change abruptly between the high state and the low state, but may change gradually between the high state and the low state depending on the proximity of the search value to the upper / lower limits stored in the analog CAM cells 55. As a result of these nonlinearities, the rows of the analog CAM array 52 may be considered similar to each other (within a desired amount), even though the rows may not be exactly the same. For example, two branches of a decision tree model may be similar enough that they may both be stored in the same row of the analog CAM array 52. ​​The analog CAM array 52 may be compressed during a compression operation.

[0037] Figure 3B An example of a circuit configuration 80 for emulating the CAM cell 55 during a compression operation is shown. During a compression operation, the circuit configuration 80 is rewired so that the TIA 70 and ADC 72 of the sensing circuit 58 are used to sense the discharge line 66. The circuit can be rewired by using the mode selection circuit 60 (see Figure 1 For example, a multiplexer of the mode selection circuit may be connected to the discharge line 66 and used to select whether the discharge line 66 is coupled to the input of the TIA 70 (during compression operation) or to the reference voltage V NS (during the search operation). Therefore, the discharge line 66 is configured to be coupled to the reference voltage V NS and TIA 70, and can switch between the reference voltage and the TIA by the mode selection circuit 60 during operation.

[0038] exist Figure 4, the configuration of the analog CAM cells 55 within the analog CAM array 52 during a compression operation is shown. All of the analog CAM cells 55 of each analog CAM row are connected to and share a corresponding discharge line 66. During the compression operation, the match line ML of the analog CAM row is maintained at a constant voltage (e.g., using a precharge circuit 56). As a result, a discharge current flows from the match line ML through the analog CAM cells 55 of the analog CAM row to the discharge line 66 of the analog CAM row. The discharge currents flowing through the corresponding discharge lines 66 of different analog CAM rows can be used as a basis for comparing and determining how similar the analog CAM rows are to each other (e.g., via determining a similarity metric). This is because, due to the previously mentioned nonlinearity, the discharge current in each discharge line 66 is a collective measure of the mismatch between the target search value of the analog input data applied to the corresponding analog CAM cell 55 of the analog CAM row and the range of storage voltage values ​​that have been encoded in the corresponding analog CAM cell 55 of the analog CAM row.

[0039] The analog voltage output of each analog CAM row generated by the TIA 70 can be sensed and converted to a digital representation by the ADC 72. The digital values ​​generated by the ADC 72 represent the analog voltage outputs (AOUT0 to AOUT2) resulting from the corresponding discharge currents in the different discharge lines 66. Since each voltage output is proportional to the discharge current in the corresponding discharge line 66, the digital values ​​generated by the ADC 72 are also proportional to the discharge current in the corresponding discharge line 66. These digital representations can now be used as a similarity metric for the analog CAM rows, which can be compared to each other to identify similar analog CAM rows of the analog CAM array 52.

[0040] exist Figure 5 , a schematic diagram for simulating a CAM array 52 (previously described in Figures 1 to 4 The analog CAM array 52 may be used to implement a sparse lookup table (LUT) that is an analog representation of a machine learning model. The analog CAM array 52 includes a plurality of analog CAM cells 55 arranged in rows (e.g., R1, R2, R3, etc.) and columns (e.g., C1, C2, C3, etc.), and may also be represented as a matrix T of size M×N, where M is the number of rows and N is the number of columns.

[0041] In step 102, a voltage is programmed into the analog storage element (e.g., the first memristor M1 and the second memristor M2) of each analog CAM cell 55 of the analog CAM array 52. ​​This programming may involve using the search / write circuit 54 (previously described in Figure 1The analog CAM cell 55 is programmed with a digital-to-analog converter (DAC) to set the appropriate analog voltage level to program the voltage range (e.g., variance range) for each analog CAM cell 55. This is done by applying a higher voltage level to the first source line SL HI To define the upper limit or higher threshold of the variance range (T high ) and by applying a lower voltage level to the second source line SL LO To define the lower limit or lower threshold (T low ) to achieve this.

[0042] In step 104, a set of random inputs is generated or simulated to create a plurality of input vectors X, each having a plurality of random elements N. Each input vector X j The number of random elements N in may be equal to the number of columns in each analog CAM row 53 of the analog CAM array 52 .

[0043] In step 106, each corresponding input vector X of the random input (generated in step 104) is j applied to each analog CAM row 53 and for the corresponding input vector X j Calculate the similarity vector. Each element of the similarity vector is the sum of each analog CAM row 53 and the corresponding input vector X j As previously mentioned in Figure 3B and Figure 4 As described in , the discharge currents flowing through the corresponding discharge lines 66 of different analog CAM rows 53 can be used as a basis for comparing and determining how similar the analog CAM rows 53 are to one another (e.g., by using a similarity metric S). The discharge current in each discharge line 66 is a collective measure of the mismatch between the target search value of the random input applied to the corresponding analog CAM cell 55 of the analog CAM row 53 and the range of stored voltage values ​​that have been encoded in the corresponding analog CAM cell 55 of the analog CAM row 53. Each of the analog CAM cells 55 of an analog CAM row 53 contributes to the discharge current in the discharge line 66 of that row. Also as previously described in Figure 3B and Figure 4 As described in , the discharge current in the discharge line 66 of each analog CAM row 53 is converted by the TIA 70 to an analog voltage output (AOUT). This analog voltage output is then sensed by the ADC 72 and converted to a digital representation. This digital representation can be used as a similarity metric S for the analog CAM row 53 and compared to similarity metrics S of other analog CAM rows 53. Thus, for an input vector X j , for each row T of the matrix T representing the analog CAM array 52 i Calculate the similarity measure S ij It can be expressed as:

[0044] S ij =SIM(T i ,X j ) (1)

[0045] In step 108, an average (also referred to as mean) similarity measure S for each simulated CAM row 53 is then calculated based on the similarity measures S of the corresponding simulated CAM rows 53 (determined in step 106). ave . Calculate the average similarity measure S on multiple input vectors X ave The average similarity measure S ave It can be expressed as:

[0046]

[0047] In step 110, the average similarity metric S of each simulated CAM row 53 is calculated. ave The average similarity metric S with each of the other analog CAM rows 53 of the analog CAM array 52 ave The distance D is used to evaluate the similarity or dissimilarity of each analog CAM row 53 to each of the other analog CAM rows 53. For example, the average similarity metric S of the first analog CAM row 53 is p The average similarity measure S with the second simulated CAM row 53 q The distance D calculated between them can be expressed as the average similarity measure S p With the average similarity measure S q The magnitude of the difference between the first analog CAM row 53 and the second analog CAM row 53 can indicate the amount of similarity between the first analog CAM row 53 and the second analog CAM row 53. During this step, the analog CAM row 53 is excluded from comparison with itself. The average similarity metric S of the first analog CAM row 53 is p The average similarity measure S with the second simulated CAM row 53 q The distance D calculated between can be expressed as:

[0048] D pq =|S p -S q | (3)

[0049] In step 112, the average similarity metric S of two similar analog CAM rows 53 of the analog CAM array 52 is calculated. ave The distance D between the two similar analog CAM rows is lower than the target value to select the two similar analog CAM rows. The two analog CAM rows 53 have an average similarity metric S aveSuch a distance D between them can be considered to have a high degree of similarity. The target value is selected to ensure that the two selected simulated CAM rows 53 have average similarity measures S that are close to each other (eg, within a desired amount). ave For example, a first analog CAM row 53 and a second analog CAM row 53 may be selected to be similar by using a selection variable in the calculation to ensure that their average similarity measure S is ave The distance D between them is below the minimum target value. The selection of two similar rows (e.g., row i and row k) of the analog CAM array 52 can be performed by calculating the argument (argmin) of the minimum value of each distance D, for example, by the expression:

[0050] i,k=argmin(D) (4)

[0051] In step 114, one of the two similar analog CAM rows 53 (selected in step 112) may be removed from the analog CAM array 52. Fig. 6A , where two similar analog CAM rows 53 (e.g., row k and row i) of the analog CAM array 52 previously selected in step 112 are shown. Fig. 6A , a conceptual depiction of the voltage range (e.g., variance range) that can be programmed into each analog CAM cell 55 of row k and row i is shown. The shaded portion of each analog CAM cell 55 of row k and row i represents its variance range (also referred to as storage range or width) having upper and lower limits. A target search value for analog input data applied to an analog CAM cell 55 of row k or row i indicates a match if the target search value matches (e.g., falls within the shaded portion) the range of stored voltage values ​​encoded in the analog CAM cell 55.

[0052] As in Fig. 6A As can be seen in FIG. 5 , row i is removed from analog CAM array 52, leaving only row k. In other embodiments, row k is removed from analog CAM array 52, leaving only row i. In this way, either of two similar analog CAM rows 53 can be removed, leaving the other remaining analog CAM row 53 operational and able to function without interruption. The selection of which row to remove can be performed randomly.

[0053] Figure 6B The steps performed in step 114 according to some other embodiments are illustrated. Figure 6B The steps performed in Fig. 6A The steps performed in step 114 differ in that instead of removing one of the two similar analog CAM rows 53 (e.g., Fig. 6A) and merging two similar analog CAM rows 53 together (as described in Figure 6B to form a new analog CAM row 53. Figure 6B , two similar analog CAM rows 53 (e.g., row k and row i) of the analog CAM array 52 previously selected in step 112 are shown. Figure 6B , a conceptual depiction of the voltage range (e.g., variance range) that can be programmed into each analog CAM cell 55 of row k and row i is shown. The shaded portion of each analog CAM cell 55 of row k and row i represents this variance range (also referred to as storage range or width) having upper and lower limits. A target search value for analog input data applied to an analog CAM cell 55 of row k or row i indicates a match if the target search value matches (e.g., falls within the shaded portion) the range of stored voltage values ​​encoded in that analog CAM cell 55.

[0054] As in Figure 6BAs can be seen in FIG. 1 , row k is merged with row i to form a new row m. Specifically, each analog CAM cell 55 of row k is merged with the corresponding analog CAM cell 55 of row i to form a new variance range of the analog CAM cell 55 of the new row m, wherein the analog CAM cell 55 of row k, the corresponding analog CAM cell 55 of row i, and the new analog CAM cell 55 of row m are in the same column of the analog CAM array 52. ​​Each new analog CAM cell 55 of row m may have a new voltage range (e.g., a new variance range) that is different from the voltage range (e.g., a variance range) of each of the corresponding analog CAM cells 55 of row k and row i (merged to form the new analog CAM cell 55). Therefore, the new analog CAM cell 55 of row m is shown with different shaded portions to represent the new variance range. For example, the first analog CAM cell 55 of row k may have a first variance range having a first upper limit U1 and a first lower limit L1. The second analog CAM cell 55 of row i may have a second variance range having a second upper limit U2 and a second lower limit L2. The first analog CAM cell 55 is merged with the second analog CAM cell 55 to form a third analog CAM cell 55 of a new row m, and the third analog CAM cell 55 has a third variance range having a third upper limit U3 and a third lower limit L3. The voltage value of the third upper limit U3 of the third analog CAM cell 55 is equal to the voltage value of the larger one between the upper limit U1 of the first analog CAM cell 55 and the upper limit U2 of the second analog CAM cell 55. The voltage value of the third lower limit L3 of the third analog CAM cell 55 is equal to the voltage value of the smaller one between the lower limit L1 of the first analog CAM cell 55 and the lower limit L2 of the second analog CAM cell 55. After the merged row m is added to the analog CAM array 52, the row k and the row i may be removed from the analog CAM array 52.

[0055] In such Fig. 6A Removal of one of two similar analog CAM rows 53 is performed as shown or as Figure 6BAfter performing the merge of two similar analog CAM rows 53, as shown in step 116, the size of the analog CAM array 52 is evaluated to check whether the desired compression factor (α) has been achieved. The compression factor (α) is expressed as a percentage (or its equivalent in decimal form) by which the size of the analog CAM array 52 is expected to be reduced. If the desired compression factor (α) has been achieved, the compression method 100 ends. If the desired compression factor (α) has not been achieved, the steps of the compression method 100 previously described in steps 104 to 116 are repeated until the desired compression factor (α) is achieved. For example, before performing the compression method 100, the analog CAM array 52 may have a first number (H) of analog CAM rows 53. The compression method 100 may then be performed to reduce the size by the desired compression factor (α) (e.g., by reducing the first number H of analog CAM rows). After performing the compression method 100 and achieving the desired compression factor (α), the size of the analog CAM array 52 may be expressed as:

[0056] (1-α)H(5)

[0057] Figure 7 2 is a block diagram of a computing system 200 according to some embodiments. The computing system 200 is used to operate a machine learning model, such as a decision tree model. The computing system 200 can be implemented in an electronic device. Examples of electronic devices include servers, desktop computers, laptop computers, mobile devices, gaming systems, etc. The computing system 200 may include a processor 202, one or more interfaces 204, a memory 206, and a content addressable memory device 50 (previously described in Figures 1 to 4 ). The hardware components may be interconnected via a plurality of buses and / or network connections. In one example, the processor 202, one or more interfaces 204, the memory 206, and the content addressable memory device 50 may be communicatively coupled via the bus 208.

[0058] The processor 202 retrieves the executable code from the memory 206 and executes the executable code. The executable code, when executed by the processor 202, may cause the processor 202 to implement any of the functions described herein. The processor 202 may be a microprocessor, an application specific integrated circuit, a microcontroller, etc. The processor 202 may interact with and control the content addressable memory device 50.

[0059] The one or more interfaces 204 enable the processor 202 to interface with various other hardware elements external and internal to the computing system 200. For example, the one or more interfaces 204 may include one or more interfaces to input / output devices (e.g., a display device, a mouse, a keyboard, etc.). Additionally or alternatively, the one or more interfaces 204 may include one or more interfaces to external storage devices or to a plurality of network devices (e.g., servers, switches and routers, client devices, other types of computing devices, and combinations thereof).

[0060] Memory 206 may include various types of memory modules, including volatile memory and non-volatile memory. For example, memory 206 may include random access memory (RAM), read-only memory (ROM), hard disk drive (HDD), etc. Memory 206 may include a non-transitory computer-readable medium storing instructions executed by processor 202. One or more modules within computing system 200 may be partially or completely embodied as software and / or hardware for performing any of the functions described herein. Different types of memory may be used for different data storage needs. For example, in some examples, processor 202 may boot from ROM, maintain non-volatile storage in HDD, and execute program code stored in RAM.

[0061] The compression method 100 may be implemented as software stored in the memory 206. Some steps of the compression method 100 may be performed in software by the processor 202. Other steps of the compression method 100 may be performed in hardware by the content addressable memory device 50 (under the control of the processor 202). In some implementations, steps 102, 106, and 114 of the compression method 100 are performed in hardware, while steps 104, 108, 110, 112, and 116 are performed in software. Other suitable combinations of software / hardware processing may be utilized.

[0062] Advantages may be achieved as a result of performing a compression method 100 that includes generating a set of random inputs to create input vectors X each having a plurality of random elements N, and applying each random input vector X to each analog CAM row 53 of an analog CAM array 52 to calculate a result vector showing a similarity metric S of each corresponding analog CAM row 53 to the random input vector X. The similarity metric S of each analog CAM row 53 is calculated by sensing a discharge current flowing through a corresponding discharge line 66 of the corresponding analog CAM row 53 and converting each measured discharge current into an analog voltage output using a TIA 70. The analog voltage output is then sensed by an ADC 72 and converted into a digital representation. The digital representation is then used as the similarity metric S of the corresponding analog CAM row 53. The average similarity metric S of each analog CAM row 53 is then calculated over the input vector X.ave , and calculate the average similarity measure S for each simulated CAM row 53 ave The average similarity metric S with each of the other analog CAM rows 53 of the analog CAM array 52 ave The distance D between the first analog CAM row 53 and the second analog CAM row 53 can be expressed as the average similarity metric S of the first analog CAM row 53. ave The average similarity measure S with the second simulated CAM row 53 ave Then, based on the average similarity metric S of two similar analog CAM rows 53 of the analog CAM array 52, ave The two similar analog CAM rows are selected when the distance D between them is lower than the minimum target value. After selecting the two similar analog CAM rows 53, one of the two similar analog CAM rows 53 can be eliminated from the analog CAM array 52, such as by removing it from the analog CAM array 52 or by merging two similar analog CAM rows 53 to form a new analog CAM row 53, thereby reducing the total number of analog CAM rows 53 of the analog CAM array 52 (e.g., reducing the size of the analog CAM array 52). The steps of the compression method 100 described above can be repeated until the size of the analog CAM array 52 achieves the desired reduction (e.g., according to the compression factor (α)). These advantages include allowing the size of the analog CAM array 52 to be reduced by up to 15 percent without a significant loss of model accuracy (e.g., the accuracy of the machine learning model stored in the analog CAM array 52). This allows the number of analog CAM rows 53 that need to be programmed during manufacturing to be reduced, thereby saving time. In addition, due to the smaller size of the analog CAM array 52, a reduction in occupied area or memory size can be achieved. This results in lower power consumption because a smaller memory array requires fewer active components and consumes less energy during search and write operations. Further, use of the compression method 100 allows larger machine learning models to be converted to analog representations using the analog CAM array 52 because the machine learning models are not limited to the size that the physical array (e.g., the analog CAM array 52) can encode.

[0063] Figure 8 A flow chart for performing a compression method 300 on an analog CAM array according to some embodiments is illustrated. The compression method 300 may be performed in addition to or instead of the compression method 100 (previously described).

[0064] In step 302, a first range of voltages is programmed into a first analog CAM cell in a first row of an analog CAM array.

[0065] In step 304, a second range of voltages is programmed into a second analog CAM cell in a second row of the analog CAM array.

[0066] In step 306, an input vector including a set of random inputs is applied to the first analog CAM cell. Each of the first analog CAM cells is configured to contribute to a first discharge current on a first discharge line coupled to the first analog CAM cell based on whether the corresponding random input applied to the corresponding first analog CAM cell is within a range of a first voltage of the corresponding first analog CAM cell. The set of random inputs may be simulated, wherein the number of random inputs in the set of random inputs is equal to the number of columns of the analog CAM array. The input vector may be one of a plurality of input vectors applied to the first analog CAM cell and applied to the second analog CAM cell. When the input vector is one of a plurality of input vectors, a first average similarity metric for a first row of the analog CAM array may be determined by calculating an average of the first similarity metric over the input vectors.

[0067] In step 308, the input vector is applied to the second analog CAM cells. Each of the second analog CAM cells is configured to contribute to a second discharge current on a second discharge line coupled to the second analog CAM cell based on whether the corresponding random input applied to the corresponding second analog CAM cell is within a range of a second voltage of the corresponding second analog CAM cell. When the input vector is one of a plurality of input vectors, a second average similarity metric for the second row of the analog CAM array may be determined by calculating an average of the second similarity metrics over the input vectors.

[0068] In step 310, the first discharge current is converted into a first digital representation representing a first similarity measure between a first row of the analog CAM array and the set of random inputs.

[0069] In step 312, the second discharge current is converted into a second digital representation representing a second similarity measure between a second row of the analog CAM array and the set of random inputs.

[0070] In step 314, a first distance between the first average similarity measure and the second average similarity measure is calculated. The first distance is equal to the magnitude of the difference between the first average similarity measure and the second average similarity measure.

[0071] In step 316, the first row of the analog CAM array or the second row of the analog CAM array is eliminated. The first row of the analog CAM array or the second row of the analog CAM array may be removed based on whether the first distance is below a minimum target value. Alternatively, the first row of the analog CAM array and the second row of the analog CAM array may be merged into a single row of the analog CAM array based on whether the first distance is below a minimum target value.

[0072] As used herein, circuits can be implemented using any form of hardware, software or a combination thereof. For example, one or more processors, controllers, ASIC, PLA, PAL, CPLD, FPGA, logic components, software routines or other mechanisms can be implemented to form circuits. In an embodiment, various circuits described herein can be implemented as discrete circuits, or described functions and features can be shared partially or entirely between one or more circuits. Although various features or functional elements can be described or advocated individually as separate circuits, these features and functions can also be shared among one or more common circuits, and this description should not require or imply that separate circuits are needed to implement such features or functions. In the case of using software to implement circuits in whole or in part, this software can be implemented to operate together with a computing system or a processing system that can perform the functions described about the software.

[0073] As used herein, the term "or" may be interpreted in an inclusive or exclusive sense. Furthermore, descriptions of resources, operations, or structures in the singular should not be construed to exclude the plural. Unless expressly stated otherwise, or understood otherwise within the context as used, conditional language (such as, among others, "may," "might," "could," or "might") is generally intended to convey that certain embodiments include and other embodiments do not include certain features, elements, and / or steps.

[0074] Unless expressly stated otherwise, the terms and phrases used in this document and their variations should be interpreted as open-ended and not restrictive. Adjectives such as "traditional," "customary," "normal," "standard," "known," and terms of similar meaning should not be interpreted as limiting the items described to items available for a given time period or before a given time, but should be understood to cover traditional, customary, normal, or standard technologies that may be available or known now or at any time in the future. In some cases, the presence of broad words and phrases (such as "one or more," "at least," "but not limited to," or other similar phrases) should not be understood to mean that narrower cases are intended or required where such broad phrases may not be present.

[0075] The foregoing summarizes the features of multiple examples so that those skilled in the art can better understand the various aspects of the present disclosure. Various modifications and combinations of the illustrative examples and other examples will be apparent to those skilled in the art upon reference to the specification. Therefore, the appended claims are intended to cover any such modifications.

Claims

1. A content addressable memory (CAM) device, comprising: An analog CAM array, a first row of the analog CAM array comprising: first analog CAM cells, each of the first analog CAM cells storing data associated with a respective first stored analog value range having a first lower limit and a first upper limit; and a first match line horizontally aligned with and coupled to the first analog CAM cell; and a first discharge line horizontally aligned with and coupled to the first analog CAM cells, wherein each of the first analog CAM cells is configured to contribute to a first discharge current on the first discharge line based on whether a corresponding search value is within the corresponding first stored analog value range; a first transimpedance amplifier configured to be coupled to the first discharge line, the first transimpedance amplifier configured to convert the first discharge current into a first analog output; and A first analog-to-digital converter is coupled to the first transimpedance amplifier, and the first analog-to-digital converter is configured to convert the first analog output into a first digital output.

2. The CAM device according to claim 1, wherein: The second row of the analog CAM array includes: a second analog CAM unit; and A second discharge line is horizontally aligned with and coupled to the second analog CAM unit.

3. The CAM device as claimed in claim 2, wherein: The first discharge line is different from the second discharge line.

4. The CAM device as claimed in claim 2, wherein: Each of the second analog CAM cells stores data associated with a corresponding second stored analog value range having a second lower limit and a second upper limit, and wherein each of the second analog CAM cells is configured to contribute to a second discharge current on the second discharge line based on whether a corresponding search value is within the corresponding second stored analog value range.

5. The CAM device as claimed in claim 4, wherein: The second row of the analog CAM array further comprises: a second transimpedance amplifier configured to be coupled to the second discharge line, the second transimpedance amplifier configured to convert the second discharge current into a second analog output; and A second analog-to-digital converter is coupled to the second transimpedance amplifier, and the second analog-to-digital converter is configured to convert the second analog output into a second digital output.

6. The CAM device as claimed in claim 1, wherein: Each of the first analog CAM cells comprises: a first pull-down transistor coupled between the first match line and the first discharge line; and A second pull-down transistor is coupled between the first matching line and the first discharging line.

7. The CAM device of claim 1, further comprising: A mode selection circuit is coupled to the analog CAM array.

8. A content addressable memory (CAM) device comprising: An analog CAM array, a first row of the analog CAM array comprising: A first analog CAM unit, wherein the first analog CAM unit comprises: a first memristor storing a first analog value; and a second memristor storing a second analog value; a first match line coupled to the first analog CAM cell; and a first discharge line coupled to the first analog CAM cell, wherein the first analog CAM cell is configured to contribute a first discharge current on the first discharge line based on whether a search value is between the first analog value and the second analog value; and A sensing circuit, the sensing circuit comprising: a first transimpedance amplifier configured to be coupled to the first discharge line, the first transimpedance amplifier configured to convert the first discharge current into a first analog output; and A first analog-to-digital converter is coupled to the first transimpedance amplifier, wherein the first analog-to-digital converter is configured to generate a first digital representation of the first analog output.

9. The CAM device of claim 8, wherein: The first row of the analog CAM array further comprises: A second analog CAM unit, wherein the second analog CAM unit comprises: a third memristor storing a third analog value; and a fourth memristor storing a fourth analog value; The first match line is coupled to the second analog CAM cell, the first discharge line is coupled to the second analog CAM cell, and the second analog CAM cell is configured to contribute to the first discharge current on the first discharge line based on whether the search value is between the third analog value and the fourth analog value.

10. The CAM device of claim 8, wherein: The first analog CAM unit further comprises: a first pull-down transistor coupled between the first match line and the first discharge line; and A second pull-down transistor is coupled between the first matching line and the first discharging line.

11. The CAM device according to claim 8, wherein: The second row of the analog CAM array includes: A third analog CAM unit, the third analog CAM unit comprising: a fifth memristor storing a fifth analog value; and a sixth memristor storing a sixth analog value; a second match line coupled to the third analog CAM cell; and A second discharge line is coupled to the third analog CAM cell, wherein the third analog CAM cell is configured to contribute to a second discharge current on the second discharge line based on whether a search value is between the fifth analog value and the sixth analog value.

12. The CAM device of claim 11 , further comprising a first data line vertically aligned and coupled to the first analog CAM cell and the third analog CAM cell, the first data line being configured to receive an applied voltage associated with input data for searching the first analog CAM cell and the third analog CAM cell.

13. The CAM device of claim 11, wherein: The sensing circuit further comprises: a second transimpedance amplifier configured to be coupled to the second discharge line, the second transimpedance amplifier configured to convert the second discharge current into a second analog output; and A second analog-to-digital converter is coupled to the second transimpedance amplifier, wherein the second analog-to-digital converter is configured to generate a second digital representation of the second analog output.

14. The CAM device according to claim 8, wherein: The first transimpedance amplifier is also configured to be coupled to the first matching line.

15. A content addressable memory (CAM) compression method, comprising: programming a first voltage range into a first analog CAM cell in a first row of an analog CAM array; programming a second range of voltages into a second analog CAM cell in a second row of the analog CAM array; applying an input vector comprising a set of random inputs to the first analog CAM cells, wherein each of the first analog CAM cells is configured to contribute to a first discharge current on a first discharge line coupled to the first analog CAM cell based on whether a corresponding random input applied to the corresponding first analog CAM cell is within a range of the first voltage of the corresponding first analog CAM cell; applying the input vector to the second analog CAM cells, wherein each of the second analog CAM cells is configured to contribute to a second discharge current on a second discharge line coupled to the second analog CAM cell based on whether a corresponding random input applied to the corresponding second analog CAM cell is within a range of the second voltage of the corresponding second analog CAM cell; converting the first discharge current into a first digital representation representing a first similarity measure between the first row of the analog CAM array and the set of random inputs; and The second discharge current is converted into a second digital representation representing a second similarity measure between the second row of the analog CAM array and the set of random inputs.

16. The CAM compression method according to claim 15, wherein: The input vector is one of a plurality of input vectors applied to the first analog CAM unit and applied to the second analog CAM unit, the CAM compression method comprising: determining a first average similarity metric for the first row of the analog CAM array by averaging the first similarity metric over the input vectors; and A second average similarity metric for the second row of the analog CAM array is determined by averaging the second similarity metric over the input vectors.

17. The CAM compression method of claim 16, further comprising: A first distance between the first average similarity measure and the second average similarity measure is calculated, wherein the first distance is equal to a magnitude of a difference between the first average similarity measure and the second average similarity measure.

18. The CAM compression method of claim 17, further comprising: The first row of the analog CAM array or the second row of the analog CAM array is removed based on whether the first distance is below a minimum target value.

19. The CAM compression method of claim 17, further comprising: The first row of the analog CAM array and the second row of the analog CAM array are merged into a single row of the analog CAM array based on whether the first distance is below a minimum target value.

20. The CAM compression method of claim 15, further comprising: The set of random inputs is simulated, the number of random inputs in the set of random inputs being equal to the number of columns of the analog CAM array.

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