Recovery of failed NAND by AI data modulation

Abstract

The invention provides a system, a device and a method for recovering a fault NAND through AI data modulation. The method comprises the following steps: obtaining a plurality of data symbols; providing the plurality of data symbols to a neural network; obtaining a plurality of threshold voltage targets based on the output of the neural network; and programming the plurality of data symbols to a plurality of memory cells included in the memory device based on the plurality of threshold voltage targets.

Description

Technical Field

[0001] Apparatus and methods consistent with embodiments relate to processes for programming memory cells, and more particularly to setting threshold voltage targets for memory cells using artificial intelligence (AI). Background Art

[0002] The continued scaling of Flash memory technology to smaller process nodes, combined with the increased information capacity per Flash memory cell (e.g., more bits stored per cell), comes at the expense of an increased number of errors. Even with advanced error correction codes (ECC), Flash memory devices are still subject to multiple error sources, which limits their use in terms of both program-erase (PE) cycles and data retention time.

[0003] The endurance of a flash memory cell can be measured by the number of PE cycles that the cell can go through before reaching a point where the ECC decoder cannot reconstruct the true programmed bits. This point can be referred to as the end-of-life (EOL) operating point of the flash memory cell. One of the main sources of errors that highly affects the EOL operating point of a chip is inter-cell interference (ICI). ICI is the phenomenon where the charge stored at a memory cell is affected by the charge stored at neighboring cells. This charge dependency changes the threshold voltage v of the affected memory cell. th The threshold voltage target t.

[0004] Some modulation methods for assigning a threshold voltage target t to each memory cell are based only on the data symbol or data symbols stored in the cell and therefore do not consider data symbols stored in neighboring cells. Therefore, these modulation methods may not fully address ICI. Summary of the invention

[0005] Systems, devices, and methods are provided for setting a threshold voltage target for programming a memory cell using artificial intelligence (AI).

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.

[0007] According to one aspect of the present disclosure, a storage system includes: a storage device including a plurality of memory cells; and at least one processor configured to: obtain a plurality of data symbols; provide the plurality of data symbols to a neural network; obtain a plurality of threshold voltage targets based on an output of the neural network; and program the plurality of data symbols to the plurality of memory cells based on the plurality of threshold voltage targets.

[0008] According to one aspect of the present disclosure, an apparatus for programming a plurality of memory cells includes at least one processor configured to: obtain a plurality of data symbols; obtain a plurality of threshold voltage targets by providing the plurality of data symbols to a neural network, wherein each of the plurality of threshold voltage targets corresponds to a memory cell among a plurality of memory cells and is determined based on the data symbol corresponding to the memory cell and at least one adjacent data symbol corresponding to at least one adjacent memory cell; and program the plurality of data symbols to the plurality of memory cells based on the plurality of threshold voltage targets.

[0009] According to one aspect of the present disclosure, a method of controlling a storage system includes: obtaining a plurality of data symbols; providing the plurality of data symbols to a neural network; obtaining a plurality of threshold voltage targets based on an output of the neural network; and programming the plurality of data symbols to a plurality of memory cells included in a storage device based on the plurality of threshold voltage targets.

[0010] According to one aspect of the present disclosure, a method for programming multiple memory cells includes: obtaining multiple data symbols; obtaining multiple threshold voltage targets by providing the multiple data symbols to a neural network, wherein each threshold voltage target in the multiple threshold voltage targets corresponds to a memory cell in the multiple memory cells and is determined based on the data symbol corresponding to the memory cell and at least one adjacent data symbol corresponding to at least one adjacent memory cell; and programming the multiple data symbols to the multiple memory cells based on the multiple threshold voltage targets. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a block diagram of a computer system according to an embodiment;

[0013] Figure 2 is a block diagram of a host storage system according to an embodiment;

[0014] Figure 3 is a block diagram of a memory system according to an embodiment;

[0015] Figure 4 is a block diagram of a memory device according to an embodiment.

[0016] Figure 5 is a block diagram of a UFS system according to an embodiment.

[0017] FIG. 6A to FIG. 6C is a diagram of a form factor of a UFS card according to an embodiment.

[0018] Figure 7 is a block diagram of a memory system according to an embodiment.

[0019] Figure 8 is a diagram of a 3D V-NAND structure suitable for a UFS device according to an embodiment.

[0020] Fig. 9 is a diagram showing a memory device according to an embodiment.

[0021] Fig.10 An example of an algorithm that may be used to program a word line according to an embodiment is shown.

[0022] Fig.11 An example of a retained ICI phenomenon measured on a 3D-NAND chip programmed with QLC data according to an embodiment is shown.

[0023] Fig.12 An example of a communication system that may be used to perform end-to-end training according to an embodiment is shown.

[0024] Fig.13 is a block diagram of a training architecture for training a modulator according to an embodiment.

[0025] Fig.14 is a block diagram of a training architecture for training a channel generator according to an embodiment.

[0026] Fig.15 An example of a training algorithm that may be used to perform the training step is shown.

[0027] Fig.16 is a graph illustrating the performance of a quantization process according to an embodiment.

[0028] Fig.17 An example of an algorithm that may be used to program a word line according to an embodiment is shown.

[0029] Figures 18A-18C , Figure 19A-Figure 19C and Figure 20-21 is a diagram showing results obtained from experiments performed using an example of a channel generator and a modulator according to an embodiment.

[0030] Fig. 22 is a flow chart of a process for controlling a storage system according to an embodiment.

[0031] Fig.23 is a block diagram of a data center according to an embodiment. DETAILED DESCRIPTION

[0032] Embodiments may be directed to a method for programming a memory cell by optimizing a threshold voltage v of a memory cell relative to data to be stored at adjacent memory cells.th The threshold voltage target t is used to mitigate inter-cell interference (ICI). Different memory cells are programmed to different threshold voltages v by conditioning on their neighbors. th Objective, we preemptively cancel inter-cell interference. Based on concepts from the field of communication research, embodiments can be implemented by performing one or more components used in a flash memory system (e.g., Figure 4 and Figure 6A-6C End-to-end training of one or more elements included in the discussed memory device 300) is performed to optimize the modulation of the threshold voltage target t.

[0033] According to an embodiment, an unsupervised learning method can be used to jointly train a modulator and a demodulator using a training architecture similar to the architecture used to train the transmitter and receiver of a communication system as an autoencoder. The modulator can be trained using a reconstruction loss between the input of the modulator and the output of the demodulator. In an embodiment, the modulator can correspond to the following reference Fig.13 The modulator 1301 discussed above can be used to convert information bits corresponding to data symbols into threshold voltage targets t for programming the data symbols into memory cells.

[0034] Joint optimization of the modulator and demodulator using back-propagation may involve computing the channel gradient with respect to the transmitted signal. Because flash channels may be non-differentiable, techniques for training the transmitter and receiver of a communication system as autoencoders cannot be naively implemented in the flash context. To overcome this problem, embodiments may include training a channel model based on a conditional generative adversarial network (cGAN), such as the following reference Fig.13 The channel generator 1303 discussed. Generative adversarial networks (GANs) are used to generate v th According to an embodiment, given the threshold voltage targets t of a memory cell and neighboring memory cells, the trained channel model can learn the voltage threshold v of the memory cell. th Using data about neighboring memory cells, the channel model can capture the ICI statistics, allowing the modulator to counteract the ICI phenomenon.

[0035] In order to reduce the additional programming delay caused by the neural network modulator, a novel shared pulse programming scheme can be used. The shared pulse programming scheme (which can be a modification of the incremental step pulse programming (ISPP) scheme) can achieve accurate programming without increasing the amount of programming pulses and with only a relatively small increase in programming time.

[0036] When optimized for the EOL operating point, embodiments can outperform other modulation methods by up to 30% in raw bit error rate (RBER), which can extend the tested EOL operating point of the chip by an additional 600 PE cycles. In embodiments, this gain can be achieved without increasing read latency.

[0037] Figure 1 is a diagram of a system 1000 in which an embodiment may be applied. Figure 1 The system 1000 may be, for example, a mobile system such as a portable communication terminal (eg, a mobile phone), a smartphone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IoT) device. However, Figure 1 The system 1000 is not necessarily limited to a mobile system and may be a PC, a laptop computer, a server, a media player, or an automotive device (eg, a navigation device).

[0038] refer to Figure 1 , the system 1000 may include a main processor 1100, a memory (e.g., 1200a and 1200b), and a storage device (e.g., 1300a and 1300b). In addition, the system 1000 may include at least one of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0039] The main processor 1100 may control all operations of the system 1000, and more specifically, may control operations of other components included in the system 1000. The main processor 1100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

[0040] The main processor 1100 may include at least one central processing unit (CPU) core 1110, and also include a controller 1120 configured to control memories 1200a and 1200b and / or storage devices 1300a and 1300b. In some embodiments, the main processor 1100 may further include an accelerator 1130, which is a dedicated circuit for high-speed data operations such as artificial intelligence (AI) data operations. The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and is implemented as a chip physically separated from other components of the main processor 1100.

[0041] Memories 1200a and 1200b may be used as main memory devices of system 1000. Although memories 1200a and 1200b may include volatile memories such as static random access memory (SRAM) and / or dynamic random access memory (DRAM), memories 1200a and 1200b may include nonvolatile memories such as flash memory, phase change RAM (PRAM) and / or resistive RAM (RRAM), respectively. Memories 1200a and 1200b may be implemented in the same package as main processor 1100.

[0042] The storage devices 1300a and 1300b may be used as non-volatile storage devices, which are configured to store data regardless of whether they are powered and have a larger storage capacity than the memories 1200a and 1200b. The storage devices 1300a and 1300b may include storage controllers (STRG CTRL) 1310a and 1310b and non-volatile memories (NVM) 1320a and 1320b, respectively, which are configured to store data via the control of the storage controllers 1310a and 1310b. Although the NVMs 1320a and 1320b may include V-NAND flash memories having a two-dimensional (2D) or three-dimensional (3D) structure, the embodiment is not limited thereto, and the NVMs 1320a and 1320b may include other types of NVMs, such as PRAM and / or RRAM.

[0043] The storage devices 1300a and 1300b may be physically separated from the main processor 1100 and included in the system 1000, or may be implemented in the same package as the main processor 1100. In addition, the storage devices 1300a and 1300b may have a type of SSD or memory card, and may be removably combined with other components of the system 1000 through an interface such as a connection interface 1480 to be described later. The storage devices 1300a and 1300b may be devices to which a standard protocol such as Universal Flash Storage (UFS), Embedded Multimedia Card (eMMC), or Non-Volatile Express Memory (NVMe) is applied, but are not limited thereto.

[0044] The image capture device 1410 may capture still images or moving images. The image capture device 1410 may include a camera, a camcorder, and / or a webcam.

[0045] The user input device 1420 may receive various types of data input by a user of the system 1000 and include a touch pad, a keypad, a keyboard, a mouse, and / or a microphone.

[0046] The sensor 1430 may detect various types of physical quantities that may be obtained from the outside of the system 1000 and convert the detected physical quantities into electrical signals. The sensor 1430 may include a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyro sensor.

[0047] The communication device 1440 may transmit and receive signals between other devices outside the system 1000 according to various communication protocols. The communication device 1440 may include an antenna, a transceiver, and / or a modem.

[0048] Display 1450 and speaker 1460 may be used as output devices configured to output visual information and auditory information, respectively, to a user of system 1000 .

[0049] The power supply device 1470 may appropriately convert power supplied from a battery embedded in the system 1000 and / or an external power source, and supply the converted power to each of the components of the system 1000 .

[0050] The connection interface 1480 may provide a connection between the system 1000 and an external device that is connected to the system 1000 and is capable of transmitting and receiving data to and from the system 1000. The connection interface 1480 may be implemented by using various interface schemes such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI express (PCIe), NVMe, IEEE1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, MultiMediaCard (MMC) interface, eMMC interface, UFS interface, Embedded UFS (eUFS) interface, and Compact Flash (CF) card interface.

[0051] Figure 2 is a block diagram of a host storage system 10 according to an example embodiment.

[0052] The host storage system 10 may include a host 100 and a storage device 200. In addition, the storage device 200 may include a storage controller 210 and an NVM 220. According to an example embodiment, the host 100 may include a host controller 110 and a host memory 120. The host memory 120 may be used as a buffer memory configured to temporarily store data to be transmitted to or received from the storage device 200.

[0053] The storage device 200 may include a storage medium configured to store data in response to a request from the host 100. As an example, the storage device 200 may include at least one of an SSD, an embedded memory, and a removable external memory. When the storage device 200 is an SSD, the storage device 200 may be a device that complies with the NVMe standard. When the storage device 200 is an embedded memory or an external memory, the storage device 200 may be a device that complies with the UFS standard or the eMMC standard. Each of the host 100 and the storage device 200 may generate a packet and send the packet according to the adopted standard protocol.

[0054] When the NVM 220 of the storage device 200 includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device 200 may include various other types of NVM. For example, the storage device 200 may include a magnetic RAM (MRAM), a spin transfer torque MRAM, a conductive bridge RAM (CBRAM), a ferroelectric RAM (FRAM), a PRAM, an RRAM, and various other types of memory.

[0055] According to an embodiment, the host controller 110 and the host memory 120 may be implemented as separate semiconductor chips. Alternatively, in some embodiments, the host controller 110 and the host memory 120 may be integrated in the same semiconductor chip. As an example, the host controller 110 may be any one of a plurality of modules included in an application processor (AP). The AP may be implemented as a system on chip (SoC). In addition, the host memory 120 may be an embedded memory included in the AP or a memory module outside the AP.

[0056] The host controller 110 may manage an operation of storing data (eg, write data) of the buffer area of ​​the host memory 120 in the NVM 220 or an operation of storing data (eg, read data) of the NVM 220 in the buffer area.

[0057] The storage controller 210 may include a host interface 211, a memory interface 212, and a CPU 213. In addition, the storage controller 210 may further include a flash translation layer (FTL), a package manager 215, a buffer memory 216, an error correction code (ECC) engine 217, and an advanced encryption standard (AES) engine 218. The storage controller 210 may further include a working memory in which the FTL 214 is loaded. The CPU 213 may execute the FTL 214 to control data write and read operations on the NVM 220.

[0058] The host interface 211 may transmit and receive packets to and from the host 100. The packet transmitted from the host 100 to the host interface 211 may include a command or data to be written to the NVM 220. The packet transmitted from the host interface 211 to the host 100 may include a response to a command or data read from the NVM 220. The memory interface 212 may transmit data to be written to the NVM 220 to the NVM 220 or receive data read from the NVM 220. The memory interface 212 may be configured to comply with a standard protocol such as Toggle or Open NAND Flash Interface (ONFI).

[0059] The FTL 214 may perform various functions, such as an address mapping operation, a wear leveling operation, and a garbage collection operation. The address mapping operation may be an operation of converting a logical address received from the host 100 into a physical address for actually storing data in the NVM 220. The wear leveling operation may be a technique for preventing excessive degradation of a specific block by allowing the blocks of the NVM 220 to be used evenly. As an example, the wear leveling operation may be implemented using a firmware technique for balancing the erase counts of physical blocks. The garbage collection operation may be a technique for ensuring usable capacity in the NVM 220 by erasing an existing block after copying valid data of the existing block to a new block.

[0060] The packet manager 215 may generate a packet according to a protocol agreed with an interface of the host 100, or parse various types of information from a packet received from the host 100. In addition, the buffer memory 216 may temporarily store data to be written to or read from the NVM 220. Although the buffer memory 216 may be a component included in the storage controller 210, the buffer memory 216 may be outside the storage controller 210.

[0061] The ECC engine 217 may perform error detection and correction operations on read data read from the NVM 220. More specifically, the ECC engine 217 may generate parity bits for write data to be written to the NVM 220, and the generated parity bits may be stored together with the write data in the NVM 220. During reading of data from the NVM 220, the ECC engine 217 may correct errors in the read data by using the read data and the parity bits read from the NVM 220, and output the error-corrected read data.

[0062] The AES engine 218 may perform at least one of an encryption operation and a decryption operation on data input to the memory controller 210 by using a symmetric key algorithm.

[0063] Figure 3 is a block diagram of a memory system 15 according to an embodiment. Figure 3 , the memory system 15 may include a memory device 17 and a memory controller 16. The memory system 15 may support a plurality of channels CH1 to CHm, and the memory device 17 may be connected to the memory controller 16 through the plurality of channels CH1 to CHm. For example, the memory system 15 may be implemented as a storage device such as an SSD.

[0064] The memory device 17 may include a plurality of NVM devices NVM11 to NVMmn. Each of the NVM devices NVM11 to NVMmn may be connected to one of the plurality of channels CH1 to CHm through a path corresponding thereto. For example, the NVM devices NVM11 to NVM1n may be connected to the first channel CH1 through paths W11 to W1n, and the NVM devices NVM21 to NVM2n may be connected to the second channel CH2 through paths W21 to W2n. In example embodiments, each of the NVM devices NVM11 to NVM1n may be implemented as an arbitrary memory unit that may be operated according to a separate command from the memory controller 16. For example, each of the NVM devices NVM11 to NVM1n may be implemented as a chip or a die, but embodiments of the present disclosure are not limited thereto.

[0065] The memory controller 16 may send and receive signals to and from the memory device 17 through the plurality of channels CH1 to CHm. For example, the memory controller 16 may send commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the memory device 17 through the channels CH1 to CHm, or receive data DATAa to DATAm from the memory device 17.

[0066] The memory controller 16 may select one of the NVM devices NVM11 to NVMmn connected to a corresponding channel of the channels CH1 to CHm by using each of the channels CH1 to CHm, and transmit and receive signals to and from the selected NVM device. For example, the memory controller 16 may select the NVM device NVM11 from the NVM devices NVM11 to NVM1n connected to the first channel CH1. The memory controller 16 may transmit a command CMDa, an address ADDRa, and data DATAa to the selected NVM device NVM11 through the first channel CH1, or receive data DATAa from the selected NVM device NVM11.

[0067] The memory controller 16 may send and receive signals to and from the memory device 17 in parallel through different channels. For example, the memory controller 16 may send a command CMDa to the memory device 17 through the first channel CH1 while sending a command CMDb to the memory device 17 through the second channel CH2. For example, the memory controller 16 may receive data DATAa from the memory device 17 through the first channel CH1 while receiving data DATAb from the memory device 17 through the second channel CH2.

[0068] The memory controller 16 may control all operations of the memory device 17. The memory controller 16 may send signals to the channels CH1 to CHm and control each of the NVM devices NVM11 to NVMmn connected to the channels CH1 to CHm. For example, the memory controller 16 may send a command CMDa and an address ADDRa to the first channel CH1 and control one selected from the NVM devices NVM11 to NVM1n.

[0069] Each of the NVM devices NVM11 to NVMmn may operate via the control of the memory controller 16. For example, the NVM device NVM11 may program data DATAa based on a command CMDa, an address ADDRa, and data DATAa provided to the first channel CH1. For example, the NVM device NVM21 may read data DATAb based on a command CMDb and an address ADDb provided to the second channel CH2, and transmit the read data DATAb to the memory controller 16.

[0070] although Figure 3 An example is shown in which the memory device 17 communicates with the memory controller 16 through m channels and includes n NVM devices corresponding to each channel, but the number of channels and the number of NVM devices connected to one channel may be changed.

[0071] Figure 4 is a block diagram of a memory device 300 according to an example embodiment. Figure 4 , the memory device 300 may include a control logic circuit 320, a memory cell array 330, a page buffer 340, a voltage generator 350, and a row decoder 360. The memory device 300 may further include a memory interface circuit 310 shown in FIG6. In addition, the memory device 300 may further include a column logic, a pre-decoder, a temperature sensor, a command decoder, and / or an address decoder.

[0072] The control logic circuit 320 may control all various operations of the memory device 300. The control logic circuit 320 may output various control signals in response to the command CMD and / or the address ADDR from the memory interface circuit 310. For example, the control logic circuit 320 may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

[0073] The memory cell array 330 may include a plurality of memory blocks BLK1 to BLKz (where z is a positive integer), and each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. The memory cell array 330 may be connected to the page buffer 340 through the bit lines BL, and connected to the row decoder 360 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL.

[0074] In an example embodiment, the memory cell array 330 may include a 3D memory cell array including a plurality of NAND strings. Each of the NAND strings may include a plurality of memory cells, each of which is connected to a word line vertically stacked on a substrate. U.S. Patent Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and U.S. Patent Publication No. 2011 / 0233648 are incorporated herein by reference. In an example embodiment, the memory cell array 330 may include a 2D memory cell array including a plurality of NAND strings arranged in a row direction and a column direction.

[0075] The page buffer 340 may include a plurality of page buffers PB1 to PBn (where n is an integer greater than or equal to 3), which may be connected to the memory cells respectively through a plurality of bit lines BL. The page buffer 340 may select at least one of the plurality of bit lines BL in response to the column address Y-ADDR. Depending on the operation mode, the page buffer 340 may operate as a write driver or a sense amplifier. For example, during a programming operation, the page buffer 340 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, the page buffer 340 may sense the current or voltage of the selected bit line BL and sense the data stored in the memory cell.

[0076] The voltage generator 350 may generate various voltages for program, read, and erase operations based on the voltage control signal CTRL_vol. For example, the voltage generator 350 may generate a program voltage, a read voltage, a program verification voltage, and an erase voltage as the word line voltage VWL.

[0077] The row decoder 360 may select one of the plurality of word lines WL and select one of the plurality of string selection lines SSL in response to the row address X-ADDR. For example, the row decoder 360 may apply a program voltage and a program verification voltage to the selected word line WL during a program operation, and apply a read voltage to the selected word line WL during a read operation.

[0078] Figure 5 2 is a diagram of a UFS system 2000 according to an embodiment. The UFS system 2000 may be a system conforming to the UFS standard announced by the Joint Electron Device Engineering Council (JEDEC), and includes a UFS host 2100, a UFS device 2200, and a UFS interface 2300. Figure 5 To the extent that the description conflicts, Figure 1 The above description of system 1000 may also be applied to Figure 5 UFS system 2000.

[0079] refer to Figure 5 , the UFS host 2100 may be connected to the UFS device 2200 through the UFS interface 2300. Figure 1 When the main processor 1100 is an AP, the UFS host 2100 may be implemented as a part of the AP. The UFS host controller 2110 and the host memory 2140 may correspond to Figure 1 The UFS device 2200 may correspond to the controller 1120 of the main processor 1100 and the memories 1200a and 1200b. Figure 1 The storage devices 1300a and 1300b, and the UFS device controller 2210 and the NVM 2220 may correspond to Figure 1 Storage controllers 1310a and 1310b and NVMs 1320a and 1320b.

[0080] The UFS host 2100 may include a UFS host controller 2110, an application 2120, a UFS driver 2130, a host memory 2140, and a UFS interconnect (UIC) layer 2150. The UFS device 2200 may include a UFS device controller 2210, an NVM 2220, a storage interface 2230, a device memory 2240, a UIC layer 2250, and a regulator 2260. The NVM 2220 may include a plurality of memory elements 2221. Although each memory element 2221 may include a V-NAND flash memory having a 2D structure or a 3D structure, each memory element 2221 may include another type of NVM, such as PRAM and / or RRAM. The UFS device controller 2210 may be connected to the NVM 2220 through a storage interface 2230. The storage interface 2230 may be configured to comply with a standard protocol such as Toggle or ONFI.

[0081] The application 2120 may refer to a program that wants to communicate with the UFS device 2200 to use the functions of the UFS device 2200. The application 2120 may send an input-output request (IOR) to the UFS driver 2130 for an input / output (I / O) operation on the UFS device 2200. The IOR may refer to a data read request, a data storage (or write) request, and / or a data erase (or discard) request, but is not limited thereto.

[0082] The UFS driver 2130 may manage the UFS host controller 2110 through a UFS-Host Controller Interface (UFS-HCI). The UFS driver 2130 may convert the IOR generated by the application 2120 into a UFS command defined by the UFS standard, and send the UFS command to the UFS host controller 2110. One IOR may be converted into a plurality of UFS commands. Although the UFS command may be basically defined by the SCSI standard, the UFS command may be a command dedicated to the UFS standard.

[0083] The UFS host controller 2110 may transmit the UFS command converted by the UFS driver 2130 to the UIC layer 2250 of the UFS device 2200 through the UIC layer 2150 and the UFS interface 2300. During transmission of the UFS command, the UFS host register 2111 of the UFS host controller 2110 may function as a command queue (CQ).

[0084] The UIC layer 2150 on the side of the UFS host 2100 may include a Mobile Industry Processor Interface (MIPI) M-PHY 2151 and a MIPI UniPro 2152 , and the UIC layer 2150 on the side of the UFS device 2200 may also include a MIPI M-PHY 2251 and a MIPI UniPro 2252 .

[0085] The UFS interface 2300 may include a line configured to transmit a reference clock signal REF_CLK, a line configured to transmit a hardware reset signal RESET_n of the UFS device 2200 , a pair of lines configured to transmit a pair of differential input signals DIN_t and DIN_c, and a pair of lines configured to transmit a pair of differential output signals DOUT_t and DOUT_c.

[0086] The frequency of the reference clock signal REF_CLK provided from the UFS host 2100 to the UFS device 2200 may be one of 19.2 MHz, 26 MHz, 38.4 MHz, and 52 MHz, but is not limited thereto. The UFS host 2100 may change the frequency of the reference clock signal REF_CLK during operation, that is, during a data transmission / reception operation between the UFS host 2100 and the UFS device 2200. The UFS device 2200 may generate a clock signal having various frequencies from the reference clock signal REF_CLK provided by the UFS host 2100 by using a phase-locked loop (PLL). In addition, the UFS host 2100 may set a data rate between the UFS host 2100 and the UFS device 2200 by using the frequency of the reference clock signal REF_CLK. That is, the data rate may be determined depending on the frequency of the reference clock signal REF_CLK.

[0087] The UFS interface 2300 may support multiple lanes, each of which may be implemented as a pair of differential lines. For example, the UFS interface 2300 may include at least one receiving lane and at least one transmitting lane. Figure 5 In the embodiment, a pair of lines configured to transmit a pair of differential input signals DIN_T and DIN_C may constitute a receiving path, and a pair of lines configured to transmit a pair of differential output signals DOUT_T and DOUT_C ​​may constitute a transmitting path. Figure 5 One transmission path and one reception path are shown in FIG. 1 , but the number of transmission paths and the number of reception paths may be changed.

[0088] The receiving path and the transmitting path may transmit data based on a serial communication scheme. Due to the structure in which the receiving path is separated from the transmitting path, full-duplex communication between the UFS host 2100 and the UFS device 2200 may be enabled. That is, while receiving data from the UFS host 2100 through the receiving path, the UFS device 2200 may send data to the UFS host 2100 through the transmitting path. In addition, control data (e.g., commands) from the UFS host 2100 to the UFS device 2200 and user data to be stored in the NVM 2220 of the UFS device 2200 or read from the NVM 2220 by the UFS host 2100 may be sent through the same channel. Therefore, between the UFS host 2100 and the UFS device 2200, in addition to a pair of receiving paths and a pair of transmitting paths, there is no need to further provide a separate channel for data transmission.

[0089] The UFS device controller 2210 of the UFS device 2200 may control all operations of the UFS device 2200. The UFS device controller 2210 may manage the NVM 2220 by using a logical unit (LU) 2211, which is a logical data memory unit. The number of LUs 2211 may be 8, but is not limited thereto. The UFS device controller 2210 may include an FTL, and converts a logical data address (e.g., a logical block address (LBA)) received from the UFS host 2100 into a physical data address (e.g., a physical block address (PBA)) by using address mapping information of the FTL. A logical block configured to store user data in the UFS system 2000 may have a size within a predetermined range. For example, the minimum size of a logical block may be set to 4Kbyte.

[0090] When a command from the UFS host 2100 is applied to the UFS device 2200 through the UIC layer 2250 , the UFS device controller 2210 may perform an operation in response to the command and transmit a completion response to the UFS host 2100 when the operation is completed.

[0091] As an example, when the UFS host 2100 intends to store user data in the UFS device 2200, the UFS host 2100 may send a data storage command to the UFS device 2200. When receiving a response (“transfer ready” response) indicating that the UFS host 2100 is ready to receive user data (transfer ready) from the UFS device 2200, the UFS host 2100 may send the user data to the UFS device 2200. The UFS device controller 2210 may temporarily store the received user data in the device memory 2240, and store the user data temporarily stored in the device memory 2240 in a selected location of the NVM 2220 based on the address mapping information of the FTL.

[0092] As another example, when the UFS host 2100 intends to read user data stored in the UFS device 2200, the UFS host 2100 may send a data read command to the UFS device 2200. The UFS device controller 2210, which has received the command, may read the user data from the NVM 2220 based on the data read command, and temporarily store the read user data in the device memory 2240. During the read operation, the UFS device controller 2210 may detect and correct errors in the read user data by using an ECC engine embedded therein. More specifically, the ECC engine may generate parity bits for write data to be written to the NVM 2220, and the generated parity bits may be stored in the NVM 2220 together with the write data. During the reading of data from the NVM 2220, the ECC engine may correct errors in the read data by using the read data and the parity bits read from the NVM 2220, and output the error-corrected read data.

[0093] In addition, the UFS device controller 2210 may transmit user data temporarily stored in the device memory 2240 to the UFS host 2100. In addition, the UFS device controller 2210 may further include an AES engine. The AES engine may perform at least one of an encryption operation and a decryption operation on data transmitted to the UFS device controller 2210 by using a symmetric key algorithm.

[0094] The UFS host 2100 may sequentially store the commands to be sent to the UFS device 2200 in the UFS host register 2111, which may be used as a common queue, and sequentially send the commands to the UFS device 2200. In this case, even when the previously sent command is still being processed by the UFS device 2200, that is, even before receiving a notification that the previously sent command has been processed by the UFS device 2200, the UFS host 2100 may send the next command on standby in the CQ to the UFS device 2200. Therefore, during the processing of the previously sent command, the UFS device 2200 may also receive the next command from the UFS host 2100. The maximum number of commands (or queue depth) that can be stored in the CQ may be, for example, 32. In addition, the CQ may be implemented as a circular queue in which the start and end of the command line stored in the queue are indicated by a head pointer and a tail pointer.

[0095] Each of the plurality of memory elements 2221 may include a memory cell array and a control circuit configured to control the operation of the memory cell array. The memory cell array may include a 2D memory cell array or a 3D memory cell array. The memory cell array may include a plurality of memory cells. Although each of the memory cells is a single-layer cell (SLC) configured to store 1 bit of information, each memory cell may be a cell configured to store 2 bits or more bits of information, such as a multi-layer cell (MLC), a triple-layer cell (TLC), and a quad-layer cell (QLC). The 3D memory cell array may include a vertical NAND string in which at least one memory cell is vertically oriented and located on another memory cell.

[0096] Voltages VCC, VCCQ, and VCCQ2 may be applied to the UFS device 2200 as power supply voltages. Voltage VCC may be a main power supply voltage for the UFS device 2200 and may be in the range of 2.4V to 3.6V. Voltage VCCQ may be a power supply voltage mainly used to supply a low voltage to the UFS device controller 2210 and may be in the range of 1.14V to 1.26V. Voltage VCCQ2 may be a power supply voltage mainly used to supply a voltage lower than voltage VCC and higher than voltage VCCQ to an I / O interface such as MIPI M-PHY 2251 and may be in the range of 1.7V to 1.95V. The power supply voltage may be supplied to the various components of the UFS device 2200 by the regulator 2260. The regulator 2260 may be implemented as a group of unit regulators, which are respectively connected to different power supply voltages among the above-mentioned power supply voltages.

[0097] As described above, embodiments may involve efficient BCH decoding with low error correction capability that can correct t and (t+1) errors in polar codewords. As described above, an error correction capability of t=2 may be used, however embodiments are not limited thereto. In embodiments, a BCH decoder may be used instead of a polar decoder to decode at least some of a plurality of polar codewords that may be stored, for example, in a storage device, thereby increasing overall throughput. In some embodiments, one or more polarization parity checks may be used to check or verify polar frames, and to perform smart chase decoding, examples of which are discussed in more detail below.

[0098] FIG. 6A to FIG. 6C This is a diagram of the form factor of the UFS card 4000. Figure 5 When the UFS device 2200 described above is implemented as a UFS card 4000, the appearance of the UFS card 4000 may be as follows: FIG. 6A to FIG. 6C shown.

[0099] Fig. 6Ais a top view of a UFS card 4000 according to an example embodiment. Fig. 6A , it can be seen that the UFS card 4000 fully follows the shark-shaped design. Fig. 6A The UFS card 4000 may have the sizes shown in the following Table 1 as an example.

[0100] [Table 1]

[0101] project Dimensions (mm) T1 9.70 T2 15.00 T3 11.00 T4 9.70 T5 5.15 T6 0.25 T7 0.60 T8 0.75 T9 R0.80

[0102] Figure 6B is a side view of a UFS card 4000 according to an example embodiment. Figure 6B The UFS card 4000 may have the sizes shown in the following Table 2 as an example.

[0103] [Table 2]

[0104] project Dimensions (mm) S1 0.74±0.06 S2 0.30 S3 0.52 S4 1.20 S5 1.05 S6 1.00

[0105] Figure 6C is a bottom view of a UFS card 4000 according to an example embodiment. Figure 6C , a plurality of pins for electrically contacting the UFS slot may be formed on the bottom surface of the UFS card 4000. The function of each of the pins will be described below. Based on the symmetry between the top and bottom surfaces of the UFS card 4000, some information about the dimensions described in reference 6A and Table 1 (e.g., T1 to T5 and T9) may also be applied Figure 6C A bottom view of a UFS card 4000 is shown in FIG.

[0106] A plurality of pins for electrical connection with a UFS host may be formed on the bottom surface of the UFS card 4000. Figure 6C , the total number of pins may be 12. Each of the pins may have a rectangular shape, and a signal name corresponding to the pin may be as follows: Figure 6C Refer to Table 3 below and Figure 5 Given the above description, specific information about each of the pins will be understood.

[0107] [Table 3]

[0108]

[0109] Figure 7 is a block diagram of a memory system 20 according to an embodiment. Figure 7 , the memory system 20 may include a memory device 300 and a memory controller 400. The memory device 300 may correspond to one of the NVM devices NVM11 to NVMmn, which is based on Figure 3The memory controller 400 may communicate with one of the plurality of channels CH1 to CHm. The memory controller 400 may correspond to Figure 3 A storage controller 200 is provided.

[0110] The memory device 300 may include first to eighth pins P11 to P18 , a memory interface circuit 310 , a control logic circuit 320 , and a memory cell array 330 .

[0111] The memory interface circuit 310 may receive a chip enable signal nCE from the memory controller 400 through the first pin P11. The memory interface circuit 310 may send and receive signals to and from the memory controller 400 through the second to eighth pins P12 to P18 in response to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., a low level), the memory interface circuit 310 may send and receive signals to and from the memory controller 400 through the second to eighth pins P12 to P18.

[0112] The memory interface circuit 310 can receive a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the memory controller 400 through the second pin to the fourth pin P12 to P14. The memory interface circuit 310 can receive a data signal DQ from the memory controller 400 through the seventh pin P17, or send the data signal DQ to the memory controller 400. The command CMD, the address ADDR, and the data can be transmitted via the data signal DQ. For example, the data signal DQ can be transmitted through a plurality of data signal lines. In this case, the seventh pin P17 may include a plurality of pins corresponding to the plurality of data signals DQ, respectively.

[0113] The memory interface circuit 310 may obtain a command CMD from a data signal DQ received in an enable interval (e.g., a high level state) of a command latch enable signal CLE based on a switching time point of the write enable signal nWE. The memory interface circuit 310 may obtain an address ADDR from a data signal DQ received in an enable interval (e.g., a high level state) of an address latch enable signal ALE based on a switching time point of the write enable signal nWE.

[0114] In an example embodiment, the write enable signal nWE may be maintained at a static state (e.g., a high level or a low level) and switched between a high level and a low level. For example, the write enable signal nWE may be switched in an interval in which a command CMD or an address ADDR is sent. Therefore, the memory interface circuit 310 may obtain a command CMD or an address ADDR based on a switching time point of the write enable signal nWE.

[0115] The memory interface circuit 310 may receive a read enable signal nRE from the memory controller 400 through a fifth pin P15. The memory interface circuit 310 may receive a data strobe signal DQS from the memory controller 400 through a sixth pin P16 or may transmit the data strobe signal DQS to the memory controller 400.

[0116] In the data (DATA) output operation of the memory device 300, the memory interface circuit 310 may receive a read enable signal nRE switched by the fifth pin P15 before outputting the data DATA. The memory interface circuit 310 may generate a data strobe signal DQS, which is switched based on the switching of the read enable signal nRE. For example, the memory interface circuit 310 may generate a data strobe signal DQS based on the switching start time of the read enable signal nRE, which starts switching after a predetermined delay (e.g., tDQSRE). The memory interface circuit 310 may send a data signal DQ including data DATA based on the switching time point of the data strobe signal DQS. Therefore, the data DATA may be aligned with the switching time point of the data strobe signal DQS and sent to the memory controller 400.

[0117] In the data (DATA) input operation of the memory device 300, when the data signal DQ including the data DATA is received from the memory controller 400, the memory interface circuit 310 may receive the switched data strobe signal DQ and the data DATA. The memory interface circuit 310 may obtain the data DATA from the data signal DQ based on the switching time point of the data strobe signal DQS. For example, the memory interface circuit 310 may sample the data signal DQ at the rising edge and the falling edge of the data strobe signal DQS and obtain the data DATA.

[0118] The memory interface circuit 310 may transmit the ready / busy output signal nR / B to the memory controller 400 through the eighth pin P18. The memory interface circuit 310 may transmit the state information of the memory device 300 to the memory controller 400 through the ready / busy output signal nR / B. When the memory device 300 is in a busy state (i.e., when an operation is being performed in the memory device 300), the memory interface circuit 310 may transmit the ready / busy output signal nR / B indicating the busy state to the memory controller 400. When the memory device 300 is in a ready state (i.e., when an operation is not being performed or completed in the memory device 300), the memory interface circuit 310 may transmit the ready / busy output signal nR / B indicating the ready state to the memory controller 400. For example, when the memory device 300 reads data DATA from the memory cell array 330 in response to a page read command, the memory interface circuit 310 may transmit the ready / busy output signal nR / B indicating the busy state (e.g., a low level) to the memory controller 400. For example, when the memory device 300 programs the data DATA to the memory cell array 330 in response to a program command, the memory interface circuit 310 may transmit a ready / busy output signal nR / B indicating a busy state to the memory controller 400 .

[0119] The control logic circuit 320 may control all operations of the memory device 300. The control logic circuit 320 may receive the command / address CMD / ADDR obtained from the memory interface circuit 310. The control logic circuit 320 may generate control signals for controlling other components of the memory device 300 in response to the received command / address CMD / ADDR. For example, the control logic circuit 320 may generate various control signals for programming data DATA to the memory cell array 330 or reading data DATA from the memory cell array 330.

[0120] The memory cell array 330 may store the data DATA obtained from the memory interface circuit 310 via the control of the control logic circuit 320. The memory cell array 330 may output the stored data DATA to the memory interface circuit 310 via the control of the control logic circuit 320.

[0121] The memory cell array 330 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the inventive concept is not limited thereto, and the memory cells may be RRAM cells, FRAM cells, PRAM cells, thyristor RAM (TRAM) cells, or MRAM cells. Hereinafter, an embodiment in which the memory cells are NAND flash memory cells will be mainly described.

[0122] The memory controller 400 may include first to eighth pins P21 to P28 and a controller interface circuit 410. The first to eighth pins P21 to P28 may correspond to first to eighth pins P11 to P18 of the memory device 300, respectively.

[0123] The controller interface circuit 410 may send a chip enable signal nCE to the memory device 300 through the first pin P21. The controller interface circuit 410 may send and receive signals to and from the memory device 300 through the second to eighth pins P22 to P28, and the memory device 300 is selected by the chip enable signal nCE.

[0124] The controller interface circuit 410 may transmit the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the memory device 300 through the second to fourth pins P22 to P24. The controller interface circuit 410 may transmit or receive the data signal DQ to or from the memory device 300 through the seventh pin P27.

[0125] The controller interface circuit 410 may transmit the data signal DQ including the command CMD or the address ADDR together with the switched write enable signal nWE to the memory device 300. The controller interface circuit 410 may transmit the data signal DQ including the command CMD to the memory device 300 by transmitting the command latch enable signal CLE having an enable state. In addition, the controller interface circuit 410 may transmit the data signal DQ including the address ADDR to the memory device 300 by transmitting the address latch enable signal ALE having an enable state.

[0126] The controller interface circuit 410 may transmit the read enable signal nRE to the memory device 300 through the fifth pin P25. The controller interface circuit 410 may receive the data strobe signal DQS from the memory device 300 or transmit the data strobe signal DQS to the memory device 300 through the sixth pin P26.

[0127] In the data (DATA) output operation of the memory device 300, the controller interface circuit 410 may generate a switched read enable signal nRE and send the read enable signal nRE to the memory device 300. For example, before outputting the data DATA, the controller interface circuit 410 may generate a read enable signal nRE that changes from a static state (e.g., a high level or a low level) to a switched state. Therefore, the memory device 300 may generate a switched data strobe signal DQS based on the read enable signal nRE. The controller interface circuit 410 may receive a data signal DQ including data DATA and a switched data strobe signal DQS from the memory device 300. The controller interface circuit 410 may obtain data DATA from the data signal DQ based on the switching time point of the data strobe signal DQS.

[0128] In the data (DATA) input operation of the memory device 300, the controller interface circuit 410 may generate a switched data strobe signal DQS. For example, before sending the data DATA, the controller interface circuit 410 may generate a data strobe signal DQS that changes from a static state (e.g., a high level or a low level) to a switched state. The controller interface circuit 410 may send a data signal DQ including the data DATA to the memory device 300 based on a switching time point of the data strobe signal DQS.

[0129] The controller interface circuit 410 may receive the ready / busy output signal nR / B from the memory device 300 through the eighth pin P28. The controller interface circuit 410 may determine the state information of the memory device 300 based on the ready / busy output signal nR / B.

[0130] Figure 8 is a diagram of a 3D V-NAND structure applicable to a UFS device according to an embodiment. When a memory module of the UFS device is implemented as a 3D V-NAND flash memory, each of a plurality of memory blocks included in the memory module may be composed of Figure 8 The equivalent circuit shown in .

[0131] Figure 8 The memory block BLKi shown in may refer to a 3D memory block having a 3D structure formed on a substrate. For example, a plurality of memory NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate.

[0132] refer to Figure 8, the memory block BLKi may include a plurality of memory NAND strings (e.g., NS11 to NS33) connected between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the memory NAND strings NS11 to NS33 may include a string selection transistor SST, a plurality of memory cells (e.g., MC1, MC2, ..., and MC8), and a ground selection transistor GST. Although Figure 8 Each of the memory NAND strings NS11 to NS33 is shown to include eight memory cells MC1, MC2, . . . and MC8, but is not limited thereto.

[0133] The string selection transistor SST may be connected to the string selection lines SSL1, SSL2, and SSL3 corresponding thereto. Each of the memory cells MC1, MC2, ..., and MC8 may be connected to a corresponding one of the gate lines GTL1, GTL2, ..., and GTL8. The gate lines GTL1, GTL2, ..., and GTL8 may correspond to word lines, respectively, and some of the gate lines GTL1, GTL2, ..., and GTL8 may correspond to virtual word lines. The ground selection transistor GST may be connected to the ground selection lines GSL1, GSL2, and GSL3 corresponding thereto. The string selection transistor SST may be connected to the bit lines BL1, BL2, and BL3 corresponding thereto, and the ground selection transistor GST may be connected to the common source line CSL.

[0134] Word lines (eg, WL1) of the same level may be commonly connected, and ground selection lines GSL1, GSL2, and GSL3 and string selection lines SSL1, SSL2, and SSL3 may be separated from each other. Figure 8 A case is shown in which the memory block BLK is connected to eight gate lines GTL1 , GTL2 , and GTL8 corresponding thereto and three bit lines BL1 , BL2 , and BL3 , but is not limited thereto.

[0135] Fig. 9 is a diagram illustrating a memory device 600 according to another example embodiment.

[0136] refer to Fig. 9, the memory device 600 may have a chip-to-chip (C2C) structure. The C2C structure may refer to a structure formed by manufacturing an upper chip including a cell area CELL on a first wafer, manufacturing a lower chip including a peripheral circuit area PERI on a second wafer separated from the first wafer, and then bonding the upper chip and the lower chip to each other. Here, the bonding process may include a method of electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip and a bonding metal formed on the uppermost metal layer of the lower chip. For example, when the bonding metal may include copper (Cu), copper-to-copper (Cu-to-Cu) bonding is used. However, example embodiments are not limited thereto. For example, the bonding metal may also be formed of aluminum (Al) or tungsten (W).

[0137] Each of the peripheral circuit region PERI and the cell region CELL of the memory device 600 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0138] The peripheral circuit region PERI may include a first substrate 710, an interlayer insulating layer 715, a plurality of circuit elements 720a, 720b, and 720c formed on the first substrate 710, first metal layers 730a, 730b, and 730c respectively connected to the plurality of circuit elements 720a, 720b, and 720c, and second metal layers 740a, 740b, and 740c formed on the first metal layers 730a, 730b, and 730c. In example embodiments, the first metal layers 730a, 730b, and 730c may be formed of tungsten having a relatively high resistance, and the second metal layers 740a, 740b, and 740c may be formed of copper having a relatively low resistance.

[0139] exist Fig. 9 In the illustrated example embodiment, although the first metal layers 730a, 730b, and 730c and the second metal layers 740a, 740b, and 740 are illustrated and described, they are not limited thereto, and one or more metal layers may be further formed on the second metal layers 740a, 740b, and 740c. At least a portion of the one or more metal layers formed on the second metal layers 740a, 740b, and 740c may be formed of aluminum or the like having a lower resistance than copper forming the second metal layers 740a, 740b, and 740c.

[0140] The interlayer insulating layer 715 may be disposed on the first substrate 710 and cover the plurality of circuit elements 720a, 720b, and 720c, the first metal layers 730a, 730b, and 730c, and the second metal layers 740a, 740b, and 740c. The interlayer insulating layer 715 may include an insulating material such as silicon oxide, silicon nitride, or the like.

[0141] The lower bonding metals 771b and 772b may be formed on the second metal layer 740b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 771b and 772b in the peripheral circuit area PERI may be electrically bonded to the upper bonding metals 871c and 872c of the cell area CELL. The lower bonding metals 771b and 772b and the upper bonding metals 871b and 872b may be formed of aluminum, copper, tungsten, etc. In addition, the upper bonding metals 871b and 872b in the cell area CELL may be referred to as first metal pads, and the lower bonding metals 771b and 772b in the peripheral circuit area PERI may be referred to as second metal pads.

[0142] The cell region CELL may include at least one memory block. The cell region CELL may include a second substrate 810 and a common source line 820. On the second substrate 810, a plurality of word lines 831 to 838 (i.e., 830) may be stacked in a direction (Z-axis direction) perpendicular to the upper surface of the second substrate 810. At least one string selection line and at least one ground selection line may be arranged above and below the plurality of word lines 830, respectively, and the plurality of word lines 830 may be arranged between at least one string selection line and at least one ground selection line.

[0143] In the bit line bonding area BLBA, the channel structure CH may extend in a direction perpendicular to the upper surface of the second substrate 810 and pass through a plurality of word lines 830, at least one string selection line, and at least one ground selection line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer may be electrically connected to the first metal layer 850c and the second metal layer 860c. For example, the first metal layer 850c may be a bit line contact, and the second metal layer 860c may be a bit line. In example embodiments, the bit line 860c may extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 810.

[0144] exist Fig. 9In the example embodiment shown, a region in which a channel structure CH, a bit line 860c, etc. are provided may be defined as a bit line bonding region BLBA. In the bit line bonding region BLBA, the bit line 860c may be electrically connected to a circuit element 720c providing a page buffer 893 in the peripheral circuit region PERI. For example, the bit line 860c may be connected to upper bonding metals 871c and 872c in the cell region CELL, and the upper bonding metals 871c and 872c may be connected to lower bonding metals 771c and 772c connected to the circuit element 720c of the page buffer 893. In an example embodiment, when write data of a page unit is stored in the page buffer 893, a programming operation may be performed based on the page unit, and when read data of a sub-page unit is stored in the page buffer 893, a read operation may be performed based on the sub-page unit. In addition, in the programming operation and the read operation, the units of the data transmitted through the bit line may be different from each other.

[0145] In the word line bonding area WLBA, a plurality of word lines 830 may extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 810, and may be connected to a plurality of cell contact plugs 841 to 847 (i.e., 840). The plurality of word lines 830 and the plurality of cell contact plugs 840 may be connected to each other in a pad provided by at least a portion of the plurality of word lines 830 extending in different lengths in the second direction. The first metal layer 850b and the second metal layer 860b may be sequentially connected to the upper portions of the plurality of cell contact plugs 840 connected to the plurality of word lines 830. In the word line bonding area WLBA, the plurality of cell contact plugs 840 may be connected to the circuit region PERI through the upper bonding metals 871b and 872b of the cell region CELL and the lower bonding metals 771b and 772b of the peripheral circuit region PERI.

[0146] The plurality of cell contact plugs 840 may be electrically connected to the circuit elements 720 b forming the row decoder 894 in the peripheral circuit region PERI. In example embodiments, the operating voltage of the circuit elements 720 b forming the row decoder 894 may be different from the operating voltage of the circuit elements 720 c forming the page buffer 893. For example, the operating voltage of the circuit elements 720 c forming the page buffer 893 may be greater than the operating voltage of the circuit elements 720 b forming the row decoder 894.

[0147] The common source line contact plug 880 may be disposed in the external pad bonding area PA. The common source line contact plug 880 may be formed of a conductive material such as a metal, a metal compound, polysilicon, etc., and may be electrically connected to the common source line 820. The first metal layer 850a and the second metal layer 860a may be sequentially stacked on the upper portion of the common source line contact plug 880. For example, a region where the common source line contact plug 880, the first metal layer 850a, and the second metal layer 860a are disposed may be defined as the external pad bonding area PA.

[0148] The input-output pads 705 and 805 may be disposed in the external pad bonding area PA. Fig. 9 , a lower insulating film 701 covering the lower surface of the first substrate 710 may be formed below the first substrate 710, and a first input-output pad 705 may be formed on the lower insulating film 701. The first input-output pad 705 may be connected to at least one of a plurality of circuit elements 720a, 720b, and 720c provided in the peripheral circuit region PERI through the first input-output contact plug 703, and may be separated from the first substrate 710 by the lower insulating film 701. In addition, a side insulating film may be provided between the first input-output contact plug 703 and the first substrate 710 to electrically separate the first input-output contact plug 703 from the first substrate 710.

[0149] refer to Fig. 9 , an upper insulating film 801 covering the upper surface of the second substrate 810 may be formed on the second substrate 810, and a second input-output pad 805 may be disposed on the upper insulating layer 801. The second input-output pad 805 may be connected to at least one of the plurality of circuit elements 720a, 720b, and 720c disposed in the peripheral circuit region PERI through a second input-output contact plug 803. In example embodiments, the second input-output pad 805 may be electrically connected to the circuit element 720a.

[0150] According to an embodiment, the second substrate 810 and the common source line 820 may not be disposed in the region where the second input-output contact plug 803 is disposed. In addition, the second input-output pad 805 may not overlap with the word line 830 in the third direction (Z-axis direction). Fig. 9 The second input-output contact plug 803 may be separated from the second substrate 810 in a direction parallel to the upper surface of the second substrate 810 , and may pass through the interlayer insulating layer 815 of the cell region CELL to be connected to the second input-output pad 805 .

[0151] According to an embodiment, the first input-output pad 705 and the second input-output pad 805 may be selectively formed. For example, the memory device 600 may include only the first input-output pad 705 disposed on the first substrate 710 or the second input-output pad 805 disposed on the second substrate 810. Alternatively, the memory device 600 may include both the first input-output pad 705 and the second input-output pad 805.

[0152] The metal pattern disposed on the uppermost metal layer respectively included in the cell region CELL and the peripheral circuit region PERI in each of the external pad bonding region PA and the bit line bonding region BLBA may be set as a dummy pattern, or the uppermost metal layer may not exist.

[0153] In the external pad bonding area PA, the memory device 600 may include a lower metal pattern 773a, which corresponds to the upper metal pattern 872a formed in the uppermost metal layer of the cell area CELL and has the same cross-sectional shape as the upper metal pattern 872a of the cell area CELL, so as to be connected to each other in the uppermost metal layer of the peripheral circuit area PERI. In the peripheral circuit area PERI, the lower metal pattern 773a formed in the uppermost metal layer of the peripheral circuit area PERI may not be connected to the contact. Similarly, in the external pad bonding area PA, an upper metal pattern 872a may be formed in the uppermost metal layer of the cell area CELL, which corresponds to the lower metal pattern 773a formed in the uppermost metal layer of the peripheral circuit area PERI and has the same shape as the lower metal pattern 773a of the peripheral circuit area PERI.

[0154] The lower bonding metals 771b and 772b may be formed on the second metal layer 740b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 771b and 772b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 871b and 872b of the cell area CELL by Cu-to-Cu bonding.

[0155] In addition, in the bit line bonding area BLBA, an upper metal pattern 892 may be formed in the uppermost metal layer of the cell area CELL, corresponding to the lower metal pattern 752 formed in the uppermost metal layer of the peripheral circuit area PERI and having the same cross-sectional shape as the lower metal pattern 752 of the peripheral circuit area PERI. No contact may be formed on the upper metal pattern 892 formed in the uppermost metal layer of the cell area CELL.

[0156] In example embodiments, a reinforcement metal pattern having the same cross-sectional shape as that of the metal pattern may be formed in the uppermost metal layer in the other of the cell region CELL and the peripheral circuit region PERI, corresponding to the metal pattern formed in the uppermost metal layer in one of the cell region CELL and the peripheral circuit region PERI. No contact may be formed on the reinforcement metal pattern.

[0157] As described above, the basic unit of a flash memory (such as a 3D NAND flash memory or a V-NAND flash memory) may be a memory cell. In an embodiment, a memory cell may be based on a semiconductor device that may be referred to as a floating gate transistor. Each memory cell included in a memory cell array (such as the memory cell array 330 discussed above) may maintain a voltage level using its transistor threshold voltage v th Encoded information.

[0158] In an embodiment, a flash memory cell can be viewed as storing a real value v th ∈[v min ,v max ] means, where the range [v min ,v max ] can be called the dynamic range of the memory cell. Some flash memory devices are able to store multiple bits per cell (bits per cell, BPC). This can be achieved by dividing the dynamic range into 2 BPC The memory cells may be arranged in a plurality of regions, each of which may correspond to different symbols, for example, different combinations of information bits. A group of memory cells that hold the same symbol may be referred to as a level. In an embodiment, a flash memory device that stores one bit per cell (one BPC) may be referred to as a single-level cell (SLC), a flash memory device that stores two bits per cell (two BPCs) may be referred to as a multi-level cell (MLC), a flash memory device that stores three bits per cell (three BPCs) may be referred to as a triple-level cell (TLC), and a flash memory device that stores four bits per cell (four BPCs) may be referred to as a quad-level cell (QLC).

[0159] In an embodiment, the memory cells may be organized into a two-dimensional array called a string or pillar, such as the NAND string discussed above. The strings may be arranged in two directions, such as a pillar axis and a word line (WL) axis. In an embodiment, the pillar axis may correspond to Figure 8 The Z axis, and the WL axis can correspond to Figure 8 To further increase device capacity, a 3D NAND device may stack four string arrays one on top of another along a third direction, which may be referred to as a bit line (BL) axis. In an embodiment, the BL axis may correspond to Figure 8 Y-axis.

[0160] According to an embodiment, a memory device (such as memory device 300) can perform several basic operations on flash memory cells. For example, a program pulse operation can be an operation that increases the voltage value stored in a flash memory cell. It can be applied to a subset of cells I from a single WL. In some embodiments, due to limitations of flash memory technology, the reduction of the voltage of the memory cells can only be performed on a complete block. Therefore, an erase operation can reduce the voltage stored in the memory cells of the complete block to a minimum voltage v min or close to the minimum voltage v min The program verification operation can check or determine the threshold voltage v of the memory cell from a given WL. th Is it higher than a certain reference voltage t? Theoretically, if v th represents a vector of threshold voltages stored in memory cells of a particular WL, then the verification function f for the i-th cell in that WL is verify The output can be expressed according to the following equation 1:

[0161]

[0162] Based on these basic operations, the memory device 300 can perform more complex operations. An example of a complex operation may be a programming operation that may be performed to program a block of memory cells with data, such as by bringing a voltage to each memory cell to a voltage region assigned to a data symbol to be stored in the memory cell. In an embodiment, the programming operation may be performed WL by WL using iterative calls to a programming algorithm such as the ISPP algorithm, described below with reference to Fig.10 and Fig.17 An example of this is provided. In an embodiment, programming each WL may require 2 BPC -1 call, once for each layer except the erase layer.

[0163] Another example of a complex operation may be a read operation, which may be performed to read data stored in WL. The read operation may include utilizing a minimum voltage v min The maximum voltage of the memory cell is v max A series of program verification operations are performed with a predefined value between 1 and 2 so that the memory device 300 can obtain sufficient information to determine which symbol is stored in each cell. The most basic read operation is performed by performing 2 BPC -1 verification operation is completed, which can be [v min ,v max ] segmented into 2 BPC The corresponding symbol is 2 BPC voltage region.

[0164] Fig.10 An example of an ISPP algorithm that can be used to program a WL is shown. In an embodiment, Algorithm 1 can represent an ISPP algorithm that can be performed by any element discussed herein (e.g., memory device 300 or any element thereof). In an embodiment, Fig.10 The algorithm 1 shown in FIG. 1 may be used to program a group of cells from a single WL to a given threshold voltage v th If the i-th cell of the WL is to be programmed, Algorithm 1 can receive I i =0 prohibits vector I, otherwise receives I i = 1. Considering the inhibition vector I, Algorithm 1 can be executed from the vector with magnitude v pgm_start A series of at most M pulses starting with a pulse of pgm_start After each pulse, the voltage v verify Apply program verification operation, and can prohibit higher than the verification voltage v verify This may mean, for example, that they will not receive a pulse in the next step.

[0165] As discussed above, reading data stored at a particular WL can be done by segmenting the dynamic range of the chip into two BPC predefined voltage regions and assigning each memory cell its threshold voltage v th However, sometimes the threshold voltage v of the memory cell th Falling outside the voltage region assigned to the data symbol it is supposed to hold. This can cause read errors. The ratio of incorrectly assigned bits to all bits read during a read operation can be referred to as the bit error rate (BER). Errors in flash memory devices can be caused by a variety of factors, including, for example, programming variation and retention disturb.

[0166] In an embodiment, the threshold voltage v of the memory cell after receiving a programming pulse th Can be the initial cell threshold voltage v th and the pulse amplitude. Therefore, using any programming algorithm, programming level l in a particular WL can result in a threshold voltage v th Rather than having all cells at the desired threshold voltage v th In an embodiment, the programming variation may be or may include noise injected by the programming algorithm. After the programming phase has been completed, the threshold voltage vth Changes during the data storage time may be referred to as retention disturbance. Retention disturbance may occur due to charge leakage from the transistor of the memory cell over time. This charge loss phenomenon, which can be a major source of errors in flash memory devices, may depend largely on the initial threshold voltage v of the cell. th and other factors, some of which are described below.

[0167] In an embodiment, both program variation and retention disturbance may affect different WLs and strings differently, which may result in different threshold voltages v at different parts of a 3D NAND block. th Distribution. In addition, the number of PE cycles that a memory block has previously experienced may also affect the programming variation and retention disturbance experienced by the memory block. Each PE cycle may wear out the memory cells included in the block, making them more susceptible to disturbance and thus increasing the BER of the block.

[0168] In an embodiment, the BER of a memory block may also be affected by ICI. As discussed above, ICI may be the threshold voltage v of a particular memory cell. th Affected by the threshold voltage v of one or more adjacent memory cells th In an embodiment, the neighboring memory cell may be, for example, another memory cell that is adjacent to the memory cell along an axis (e.g., a column axis). ICI can be divided into two separate phenomena, programming ICI and retention ICI. When a programming operation performed on a memory cell inadvertently increases the threshold voltage v of the neighboring memory cell, th Program ICI may occur when the program ICI for a memory cell is 100 ms. The program ICI effect on a memory cell may be a random function of the amount and amplitude of the pulses experienced by the neighboring memory cells. Therefore, it may also be a function of the threshold voltage target t of the neighboring memory cells. Retention ICI may occur during the data retention process. For example, if two neighboring memory cells have different threshold voltages v th , then the source with a higher threshold voltage v th The charge of a memory cell may leak into another memory cell within a cycle during the data retention period.

[0169] Fig.11 An example of the retained ICI phenomenon measured on a 3D-NAND chip programmed with QLC data is shown. In particular, Fig.11 shows the threshold voltage v of the memory cell th Changes immediately after programming the block and again after a simulated retention period of one month using an oven simulation according to Arrehenius's law. Fig.11The mean threshold voltage v of the memory cells programmed to a certain data symbol (e.g., symbol 1, symbol 4, symbol 12, and symbol 15) is shown. th changes as a function of the sign of two adjacent memory cells with a 95% confidence interval. Fig.11 As can be seen in , adjacent memory calls with low symbols may result in larger voltage loss over time.

[0170] According to an embodiment, the Wasserstein distance may be a distance function defined between two probability metrics on a given metric space. In theory, given a metric space (M, d) and two probability metrics μ and ν on M, the p-th Wasserstein distance between μ and ν may be defined according to the following equation 2:

[0171]

[0172] In Equation 2 above, Γ(u,v) represents the set of probability metrics with marginal μ and ν on MxM. The intuition for the above definition comes from the optimal transportation problem, where γ(x,y) represents how much "mass" must be transferred from x to y in order to transform the distribution of μ into the distribution of v. In an embodiment, the 1-Wasserstein distance can be used, which is also called the Earth-Movers distance. Therefore, for ease of description, W(μ,v) may be used herein to represent W 1 (μ,v).

[0173] In μ and v are In the special case of a probability metric on , the Wasserstein distance has an analytical solution, which can be expressed according to the following equation 3:

[0174]

[0175] In Equation 3 above, F μ (z) and F v (z) denotes the cumulative distribution function of μ and v. This closed form is the Wasserstein distance to be estimated between μ and v given n samples drawn from each distribution. As n→∞, the sorted mth element in μ approaches Therefore, numerical integration can be used to evaluate the integral of Equation 3.

[0176] Generally speaking, GAN can be a type of generative model that includes two independent neural networks (NNs), the generator G Θ and the discriminator D ΨGANs can be used to “learn” a set of samples drawn from a distribution of interest p To generate new samples. GAN can fix a relatively simple distribution p on the latent space Z Z (e.g. Gaussian distribution) to learn the distribution p and then optimize the generator function G Θ :Z→Y, making the push-forward measure As close to p as possible.

[0177] In an embodiment, the Wasserstein GAN (WGAN) may use the above 1-Wasserstein distance as the training loss of the generator. Due to the contentious nature of the Wasserstein distance, the WGAN may achieve more stable training and convergence. The definition of the Wasserstein distance provided above includes an infimum on γ∈Γ(μ,v), which may be very difficult to handle. Therefore, according to the following equation 4, the Kantorovich-Rubinstein duality theorem may be used:

[0178]

[0179] In Equation 4 above, ‖f‖ L ≤1 can be expressed as is a 1-Liphsitz function. Using Equation 4, the discriminator D Ψ (which may be referred to as a critic in the context of WGAN) may be used as the function f in Equation 4 and is thereby replaced by a min-max optimization of the form of Equation 5 below Minimization of:

[0180]

[0181] To enforce the 1-Liphsitz constraint on the learned critic function, the following gradient penalty (GP) loss of Equation 6 can be used:

[0182]

[0183] In Equation 6 above, can be obtained by following the path from p and The loss term is implicitly defined by uniform sampling of straight lines between pairs of samples. This loss term may penalize the critic if the gradient norm is greater than 1. Combining these two terms, the generator objective can be expressed according to Equation 7 below, while the critic objective can be expressed according to Equation 8 below:

[0184]

[0185]

[0186] Conditional GANs (cGANs) can be used to extend the basic GAN architecture to conditional models by adding conditional inputs x∈X to the NN for both the generator and the discriminator. For example, in an embodiment, a conditional vector x can be fed to the NN by concatenating it with the standard network input; some z∈Z for the generator and y∈Y for the discriminator. Given a conditional vector x∈X, the cGAN model can be used to sample from a conditional probability distribution P(y|x) by sampling the latent vector z∈Z and computing G(z,x). Applying the same extensions to the above WGAN yields the conditional Wasserstein GAN (cWGAN) architecture. In the conditional model setting, the gradient penalty loss can be modified according to Equation 9 below:

[0187]

[0188] Therefore, the cWGAN objective can be expressed according to the following Equation 10:

[0189]

[0190] Fig.12 An example of a communication system that can be used to perform end-to-end training according to an embodiment is shown. Fig.12 As can be seen in FIG. 1 , the communication system 1200 may include a transmitter 1201, a channel 1202, and a receiver 1203. End-to-end training of the communication system based on the autoencoder can be used to jointly optimize both the transmitter 1201 and the receiver 1203. With this approach, a class autoencoder architecture can be used, such as the communication system 1200, where the transmitter 1201 is used as an encoder and the receiver 1203 is used as a decoder. Both the transmitter 1201 and the receiver are represented as having parameters θ T and θ R The training can be done by using the level s∈[L] at the input of the transmitter and the reconstructed level at the output of the receiver. The reconstruction loss between It can be expressed according to the following equation 11:

[0191]

[0192] In equation 11 above, A receiver function corresponding to the receiver 1203 may be represented, and The transmitter function corresponding to the transmitter 1201 may be represented by . The reconstruction loss may be referred to as s and The categorical cross-entropy (CE) between , where C represents the system channel. Assume that p is the distribution of s, q is The distribution of , then the CE loss can be expressed according to the following equation 12:

[0193]

[0194] Although autoencoder-based systems may be useful in multiple domains, implementing them may not be feasible in some domains due to the lack of channel gradients. As described above, the transmitter 1201 and receiver 1203 can be jointly trained using backpropagation, but the gradients must flow back through the channel 1202 to update the transmitter parameters θ T To address this problem, cGAN can be used as a channel model by learning the distribution of channel outputs given the output of transmitter 1201, which can be expressed as The NN for the cGAN generator may be fully differentiable and thus may be used as a channel model for channel 1202, thereby allowing gradients to be back-propagated to the transmitter 1201. In an embodiment, the cGAN for channel 1202 may be trained before training the NNs for the transmitter 1201 and the receiver 1203 in the communication system 1200, and thus the weights of the cGAN for channel 1202 may be frozen during the training of the transmitter 1201 and the receiver 1203.

[0195] As described above, the basic program-read flow of flash memory (e.g., 3D-NAND flash memory) may be affected by multiple error sources, which may degrade its performance in terms of PE cycles and data retention time. To mitigate the effects of these errors, embodiments may involve a modulator that can use a modulator similar to that described above with reference to Fig.12 The described end-to-end training method is trained.

[0196] According to an embodiment, a modulator that can be trained as described below can be used to optimize a threshold voltage target t for programming a flash memory block. For example, given a specific programming scheme or algorithm, a modulator according to an embodiment can be used to optimize the threshold voltage target t of the programming scheme or algorithm. In addition to optimizing the threshold voltage target t, a modulator according to an embodiment can also perform pre-distortion on the memory cell by further modifying the threshold voltage target t of each memory cell to offset the ICI phenomenon discussed above. This can be accomplished by optimizing the threshold voltage target t of a given memory cell based on the levels of its neighboring memory cells (e.g., neighboring memory cells in the same string or column). Therefore, an embodiment can provide a significant BER reduction and thus extend the EOL operating point of a NAND flash memory block.

[0197] Fig.13 is a block diagram of a training architecture for training a modulator according to an embodiment. Fig.13 As shown, the training architecture 1300 may include a modulator 1301, a target database (DB) 1302, a channel generator 1303, and a demodulator 1304. In an embodiment, the channel generator 1303 may be a pre-trained channel model, which may be used to perform end-to-end training of the modulator 1301 and the demodulator 1304. Considering the data symbol to be programmed to the memory cell and one or more data symbols to be programmed to one or more adjacent memory cells, the modulator 1301 may be trained to output an optimal threshold voltage target t for each memory cell. The modulator 1301 may output a threshold voltage v th target, the threshold voltage v th The target may then flow through the channel generator 1303. The channel generator 1303 may receive the threshold voltage target t of the memory cell, and the adjacent threshold voltage target t corresponding to the adjacent memory cell, which may be obtained from the target database (DB) 1302 or may be obtained from another element in which the adjacent threshold voltage target t is stored. The channel generator 1303 may then simulate a programming operation, a data retention process that may include one or more data retention operations, and a subsequent read operation to output a random threshold voltage v for the memory cell. th Read. The threshold voltage v th The readings may then be passed to a demodulator 1304 which may recover or attempt to recover the data symbols.

[0198] To describe the end-to-end training method according to an embodiment, NAND flash memory can be analogized to a classic communication system, such as the communication system 1200 discussed above. Therefore, the modulator 1301 can correspond to the transmitter 1201, and the modulator function Can correspond to the transmitter function According to an embodiment, the input data symbol of each memory cell and the adjacent data symbols of the adjacent cells may correspond to Fig.12 The level s of , and thus can be converted by the modulator 1301 into a threshold voltage target t, which can be used by the programming algorithm to program the memory cell. In addition, the channel generator 1303 can correspond to the channel 1202, and can represent a combination of a programming scheme or algorithm, a data retention process, and a read operation. In addition, the demodulator 1304 can correspond to the receiver 1203, and the demodulator function can correspond to the receiver function According to various embodiments, the threshold voltage v th Reading can correspond to Fig.12 The output y of the channel shown in , and can therefore be converted into recovered data symbols by the demodulator 1304.

[0199] Using this analogy, the reference above Fig.12 The described end-to-end learning based approach can be used to train or optimize the modulator 1301 for a specific combination of programming scheme, data retention process, and read operation, which can be represented by the channel generator 1303. Thus, embodiments can be used to train or learn the modulator 1301, which can be used to convert input symbols for each memory cell of the block to a threshold voltage target t of a programming scheme (e.g., ISPP algorithm).

[0200] Fig.14 is a block diagram of a training architecture for training a channel generator according to an embodiment.

[0201] As described above, the cGAN model can be used to model the memory channel because the cGAN model can allow the channel gradient to be calculated and can therefore be used to train the modulator 1301. According to an embodiment, the cWGAN architecture as described above can be used for better training convergence. Fig.14 As shown, the channel generator 1303 can be trained to learn the threshold voltage of a specific memory cell given its context (which can correspond to the cGAN condition) In an embodiment, the context may include the following:

[0202] 1) The programming target of the cell, which can be expressed as t cell

[0203] 2) The target of the two neighboring memory cells of the cell, which can be expressed as

[0204] 3) The SSL index of the memory cell, which can be expressed as ssl∈[N ssls], and the WI index of the memory cell, which can be expressed as wl∈[N wls ]

[0205] By including T neighbors As part of the context of the memory cell, the channel generator 1303 can be trained to model ICI as described above. This can then allow the modulator 1301 to be trained to select different threshold voltage targets t for different memory cells based on their neighbors, and thus perform pre-distortion to address the ICI phenomenon. The SSL index and WL index can be used to learn the behavior of different parts of the block. Based on the above representation, the GAN objective can be formulated as learning to generate according to the following equation 13 A sample of:

[0206]

[0207] like Fig.14 As further shown in FIG. 1 , the threshold voltage v th The read may be provided to discriminator 1402, which may correspond to the discriminator or critic described above. In an embodiment, the discriminator may receive the generated threshold voltage v from channel generator 1303. th Reads, and real reads may be received from the read DB 1401 , and the output of the discriminator 1402 may be used to train the channel generator 1303 .

[0208] An example of a model specification is provided in Table 4 below.

[0209] [Table 4]

[0210] parameter value Learning Rate <![CDATA[5·10 -5 ]]> Batch size 20000 Generator hidden layer size [128,64,64,16] Generator condition input size 5 Generator nz 1 Generator output layer size 1 Generator Activation tanh Critic hidden layer size [128,128,64,64,16] Critics input layer size 6 Critic output layer size 1 critic activation ReLU

[0211] return Fig.13 According to an embodiment, the modulator function corresponding to the modulator 1301 is It can be expressed according to the following equation 13:

[0212]

[0213] For example, considering the context c∈C of the target memory cell, the modulator 1301 may use the modulator function To map an information level l∈[L] to a threshold voltage target t to be programmed into a memory cell. According to an embodiment, the information level l may correspond to a data symbol. The context c may be provided by adjacent information levels l to be programmed into adjacent memory cells along the string according to the SSL index (which may be referred to as the string index) and the WL index of the target memory cell, and may be expressed according to the following equation 14:

[0214] C=[L]×[L]×[N ssls ]×[N wls Equation 14

[0215] According to an embodiment, the demodulator function corresponding to the demodulator 1304 is According to the following

[0216] Formula 15 indicates:

[0217]

[0218] For example, the demodulator 1304 may receive a threshold voltage v from the channel generator 1303. th The programmed information level l is read and reconstructed by learning the log-likelihood ratio (LLR) of each information level l, which may correspond to recovering the programmed data symbol.

[0219] According to an embodiment, the demodulator 1304 may not take into account the reading of adjacent memory cells. Therefore, according to an embodiment, the data of adjacent memory cells may be utilized in the modulation stage, and thus the modulator 1301 may be used to perform pre-distortion to address ICI. This also ensures that a memory device (e.g., memory device 300) using the modulator 1301 may not require any changes to the current read algorithm to read data programmed using the modulator 1301. In an embodiment, the SSL index and the WL index may be used as inputs to both the modulator 1301 and the demodulator 1304 to select the optimal threshold voltage target t for each portion of the memory block based on the physical differences between them. Both the modulator 1301 and the demodulator 1304 may be represented by a NN. In addition, both the modulator 1301 and the demodulator 1304 may be multilayer perceptrons (MLPs), which may mean that they are constructed as a series of fully connected layers, each followed by a non-linearity. Examples of the number of layers and non-linearity types are given in Table 5 below.

[0220] [Table 5]

[0221] parameter value Learning Rate <![CDATA[5·10 -5 ]]> Batch size 5000 Modulator hidden layer size [128,128,64] Modulator input layer size 5 Modulator output layer size 1 Modulator Activation ReLU Demodulator hidden layer size [128,128,64] Demodulator input layer size 3 Demodulator output layer size 1 Demodulator Activation ReLU

[0222] In an embodiment, the nonlinearity of the output layer of the modulator 1301 can be a hyperbolic tangent function tanh, which can force the output of the modulator to be in the range (-1, 1). The output can then be scaled back to the dynamic range of the memory unit (v min ,v max ). Thus, the modulator 1301 can be forced to select only threshold voltage targets t that are feasible for programming.

[0223] The overall training process for the modulator 1301 can be divided into two steps, which can include a first training step of training the channel generator 1303, and a second training step of jointly training the modulator 1301 and the demodulator 1304. In the first training step, the channel generator 1303 can be trained using conventional Wasserstein loss and GP loss, which can ensure that the learned critic function is 1-Liphshitz, as described above. The training data set can be, for example, the threshold voltage v of a single block programmed with a certain set of threshold voltage targets t (which can be stored in the read DB 1401). th Read. In an embodiment, the training data set may be estimated by performing a series of programming verification operations at 20mV resolution over the dynamic range of the memory cell, and the threshold voltage target t may include, for example, a set of 15 threshold voltage targets t that are evenly spread over the dynamic range of the memory cell. At the end of the first training step, a NN for the channel generator 1303 and a NN for the discriminator 1402 may be obtained. In an embodiment, the discriminator 1402 may not be used for any further training or programming operations. The second training step may include joint training of the modulator 1301 and the demodulator 1304, which may be performed using a pre-trained frozen channel generator 1303.

[0224] Fig.15 An example of a training algorithm that can be used to perform the second training step according to an embodiment is shown. In an embodiment, Algorithm 2 may describe a training epoch that may be used to train the modulator 1301. At each iteration, a batch of B samples b∈[L]×C may be taken as input x M Provided to the modulator 1301, the modulator 1301 can generate a threshold voltage target t for each sample. At this time, the threshold voltage target t can be used for each memory cell, but the threshold voltage target t of the adjacent memory cell can be obtained to generate the input x of the channel generator 1303 G In an embodiment, the threshold voltage target t of the adjacent memory cell can be based on the dynamic range [v min ,v max Then, the threshold voltage target t can be selected by the channel generator 1303 to simulate the threshold voltage v corresponding to the input data. th Finally, the demodulator 1304 can be used to generate a voltage at a given analog threshold voltage v thThe original level is predicted with the SSL and WL index of the memory cell. The CE loss between the recovered level and the input level can be used as the training loss as described above. Since the demodulator can be trained to learn the recovered level LLR, the training loss can be expressed according to the following equation 17:

[0225]

[0226] In Equation 17, N may represent the batch size, L may represent the number of levels, and TL i can represent the true level of the i-th sample, and The output of the demodulator 1304 for the i-th sample may be represented as . Examples of training parameters for two steps are provided in Tables 4 and 5 above, including batch sizes and learning rates for all NNs.

[0227] At the end of the second training step, a NN for the modulator 1301 and a NN for the demodulator 1304 may be obtained. In an embodiment, the demodulator 1304 may not be used for any further training or programming operations. In an embodiment, the trained modulator 1301 may be used to convert a block of data symbols into a block that can be programmed to a threshold voltage target t of a memory cell. However, in an embodiment, programming all values ​​of the threshold voltage target t suggested by the modulator 1301 may not be feasible for some programming schemes (e.g., Algorithm 1 discussed above) due to programming time constraints. For example, the number of possible output values ​​of the modulator 1301 may be equal to the number of possible input values, and therefore may be significantly greater than the number of data symbols. For example, for a QLC modulation with 15 possible symbols and two "other features" that may be the values ​​of adjacent data symbols to be programmed in adjacent memory cells (e.g., 16*16=256 possible values ​​for the other features for each level), there may be a total of 256*15=3840 possible input values, and therefore, for each WL, there are also 3840 possible threshold voltage target t values ​​at the output of the modulator 1301. Thus, several techniques may be used to modify the output of the modulator 1301 for programming memory cells, depending on the embodiment.

[0228] According to a first technique, the output of modulator 1301 can be quantized before it is used to program the memory cell. This technique can significantly reduce the amount of programming targets for each WL. As an example, quantization can be performed by clustering the set of targets generated by modulator 1301 for each WL into 60 groups, but the embodiment is not limited thereto. For example, a Gaussian mixture model (GMM) with 60 components can be fitted and the component means can be used as the set of quantized targets. The threshold voltage target t is clustered by assigning the threshold voltage target t for the memory cell output from the modulator 1301 to the GMM component and then using the mean of the component as the quantized threshold voltage target Each memory cell of WL may be assigned a quantized threshold voltage target t q Due to the nature of the expectation–maximization (EM) algorithm used to fit the GMM, a different target amount may be selected for each level l (e.g., l∈16). In an embodiment, the output of the modulator 1301 may be quantized to 60 programming targets after considerations based on WL programming time and quantization loss. Fig.16 An example of the gain in BER improvement due to the use of quantization is shown as a function of the number of quantization levels. Fig.16 As can be seen in , programming 60 targets (which may be equivalent to approximately four threshold voltage targets per level t) may preserve most of the model gain.

[0229] According to a second technique, a shared pulse incremental pulse programming scheme may be used, which may enable programming of multiple relatively close threshold voltage targets t using a shared pulse mechanism. Fig.17 An example of a shared pulse ISPP algorithm that can be used to program WLs is shown. In an embodiment, Algorithm 3 may represent a shared pulse ISPP algorithm that may be performed by any element discussed herein (e.g., memory device 300 or any element thereof). After performing quantization, for example, a set of quantized threshold voltage targets t may be obtained for each WL. q For example, 60 programming targets are obtained for each WL, where the target of each memory cell can be determined based on the level corresponding to the memory cell and the level of the adjacent memory cell. Fig.10The ISPP programming discussed, the shared pulse ISPP can use an incremental step pulse programming scheme for each level. In order to distinguish cells with the same level but different threshold voltage targets t, according to the shared pulse ISPP scheme of Algorithm 3, a memory device (such as memory device 300) can perform an additional programming verification operation after each pulse, for example, one programming verification operation for each threshold voltage target t. Therefore, if the quantization discussed above results in four threshold voltage targets t being assigned for a certain level, the memory device can perform four programming verification operations after each pulse. According to an embodiment, pulses can be shared between threshold voltage targets t of memory cells of the same level, and thus the shared pulse ISPP scheme of Algorithm 3 may not result in an increase in the amount of pulses required for each WL. In addition, compared to a single programming verification operation, performing the programming verification operations with different (but close) v verify Multiple program-verify operations of a value may impose only a small overhead cost in terms of latency, which may make Algorithm 3 practical to implement.

[0230] Depending on the embodiment, one or both of the above techniques may be used to program multiple threshold voltage targets t that may be learned by the modulator 1301 for each WL while maintaining a reasonable programming time.

[0231] 18A to 18C , FIG. 19A to FIG. 19C and Figure 20 to Figure 21 13 is a diagram showing results obtained from an experiment performed using an example of the channel generator 1303 and the modulator 1301 according to the embodiment.

[0232] As discussed above, modulator 1301 can be used to extend the EOL operating point of the flash chip in terms of PE cycles and data retention time. Therefore, experiments were conducted at an operating point of 2500 PE cycles and a storage duration of one month since the last programming cycle, as simulated using a heating oven according to the Arrhenius law as described above.

[0233] To evaluate an example of channel generator 1303, a single block of v programmed with 15 linearly scattered targets within the dynamic range is th The training is performed by reading. The trained examples of the channel generator 1303 are then evaluated on a test set consisting of 6 blocks. In each test block, for Δ in {15, 30, 45, 60, 75, 90}, the original targets are modified by offsetting all target threshold voltages according to Table 6 below.

[0234] [Table 6]

[0235]

[0236] Three metrics are then used to evaluate the performance of the example of channel generator 1303:

[0237] 1) Histogram: Compare the histogram generated by the example of channel generator 1303 with the histogram we measured on the real chip

[0238] 2) Wasserstein distance: Compare the mean 1-Wasserstein distance of each programming level between the generated distribution and the true data distribution

[0239] 3) Average BER: Compare the true BER and the generated BER for each WL in the block.

[0240] As in Fig.18A As can be seen in the example of channel generator 1303, a very realistic threshold voltage v th Histogram. As in Fig.18A As can be seen in , the example of channel generator 1303 generates WL data with a BER of up to 5% error compared to the real measured data. th A Wasserstein distance of approximately 8mV was measured between the histogram and the generated histogram. In particular, the Wasserstein distance between each level was measured separately and the results were averaged. For context, a Wasserstein distance of 8mV may be equal to the distance between two normal distributions with the same standard deviation and a mean difference of 8mV.

[0241] Fig.18B and Fig.18C shows the warp offset v th Histogram predictions. In particular, Fig.18B shows a predicted threshold voltage shift of 45mV, Fig.18C shows a predicted threshold voltage shift of 90 mV. Figures 18A-18C As can be seen in , the example of channel generator 1303 generates true histograms for the training data and the offset target data, which were not seen during training.

[0242] FIG. 19A to FIG. 19C A comparison of the true BER measured on the QLC block with the BER predicted by an example of the channel generator 1303 given a shifted target is shown. Again, for most of the tested blocks, the BER predictions are very good, up to 5% error. This allows the trained channel generator 1303 to be used for optimization of the modulator 1301.

[0243] After training the instance of channel generator 1303, its weights are fixed and it is used to train the instance of modulator 1301 using training architecture 1300. The learned target is then quantized and used to program the memory block as described above. Table 7 summarizes the performance of the model in terms of average block BER.

[0244] [Table 7]

[0245]

[0246] As can be seen above, the voltage threshold target t produced by the example of modulator 1301 results in a significant BER improvement compared to the baseline target, and the output BER of the system is also accurately predicted by passing the voltage threshold target t through the example of channel generator 1303, generating a histogram, and then calculating the error rate.

[0247] Fig. 20 1 is a diagram showing an example of a learned pulse amplitude modulation (PAM) constellation diagram compared to an original constellation diagram. The first row presents the original voltage threshold target t for WL of the example used to train the channel generator 1303. The second row shows the voltage threshold target t output by the example of the modulator 1301. The third row shows the learned voltage threshold target t for level 1, and the fourth row shows the quantized voltage threshold target t corresponding to the voltage threshold target t of row 3. q As in Figures 18A-18C As can be seen in , the example of modulator 1301 selects to space higher levels apart. For example, the target for level 14 is left-shifted compared to the original level target. The example of modulator 1301 selects a lower target for memory cells with higher sign neighbors. This can allow memory cells with high sign neighbors to lose less voltage over time, and therefore can prevent or reduce ICI. In addition, Fig. 20 The quantization process is shown to produce approximately four targets for each programming level, which totals 60 targets for the entire WL.

[0248] Fig.21 is a diagram illustrating an example of the performance of programming a memory cell using a target generated by an example of modulator 1301, according to an embodiment. In particular, Fig.21 An example of training the modulator 1301 at 3 different PE cycle points and measuring the results of how many PE cycles are added until the original BER is returned. Fig.21 As can be seen, programming the memory block using the voltage threshold target t produced by the example of modulator 1301 allows the memory block to be used for approximately 600 additional PE cycles while maintaining the same BER.

[0249] Thus, embodiments relate to pre-distortion programming of flash memory devices to prevent errors caused by interference between adjacent memory cells in a memory block. Embodiments also relate to pre-distortion programming of a flash memory device by performing end-to-end training of a modulator and demodulator of a channel using a pre-trained channel model. th For example, embodiments relate to a cWGAN-based NAND channel model, an autoencoder-based modulator, and a shared pulse ISPP programming scheme. The cWGAN channel model can allow accurate estimation of a voltage threshold v of a memory cell based on a voltage threshold target t received by a received programming algorithm. th Distribution. A channel model according to an embodiment can interpolate the targets seen during the training phase, allowing for voltage thresholds v outside a given target sample set to be th The neural modulator according to the embodiment can learn the optimal v based on the learned channel function. th Target constellation. According to an embodiment, programming the learned target constellation can result in a significant BER reduction, e.g., about 22%, compared to the previous 15 linearly spaced targets. Thus, programming the memory block with the target learned by the modulator 1301 can extend the life of the memory block by about 600 PE cycles at the measured EOL operating point. Furthermore, the shared pulse ISPP programming scheme according to an embodiment can achieve efficient programming of multiple targets learned by the neuromodulator, making the embodiment feasible for competitive industrial products.

[0250] Fig. 22 is a flow chart of a process 2200 for controlling a storage device according to an embodiment. In some embodiments, Fig. 22 One or more processing blocks of may be performed by any of the elements discussed above, such as one or more of the memory device 300, the modulator 1301, the channel generator 1303, the training architecture 1300, the training architecture 1400, and any elements included therein.

[0251] like Fig. 22 As shown in , at operation 2201, process 2200 may include obtaining a plurality of data symbols.

[0252] like Fig. 22 As further shown in FIG. 22, at operation 2202, process 2200 may include providing the plurality of data symbols to a neural network. In an embodiment, the neural network may correspond to modulator 1301 discussed above.

[0253] like Fig. 22 As further shown in FIG. 22 , at operation 2203 , process 2200 may include obtaining a plurality of threshold voltage targets based on outputs of the neural network.

[0254] like Fig. 22 As further shown in FIG. 22, at operation 2204, process 2200 may include programming a plurality of data symbols to a plurality of memory cells included in a storage device based on a plurality of threshold voltage targets.

[0255] In an embodiment, each of the plurality of threshold voltage targets may correspond to a memory cell of the plurality of memory cells and may be determined based on a data symbol corresponding to the memory cell and at least one adjacent data symbol corresponding to at least one adjacent memory cell.

[0256] In an embodiment, the neural network may include a modulator, and the modulator may be trained using a first training architecture including a modulator, a channel generator, and a demodulator. In an embodiment, the first training architecture may correspond to training architecture 1300, the modulator may correspond to modulator 1301, the channel generator may correspond to channel generator 1303, and the demodulator may correspond to demodulator 1304.

[0257] In an embodiment, the channel generator may be trained using a second training architecture to simulate a cycle including a programming operation, a data retention operation, and a read operation. In an embodiment, the second training architecture may correspond to the training architecture 1400.

[0258] In an embodiment, at least one of the first training architecture and the second training architecture may include an end-to-end conditional Wasserstein generative adversarial network (cWGAN).

[0259] In an embodiment, process 2200 may further include quantizing the plurality of threshold voltage targets prior to programming the plurality of data symbols to the plurality of memory cells.

[0260] In an embodiment, multiple data symbols may be programmed to multiple memory cells using incremental step pulse programming.

[0261] In an embodiment, programming may further include performing a plurality of program verification operations for each program pulse included in the incremental step pulse programming.

[0262] although Fig. 22 An example block diagram of process 2200 is shown, but in some implementations, process 2200 may include Fig.11 The process 2200 may include more boxes, fewer boxes, different boxes, or boxes arranged differently than those boxes depicted in the process 2200. Additionally or alternatively, two or more boxes in the boxes of process 2200 may be arranged or combined in any order, or executed in parallel.

[0263] Fig.23 is a diagram of a data center 3000 to which a memory device is applied according to an embodiment.

[0264] refer to Fig.23 , the data center 3000 may be a facility that collects various types of data and provides services, and is referred to as a data storage center. The data center 3000 may be a system for operating a search engine and a database, and may be a computing system used by a company (such as a bank) or a government agency. The data center 3000 may include application servers 3100 to 3100n and storage servers 3200 to 3200m. According to an embodiment, the number of applications 3100 to 3100n and the number of storage servers 3200 to 3200m may be selected differently. The number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m may be different from each other.

[0265] The application server 3100 or the storage server 3200 may include at least one of the processors 3110 and 3210 and the memories 3120 and 3220. Now, the storage server 3200 will be described as an example. The processor 3210 may control all operations of the storage server 3200, access the memory 3220, and execute instructions and / or data loaded into the memory 3220. The memory 3220 may be a double data rate synchronous DRAM (DDR SDRAM), a high bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an Optane DIMM (Optane DIMM) and / or a non-volatile DIMM (NVMDIMM). In some embodiments, the number of processors 3210 and memories 3220 included in the storage server 3200 may be selected differently. In an embodiment, the processor 3210 and the memory 3220 may provide a processor-memory pair. In an embodiment, the number of processors 3210 and the number of memories 3220 may be different from each other. The processor 3210 may include a single-core processor or a multi-core processor. The above description of the storage server 3200 may be similarly applied to the application server 3100. In some embodiments, the application server 3100 may not include the storage device 3150. The storage server 3200 may include at least one storage device 3250. According to embodiments, the number of storage devices 3250 included in the storage server 3200 may be variously selected.

[0266] The application servers 3100 to 3100n can communicate with the storage servers 3200 to 3200m through the network 3300. The network 3300 can be implemented by using Fibre Channel (FC) or Ethernet. In this case, FC can be a medium for relatively high-speed data transmission, and an optical switch with high performance and high availability can be used. According to the access method of the network 3300, the storage servers 3200 to 3200m can be set to file storage, block storage, or object storage.

[0267] In an embodiment, the network 3300 may be a storage-specific network, such as a storage area network (SAN). For example, the SAN may be an FC-SAN, which uses an FC network and is implemented according to the FC protocol (FCP). As another example, the SAN may be an Internet Protocol (IP)-SAN, which uses a transmission control protocol (TCP) / IP network and is implemented according to the SCSI or Internet SCSI (iSCSI) protocol over TCP / IP. In another embodiment, the network 3300 may be a general-purpose network, such as a TCP / IP network. For example, the network 3300 may be implemented according to protocols such as FC over Ethernet (FCoE), network attached storage (NAS), and NVMe over fabric (NVMe-oF).

[0268] Hereinafter, the application server 3100 and the storage server 3200 will be mainly described. The description of the application server 3100 may be applied to another application server 3100n, and the description of the storage server 3200 may be applied to another storage server 3200m.

[0269] The application server 3100 may store data requested to be stored by a user or client in one of the storage servers 3200 to 3200m through the network 3300. In addition, the application server 3100 may obtain data requested to be read by a user or client from one of the storage servers 3200 to 3200m through the network 3300. For example, the application server 3100 may be implemented as a network server or a database management system (DBMS).

[0270] The application server 3100 may access a memory 3120n or a storage device 3150n included in another application server 3100n through the network 3300. Alternatively, the application server 3100 may access a memory 3220 to 3220m or a storage device 3250 to 3250m included in the storage servers 3200 to 3200m through the network 3300. Therefore, the application server 3100 may perform various operations on the data stored in the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. For example, the application server 3100 may execute an instruction for moving or copying data between the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. In this case, data may be moved from the storage devices 3250 to 3250m of the storage servers 3200 to 3200m through the storage 3220 to 3220m of the storage servers 3200 to 3200m or directly to the storage 3120 to 3120n of the application servers 3100 to 3100n. The data moved through the network 3300 may be data encrypted for security or privacy.

[0271] The storage server 3200 will now be described as an example. The interface 3254 can provide a physical connection between the processor 3210 and the controller 3251 and a physical connection between the network interface card (NIC) 3240 and the controller 3251. For example, the interface 3254 can be implemented using a direct attached storage (DAS) solution, where the storage device 3250 is directly connected to a dedicated cable. For example, the interface 3254 can be implemented using various interface solutions (such as ATA, SATA, e-SATA, SCSI, SAS, PCI, PCIe, NVMe, IEEE 1394, USB interface, SD card interface, MMC interface, eMMC interface, UFS interface, eUFS interface and / or CF card interface).

[0272] The storage server 3200 may further include a switch 3230 and a network interconnect (NIC) 3240. The switch 3230 may selectively connect the processor 3210 to the storage device 3250 or selectively connect the NIC 3240 to the storage device 3250 via the control of the processor 3210.

[0273] In an embodiment, the NIC 3240 may include a network interface card and a network adapter. The NIC 3240 may be connected to the network 3300 through a wired interface, a wireless interface, a Bluetooth interface, or an optical interface. The NIC 3240 may include an internal memory, a digital signal processor (DSP), and a host bus interface, and is connected to the processor 3210 and / or the switch 3230 through the host bus interface. The host bus interface may be implemented as one of the above examples of the interface 3254. In an embodiment, the NIC 3240 may be integrated with at least one of the processor 3210, the switch 3230, and the storage device 3250.

[0274] In the storage servers 3200 to 3200m or the application servers 3100 to 3100n, the processor may send a command to the storage devices 3150 to 3150n and 3250 to 3250m or the memories 3120 to 3120n and 3220 to 3220m and program or read the data. In this case, the data may be data in which an error has been corrected by an ECC engine. The data may be data on which a data bus inversion (DBI) operation or a data masking (DM) operation has been performed, and may include cyclic redundancy code (CRC) information. The data may be data encrypted for security or privacy.

[0275] The storage devices 3150 to 3150n and 3250 to 3250m may send control signals and command / address signals to the NAND flash memory devices 3252 to 3252m in response to a read command received from the processor. Therefore, when data is read from the NAND flash memory devices 3252 to 3252m, a read enable (RE) signal may be input as a data output control signal, and thus, the data may be output to the DQ bus. The data strobe signal DQS may be generated using the RE signal. The command and address signals may be latched in the page buffer depending on the rising edge or falling edge of the write enable (WE) signal.

[0276] The controller 3251 may control all operations of the storage device 3250. In an embodiment, the controller 3251 may include an SRAM. The controller 3251 may write data to the NAND flash memory device 3252 in response to a write command, or read data from the NAND flash memory device 3252 in response to a read command. For example, a write command and / or a read command may be provided from a processor 3210 of the storage server 3200, a processor 3210m of another storage server 3200m, or processors 3110 and 3110n of application servers 3100 and 3100n. The DRAM 3253 may temporarily store (or buffer) data to be written to the NAND flash memory device 3252 or data to be read from the NAND flash memory device 3252. In addition, the DRAM 3253 may store metadata. Here, the metadata may be user data or data generated by the controller 3251 for managing the NAND flash memory device 3252. The storage device 3250 may include a secure element (SE) for security or privacy.

[0277] As traditional in the art, the embodiment is described and shown in the accompanying drawings in the form of functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques). In the case where blocks, units and / or modules are implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. Alternatively, each block, unit and / or module can be implemented by dedicated hardware or implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and associated circuits) for performing other functions. In addition, without departing from the scope, each block, unit and / or module of the embodiment can be physically divided into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of the embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope.

[0278] The various operations of the above-described methods may be performed by any suitable units capable of performing these operations (such as various hardware and / or software components, circuits and / or modules).

[0279] Software may include an ordered listing of executable instructions for implementing logical functions and may be embodied in any "processor readable medium" for use by or in conjunction with an instruction execution system, device or apparatus (such as a single-core or multi-core processor or a system containing a processor).

[0280] The blocks or steps of the methods or algorithms and functions described in conjunction with the embodiments disclosed herein may be directly embodied in hardware, in a software module executed by a processor, or in a combination of the two. If implemented in software, the functions may be stored as one or more instructions or codes on or transmitted through a tangible, non-transitory computer-readable medium. The software module may reside in a random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CDROMs, or any other form of storage medium known in the art.

[0281] The foregoing is illustrative of certain embodiments and should not be construed as limiting thereof. Although several embodiments have been described, those skilled in the art will readily appreciate that various modifications may be made in the embodiments without materially departing from the scope of the present disclosure.

Claims

1. A storage system, comprising: A storage device comprising a plurality of memory cells; as well as At least one processor configured to: obtaining a plurality of data symbols; providing the plurality of data symbols to a neural network; obtaining a plurality of threshold voltage targets based on outputs of the neural network; as well as The plurality of data symbols are programmed to the plurality of memory cells based on the plurality of threshold voltage targets.

2. The storage system according to claim 1, wherein: Each threshold voltage target of the plurality of threshold voltage targets corresponds to a memory cell of the plurality of memory cells and is determined based on a data symbol corresponding to the memory cell and at least one adjacent data symbol corresponding to at least one adjacent memory cell.

3. The storage system of claim 1 , wherein the neural network comprises a modulator, and in, The modulator is trained using a first training framework including the modulator, a channel generator, and a demodulator.

4. The storage system according to claim 3, wherein: The channel generator is trained using a second training framework to simulate a cycle including a programming operation, a data retention operation, and a read operation.

5. The storage system according to claim 4, wherein: At least one of the first training architecture and the second training architecture comprises an end-to-end conditional Wasserstein generative adversarial network (cWGAN).

6. The storage system according to claim 1, wherein: The at least one processor is further configured to quantize the plurality of threshold voltage targets prior to programming the plurality of data symbols to the plurality of memory cells.

7. The storage system according to claim 1, wherein: The at least one processor is further configured to program the plurality of data symbols to the plurality of memory cells using incremental step pulse programming.

8. The storage system according to claim 7, wherein: The at least one processor is further configured to perform a plurality of program verification operations for each programming pulse included in the incremental step pulse programming.

9. An apparatus for programming a plurality of memory cells, the apparatus comprising: At least one processor configured to: obtaining a plurality of data symbols; obtaining a plurality of threshold voltage targets by providing the plurality of data symbols to a neural network, wherein each threshold voltage target of the plurality of threshold voltage targets corresponds to a memory cell of the plurality of memory cells and is determined based on the data symbol corresponding to the memory cell and at least one adjacent data symbol corresponding to at least one adjacent memory cell; as well as The plurality of data symbols are programmed to the plurality of memory cells based on the plurality of threshold voltage targets.

10. The device according to claim 9, wherein: The neural network includes a modulator, and The modulator is trained using a first training architecture including the modulator, a channel generator, and a demodulator.

11. The device according to claim 10, wherein: The channel generator is trained using a second training framework to simulate a cycle including a programming operation, a data retention operation, and a read operation.

12. The device according to claim 11, wherein At least one of the first training architecture and the second training architecture comprises an end-to-end conditional Wasserstein generative adversarial network (cWGAN).

13. The device according to claim 9, wherein: The at least one processor is further configured to quantize the plurality of threshold voltage targets prior to programming the plurality of data symbols to the plurality of memory cells.

14. The device according to claim 9, wherein: The at least one processor is further configured to program the plurality of data symbols to the plurality of memory cells using incremental step pulse programming.

15. The device according to claim 14, wherein: The at least one processor is further configured to perform a plurality of program verification operations for each programming pulse included in the incremental step pulse programming.

16. A method of controlling a storage system, the method being executed by at least one processor and comprising: obtaining a plurality of data symbols; providing the plurality of data symbols to a neural network; obtaining a plurality of threshold voltage targets based on outputs of the neural network; as well as The plurality of data symbols are programmed to a plurality of memory cells included in a storage device based on the plurality of threshold voltage targets.

17. The method according to claim 16, wherein: Each threshold voltage target of the plurality of threshold voltage targets corresponds to a memory cell of the plurality of memory cells and is determined based on a data symbol corresponding to the memory cell and at least one adjacent data symbol corresponding to at least one adjacent memory cell.

18. The method according to claim 16, further comprising: Prior to programming the plurality of data symbols to the plurality of memory cells, the plurality of threshold voltage targets are quantized.

19. The storage system according to claim 16, wherein: The plurality of data symbols are programmed to the plurality of memory cells using incremental step pulse programming.

20. The storage system according to claim 19, wherein: The programming further includes performing a plurality of program verification operations for each programming pulse included in the incremental step pulse programming.

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