Performance analysis system and analysis method of memory

Abstract

The invention provides a memory performance analysis system and analysis method, and the system comprises a test board which is connected with a memory and a logic analyzer, and is in communication connection with a flash memory interface of the memory; the processing module is arranged on the test board and is in communication connection with the storage interface of the memory; the host is in communication connection with the processing module and the logic analyzer, and the host is used for issuing different test instructions to the memory through the processing module, so that the memory executes different operations; wherein the logic analyzer is used for acquiring an instruction stream and response data which are sent to the flash memory interface by firmware when the memories execute different operations, uploading the instruction stream and the response data to the host, and performing performance analysis on different memories. According to the performance analysis system and analysis method for the memories, the difference of firmware of different memories can be analyzed, so that the performance of the firmware is improved.

Description

Technical Field

[0001] The present invention relates to the field of storage, and in particular to a performance analysis system and analysis method for a storage device. Background Art

[0002] Memory is widely used in terminal devices such as mobile phones, tablets, TVs, and set-top boxes. There are many memory manufacturers on the market. Different manufacturers design different firmware for memory. The quality of the firmware directly affects the performance of the memory. How to quickly analyze the differences in firmware of memory produced by different manufacturers to improve the performance of the firmware is a problem that needs to be solved urgently. Summary of the invention

[0003] The object of the present invention is to provide a memory performance analysis system and analysis method, which can analyze the differences of memory firmware to improve the performance of the firmware.

[0004] To solve the above technical problems, the present invention is achieved through the following technical solutions: The present invention provides a memory performance analysis system, comprising: A test board, on which a memory is connected, wherein a plurality of detection pins are set on the test board, and the detection pins are communicatively connected with the test pins of the memory; A logic analyzer is communicatively connected to the flash memory interface of the memory through the detection pin; a processing module, disposed on the test board and communicatively connected to the storage interface of the memory; and A host, which is in communication with the processing module and the logic analyzer, and is used to send different test instructions to the memory through the processing module so that the memory performs different operations; The logic analyzer is used to obtain the instruction stream and response data sent by the firmware of the memory to the flash memory interface when the memory performs different operations, upload the instruction stream and response data to the host, and perform performance analysis on different memories.

[0005] In one embodiment of the present invention, the host is further used to send initialization instructions to the multiple memories respectively, so as to obtain the instruction streams and corresponding boot-up durations of the internal firmware of the multiple memories when the memories perform initialization operations.

[0006] In one embodiment of the present invention, the host is also used to compare and analyze the instruction stream of the memory with the shortest boot time with the instruction stream of other memories, so as to optimize the firmware from the direction of reducing unknown commands, adopting a more efficient storage mode and optimizing the data reading method.

[0007] In one embodiment of the present invention, the host is also used to send multi-page read instructions and single-page read instructions to multiple memories respectively to obtain the instruction flow and corresponding read performance value of the internal firmware of the multiple memories when performing multi-page read operations and single-page read operations.

[0008] In one embodiment of the present invention, the host is also used to compare and analyze the instruction stream of the memory with the best read performance value with the instruction stream of other memories, so as to optimize the firmware from the direction of reducing unknown commands, adopting a more efficient storage mode, optimizing data access methods, and utilizing cache and prefetch mechanisms.

[0009] In one embodiment of the present invention, the host is also used to send multi-page write instructions and single-page write instructions to multiple memories respectively to obtain the instruction flow and corresponding write performance value of the internal firmware of the multiple memories when performing multi-page write operations and single-page write operations.

[0010] In one embodiment of the present invention, the host is also used to compare and analyze the instruction stream of the memory with the best write performance value with the instruction stream of other memories, so as to optimize the firmware from the direction of reducing unknown commands, optimizing the write process to reduce read and erase operations, adopting a more efficient storage mode, and optimizing the data write strategy to reduce the number of programming times.

[0011] In one embodiment of the present invention, the host is also used to send partial erase instructions and full erase instructions to multiple memories respectively to obtain the instruction streams and corresponding erase performance values ​​of the internal firmware of the multiple memories when executing partial erase operations and full erase operations. The host is also used to compare and analyze the instruction stream of the memory with the best erase performance value with the instruction streams of other memories to optimize the firmware.

[0012] In one embodiment of the present invention, the host is also used to send queue instructions to multiple memories respectively to obtain the instruction execution order and execution time of the multiple memories when performing queue operations. The host is also used to compare and analyze the instruction execution order of the memory with the shortest execution time with the instruction execution order of other memories to optimize the firmware.

[0013] The present invention also provides a memory performance analysis method comprising: Build a test environment for storage; Sending different test instructions to the memory so that the memory performs different operations; Acquire the instruction stream and response data sent by the firmware of the memory to the flash memory interface when the memory performs different operations; The instruction stream and response data are uploaded and performance analyzed.

[0014] As described above, the present invention provides a memory performance analysis system and analysis method, which can analyze and identify the behavior differences of firmware by monitoring the execution status of the NAND Interface of different memories, and can quickly locate and analyze the differential behaviors of firmware of different storage manufacturers. By analyzing the differential behaviors of firmware, it is possible to identify deficiencies in the firmware, improve the overall system performance, and quickly take optimization measures to improve the overall system performance.

[0015] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for describing the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A schematic diagram of a performance analysis system for a memory according to an embodiment of the present invention; Figure 2 FIG. 4 is a flow chart of a method for analyzing memory performance according to an embodiment of the present invention.

[0018] In the figure: 100, test board; 200, processing module; 300, detection pin; 400, logic analyzer; 500, host; 600, power module; 700, transmission module; 800, interface module; 900, memory module; 1000, storage. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] See also Figure 1The present invention provides a memory test system, which can analyze the performance of memories produced by different manufacturers, so as to quickly analyze the differences in the firmware of memories produced by different manufacturers, and improve the firmware of the memories according to the differences. The test system may include a test board 100, a processing module 200 (CPU), a detection pin 300 (TPx), a logic analyzer 400, a host 500, a power module 600 (POWER), a transmission module 700 (USB), an interface module 800 (UART) and a memory module 900 (DRAM).

[0021] In one embodiment, the test board 100 may be a printed circuit board (PCB), on which the processing module 200 , the detection pin 300 , the power module 600 , the transmission module 700 , the interface module 800 and the memory module 900 may be integrated.

[0022] In one embodiment, the processing module 200 may be responsible for executing instructions in a computer program and controlling other hardware devices to work in coordination. The processing module 200 may acquire instructions, decode instructions, and execute instructions to complete its main functions.

[0023] In one embodiment, the detection pin 300 may be a test point on the test board 100. The number of the detection pins 300 may be the same as the number of signal channels of the flash memory interface (NAND Interface) of the memory 1000. For example, the number of signal channels of the flash memory interface inside the memory 1000 is 26. At this time, the number of the detection pins 300 is also 26, which are divided into TP1~TP26 according to the sequence number. Each detection pin 300 can be connected to a corresponding signal channel of the flash memory interface of the memory 1000.

[0024] Among them, the signal channel of the flash memory interface of the memory 1000 refers to the protocol and signal channel used inside the memory 1000 to communicate with the NAND flash memory. The signal channel of the flash memory interface of the memory 1000 processes data operations inside the memory 1000, such as reading, writing and erasing. The signals and protocols of the flash memory interface may include an instruction bus, an address bus, a data bus, a control signal, etc. The instruction bus can be used to send instructions to the NAND flash memory, such as operations such as reading, writing, and erasing. The instruction bus usually includes a group of instruction lines for transmitting specific operation instructions. The address bus can be used to transmit the address information of the data so that the NAND flash memory knows the location of the data to be operated. The data bus can be used for actual data transmission. The data bus is usually used in conjunction with the instruction bus and the address bus to transmit the stored data. The control signal may include a write enable (WE), a read enable (RE) and other signals for controlling the operating state of the NAND flash memory.

[0025] In one embodiment, a logic analyzer 400 (LA) is a tool for capturing and analyzing digital signals. The logic analyzer 400 can be electrically connected to a plurality of detection pins 300 on a test board 100, and can monitor and record the timing waveform of the NAND Interface of the memory 1000. The logic analyzer 400 can not only capture the signals of the NAND Interface of the memory 1000, but also analyze the relationship between the signals, thereby analyzing the protocol behavior of the memory 1000. For example, the read and write operations of the data bus, the address selection of the address bus, and the enable and disable of the control signal can be analyzed.

[0026] In one embodiment, the logic analyzer 400 may also be connected to the storage interface (eMMC Interface) between the memory 1000 and the processing module 200 to obtain various instructions and data sent by the processing module 200 to the memory 1000. The eMMC Interface is a protocol and signal channel for communication between the memory 1000 and the processing module 200.

[0027] Among them, the eMMC Interface can be responsible for processing external instructions and data requests to ensure that the data transmission between the processing module 200 and the memory 1000 is correct. It processes the instructions sent by the processing module 200 and converts them into internal executable operations. The signals and protocols of the storage interface may include instruction (CMD) signals, clock (CLK) signals, data (DAT) lines, power and ground (VCC, GND) lines, etc. The instruction signal can be used to send instructions from the processing module 200 to the memory 1000, and these instructions may include read and write operations, initialization, status query, etc. The data line can be used for the actual transmission of data, and there are usually multiple data lines to support different data widths (such as 1-bit, 4-bit or 8-bit). The clock signal can be used to synchronize data transmission to ensure that instructions and data are transmitted according to a predetermined timing. The power and ground lines can power the eMMC storage particles.

[0028] In one embodiment, the host 500 may be electrically connected to the logic analyzer 400 to obtain data analyzed by the logic analyzer 400 .

[0029] In one embodiment, the power module 600 can provide power to the processing module 200 .

[0030] In one embodiment, the transmission module 700 can be connected between the host 500 and the processing module 200. The host 500 can send various test instructions and corresponding test data to the processing module 200 through the transmission module 700. The processing module 200 can transmit the test information of the memory 1000 to the host 500 through the transmission module 700.

[0031] In one embodiment, the interface module 800 may be electrically connected to the processing module 200. The interface module 800 may be an interface for serial communication. The processing module 200 may perform serial communication with an external device through the interface module 800.

[0032] In one embodiment, the memory module 900 may be electrically connected to the processing module 200. The memory module 900 may be used to temporarily store currently running programs and data. The processing module 200 may quickly access these data to improve computing performance.

[0033] In one embodiment, when the performance of a memory 1000 produced by a certain manufacturer is tested, the processing module 200 , the logic analyzer 400 , and the host 500 may cooperate with each other to build a test environment for the memory 1000 .

[0034] Specifically, the memory 1000 can be firstly connected to the test board 100 for communication, so that the NANDInterface of the memory 1000 is connected to the detection pin 300 for correspondence. Afterwards, the power module 600 can supply power to the test board 100, so that the processing module 200 and other modules thereon start working. Subsequently, the processing module 200 can also be connected to the host 500 for communication through the transmission module 700, and the host 500 can select a specific firmware or operating system image (SOC Image) and burn it to the storage module (not shown in the figure) of the test board 100 through the transmission module 700. After the burning is completed, the test board 100 is powered on again to start the newly burned image.

[0035] Furthermore, after the memory 1000 is installed on the test board 100, multiple signal lines of the logic analyzer 400 can be connected to the detection pins 300 of the test board 100 in turn, and other signal lines can also be connected to the eMMC Interface of the memory 1000 to build a test environment for the memory 1000.

[0036] In one embodiment, after setting up the test environment of the memory 1000, the host 500 can send different test instructions and corresponding test data to the memory 1000 through the processing module 200, so that the memory 1000 performs different operations. At this time, the logic analyzer 400 can obtain the test instructions and corresponding test data sent by the host 500 from the eMMC Interface of the memory 1000. The logic analyzer 400 can also obtain the response data of the internal NAND Interface of the memory 1000 when performing different operations through the detection pin 300.

[0037] In one embodiment, the host 500 may send an initialization instruction to the memory 1000 through the processing module 200 to initialize the memory 1000 and obtain the power-on duration of the memory 1000 .

[0038] Specifically, after the power module 600 is powered on, the host 500 may send an initialization instruction to the memory 1000 through the processing module 200 to restart the memory 1000. The initialization instruction may include CMD 0, CMD 8, ACMD 41, CMD 2, CMD 3, etc.

[0039] Among them, the host 500 can send a CMD 0 instruction to the memory 1000 to reset the memory 1000 to the standby state (IDLE). The CMD 0 instruction can be used to reset the memory 1000 and clear any potential error state. Subsequently, the host 500 can send a CMD 8 instruction to inquire whether the memory 1000 supports the high-capacity SD card mode. If the memory 1000 supports it, the instruction will return a corresponding response. Subsequently, the host 500 can send an ACMD 41 instruction to start the initialization process of the memory 1000 and request the memory 1000 to enter the initialization state. The host 500 can also send a CMD 2 instruction to request the memory 1000 to send its CID (Card Identification) register content for identifying the memory 1000. Finally, the host 500 can also send a CMD 3 instruction to request the memory 1000 to set the corresponding relative address (RCA).

[0040] Furthermore, after receiving CMD 0, the internal firmware of the memory 1000 parses the instruction and puts the memory 1000 into the IDLE state. At the same time, the memory 1000 can continue to execute other initialization instructions received, such as setting relative addresses, checking the functions supported by the device, etc. Subsequently, the firmware can instruct the main controller of the memory 1000 to perform initialization operations on the NAND flash memory, including configuring the control registers and data transmission paths of the NAND flash memory, etc. At this time, it is necessary to ensure that the main controller sends the correct instructions through the NAND Interface, such as reading the identification information of the NAND, setting the block erase parameters, etc.

[0041] Furthermore, during the initialization process of the memory 1000, the logic analyzer 400 can monitor the protocol data of the eMMCInterface and the NAND Interface, capture the instruction stream and response during the initialization process, and record the sending time and receiving time of each instruction for subsequent analysis. The logic analyzer 400 can upload the captured instructions and responses and other data to the host 500. The host 500 can analyze these data to ensure that the instructions and responses of the memory 1000 meet the protocol requirements. At the same time, during the monitoring process of the logic analyzer 400, it is necessary to capture the timestamp of each instruction executed by the memory 1000.

[0042] Furthermore, during the initialization process of the memory 1000, the system generates various logs, including initialization timestamps, system service startup time, etc. The host 500 can check these logs, extract timestamps related to the initialization of the memory 1000 and the system startup, and calculate the boot time. The boot time is expressed as the time from the power-on time of the memory 1000 to the time when the memory 1000 is fully started.

[0043] In one embodiment, the host 500 may send a multi-page read instruction (CMD 18 ) to the memory 1000 through the processing module 200 to read multiple data pages from the memory 1000 and calculate a multi-page read performance value of the memory 1000 .

[0044] Specifically, after the memory 1000 completes the initialization operation, the host 500 can send a CMD 18 instruction to the memory 1000, and the memory 1000 will read data from the specified address and continue to transmit data until a stop instruction (such as CMD12) is received. The multi-page read instruction may include parameters such as the starting data block address and the number of data blocks to be read.

[0045] Further, after the memory 1000 receives the CMD 18 instruction, its internal firmware begins to parse the content of the multi-page read instruction. After confirming the legitimacy of the multi-page read instruction and the correctness of the parameters, the firmware forwards the multi-page read instruction to the main controller. The main controller performs the corresponding data read operation through the NAND Interface according to the instruction requirements.

[0046] Furthermore, the logic analyzer 400 can monitor the communication data on the eMMC Interface and the NAND Interface in real time. When the CMD 18 instruction is issued, the logic analyzer 400 will capture the instruction and its response data. At the same time, the logic analyzer 400 will also capture the instruction stream sent by the internal main controller to the NAND flash memory through the NAND Interface and the response data of the NAND flash memory.

[0047] Furthermore, the logic analyzer 400 can transmit the captured data to the host 500 for processing. The host 500 can parse the data and extract the key timestamp and data volume information during the execution of the CMD 18 instruction. The host 500 can also calculate the multi-page reading speed and instruction execution time of the memory 1000 based on the key timestamp and data volume information.

[0048] In one embodiment, the host 500 may send a single page read instruction (CMD 17 ) to the memory 1000 through the processing module 200 to read a single data page from the memory 1000 and calculate a single page read performance value of the memory 1000 .

[0049] Specifically, after the memory 1000 completes the initialization operation, the host 500 may send a CMD 17 instruction to the memory 1000, and the memory 1000 will read data from the specified address. The single page read instruction may include parameters such as the starting address of the data block and the size of the data block.

[0050] Further, after the memory 1000 receives the CMD 17 instruction, its internal firmware begins to parse the content of the multi-page read instruction. After confirming the legitimacy of the multi-page read instruction and the correctness of the parameters, the firmware forwards the multi-page read instruction to the main controller. The main controller performs the corresponding data read operation through the NAND Interface according to the instruction requirements.

[0051] Furthermore, the logic analyzer 400 can monitor the communication data on the eMMC Interface and the NAND Interface in real time. When the CMD 17 instruction is issued, the logic analyzer 400 will capture the instruction and its response data. At the same time, the logic analyzer 400 will also capture the instruction stream sent by the internal main controller to the NAND flash memory through the NAND Interface and the response data of the NAND flash memory.

[0052] Furthermore, the logic analyzer 400 can transmit the captured data to the host 500 for processing. The host 500 can parse the data and extract the key timestamp and data volume information during the execution of the CMD 17 instruction. The host 500 can also calculate the single-page reading speed and instruction execution time of the memory 1000 based on the key timestamp and data volume information.

[0053] In one embodiment, the host 500 may send a single page write instruction (CMD 24) and corresponding test data to the memory 1000 through the processing module 200 to write test data of a single data page into the NAND flash memory of the memory 1000 and calculate the single page write performance value of the memory 1000.

[0054] Specifically, after the memory 1000 completes the initialization operation, the host 500 can send a CMD 24 instruction and corresponding test data to the memory 1000, and the memory 1000 will write the test data to the specified storage location in the NAND flash memory. Among them, the single-page write instruction can include parameters such as the starting address of the written data and the size of the data block.

[0055] Furthermore, after the memory 1000 receives the CMD 24 instruction, its internal firmware begins to parse the content of the single-page write instruction to confirm its legitimacy and parameters. Subsequently, the firmware can forward the CMD 24 instruction and test data to the main controller. The main controller issues a write command through the NAND Interface according to the instruction requirements to write the data to the NAND flash memory. After the write is completed, the main controller can update the internal cache state of the memory 1000 and feed back the result to the host 500.

[0056] Furthermore, the logic analyzer 400 can monitor the communication data on the eMMC Interface and the NAND Interface in real time. When the CMD 24 instruction is issued, the logic analyzer 400 will capture the instruction and its response data. At the same time, the logic analyzer 400 will also record the transmission of the CMD 24 instruction and its data on the eMMC Interface, as well as the instruction stream sent by the main controller through the NAND Interface and the response of the NAND flash memory.

[0057] Furthermore, the logic analyzer 400 can transmit the captured data to the host 500 for processing. The host 500 can parse the data and extract the key timestamp and data volume information during the execution of the CMD 24 instruction. The host 500 can also calculate the single-page write speed and instruction execution time of the memory 1000 based on the key timestamp and data volume information.

[0058] In one embodiment, the host 500 may send a single page write instruction (CMD 25) and corresponding test data to the memory 1000 through the processing module 200 to write test data of multiple data pages into the NAND flash memory of the memory 1000 and calculate the multi-page write performance value of the memory 1000.

[0059] Specifically, after the memory 1000 completes the initialization operation, the host 500 can send a CMD 25 instruction and corresponding test data to the memory 1000, and the memory 1000 will write the test data to the specified storage location in the NAND flash memory. Among them, the multi-page write instruction can include parameters such as the starting address of the written data and the size of the data block.

[0060] Furthermore, after the memory 1000 receives the CMD 25 instruction, its internal firmware begins to parse the content of the single-page write instruction to confirm its legitimacy and parameters. Subsequently, the firmware can forward the CMD 25 instruction and test data to the main controller. The main controller issues a write command through the NAND Interface according to the instruction requirements to write the data to the NAND flash memory. After the write is completed, the main controller can update the internal cache state of the memory 1000 and feed back the result to the host 500.

[0061] Furthermore, the logic analyzer 400 can monitor the communication data on the eMMC Interface and the NAND Interface in real time. When the CMD 25 instruction is issued, the logic analyzer 400 will capture the instruction and its response data. At the same time, the logic analyzer 400 will also record the transmission of the CMD 25 instruction and its data on the eMMC Interface, as well as the instruction stream sent by the main controller through the NAND Interface and the response of the NAND flash memory.

[0062] Furthermore, the logic analyzer 400 can transmit the captured data to the host 500 for processing. The host 500 can parse the data and extract the key timestamp and data volume information during the execution of the CMD 24 instruction. The host 500 can also calculate the multi-page write speed and instruction execution time of the memory 1000 based on the key timestamp and data volume information.

[0063] In one embodiment, the host 500 can send an erase start address instruction (CMD 35), an erase end address instruction (CMD 36), a partial erase instruction (CMD 37) and a full disk erase instruction (CMD 38) to the memory 1000 in sequence through the processing module 200 to partially erase or fully erase the data in the data block in the NAND flash memory of the memory 1000, and calculate the data block erase performance value and the full disk erase performance value of the memory 1000.

[0064] Specifically, after the memory 1000 completes the initialization operation, the host 500 may send CMD 35, CMD 36, and CMD 37 instructions to the memory 1000. The CMD 35 instruction may include the starting address of the data block to be erased, and the CMD 36 instruction may include the ending address of the data block to be erased.

[0065] Further, after the memory 1000 receives the CMD 35 instruction, the CMD 36 instruction, and the CMD 37 instruction, the firmware inside it begins to parse the contents of the above instructions to confirm their legitimacy and parameters. Subsequently, the firmware can forward the corresponding erase command to the main controller. The main controller sends a command stream through the NAND Interface according to the erase command requirements to erase the data in the storage area within the specified range.

[0066] Furthermore, the logic analyzer 400 can monitor the communication data on the eMMC Interface and the NAND Interface in real time. The logic analyzer 400 can record the sending of the CMD 35 instruction, the CMD 36 instruction, and the CMD 37 instruction and their execution status on the eMMC Interface and the NAND Interface.

[0067] Furthermore, the logic analyzer 400 can transmit the captured data to the host 500 for processing. The host 500 can parse the data and extract the key timestamp and data volume information during the execution of the CMD 35 instruction, the CMD 36 instruction, and the CMD 37 instruction. The data volume information can be determined based on the starting address and the ending address of the erased data block. The host 500 can also calculate the data block erasure performance value and the instruction execution time of the memory 1000 based on the key timestamp and the data volume information.

[0068] Furthermore, after the memory 1000 completes the initialization operation, the host 500 can also send a CMD 38 instruction to the memory 1000. Among them, the CMD 38 instruction can perform a comprehensive erase operation (full disk erase). After the memory 1000 receives the CMD 38 instruction, its internal firmware begins to parse the content of the above instruction to confirm its legality and parameters. Subsequently, the firmware can forward the corresponding erase command to the main controller. The main controller sends a command stream through the NAND Interface according to the erase command requirements to perform a full disk erase on the data in the storage area.

[0069] Furthermore, the logic analyzer 400 can monitor the communication data on the eMMC Interface and the NAND Interface in real time. The logic analyzer 400 can record the sending of the CMD 38 instruction and its execution status on the eMMC Interface and the NAND Interface.

[0070] Furthermore, the logic analyzer 400 may transmit the captured data to the host 500 for processing. The host 500 may parse the data and extract the key timestamp and data volume information during the execution of the CMD 38 instruction. The data volume information may be all the data stored in the memory 1000. The host 500 may also calculate the full disk erase performance value and instruction execution time of the memory 1000 based on the key timestamp and data volume information.

[0071] In one embodiment, after the memory 1000 executes a multi-page read instruction, a single page read instruction, a multi-page write instruction, a single page write instruction, a partial erase instruction, and a full disk erase instruction, the host 500 can also be used to count the power consumption data of the memory 1000 during the execution of the above operations.

[0072] In one embodiment, the host 500 can simultaneously send queue instructions to the memory 1000 through the processing module 200 to monitor the instruction execution order of the memory 1000. Among them, the queue instructions may include a read queue instruction (CMD Q44), a write queue instruction (CMD Q45), a submit queue instruction (CMD Q46), a build request instruction (CMD Q47), and a queue management instruction (CMD Q48). The CMD Q44 instruction can be used to construct a series of read queue instructions to define the target address and data of the operation. The CMD Q45 instruction can be used to construct a series of write queue instructions to define the target address and data of the operation. The CMD Q46 instruction can be used to construct a submit queue instruction to inform the memory 1000 that it can start processing the commands in the previous queue. The CMDQ47 instruction can be used to construct a request to obtain the queue processing result. The CMD Q48 instruction can be used to construct an instruction to manage the queue, such as clearing or modifying the commands in the queue.

[0073] Specifically, after the memory 1000 completes the initialization operation, the host 500 can send CMD Q44 instructions, CMD Q45 instructions, CMD Q46 instructions, CMD Q47 instructions, and CMD Q48 instructions to the memory 1000 in sequence through the eMMC Interface. Subsequently, the firmware inside the memory 1000 can receive and parse the queue instructions from the host 500. Based on the received read and write tasks, the firmware instructs the main controller to optimize the order of the tasks to maximize the operating efficiency. Based on the optimized order, the main controller performs the corresponding read or write operations through the NAND Interface.

[0074] Furthermore, the logic analyzer 400 can monitor the instruction flow and response data on the eMMC Interface and the NAND Interface in real time. The logic analyzer 400 can record the sending of the CMD Q44 instruction, the CMD Q45 instruction, the CMD Q46 instruction, the CMD Q47 instruction, and the CMD Q48 instruction and their execution status on the eMMC Interface and the NAND Interface.

[0075] Furthermore, the logic analyzer 400 may transmit the captured data to the host 500 for processing. The host 500 may parse the data to obtain the instruction execution sequence and the corresponding execution time when the memory 1000 executes the queue instruction.

[0076] Furthermore, when multiple memories 1000 are executing queue instructions, the host 500 can obtain the memory 1000 with the shortest execution time, and at this time, the instruction execution order inside the memory 1000 can be considered to be the optimal order. Subsequently, the host 500 can compare and analyze the instruction execution order of the memory 1000 with the instruction execution order of other memories 1000 to optimize the firmware.

[0077] In one embodiment, after the above test, the host 500 has completed the performance test of one memory 1000. Subsequently, the host 500 may also test other different memories 1000 to obtain the performance values ​​of multiple memories 1000. Subsequently, the differences in the performance values ​​of the multiple memories 1000 may be analyzed to analyze the advantages and disadvantages of the behavior differences of the firmware of the multiple memories 1000, thereby optimizing the specific behavior of the firmware in a targeted manner and improving the performance of the memory 1000 to a certain extent.

[0078] In one embodiment, a comparative analysis of two memories 1000 is used as an example for description. The two memories 1000 can be divided into competitor 1 and competitor 2. When the host 500 sends the same instruction to competitor 1 and competitor 2, the execution states on the NAND Interface of competitor 1 and competitor 2 are also different.

[0079] In one embodiment, please refer to Table 1, which shows multiple execution states on the NAND Interface of Competitor 1 and Competitor 2 when performing initialization operations. As can be seen from Table 1, Competitor 1 and Competitor 2 will execute certain unknown instructions (Unknown CMD) internally when performing initialization operations. Among them, the unknown instruction can be indicated as the instruction is not in the JEDEC standard (such as JESD84-B51). When Competitor 1 and Competitor 2 perform initialization operations, the logic analyzer 400 can monitor the NAND Interface in real time, and the host 500 can monitor the instruction stream executed inside the memory 1000 through the logic analyzer 400 to find the direction of firmware optimization. Specific optimization directions may include reducing unknown commands, adopting more efficient storage modes, and optimizing data reading methods.

[0080] Table 1: Multiple execution states of Competitor 1 and Competitor 2 when performing initialization operations.

[0081]

[0082] Furthermore, when the memory 1000 performs the initialization operation, some unknown commands (Unknown CMD) may be processed internally, which will increase unnecessary time consumption. When the memory 1000 is working, in some cases, Unknown CMD may be generated due to incorrect command parsing or transmission problems. These unknown commands cannot be correctly processed by the memory 1000, resulting in time waste. At this time, the firmware or command parsing mechanism can be improved to ensure that only valid commands are sent to avoid the generation of invalid commands, thereby reducing the boot time.

[0083] Furthermore, the SLC (single-level cell) mode has faster data read speed and lower write latency than the XLC (multi-level cell) mode. XLC usually refers to multi-layer storage cell technologies such as MLC and TLC. Although these technologies have more advantages in unit storage capacity, they are not as fast and reliable as SLC. In scenarios where high-performance data reading is required (such as initialization operations), the firmware can be improved to give priority to the SLC mode to increase the reading speed and reduce the boot time.

[0084] Furthermore, sequential read is usually more efficient than random read because it reduces the addressing and data scheduling overhead inside the memory. At this time, the firmware data access mode can be optimized so that more data read operations are performed in a sequential read mode, thereby increasing the reading speed and shortening the boot time.

[0085] In one embodiment, please refer to Table 2, which shows multiple execution states on the NANDInterface of Competitor 1 and Competitor 2 when performing a write operation. As can be seen from Table 2, Competitor 1 and Competitor 2 will execute certain Unknown CMDs internally when performing a write operation. When Competitor 1 and Competitor 2 perform a write operation, the logic analyzer 400 can monitor the NANDInterface in real time, and the host 500 can monitor the instruction stream executed inside the memory 1000 through the logic analyzer 400 to find the optimization direction of the firmware. The optimization direction may include reducing unknown instructions, optimizing the write process to reduce read and erase operations, adopting a more efficient storage mode, and optimizing the data write strategy to reduce the number of programming times to increase the write speed.

[0086] Table 2: Multiple execution states of competitor 1 and competitor 2 when performing write operations.

[0087]

[0088] Furthermore, when writing data, if an unknown instruction is parsed inside the memory 1000, processing delays or even erroneous operations may occur. Through strict management and optimization of the instruction set, it is ensured that only valid instructions are sent during the writing process, and the occurrence of invalid or unknown instructions is avoided, thereby reducing the time consumption caused thereby. At this point, the firmware or instruction parsing mechanism can be improved to ensure that only valid instructions are sent and the generation of invalid instructions is avoided.

[0089] Furthermore, when writing data, the memory 1000 needs to reduce the action of reading data. For example, in some memory architectures, the write operation may involve the process of first reading data and then writing it. This read operation will increase additional time overhead. By optimizing the firmware write process, unnecessary read operations can be minimized or avoided to reduce the overall time consumption. This may require adjusting the firmware to ensure that the write operation is performed directly without involving redundant read processes.

[0090] Furthermore, when writing data, the memory 1000 needs to reduce the erase action. For example, in NAND Flash, an erase operation (Erase) is usually required before writing new data, and this step consumes a lot of time. By improving the management strategy of the firmware, such as erasing free blocks in advance or using a more efficient erase algorithm, the erase operation that needs to be performed immediately during the writing process is reduced, thereby improving the writing speed.

[0091] Furthermore, when writing data, the memory 1000 preferably performs the write operation in a single-level storage mode. In the single-level storage (Single-Level Cell) mode, each storage cell stores only one bit of data, which has a faster write speed and higher reliability than the multi-level storage (such as MLC, TLC) mode. In scenarios where the write speed is required to be high, the firmware can give priority to the SLC mode for writing to maximize the write speed and performance.

[0092] Furthermore, when writing data, the memory 1000 needs to reduce the number of programming operations and concentrate on writing large blocks of data rather than scattered small data. Specifically, frequent writing of small data will cause the memory to perform a large number of programming operations, which not only affects the writing efficiency, but also may increase the wear of the memory. The firmware can process data in batches, merge multiple small data blocks into large data blocks for centralized writing, reduce the number of programming operations, thereby improving writing performance and extending the life of the memory.

[0093] In one embodiment, when optimizing the read speed of the memory 1000, the host 500 can monitor the instruction stream of the read operation inside the memory 1000 through the logic analyzer 400 to find the optimization direction of the firmware. The optimization direction may include reducing invalid commands, adopting a more efficient storage mode, optimizing data access methods, using cache and pre-fetch mechanisms, etc., to improve the write and read speeds.

[0094] Furthermore, when reading data, if an unknown instruction is parsed inside the memory 1000, processing delays may occur, and even the command needs to be resent, which reduces the reading efficiency. By optimizing the firmware and command parsing process, it is ensured that only valid and correct commands are used in the reading operation, and unknown instructions are avoided, thereby reducing unnecessary time consumption.

[0095] Furthermore, when reading critical data or data that requires high performance, SLC mode is used preferentially to increase the reading speed.

[0096] Furthermore, through firmware-level optimization, the data access mode is optimized to sequential read as much as possible. For example, scattered read requests are merged and read in the order of physical storage layout, which can maximize the read bandwidth of the memory.

[0097] Furthermore, in some cases, data can be loaded into the cache in advance to reduce read latency. Using the firmware's pre-fetch and cache mechanism, data that is expected to be read is loaded into the cache of the memory 1000 in advance, so that it can be quickly accessed when needed. The cache mechanism can significantly reduce the data transmission latency between the memory 1000 and the host 500.

[0098] Furthermore, some memories may perform redundant internal operations (such as redundant checks and internal data proofreading) during the reading process, which will increase the reading delay. By optimizing the internal operation process, unnecessary internal read operations can be reduced or merged to increase the overall reading speed. For example, the reading speed can be accelerated by optimizing the calculation method of the data error correction code (ECC) or reducing the frequency of redundant data checks.

[0099] It can be seen that in the above solution, by monitoring the execution status of the NAND Interface of different memories, the behavior differences of the firmware can be analyzed and identified, and the differential behaviors of the firmware of different storage vendors can be quickly located and analyzed. By analyzing the differential behaviors of the firmware, the deficiencies in the firmware can be identified, the overall system performance can be improved, and optimization measures can be quickly taken to improve the overall system performance.

[0100] See also Figure 2 The present invention also provides a memory performance analysis method, which can be applied to the above-mentioned performance analysis system to perform performance analysis on different memories 1000. The steps of the performance analysis method correspond one-to-one to the above-mentioned performance analysis system. The performance analysis method may include the following steps: Step S10, building a test environment for the memory; Step S20, issuing different test instructions to the memory to make the memory perform different operations; Step S30, obtaining the instruction stream and response data sent by the firmware of the memory to the flash memory interface when the memory executes different operations; Step S40: Upload the instruction stream and response data, and perform performance analysis on them.

[0101] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A memory performance analysis system, characterized in that: include: A test board, on which a memory is connected, wherein a plurality of detection pins are set on the test board, and the detection pins are communicatively connected with the test pins of the memory; A logic analyzer is communicatively connected to the flash memory interface of the memory through the detection pin; A processing module is disposed on the test board and is communicatively connected to the storage interface of the memory; as well as A host, which is in communication with the processing module and the logic analyzer, and is used to send different test instructions to the memory through the processing module so that the memory performs different operations; The logic analyzer is used to obtain the instruction stream and response data sent by the firmware of the memory to the flash memory interface when the memory performs different operations, upload the instruction stream and response data to the host, and perform performance analysis on different memories.

2. The memory performance analysis system according to claim 1, characterized in that: The host is also used to send initialization instructions to the multiple memories respectively, so as to obtain the instruction streams of the internal firmware and the corresponding boot durations of the multiple memories when the multiple memories perform initialization operations.

3. The memory performance analysis system according to claim 2, characterized in that: The host is also used to compare and analyze the instruction stream of the memory with the shortest boot time with the instruction stream of other memories, so as to optimize the firmware from the direction of reducing unknown commands, adopting a more efficient storage mode and optimizing the data reading method.

4. The memory performance analysis system according to claim 1, characterized in that: The host is also used to send multi-page read instructions and single-page read instructions to multiple memories respectively, so as to obtain the instruction stream and corresponding read performance value of the internal firmware of the multiple memories when performing multi-page read operations and single-page read operations.

5. The memory performance analysis system according to claim 4, characterized in that: The host is also used to compare and analyze the instruction stream of the memory with the best read performance value with the instruction stream of other memories, so as to optimize the firmware from the direction of reducing unknown commands, adopting a more efficient storage mode, optimizing data access methods, and utilizing cache and pre-fetch mechanisms.

6. The memory performance analysis system according to claim 1, characterized in that: The host is also used to send multi-page write instructions and single-page write instructions to multiple memories respectively, so as to obtain the instruction stream and corresponding write performance value of the internal firmware of the multiple memories when performing multi-page write operations and single-page write operations.

7. The memory performance analysis system according to claim 6, characterized in that: The host is also used to compare and analyze the instruction stream of the memory with the best write performance value with the instruction stream of other memories, so as to optimize the firmware from the direction of reducing unknown commands, optimizing the write process to reduce read and erase operations, adopting a more efficient storage mode, and optimizing the data write strategy to reduce the number of programming times.

8. The memory performance analysis system according to claim 1, characterized in that: The host is also used to send partial erase instructions and full erase instructions to multiple memories respectively to obtain the instruction streams and corresponding erase performance values ​​of the internal firmware of the multiple memories when executing partial erase operations and full erase operations. The host is also used to compare and analyze the instruction stream of the memory with the best erase performance value with the instruction streams of other memories to optimize the firmware.

9. The memory performance analysis system according to claim 1, characterized in that: The host is also used to send queue instructions to multiple memories respectively to obtain the instruction execution order and execution time of the multiple memories when performing queue operations. The host is also used to compare and analyze the instruction execution order of the memory with the shortest execution time with the instruction execution order of other memories to optimize the firmware.

10. A memory performance analysis method, characterized in that: include: Build a test environment for storage; Sending different test instructions to the memory so that the memory performs different operations; Acquire the instruction stream and response data sent by the firmware of the memory to the flash memory interface when the memory performs different operations; The instruction stream and response data are uploaded and performance analyzed.

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