Method for manufacturing semiconductor element
By using a patterned mask layer and an oxide layer to fill the trench during the manufacturing process of semiconductor components, the sharpening problem is solved and the electrical performance is improved.
Patent Information
- Application Number
- CN202410121457.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-16
- Filing Date
- 2024-01-29
- Publication Date
- 2025-03-18
AI Technical Summary
Semiconductor components are prone to sharpening problems during the trench formation and filling process, resulting in electric field changes and short-circuit problems, and reducing electrical performance.
The patterned mask layer contains oxides, and the trench is formed through its hollow part, and the trench is completely filled by depositing the oxide layer, and finally the part of the oxide layer is removed through the planarization process to ensure the plane of the oxide layer and the etch stop layer.
The sharpening problem of etching due to etching selectivity at the bottom of the trench is effectively avoided, the shape consistency and filling quality of the trench are improved, and the electrical performance of the semiconductor components is improved.
Smart Images
Figure CN119650426A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a method for manufacturing a semiconductor device. Background Art
[0002] As semiconductor processes continue to evolve, trench filling processes will face challenges. For example, one of the challenges associated with semiconductor components is that if the trenches are not formed and filled in a suitable manner (for example, by using a polymer that is likely to affect the trench profile), a tip problem may occur. More specifically, the tip problem may occur at the bottom of the trench (for example, the bottom of the shallow trench isolation (STI)). The tip problem is likely to cause electric field changes and short circuit problems (for example, leakage current) in subsequent related processes, thereby reducing the electrical performance of the entire semiconductor component. Summary of the invention
[0003] In view of this, an object of the present disclosure is to provide a method for manufacturing a semiconductor device that can solve the above-mentioned problem.
[0004] In order to achieve the above-mentioned purpose, according to one embodiment of the present disclosure, a method for manufacturing a semiconductor element includes: providing a substrate having an array area and a peripheral area; forming an etch stop layer on the top surface of the substrate in the array area and the peripheral area; forming a patterned mask layer on the top surface of the etch stop layer in the array area and the peripheral area, wherein the patterned mask layer has a plurality of hollow portions, and wherein the patterned mask layer comprises an oxide; utilizing the hollow portions of the patterned mask layer to form a plurality of grooves on the top surface of the etch stop layer in the array area and the peripheral area, wherein the grooves penetrate the etch stop layer and are recessed from the top surface of the substrate; removing the patterned mask layer; and depositing an oxide layer through a deposition process to fill the grooves.
[0005] In one or more embodiments of the present disclosure, the step of depositing an oxide layer is performed such that the oxide layer completely fills the trench.
[0006] In one or more embodiments of the present disclosure, the step of removing the patterned mask layer is performed before the step of depositing the oxide layer.
[0007] In one or more embodiments of the present disclosure, the patterned mask layer has a thickness ranging between 30 nm and 150 nm.
[0008] In one or more embodiments of the present disclosure, the step of forming a patterned mask layer is performed before the step of depositing an oxide layer.
[0009] In one or more embodiments of the present disclosure, the step of depositing an oxide layer is performed such that a top surface of the oxide layer is coplanar with a top surface of the etch stop layer.
[0010] In one or more embodiments of the present disclosure, the method for manufacturing a semiconductor device further includes removing a portion of the oxide layer by a planarization process.
[0011] In one or more embodiments of the present disclosure, the step of removing a portion of the oxide layer is performed such that a top surface of the oxide layer is coplanar with a top surface of the etch stop layer.
[0012] In one or more embodiments of the present disclosure, a groove is formed on the top surface of the etch stop layer in the array region and the peripheral region using the hollow portion of the patterned mask layer, so that the aspect ratio of the groove in the array region is different from that of the groove in the peripheral region.
[0013] In one or more embodiments of the present disclosure, a groove is formed on the top surface of the etch stop layer in the array area and the peripheral area using the hollow portion of the patterned mask layer, so that the aspect ratio of the depth to the width of the groove located in the array area is greater than the aspect ratio of the depth to the width of the groove located in the peripheral area.
[0014] In one or more embodiments of the present disclosure, the etch stop layer has a thickness in a range between 15 nm and 50 nm.
[0015] In one or more embodiments of the present disclosure, the etch stop layer comprises nitride.
[0016] In order to achieve the above-mentioned purpose, according to one embodiment of the present disclosure, a method for manufacturing a semiconductor element includes: providing a substrate having an array area and a peripheral area; forming an etch stop layer on the top surface of the substrate in the array area and the peripheral area; forming a patterned mask layer on the top surface of the etch stop layer in the array area and the peripheral area, wherein the patterned mask layer has a plurality of hollow portions, and wherein the patterned mask layer comprises an oxide; utilizing the hollow portions of the patterned mask layer to form a plurality of grooves on the top surface of the etch stop layer in the array area and the peripheral area, wherein the grooves penetrate the etch stop layer and are recessed from the top surface of the substrate; removing the patterned mask layer; overfilling the grooves by depositing an oxide layer; and removing portions of the oxide layer by a planarization process so that the top surface of the oxide layer is coplanar with the top surface of the etch stop layer.
[0017] In one or more embodiments of the present disclosure, the step of removing the patterned mask layer is performed before the step of depositing the oxide layer.
[0018] In one or more embodiments of the present disclosure, the patterned mask layer has a thickness ranging between 30 nm and 150 nm.
[0019] In one or more embodiments of the present disclosure, the step of forming a patterned mask layer is performed before the step of depositing an oxide layer.
[0020] In one or more embodiments of the present disclosure, a groove is formed on the top surface of the etch stop layer in the array region and the peripheral region using the hollow portion of the patterned mask layer, so that the aspect ratio of the groove in the array region is different from that of the groove in the peripheral region.
[0021] In one or more embodiments of the present disclosure, a groove is formed on the top surface of the etch stop layer in the array area and the peripheral area using the hollow portion of the patterned mask layer, so that the aspect ratio of the depth to the width of the groove located in the array area is greater than the aspect ratio of the depth to the width of the groove located in the peripheral area.
[0022] In one or more embodiments of the present disclosure, the etch stop layer has a thickness in a range between 15 nm and 50 nm.
[0023] In one or more embodiments of the present disclosure, the hollowed-out portion of the patterned mask layer is used to form trenches on the top surface of the etch stop layer in the array region and the peripheral region, so that the patterned mask layer is removed at the same time.
[0024] In summary, in the method for manufacturing a semiconductor element disclosed in the present invention, since the patterned mask layer includes oxide, polymers will not be generated in the step of forming the groove, thereby avoiding the problem of sharpening at the bottom of the groove due to etching selectivity. In the method for manufacturing a semiconductor element disclosed in the present invention, since the step of forming an etching stop layer is performed before the portion of the oxide layer is removed, the etching stop layer can prevent the oxide layer from being over-etched, so that the top surface etching stop layer of the oxide layer is flush with the top surface of the etching stop layer. In the method for manufacturing a semiconductor element disclosed in the present invention, since the patterned mask layer is configured as a sacrificial patterned mask, it is no longer necessary to modify the manufacturing parameters in subsequent related processes, thereby reducing the time and cost of the entire process. In summary, the method for manufacturing a semiconductor element disclosed in the present invention improves the electrical performance of the entire semiconductor element.
[0025] The above description is only used to illustrate the problem to be solved by the present disclosure, the technical means to solve the problem, and the effects produced, etc. The specific details of the present disclosure will be described in detail in the following implementation methods and related drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] In order to make the above and other objects, features, advantages and embodiments of the present disclosure more clearly understood, the accompanying drawings are described as follows:
[0027] Figure 1 The flowchart is a method for manufacturing a semiconductor device according to one embodiment of the present disclosure.
[0028] Figure 2 The figure is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to one embodiment of the present disclosure.
[0029] Figure 3 The figure is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to one embodiment of the present disclosure.
[0030] Figure 4 The figure is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to one embodiment of the present disclosure.
[0031] Figure 5 The figure is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to one embodiment of the present disclosure.
[0032] Figure 6 The figure is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to one embodiment of the present disclosure.
[0033] Figure 7 The figure is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to one embodiment of the present disclosure.
[0034] Figure 8 The figure is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to one embodiment of the present disclosure. DETAILED DESCRIPTION
[0035] The following disclosure provides many different embodiments or examples of the different features for realizing the patent target provided. The specific embodiments of components and configurations are described below to simplify the disclosure. Of course, these are only embodiments and are not intended to be limiting. For example, in the following specification, a first feature is formed on or on a second feature and may include an embodiment in which the first feature and the second feature are formed as direct contacts, and may also include an embodiment in which additional features may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numerals and / or letters in various embodiments. Such repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and / or configurations discussed.
[0036] Additionally, for ease of description, spatially relative terms such as "below," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship between one element or feature and another element or feature shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative terms used herein may likewise be interpreted accordingly.
[0037] As used herein, "approximately," "about," "roughly," or "substantially" generally means within 20%, or within 10%, or within 5% of a given value or range. The numerical values given herein are approximate, meaning that if not explicitly stated, the term "approximately," "about," "roughly," or "substantially" can be inferred.
[0038] Please refer to Figure 1 . Figure 1 According to one embodiment of the present disclosure, Figure 8 A flow chart of method M of semiconductor device 100 is shown. Figure 1 The method M shown includes step S101, step S102, step S103, step S104, step S105, step S106 and step S107. For a better understanding of step S101, please refer to Figure 1 as well as Figure 2 For a better understanding of step S102, please refer to Figure 1 as well as Figure 3 For a better understanding of step S103, please refer to Figure 1 as well as Figure 4 For a better understanding of step S104, please refer to Figure 1 as well as Figure 5 For a better understanding of step S105, please refer to Figure 1 as well as Figure 6 For a better understanding of step S106, please refer to Figure 1 as well as Figure 7 For a better understanding of step S107, please refer to Figure 1 as well as Figure 8 .
[0039] Step S101 , step S102 , step S103 , step S104 , step S105 , step S106 , and step S107 are described in detail below.
[0040] In step S101 , a substrate 110 is provided.
[0041] Please refer to Figure 1 as well as Figure 2 . Figure 2 FIG. 1 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. In this embodiment, a substrate 110 is formed. Figure 2 As shown, the substrate 110 has an array region 100A and a peripheral region 100B. Figure 2 As shown, the substrate 110 has a top surface 110 a , and the top surface 110 a is exposed.
[0042] In some embodiments, the substrate 110 may be a silicon-based substrate. In some embodiments, the substrate 110 may include, for example, single crystal silicon, polycrystalline silicon, amorphous silicon, or other similar materials. However, any suitable material may be used.
[0043] In some embodiments, the substrate 110 may be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating or other similar methods. The present disclosure is not intended to limit the method for forming the substrate 110.
[0044] In step S102 , an etching stop layer 120 is formed.
[0045] Please refer to Figure 1 as well as Figure 3 . Figure 3 FIG. 1 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. In this embodiment, an etching stop layer 120 is formed on the top surface 110a of the substrate 110 in the array region 100A and the peripheral region 100B of the substrate 110. Figure 3 As shown, the etch stop layer 120 has a top surface 120a, and the top surface 120a is exposed. In some embodiments, the etch stop layer 120 is configured as a stop layer in subsequent steps.
[0046] In some embodiments, the etch stop layer 120 may include, for example, silicon nitride (Si x N y ), titanium nitride (Ti x N y ) or other similar materials. However, any suitable material may be used.
[0047] In some embodiments, the etch stop layer 120 may be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating or other similar methods. The present disclosure is not intended to be limited to the method of forming the etch stop layer 120.
[0048] In step S103 , a patterned mask layer 130 is formed.
[0049] Please refer to Figure 1 as well as Figure 4 . Figure 41 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. In this embodiment, the patterned mask layer 130 is disposed above the substrate 110. In some embodiments, the patterned mask layer 130 is disposed on the etch stop layer 120. Figure 4 As shown, the patterned mask layer 130 has a plurality of hollow portions O1 and a plurality of hollow portions O2. The hollow portions O1 are located in the array region 100A, while the hollow portions O2 are located in the peripheral region 100B. Figure 4 The hollow portion O2 is shown as a single hollow portion. Figure 4 As shown, the patterned mask layer 130 has a top surface 130 a , and the top surface 130 a is exposed.
[0050] In some embodiments, the hollow portion O1 and the hollow portion O2 may be formed by any suitable method, such as wet etching, dry etching or other similar methods. The present disclosure is not intended to limit the method for forming the hollow portion O1 and the hollow portion O2.
[0051] In some embodiments, the width of each hollow portion O2 is greater than the width of each hollow portion O1.
[0052] In some embodiments, the patterned mask layer 130 comprises an oxide. In some embodiments, the patterned mask layer 130 may comprise, for example, silicon dioxide (SiO2) or other similar materials. However, any suitable material may be used.
[0053] In some embodiments, the patterned mask layer 130 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating or other similar methods. The present disclosure is not intended to limit the method for forming the patterned mask layer 130.
[0054] In step S104 , a plurality of trenches T1 and a plurality of trenches T2 are formed.
[0055] Please refer to Figure 1 as well as Figure 5 . Figure 5 FIG. 1 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. In step S102, a plurality of trenches T1 and a plurality of trenches T2 are formed on the top surface 110a of the substrate 110 in the array region 100A and the peripheral region 100B using the hollow portions O1 and O2 of the patterned mask layer 130. Figure 5As shown, the trench T1 and the trench T2 are formed to pass through the hollow portion O1 and the hollow portion O2 of the patterned mask layer 130, respectively. In some embodiments, the trench T1 and the trench T2 pass through the etch stop layer 120. In some embodiments, the trench T1 and the trench T2 pass through the etch stop layer 120 and are recessed from the top surface 110a of the substrate 110. In some embodiments, each trench T1 has an inner surface T1a and each trench T2 has an inner surface T2a.
[0056] like Figure 5 As shown, each trench T1 includes a depth D1 and a width W1. In some embodiments, the depth D1 is defined as the distance from the top surface 110a of the substrate 110 to the bottom of each trench T1. In some embodiments, the depth D1 may be greater than the width W1, but the present disclosure is not limited thereto. In some embodiments, the depth D1 is about 300 nanometers. In some embodiments, the width W1 is in a range between about 8 nanometers and about 20 nanometers. In some embodiments, the aspect ratio of the depth D1 to the width W1 of the trench T1 is in a range between about 15 and about 37.5, but the present disclosure is not limited thereto.
[0057] like Figure 5 As shown, each trench T2 includes a depth D2 and a width W2. In some embodiments, the depth D2 is defined as the distance from the top surface 110a of the substrate 110 to the bottom of each trench T2. In some embodiments, the width W2 may be greater than the width W1. In some embodiments, the depth D2 may be less than or greater than the width W2, but the present disclosure is not limited thereto.
[0058] In some embodiments, the depth D1 may be equal to the depth D2 , but the disclosure is not limited thereto.
[0059] In some embodiments, the aspect ratio of the depth D1 of each trench T1 in the array region 100A to the width W1 is different from the aspect ratio of the depth D2 of each trench T2 in the peripheral region 100B to the width W2. In some embodiments, the aspect ratio of the depth D1 of each trench T1 in the array region 100A to the width W1 is smaller than the aspect ratio of the depth D2 of each trench T2 in the peripheral region 100B to the width W2.
[0060] In some embodiments, the trench T1 and the trench T2 may be formed by any suitable method, such as wet etching, dry etching or other similar methods. The present disclosure is not intended to be limited to the method for forming the trench T1 and the trench T2.
[0061] In step S105 , the patterned mask layer 130 is removed.
[0062] Please refer to Figure 1 as well as Figure 6 . Figure 6 FIG. 1 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. In this embodiment, the patterned mask layer 130 is removed from the top surface 120a of the etch stop layer 120. Figure 6 As shown, after step S104, the patterned mask layer 130 is removed. In some embodiments, the patterned mask layer 130 is removed by a removal process.
[0063] In some embodiments, the patterned mask layer 130 may be removed by any suitable method, such as wet etching, dry etching, or other similar methods. The present disclosure is not intended to be limited to the method of forming the patterned mask layer 130 .
[0064] In some embodiments, the patterned mask layer 130 has a thickness in a range between about 30 nanometers and about 150 nanometers. In some embodiments where the patterned mask layer 130 has a thickness greater than 150 nanometers, the patterned mask layer 130 is not easily removed during the execution of step S105. In some embodiments where the patterned mask layer 130 has a thickness less than 30 nanometers, the patterned mask layer 130 may be excessively consumed, causing the trenches T1 and T2 to not easily pass through the etching stop layer 120 and be recessed on the substrate 110 during the execution of step S104.
[0065] In some other embodiments, the steps of forming the trench T1 and the trench T2 on the top surface 120a of the etching stop layer 120 in the array region 100A and the peripheral region 100B using the hollow portions O1 and O2 of the patterned mask layer 130 are performed, so that the patterned mask layer 130 is removed at the same time. In other words, step S104 and step S105 can be performed at the same time. More specifically, when the trench T1 and the trench T2 are formed downward, the patterned mask layer 130 is also consumed.
[0066] In step S106 , an oxide layer 140 is deposited to fill the trench T1 and the trench T2 .
[0067] Please refer to Figure 1 as well as Figure 7 . Figure 7 FIG. 1 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. In step S106, an oxide layer 140 is deposited on the inner surface T1a of each trench T1 and the inner surface T2a of each trench T2 of the substrate 110. Figure 7As shown, after step S105, an oxide layer 140 is formed on the top surface 120a of the etch stop layer 120. More specifically, the oxide layer 140 fills the trench T1 located in the array region 100A and the trench T2 located in the peripheral region 100B. In some embodiments, the trench T1 and the trench T2 are completely filled with the oxide layer 140. In some embodiments, the oxide layer 140 overfills the trench T1 and the trench T2.
[0068] In some embodiments, the oxide layer 140 may include a material such as an oxide. For example, the material of the oxide layer 140 may include silicon dioxide (SiO 2 ), etc. The present disclosure is not intended to limit the material of the oxide layer 140 .
[0069] In some embodiments, the oxide layer 140 may be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating or other similar methods. The present disclosure is not intended to be limited to the method of forming the oxide layer 140.
[0070] In some embodiments, the oxide layer 140 may be deposited by a flowable chemical vapor deposition (FCVD) process, a spin-on dielectric coating deposition, or other similar methods.
[0071] In step S107 , portions of the oxide layer 140 are removed.
[0072] Please refer to Figure 1 as well as Figure 8 . Figure 8 FIG. 1 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. Figure 8 As shown, the portion of the oxide layer 140 is removed to form the semiconductor device 100. More specifically, the portion of the oxide layer 140 located on the top surface 120a of the etch stop layer 120 is removed during step S107. In some embodiments, the portion of the oxide layer 140 is removed by a planarization process. Figure 8 As shown, the removal of the oxide layer 140 is performed such that the top surface 140a of the remaining oxide layer 140 is coplanar with the top surface 120a of the etch stop layer 120. In other words, the top surface 140a of the oxide layer 140 is flush with the top surface 120a of the etch stop layer 120.
[0073] In some embodiments, the planarization process may be performed by a chemical mechanical planarization (CMP) process.
[0074] In some embodiments, the etch stop layer 120 has a thickness in a range between about 15 nanometers and about 50 nanometers. In some embodiments where the thickness of the etch stop layer 120 is greater than 50 nanometers, the trench T1 and the trench T2 may not easily penetrate the etch stop layer 120 and be recessed on the substrate 110 during the execution of step S104. In some embodiments where the thickness of the etch stop layer 120 is less than 15 nanometers, the etch stop layer 120 may be excessively consumed during the execution of step S107.
[0075] By executing this disclosure Figure 1 The method M shown can form a semiconductor device 100 with better electrical performance.
[0076] From the above detailed description of the specific embodiments of the present disclosure, it can be clearly seen that in the manufacturing method of the semiconductor element disclosed in the present disclosure, since the patterned mask layer contains oxide, polymers will not be generated in the step of forming the groove, thereby avoiding the problem of sharpening at the bottom of the groove due to etching selectivity. In the manufacturing method of the semiconductor element disclosed in the present disclosure, since the step of forming the etching stop layer is performed before the part of the oxide layer is removed, the etching stop layer can prevent the oxide layer from being over-etched, so that the top surface etching stop layer of the oxide layer is flush with the top surface of the etching stop layer. In the manufacturing method of the semiconductor element disclosed in the present disclosure, since the patterned mask layer is configured as a sacrificial patterned mask, it is no longer necessary to modify the manufacturing parameters in the subsequent related processes, thereby reducing the time and cost of the entire process. In summary, the manufacturing method of the semiconductor element disclosed in the present disclosure improves the electrical performance of the entire semiconductor element.
[0077] Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
[0078] The above content summarizes the features of several embodiments so that those skilled in the art can better understand the shape of the present invention. Those skilled in the art should understand that the above content can be easily used as a basis for designing or modifying other changes without departing from the spirit and scope of the present invention to implement the same purpose and / or achieve the same advantages of the embodiments described herein. The above content should be understood as an example of the present disclosure, and its scope of protection should be based on the claims.
[0079]
Explanation of symbols
[0080] 100:Semiconductor components
[0081] 100A: Array area
[0082] 100B: Surrounding area
[0083] 110:Substrate
[0084] 110a, 120a, 130a, 140a: top surface
[0085] 120: Etching stop layer
[0086] 130: Patterned shielding layer
[0087] 140: Oxide layer
[0088] D1,D2: Depth
[0089] M: Method
[0090] O1,O2: Hollow part
[0091] S101, S102, S103, S104, S105, S106, S107: Steps
[0092] T1, T2: Groove
[0093] T1a, T2a: inner surface
[0094] W1,W2: width.
Claims
1. A method for manufacturing a semiconductor element, characterized in that: Include: Providing a substrate having an array region and a peripheral region; forming an etch stop layer on the top surface of the substrate in the array region and the peripheral region; forming a patterned mask layer on the top surface of the etching stop layer in the array region and the peripheral region, wherein the patterned mask layer has a plurality of hollow portions, and wherein the patterned mask layer comprises oxide; Using the plurality of hollow portions of the patterned mask layer to form a plurality of grooves on the top surface of the etch stop layer in the array region and the peripheral region, wherein the plurality of grooves penetrate the etch stop layer and are recessed from the top surface of the substrate; removing the patterned mask layer; as well as An oxide layer is deposited by a deposition process to fill the plurality of trenches.
2. The method according to claim 1, characterized in that The step of depositing the oxide layer is performed such that the oxide layer completely fills the plurality of trenches.
3. The method according to claim 1, characterized in that The step of removing the patterned mask layer is performed before the step of depositing the oxide layer.
4. The method according to claim 1, characterized in that: The patterned mask layer has a thickness ranging between 30 nanometers and 150 nanometers.
5. The method according to claim 1, characterized in that The step of forming the patterned mask layer is performed before the step of depositing the oxide layer.
6. The method according to claim 1, characterized in that The step of depositing the oxide layer is performed such that a top surface of the oxide layer is coplanar with the top surface of the etch stop layer.
7. The method according to claim 1, characterized in that The method further includes removing portions of the oxide layer by a planarization process.
8. The method according to claim 7, characterized in that The step of removing the portion of the oxide layer is performed such that a top surface of the oxide layer is coplanar with the top surface of the etch stop layer.
9. The method according to claim 1, characterized in that: The method of utilizing the multiple hollow portions of the patterned mask layer to form the multiple grooves on the top surface of the etching stop layer in the array area and the peripheral area causes the aspect ratio of the multiple grooves in the array area to be different from the aspect ratio of the multiple grooves in the peripheral area.
10. The method according to claim 1, characterized in that The method of utilizing the multiple hollow portions of the patterned mask layer to form the multiple grooves on the top surface of the etch stop layer in the array area and the peripheral area causes the aspect ratio of the depth to the width of the multiple grooves in the array area to be greater than the aspect ratio of the depth to the width of the multiple grooves in the peripheral area.
11. The method according to claim 1, characterized in that The etch stop layer has a thickness in a range between 15 nanometers and 50 nanometers.
12. The method according to claim 1, characterized in that The etch stop layer includes nitride.
13. A method for manufacturing a semiconductor element, characterized in that: Include: Providing a substrate having an array region and a peripheral region; forming an etch stop layer on the top surface of the substrate in the array region and the peripheral region; forming a patterned mask layer on the top surface of the etching stop layer in the array region and the peripheral region, wherein the patterned mask layer has a plurality of hollow portions, and wherein the patterned mask layer comprises oxide; Using the plurality of hollow portions of the patterned mask layer to form a plurality of grooves on the top surface of the etch stop layer in the array region and the peripheral region, wherein the plurality of grooves penetrate the etch stop layer and are recessed from the top surface of the substrate; removing the patterned mask layer; overfilling the plurality of trenches by depositing an oxide layer; as well as Portions of the oxide layer are removed by a planarization process so that a top surface of the oxide layer is coplanar with the top surface of the etch stop layer.
14. The method according to claim 13, characterized in that The step of removing the patterned mask layer is performed before the step of depositing the oxide layer.
15. The method according to claim 13, characterized in that The patterned mask layer has a thickness ranging between 30 nanometers and 150 nanometers.
16. The method according to claim 13, characterized in that The step of forming the patterned mask layer is performed before the step of depositing the oxide layer.
17. The method according to claim 13, characterized in that The method of utilizing the multiple hollow portions of the patterned mask layer to form the multiple grooves on the top surface of the etching stop layer in the array area and the peripheral area causes the aspect ratio of the multiple grooves in the array area to be different from the aspect ratio of the multiple grooves in the peripheral area.
18. The method according to claim 13, characterized in that The method of utilizing the multiple hollow portions of the patterned mask layer to form the multiple grooves on the top surface of the etch stop layer in the array area and the peripheral area causes the aspect ratio of the depth to the width of the multiple grooves in the array area to be greater than the aspect ratio of the depth to the width of the multiple grooves in the peripheral area.
19. The method according to claim 13, characterized in that The etch stop layer has a thickness in a range between 15 nanometers and 50 nanometers.
20. The method according to claim 13, characterized in that The step of forming the plurality of grooves on the top surface of the etching stop layer in the array region and the peripheral region by using the plurality of hollow portions of the patterned mask layer is performed, so that the patterned mask layer is removed at the same time.