Packaging test method for interconnection of bumps of different sizes based on active surface lamination of CoW module
By adopting the active surface stacked packaging test method under the CoW module, using the metallization layer under the bump, copper column bump and two reflow technologies, the problem of interconnection of the bumps of different sizes under the CoW module is solved, miniaturized and high-density packaging is achieved, and manufacturing difficulty and cost are reduced.
Patent Information
- Application Number
- CN202411747803.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-02
- Publication Date
- 2025-03-18
AI Technical Summary
The prior art is difficult to effectively solve the interconnection problem of convex points of different sizes between stacks under CoW modules, resulting in large packaging volume, slow transmission speed, high cost of TSV stacking and high process difficulty.
The active surface stacked packaging test method based on CoW module is adopted to prepare metallized layers and copper column bumps under the bumps on the lower wafer surface, and use two reflow and ball-planting mesh technology to achieve interconnection and packaging of bumps of different sizes.
It effectively reduces the overall size of the chip, improves the utilization rate of the packaging structure, reduces the difficulty and cost of chip manufacturing, and does not require the introduction of frames or heterogeneous structures, making the product reliable.
Smart Images
Figure CN119650444A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductor packaging, and in particular relates to a packaging test method for interconnecting bumps of different sizes based on active surface stacking of a CoW module. Background Art
[0002] As the demand for miniaturization and multifunctionality of electronic devices increases, the demand for miniaturization and high density of semiconductor packaging is also gradually increasing.
[0003] Traditional POP packaging solutions usually use BGA solder balls to achieve upper and lower interconnections, which makes it difficult to achieve stacked packaging and has a poor effect on shortening the I / O terminal spacing, which is not conducive to the miniaturization of devices.
[0004] Furthermore, a solution has emerged in which grooves are filled with metal to achieve upper and lower interconnections. Although this method can further shorten the I / O terminal spacing, it requires the TSV process, which achieves interconnection between chips by making vertical vias inside the silicon wafer. This process method is complex and has high requirements for positioning.
[0005] Especially for CoW modules, in the chip-to-wafer mode, there are bumps of different sizes between the stacked layers, and the interconnection process is an urgent problem to be solved. Summary of the invention
[0006] In order to solve the above problems in the prior art, namely, the slow transmission speed and large volume of the current POP packaging, the high cost and difficult process of TSV stacking, and the problem of interconnection of bumps of different sizes between stacks in the CoW mode, the present invention provides a method for preparing the interconnection of bumps of different sizes applied to the active surface stack of the chip.
[0007] The technical solution of the present invention includes:
[0008] A packaging test method for interconnecting bumps of different sizes based on active surface stacking of a CoW module, characterized by comprising the following steps:
[0009] S1, preparing an under-bump metallization layer on a pad at a position corresponding to a solder ball bump on an insulating layer on a surface of a lower wafer;
[0010] S2: preparing copper pillar bumps at positions corresponding to the copper pillar bumps on the insulating layer on the surface of the lower wafer;
[0011] S3: Align the upper chip pads with the lower wafer copper pillar bumps for mounting;
[0012] S4: reflow the mounted wafer for the first time according to the corresponding reflow curve to achieve the interconnection between the upper chip and the lower wafer;
[0013] S5: Use high temperature tape or protective film on the under bump metallization layer for protection;
[0014] S6: Use bottom filling glue to fill between the upper chip and the lower wafer;
[0015] S7: placing solder at the location of the metallization layer under the wafer bump through the stencil;
[0016] S8: reflowing the wafer for the second time according to the corresponding reflow curve to prepare solder bumps on the wafer;
[0017] S9: Clean the wafer to remove residual flux and excess materials;
[0018] S10: Slicing the wafer to form an active surface stacking packaging structure of an upper chip and a lower chip.
[0019] The packaging and testing method for interconnection of bumps of different sizes based on the active surface stack of the CoW module according to claim 1 is characterized in that: the height of the solder ball bump is greater than 150% of the sum of the thickness of the copper pillar bump and the upper chip, and the solder from the inside to the outside of the copper pillar bump structure is Cu-X, Cu-NiX or Cu-Ni-Cu-X, wherein X is Ag, SnAg alloy, SnAgCu alloy, SnAgBi alloy or SnPb alloy; the solder ball bump is a tin-based solder bump, and the solder from the inside to the outside of the solder ball bump is Cu-Y, Cu-NiY or Cu-Ni-Cu-Y, wherein Y is one of SnAg alloy, SnAgCu alloy or PbSn alloy, and the melting point of X is greater than the melting point of Y.
[0020] The packaging and testing method for interconnecting bumps of different sizes based on the active surface stack of the CoW module as claimed in claim 1 is characterized in that: the under-bump metallization layer in step S1 is a multi-layer metal structure, which is Ti, Cu, Ni or Ti, Cu, Ni, Au or Ti, Cu, Ni, Cu from bottom to top.
[0021] The packaging and testing method for interconnecting bumps of different sizes based on the active surface stack of the CoW module as described in claim 3 is characterized in that the shape of the under-bump metallization layer is a circular, hexagonal or octagonal stepped groove, and the diameter and depth of the inner and outer grooves of the stepped groove match the diameter of the solder ball.
[0022] The packaging and testing method for interconnecting different-sized bumps based on the active surface stack of the CoW module as claimed in claim 1 is characterized in that: in step S7, the stencil places solder at the position of the metallization layer under the wafer bump by wafer-level solder paste printing or wafer-level ball planting; when the wafer-level solder paste printing method is adopted, the solder paste is printed at the position of the metallization layer under the solder ball bump by the solder paste printing stencil, and the solder paste printing stencil is provided with a through hole matching the diameter of the metallization layer under the bump, so that the solder can be leaked through the through hole and placed on the corresponding bump. On the under-bump metallization layer, the position of the through hole corresponds to the position of the bump on the wafer surface. When the wafer-level ball planting method is adopted, the flux is printed on the under-bump metallization layer by needle transfer or screen printing, and the solder ball is placed on the under-bump metallization layer by the ball planting stencil. During the printing of the flux, it is necessary to avoid touching the upper chip. The ball planting stencil is provided with through holes matching the diameter of the solder ball, so that the solder ball can pass through the through holes and be placed on the corresponding under-bump metallization layer. The position of the through hole corresponds to the position of the bump on the wafer surface.
[0023] The packaging and testing method for interconnection of bumps of different sizes based on the active surface stacking of the CoW module as described in claim 5 is characterized in that: the ball planting stencil comprises three layers: an opening layer, a protective layer, and a padding layer, the opening layer has holes at positions corresponding to the solder balls, the protective layer has holes at positions corresponding to the solder balls and at the positions of the upper chips, the padding layer has holes at positions corresponding to the solder balls, the padding layer and the protective layer are bonded together, the opening layer and the protective layer are made of metal material, and the padding layer is made of polymer resin material.
[0024] The packaging and testing method for interconnecting bumps of different sizes based on the active surface stack of the CoW module as described in claim 6 is characterized in that: the diameter of the opening layer is 90%-95% or 105%-120% of the diameter of the metallization layer under the bump, the height of the protective layer is 105% to 110% of the sum of the thickness of the upper chip and the height of the copper pillar bump, and the thickness of the stencil is controlled by adjusting the thickness of the pad layer.
[0025] The packaging and testing method for interconnecting bumps of different sizes based on the active surface stack of the CoW module as described in claim 5 is characterized in that: the solder paste component is SnAg solder paste or SnAgCu solder paste or SnAgBi solder paste or SnAgGe solder paste or SnAgIn solder paste or PbSn solder paste, and its melting point should be lower than the top metal compound of the copper column bump structure.
[0026] The packaging and testing method for interconnecting bumps of different sizes based on the active surface stack of the CoW module as described in claim 1 is characterized in that: in step S4 and step S8, the wafer reflow adopts hot air reflow or vacuum reflow or hydrogen reduction reflow, and its maximum reflow temperature is positively correlated with the melting point of the solder.
[0027] The packaging and testing method for interconnecting different-sized bumps based on the active surface stacking of the CoW module as claimed in claim 1 is characterized in that: in step S3, during the alignment and mounting, the chip pad and the copper pillar deviation value are less than 20% of the copper pillar diameter. The lower wafer is a single chip wafer or an MPW panel wafer, the insulating layer on the surface of the bottom wafer is made of at least one of SiO2, SiN, and polyimide, the lower wafer includes a substrate and a lower chip, and has Al pads of different sizes; the upper chip and the lower chip, and the lower chip and the substrate are electrically connected through solder ball bumps or copper pillar bumps, the upper chip is electrically connected to the lower chip through the copper pillar bumps, and the lower chip is electrically connected to the substrate through solder ball bumps.
[0028] In step S6, the gap between the upper chip and the lower wafer is filled with bottom filling glue, and then cured in a high-temperature oven.
[0029] The copper pillar bump structure is processed by electroplating process.
[0030] The solder ball component is SnAg ball or SnAgCu ball or SnAgBi ball or SnAgGe ball or SnAgIn ball or PbSn ball or copper core ball or plastic core ball, and its melting point should be lower than the top metal compound of the copper column bump structure.
[0031] The dicing method uses a diamond knife or laser cutting to divide the wafer into chip structures.
[0032] Beneficial effects of the present invention:
[0033] (1) The present invention combines the electroplating method and the ball drop method, utilizes the melting point gradient and adopts two reflows to realize the preparation of bumps with different components and structures on the same wafer surface.
[0034] (2) The present invention designs a three-layer stencil and realizes the preparation of spherical bumps on the surface of the active surface laminated wafer through wafer-level solder paste printing or ball planting process.
[0035] (3) The present invention provides a chip active surface stacked interconnection structure, which effectively reduces the overall size of the chip. At the same time, it does not introduce heterogeneous structures such as frames, EMC, and ceramics, and the product reliability is high.
[0036] (4) The present invention adds a layer of chip stacking within the size of the original WLCSP package, thereby improving the utilization rate of the package structure, increasing the chip integration, and reducing the circuit size.
[0037] (5) Compared with the traditional 3D stacked packaging, the present invention does not require TSV inside the functional chip, which greatly reduces the difficulty and cost of chip manufacturing.
[0038] (6) Compared with the traditional 2.5D packaging, the present invention can realize the interconnection between chips without the need of an adapter board, thus reducing the signal transmission distance and greatly improving the circuit power supply and electrical performance.
[0039] (7) The present invention can be flip-chip mounted on a ceramic substrate as required, or can be directly interconnected with a circuit board. It can be flexibly matched according to different product requirements and has strong versatility. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:
[0041] Figure 1 It is a schematic diagram of the chip packaging structure with different bumps of the present invention;
[0042] Figure 2 It is a schematic diagram of the electroplated bump structure of the present invention;
[0043] Figure 3 It is a schematic diagram of the structure of the interconnection between the upper chip and the lower chip of the present invention;
[0044] Figure 4 It is an overall schematic diagram of the chip packaging structure with different bumps on the wafer of the present invention;
[0045] Figure 5 It is a schematic diagram of the ball planting grid plate structure of the present invention;
[0046] Reference numerals:
[0047] 1-lower chip, 2-upper chip, 3-column bump, 4-spherical bump, 5-pad, 10-opening layer, 20-protective layer, 30-pad layer. DETAILED DESCRIPTION
[0048] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the relevant invention are shown in the accompanying drawings.
[0049] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.
[0050] The invention provides a packaging test method for interconnecting bumps of different sizes based on active surface stacking of a CoW module.
[0051] like Figure 1 Shown is a schematic diagram of a chip packaging structure with different bumps of the present invention.
[0052] It comprises a lower chip 1, an upper chip 2, columnar bumps 3 and spherical bumps 4. The upper chip 2 is interconnected with the lower chip 1 via the columnar bumps 3.
[0053] like Figure 2 Shown is a schematic diagram of the electroplated bump structure.
[0054] It includes a lower chip 1, a pillar bump 3 and a pad 5, and the pad 5 is a UBM.
[0055] like Figure 3 The figure shows a schematic diagram of the structure of the interconnection between the upper chip and the lower chip.
[0056] It includes a lower chip 1, an upper chip 2, a pillar bump 3 and a pad 5, and the pad 5 is a UBM.
[0057] like Figure 4 The wafer shown is prepared according to the packaging and testing method of the present invention for interconnecting bumps of different sizes based on the active surface stacking of the CoW module, and includes the overall structure of the chip packaging with different bumps.
[0058] like Figure 5 Shown is a schematic structural diagram of the ball planting grid plate of the present invention.
[0059] It includes an opening layer 10, a protective layer 20, and a cushioning layer 30, wherein the opening layer has holes at positions corresponding to the solder balls, the protective layer has holes at positions corresponding to the solder balls and at positions of upper chips, and the cushioning layer has holes at positions corresponding to the solder balls. The cushioning layer and the protective layer are bonded together, the opening layer and the protective layer are made of metal material, and the cushioning layer is made of polymer resin material.
[0060] The diameter of the opening layer is 90%-95% or 105%-120% of the diameter of the metallization layer under the bump, and the height of the protection layer is 105%-110% of the sum of the thickness of the upper chip and the height of the copper column bump. The thickness of the stencil is controlled by adjusting the thickness of the pad layer.
[0061] The solder paste composition is SnAg solder paste or SnAgCu solder paste or SnAgBi solder paste or SnAgGe solder paste or SnAgIn solder paste or PbSn solder paste, and its melting point should be lower than the metal compound on the top layer of the copper column bump structure.
[0062] Example
[0063] The method for preparing a flip chip stacked package structure with different bump structures comprises the following steps:
[0064] In the first step, take a wafer and prepare a passivation layer 2 on the surface of the wafer, and prepare an under-bump metallization layer 3 under the corresponding position of the large-size solder ball bump. The passivation layer is made of SiO2, polyimide or a mixed passivation layer 2. The metallization layer 3 is in the shape of a circular, hexagonal or octagonal stepped groove, and the diameter and depth of the inner and outer grooves match the diameter of the solder ball. The metallization layer is a multi-layer metal structure, which is Ti, Cu, Ni or Ti, Cu, Ni, Au or Ti, Cu, Ni, Cu from bottom to top. Among them, Ti is used as a seed layer with a thickness of 0.1μm to 0.3μm; Cu is used as an adhesion layer with a thickness of 3μm to 5μm; Ni is used as a barrier layer with a thickness of 3μm to 4μm; Au / Cu is used as an anti-oxidation layer with a thickness of 0.5μm to 1μm.
[0065] In the second step, copper pillar bumps are prepared on the surface of the wafer completed in the first step. The copper pillar bump structure is a multi-layer metal structure, which is Cu-X, Cu-Ni-X or Cu-Ni-Cu-X from bottom to top, where X is SnAg, SnAgCu or PbSn.
[0066] The third step is to thin the top chip to 200-300μm, and use a placement machine to align the top chip pad with the bottom wafer copper pillar bump for placement. The deviation between the center of the pad and the center of the copper pillar bump is less than or equal to 5μm.
[0067] The fourth step is to reflow the mounted wafer for the first time according to the corresponding reflow curve. The reflow adopts hot air reflow, vacuum reflow or hydrogen reduction reflow. The control range is 5℃ to 25℃ above the melting point of the compound on the copper pillar bump to achieve the interconnection between the top chip and the bottom wafer.
[0068] The fifth step is to use high-temperature tape to protect the area of the metallization layer under the bump, fill the liquid bottom filler 500um outside the upper chip, place it in a nitrogen oven or pressure oven for curing, and tear off the protective tape.
[0069] The sixth step is to apply flux to the metallization layer under the wafer bumps. The flux can be applied by needle transfer or screen printing. Avoid touching the upper chip during the flux printing process.
[0070] Step 7: Place solder balls at the location of printed flux through the ball planting stencil. The opening layer is made of nickel alloy steel sheet with a thickness of 30μm and a tension of 40Mpa. The padding layer is made of nickel alloy steel sheet with a thickness of 105% to 110% of the sum of the thickness of the copper pillar bump and the upper chip. The protective layer is made of organic resin, and the thickness of the organic resin is determined according to the diameter of the solder ball.
[0071] The wafer is reflowed for the second time according to the corresponding reflow curve, using hot air reflow, vacuum reflow or hydrogen reduction reflow, and the control range is 5℃ to 25℃ above the melting point of the compound on the ball bump to achieve the interconnection between the top chip and the bottom wafer. The preparation of large-sized ball bumps on the wafer is achieved.
[0072] The solder ball is composed of SnAg ball, SnAgCu ball, SnAgBi ball, SnAgGe ball, SnAgIn ball, PbSn ball, copper core ball or plastic core ball.
[0073] Step 8: Clean the wafer after reflow in step 7 to remove residual flux and excess materials. Cleaning is done by spin immersion cleaning, chain cleaning or surface spraying, and deionized water or alkaline cleaning solution can be used;
[0074] In the ninth step, the wafer cleaned in the eighth step is sliced to form a stacked interconnect structure on the active surface of the chip. The wafer is sliced using a diamond blade or laser cutting.
[0075] In the description of the present invention, the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicating directions or positional relationships are based on the directions or positional relationships shown in the drawings, which are only for the convenience of description, and do not indicate or imply that the device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0076] In addition, it should be noted that in the description of the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0077] The term "comprise" or any other similar term is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus / device that includes a list of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to such process, method, article, or apparatus / device.
[0078] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.
Claims
1. A packaging test method for interconnecting bumps of different sizes based on active surface stacking of a CoW module, characterized in that The following steps are involved: S1, preparing an under-bump metallization layer on a pad at a position corresponding to a solder ball bump on an insulating layer on a surface of a lower wafer; S2: preparing copper pillar bumps at positions corresponding to the copper pillar bumps on the insulating layer on the surface of the lower wafer; S3: Align the upper chip pads with the lower wafer copper pillar bumps for mounting; S4: reflow the mounted wafer for the first time according to the corresponding reflow curve to achieve the interconnection between the upper chip and the lower wafer; S5: Use high temperature tape or protective film on the under bump metallization layer for protection; S6: Use bottom filling glue to fill between the upper chip and the lower wafer; S7: placing solder at the location of the metallization layer under the wafer bump through the stencil; S8: reflowing the wafer for the second time according to the corresponding reflow curve to prepare solder bumps on the wafer; S9: Clean the wafer to remove residual flux and excess materials; S10: Slicing the wafer to form an active surface stacking packaging structure of an upper chip and a lower chip.
2. The packaging test method for interconnecting bumps of different sizes based on active surface stacking of CoW modules according to claim 1, characterized in that: The height of the solder ball bump is greater than 150% of the sum of the thickness of the copper pillar bump and the upper chip; the solder from the inside to the outside of the copper pillar bump structure is Cu-X, Cu-Ni-X or Cu-Ni-Cu-X, wherein X is one of Ag, SnAg alloy, SnAgCu alloy, SnAgBi alloy or SnPb alloy; the solder ball bump is a tin-based solder bump, and the solder from the inside to the outside of the solder ball bump is Cu-Y, Cu-Ni-Y or Cu-Ni-Cu-Y, wherein Y is one of SnAg alloy, SnAgCu alloy or PbSn alloy, and the melting point of X is greater than the melting point of Y.
3. The packaging and testing method for interconnecting bumps of different sizes based on active surface stacking of CoW modules according to claim 1, characterized in that: The under bump metallization layer in step S1 is a multi-layer metal structure, which is Ti, Cu, Ni or Ti, Cu, Ni, Au or Ti, Cu, Ni, Cu from bottom to top.
4. The packaging test method for interconnecting bumps of different sizes based on active surface stacking of CoW modules as claimed in claim 3, characterized in that: The shape of the under-bump metallization layer is a circular, hexagonal or octagonal stepped groove, and the diameter and depth of the inner groove and the outer groove of the stepped groove match the diameter of the solder ball.
5. The packaging and testing method for interconnecting bumps of different sizes based on active surface stacking of CoW modules according to claim 1, characterized in that: In step S7, the stencil places solder at the position of the metallization layer under the wafer bump by wafer-level solder paste printing or wafer-level ball planting. When the wafer-level solder paste printing method is adopted, the solder paste is printed at the metallization layer under the solder ball bump by the solder paste printing stencil, and the solder paste printing stencil is provided with through holes matching the diameter of the metallization layer under the bump, so that the solder can leak through the through holes and be placed on the corresponding metallization layer under the bump, and the positions of the through holes correspond one to one with the positions of the bumps on the wafer surface. When the wafer-level ball planting method is adopted, the flux is printed at the position of the metallization layer under the bump by needle transfer or screen printing, and the solder ball is placed at the position of the metallization layer under the bump by the ball planting stencil. During the printing of the flux, it is necessary to avoid touching the upper chip, and the ball planting stencil is provided with through holes matching the diameter of the solder ball, so that the solder ball can leak through the through holes and be placed on the corresponding metallization layer under the bump, and the positions of the through holes correspond one to one with the positions of the bumps on the wafer surface.
6. The packaging test method for interconnecting bumps of different sizes based on active surface stacking of CoW modules as claimed in claim 5, characterized in that: The ball planting mesh plate includes three layers: an opening layer, a protective layer, and a cushioning layer. The opening layer has holes at positions corresponding to the solder balls, the protective layer has holes at positions corresponding to the solder balls and at positions of upper chips, and the cushioning layer has holes at positions corresponding to the solder balls. The cushioning layer and the protective layer are bonded together. The opening layer and the protective layer are made of metal material, and the cushioning layer is made of polymer resin material.
7. The packaging test method for interconnecting bumps of different sizes based on active surface stacking of CoW modules as claimed in claim 6, characterized in that: The diameter of the opening layer is 90%-95% or 105%-120% of the diameter of the metallization layer under the bump, and the height of the protection layer is 105%-110% of the sum of the thickness of the upper chip and the height of the copper column bump. The thickness of the stencil is controlled by adjusting the thickness of the pad layer.
8. The packaging test method for interconnecting bumps of different sizes based on active surface stacking of CoW modules as claimed in claim 5, characterized in that: The solder paste component is SnAg solder paste or SnAgCu solder paste or SnAgBi solder paste or SnAgGe solder paste or SnAgIn solder paste or PbSn solder paste, and its melting point should be lower than the metal compound on the top layer of the copper column bump structure.
9. The packaging test method for interconnecting bumps of different sizes based on active surface stacking of CoW modules according to claim 1, characterized in that: In step S4 and step S8, the wafer reflow adopts hot air reflow, vacuum reflow or hydrogen reduction reflow, and the maximum reflow temperature is positively correlated with the melting point of the solder.
10. The packaging test method for interconnecting bumps of different sizes based on active surface stacking of CoW modules according to claim 1, characterized in that: In step S3, during the alignment and mounting, the deviation between the chip pad and the copper pillar is less than 20% of the diameter of the copper pillar.