Semiconductor wafer fabrication with exposure defined graphene features

Abstract

The invention relates to semiconductor wafer fabrication with exposed defined graphene features. Selectively treating exposed portions of one or more polymeric interlayer dielectric (ILD) layers formed over a first conductive wiring layer by applying irradiation from a laser or a light source to form a graphene interconnect structure in the one or more polymeric ILD layers that is directly electrically connected to the first conductive wiring layer, and forming a back-end process integrated circuit on the integrated circuit structure having the one or more polymer ILD layers.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor devices. In one aspect, the present disclosure relates to an inter-level interconnect structure formed on a semiconductor device. Background Art

[0002] Modern integrated circuits typically have conductors formed on multiple interconnect layers or levels to accommodate dense circuit systems. These conductors can be used to transmit information in the form of signals that are sent to and from the integrated circuit system formed on the underlying substrate. After the integrated circuit system is formed on the substrate during the front-end process (FEOL) process, the existing semiconductor wafer manufacturing technology forms the inter-level interconnect structure by repeatedly performing deposition, etching, plating and polishing steps with various different layers and materials, all of which make the interconnect manufacturing process complex, time-consuming and expensive. In recent years, copper has been used to form inter-level interconnects, but as semiconductor manufacturing processes move toward future nodes that reduce interconnect stacking, the resistance and capacitance problems of the materials used to form the interconnects are increasing. In addition, as performance requirements increase, the signals passing through the interconnect conductors operate at very high frequencies, but the smaller spacing between the interconnect geometry may cause an increase in parasitic capacitance, which adversely affects the speed and power of the integrated circuit. Another negative aspect of the increase in parasitic capacitance may be the increase in signal crosstalk between adjacent and parallel conductors. Therefore, the existing interconnect manufacturing process cannot provide the cost, speed and electrical performance required for cutting-edge integrated circuit devices. Further limitations and disadvantages of conventional processes and techniques will become apparent to those skilled in the art after reviewing the remainder of the present application with reference to the accompanying drawings and detailed description. Summary of the invention

[0003] By now, it should be appreciated that an integrated circuit and associated manufacturing method have been provided. In the disclosed method, an integrated circuit structure is provided, the integrated circuit structure including one or more polymer interlayer dielectric (ILD) layers formed above a first conductive wiring layer. In selected embodiments, the integrated circuit structure has a semiconductor substrate on which a plurality of integrated circuit elements covered by an initial ILD layer and one or more polymer ILD layers are formed. In selected embodiments, the one or more polymer ILD layers include one or more ultra-low-k photosensitive polymer layers that respond to irradiation from a light source with a chemical reaction that can be used for ion exchange to impregnate a suitable metal into the exposed portion of the one or more polymer ILD layers. In other selected embodiments, the one or more polymer ILD layers include one or more non-photosensitive carbon-containing polymer layers that respond to irradiation from a laser source to form a graphene interconnect structure directly from the exposed portion of the one or more non-photosensitive carbon-containing polymer layers. The disclosed method also includes selectively processing exposed portions of the one or more polymer ILD layers by applying radiation from a laser or light source to form a graphene interconnect structure in the one or more polymer ILD layers that is directly electrically connected to the first conductive wiring layer. In selected embodiments, the exposed portions of the one or more polymer ILD layers are selectively processed by: patterning a first resist material on one of the one or more polymer ILD layers to form a first resist mask having a via opening; selectively applying radiation from a light source using the via opening of the first resist mask to selectively expose a first portion of the one or more polymer ILD layers in which a graphene via is to be formed from a graphene interconnect structure; patterning a second resist material on one of the one or more polymer ILD layers to form a second resist mask having a metal line opening; selectively applying radiation from a light source using the metal line opening of the second resist mask to selectively expose a second portion of the one or more polymer ILD layers in which a graphene wiring is to be formed from the graphene interconnect structure; applying a metal solution immersion to the first portion and the second portion of the one or more polymer ILD layers to form a metal-polyimide structure; and performing a thermal treatment to convert the metal-polyimide structure into a graphene interconnect structure.In other selected embodiments, the exposed portions of the one or more polymer ILD layers are selectively processed by: patterning a first resist material on one of the one or more polymer ILD layers to form a first resist mask having a via opening; selectively applying irradiation from a laser source to a defined first portion of the one or more polymer ILD layers using the via opening of the first resist mask to directly form a graphene via structure directly electrically connected to the first conductive wiring layer; patterning a second resist material on one of the one or more polymer ILD layers to form a second resist mask having a metal line opening; and selectively applying irradiation from a laser source to a defined second portion of the one or more polymer ILD layers using the metal line opening of the second resist mask to directly form graphene wiring directly electrically connected to the graphene via structure. In selected embodiments, the graphene interconnect structure includes a graphene wiring layer connected to the first conductive wiring layer using a graphene via structure, the graphene via structure being positioned to completely cover a maximized overlap area between the graphene wiring layer and the first conductive wiring layer.

[0004] In another form, a graphene interconnect structure and associated manufacturing method are provided. In the disclosed method, a first conductive layer is formed above a first dielectric layer. In selected embodiments, the first conductive layer is formed with a first graphene layer on the first dielectric layer, the first dielectric layer covering a plurality of integrated circuit components formed on a semiconductor substrate. The disclosed method also includes forming one or more polyimide dielectric layers above the first conductive layer. In addition, the disclosed method includes selectively applying radiation to directly or indirectly convert the one or more polyimide dielectric layers into a graphene interconnect structure including graphene wiring formed in an upper portion of the first polyimide dielectric layer and a graphene via structure formed in the first polyimide dielectric layer to directly electrically connect the graphene wiring to the first conductive layer. In selected embodiments, one or more polyimide dielectric layers are formed by depositing and planarizing an ultra-low k photosensitive polymer dielectric layer that responds to irradiation from a light source with a chemical reaction that can be used for ion exchange to impregnate a suitable metal into exposed portions of the ultra-low k photosensitive polymer dielectric layer. In selected embodiments, selectively applying radiation may include: patterning a first resist material over an ultra-low-k photosensitive polymer dielectric layer to form a first resist mask having a via opening; selectively applying radiation from a light source using the via opening of the first resist mask to selectively expose a first portion of the ultra-low-k photosensitive polymer dielectric layer, in which a graphene via will be formed from a graphene interconnect structure; patterning a second resist material over the ultra-low-k photosensitive polymer dielectric layer to form a second resist mask having a wiring opening; selectively applying radiation from a light source using the wiring opening of the second resist mask to selectively expose a second portion of the ultra-low-k photosensitive polymer dielectric layer, in which a graphene wiring will be formed from the graphene interconnect structure; applying a metal solution immersion to the first portion and the second portion of the ultra-low-k photosensitive polymer dielectric layer to form a metal-polyimide structure; and performing a thermal treatment to convert the metal-polyimide structure into a graphene interconnect structure. In other selected embodiments, one or more polyimide dielectric layers are formed by depositing and planarizing a non-photosensitive carbon-containing polymer dielectric layer that responds to irradiation from a laser source to form a graphene interconnect structure directly from exposed portions of the non-photosensitive carbon-containing polymer layer.In such embodiments, selectively applying radiation may include: patterning a first resist material over the non-photosensitive carbon-containing polymer dielectric layer to form a first resist mask having via openings; selectively applying radiation from a laser source to a defined first portion of the non-photosensitive carbon-containing polymer dielectric layer using the via openings of the first resist mask to directly form a graphene via structure directly electrically connected to the first conductive layer; patterning a second resist material over the non-photosensitive carbon-containing polymer dielectric layer to form a second resist mask having wiring openings; and selectively applying radiation from a laser source to a defined second portion of the non-photosensitive carbon-containing polymer dielectric layer using the wiring openings of the second resist mask to directly form a graphene wiring directly electrically connected to the graphene via structure. In other embodiments, radiation is selectively applied by a femtosecond UV laser source to directly convert one or more polyimide dielectric layers into a graphene interconnect structure. In selected embodiments, the graphene interconnect structure comprises a graphene wiring connected to a first conductive layer using a graphene via structure, the graphene via structure being positioned to completely cover a maximized overlap area between the graphene wiring and the first conductive layer. In other embodiments, the graphene wiring and the graphene via structure each comprise a laser-induced graphene foam structure. In selected embodiments, the disclosed method further comprises planarizing the top surface of the graphene wiring and one or more polyimide dielectric layers. In other selected embodiments, the graphene wiring and the graphene via structure are each formed as a heat-treated nickel and polyimide mixture, the heat-treated nickel and polyimide mixture being formed according to a photoinduced ion exchange reaction of nickel and polyimide.

[0005] In yet another form, an integrated circuit and an associated method of manufacturing have been provided. As disclosed, the integrated circuit includes a substrate having one or more semiconductor devices formed therein. In addition, the semiconductor device includes a multilayer graphene interconnect stack formed above the substrate to include a plurality of stacked graphene wirings, the plurality of stacked graphene wirings being vertically separated from each other by corresponding multiple polyimide interlayer dielectric (ILD) layers. Specifically, the multilayer graphene interconnect stack includes: a first graphene wiring in a first conductor layer; a second graphene wiring in a second conductor layer, the second graphene wiring being separated from the first graphene wiring by a first polyimide ILD layer; and a first graphene via structure formed in the first polyimide ILD layer, the first graphene via structure being used to electrically connect the first graphene wiring to the second graphene wiring. Each of the first graphene wiring, the second graphene wiring, and the first graphene via structure is formed as a graphene foam structure that does not include an underlying metal layer. In selected embodiments, the first graphene wiring, the second graphene wiring, and the first graphene via structure are each formed as a laser-induced graphene foam structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention and its numerous objects, features and advantages achieved will be understood when the following detailed description of the preferred embodiments is considered in conjunction with the following drawings.

[0007] Figure 1-8 Cross-sectional views of different fabrication stages of a semiconductor structure having a graphene interconnect structure formed using a photosensitive polymer interlayer dielectric layer in a selective polyimide to graphene conversion process according to selected embodiments of the present disclosure are shown.

[0008] Figure 9-14 Cross-sectional views of different fabrication stages of a semiconductor structure having a graphene interconnect structure formed using a non-photosensitive polymer interlayer dielectric layer in a selective polyimide to graphene conversion process according to selected embodiments of the present disclosure are shown.

[0009] Fig.15 An example plan view of a conductive interconnect layer of a through-hole connection made according to a conventional manufacturing process is shown.

[0010] Fig.16 An example plan view of a conductive interconnect layer of a via connection made according to selected embodiments of the present disclosure is shown.

[0011] Fig.17 A simplified process flow for fabricating a graphene interconnect structure according to selected embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0012] An integrated circuit manufacturing process and the integrated circuits produced therefrom are described for fabricating conductive interconnect structures having exposed defined graphene features formed using a selective polyimide to graphene conversion process, such that a via level can be formed from complete bonding of overlapping portions of interconnected interconnect layers, thereby significantly improving interconnect conductivity. In selected embodiments, a photosensitive polyimide dielectric layer is formed over a semiconductor wafer to cover a plurality of integrated circuits, and then covered with one or more patterned photoresist layers or masks, such that a light source can be selectively applied to convert one or more exposed portions of the photosensitive polyimide dielectric layer into an interconnect precursor structure, which is exposed to a nickel solution soak, followed by a heat treatment to convert the interconnect precursor structure into a graphene interconnect structure. In other embodiments, a non-photosensitive carbon-containing polyimide dielectric layer is formed to cover a plurality of integrated circuits on a semiconductor wafer, and then covered with one or more patterned photoresist layers, such that a laser light source can be selectively applied to convert one or more exposed portions of the non-photosensitive carbon-containing polyimide dielectric layer directly into a graphene foam interconnect structure. For example, lasers in the infrared, ultraviolet, or visible ranges can be used to directly laser one or more carbon-containing polyimide dielectric film layers into 3D porous graphene materials, which is a one-step process that does not require high temperature reaction conditions, solvents, or subsequent processing. By using a laser energy source to directly form a graphene foam interconnect structure from a carbon-containing polyimide dielectric layer, no additional barrier or liner layers, such as those used with nickel or copper-based interconnects, are required.

[0013] In the present disclosure, an improved integrated circuit design, structure and manufacturing method are described for forming a graphene interconnect structure as part of a mid-way process or a back-end process, thereby solving various problems in the art, wherein various limitations and disadvantages of conventional solutions and techniques will become apparent to those skilled in the art after reviewing the rest of the application with reference to the drawings and detailed descriptions provided herein. Various illustrative embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Although various details are set forth in the following description, it should be understood that the present invention can be practiced without these specific details, and many implementation-specific decisions can be made to the present invention described herein to achieve the specific goals of the device designer, such as compliance with process technology or related design constraints, which vary from implementation to implementation. Although this development work may be complex and time-consuming, it is nothing more than a routine task for ordinary technicians in the art who benefit from the present disclosure. For example, a simplified cross-sectional view of a semiconductor device is used to depict selected aspects, but not every device feature or geometry, so as not to limit or confuse the present invention. Such descriptions and representations are generally used by those skilled in the art to describe and convey the subject matter of their work to other technicians in the art. It should also be noted that throughout this detailed description, certain elements in the figures are shown for simplicity and clarity and are not necessarily drawn to scale. In addition, the dimensions of some elements in the figures may be exaggerated relative to other elements to help enhance understanding of the embodiments of the present disclosure. In addition, reference numerals have been repeated in the drawings to indicate corresponding or similar elements. In addition, the depicted device layers shown as being deposited and / or etched are represented by simplified line drawings, but it should be understood that in practice, for example, when the described etching processes are applied to different materials at different rates, or when the described deposition or growth processes generate layers based on underlying materials, the actual profiles or dimensions of the device layers will be non-linear.

[0014] Now refer to Figure 1-17 Various illustrative embodiments of the present invention are described in detail. In addition, although specific example materials, thicknesses and processes are described herein, it will be appreciated by those skilled in the art that other materials, thicknesses and processes with similar properties or characteristics can be substituted without loss of functionality. It should be noted that throughout this specific embodiment, certain material layers will be deposited and removed to form semiconductor structures. In the case of specific procedures for processing such layers or the thickness of such layers not described in detail below, it will be expected that such layers will be deposited, removed, formed or otherwise processed with appropriate thicknesses using techniques conventional to those skilled in the art. Such details are well known and are not considered necessary to teach those skilled in the art how to make or use the present invention.

[0015] In order to improve the understanding of selected embodiments of the present disclosure, reference is now made to Figure 1-8 , Figure 1-8 A cross-sectional view of different fabrication stages of a semiconductor structure having a graphene interconnect structure formed using a photosensitive polymer interlayer dielectric layer in a selective polyimide to graphene conversion process is shown. Specifically, Figure 1 A portion of a semiconductor structure 1 is shown in cross-section having a first photopolymer layer 12 and a graphene-coated nickel layer 11 formed on a substrate 10 in which one or more integrated circuit elements (not shown) are formed. As will be appreciated, the integrated circuit elements may include one or more transistors, resistors, capacitors, diodes, or other semiconductor components formed on or in a semiconductor substrate, which may be formed of any suitable semiconductor material or combination of materials, such as gallium arsenide, silicon germanium, semiconductor on insulator (SOI), silicon, single crystal silicon, etc. To protect the integrated circuit elements, the substrate 10 also includes an initial insulating layer (not shown) that may be formed of any suitable insulating material. For example, a planarized tetraethyl borophosphosilicate (BPTEOS) layer may form all or part of an initial interlayer dielectric (ILD0) layer that provides a gettering function to help protect the integrated circuit elements and control field leakage between semiconductor transistors.

[0016] After forming the initial ILD0 layer, a graphene-coated nickel layer 11 can be formed as a first metal line (M1) conductor layer using any suitable graphene coating technology. For example, the graphene-coated nickel layer 11 can be formed of nickel or other suitable metal materials, which are exposed to a growth process of a carbon-containing film using acetylene or other carbon-containing gases to form a graphene coating layer surrounding the patterned nickel layer. The carbon-containing gas can be part of a plasma, remote plasma, or chemical reaction process, so that elemental carbon or carbon ions interact with the nickel. As carbon diffuses through the nickel, it forms graphene on the outer surface of the nickel until the carbon reaches its solid solubility limit in the nickel. For example, by using plasma etching, excess carbon that may not be in the form of graphene, such as graphite, can be chemically removed. Alternatively, in order to form the graphene-coated nickel layer 11, the patterned nickel layer can be exposed to a plasma with some hydrogen and a controlled amount of methane, or can be exposed to a carbon-containing paste. Alternatively, the graphene-coated nickel layer 11 may be formed as a graphene foam layer by converting the polyimide layer directly into graphene without the need for patterning the metal layer using laser induced graphene technology as described more fully below.

[0017] After forming the graphene-coated nickel layer 11, a first photosensitive polymer layer 12 may be formed with a photosensitive polyimide to a predetermined thickness over the semiconductor structure using any suitable deposition technique, such as spin coating deposition, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), atmospheric pressure CVD (AP-CVD), chemical bath deposition (CBD), or any combination thereof. For example, the first polymer dielectric layer 12 may be formed of any suitable photosensitive engineering plastic or polyimide material that is imparted with photosensitivity by chemically modifying the molecular structure of a polyimide or poly(amic acid) as a polyimide precursor or by adding a low molecular weight additive (sensitizer, photoacid generator, photoradical generator, etc.) to the chemically modified polyimide or poly(amic acid). In other embodiments, the first photosensitive polymer layer 12 may be formed of any suitable ultra-low-k (ULK) photoimageable polymer. As will be appreciated by those skilled in the art, the ULK photoimageable dielectric material has a dielectric constant k value of less than about 2.5 and responds to light exposure with a chemical reaction that is then used for ion exchange to impregnate suitable metals (e.g., Cu, Ni, Co, Pd, Pt) into the photopolymer layer 12. These metal catalysts are used to reduce the temperature at which graphene is produced by a solid phase solubility reaction.

[0018] Figure 2 The following diagram shows a selected embodiment of the present disclosure. Figure 1Processing of the semiconductor structure 2 after forming a first patterned photoresist or hard mask layer 13 on the semiconductor structure. Although any suitable photoresist patterning process may be used, the first patterned photoresist mask 13 may be formed on the first photosensitive polymer layer 12 by depositing, patterning, etching or developing a photoresist layer formed of any material suitable for photolithography. For example, the first patterned photoresist layer 13 may be formed by: coating the first photosensitive polymer layer 12 with a photosensitive organic material; applying a light source with a patterned mask over the surface of the wafer substrate, the patterned mask blocking the light so that only unmasked areas of the material will be exposed to the light; and applying a solvent to develop the material so that the photosensitive material will dissolve away the areas exposed to the light due to degradation by the light and the developer, thereby leaving the coating where the mask was placed and leaving a through-hole etching opening over the first patterned photoresist or hard mask layer 13 from which the coating was removed. As depicted, the first patterned photoresist or hard mask layer 13 includes defined openings 13A that expose the underlying first photosensitive polymer layer 12 at intended etch locations for forming via etch openings over the depicted graphene-coated nickel layer 11. As indicated by dashed lines, in embodiments where laser direct writing is subsequently used to transform selected portions of the first photosensitive polymer layer 12, the first patterned photoresist or hard mask layer 13 may not be required.

[0019] Figure 3 The following diagram shows a selected embodiment of the present disclosure. Figure 2 The processing of the semiconductor structure 3 is followed by applying a photo-irradiation source 14 to the exposed polyimide region 12, thereby producing a via precursor structure 15. Although any suitable photo-irradiation source 14 may be used, an ultraviolet (UV) light source may be used to define the location of the via precursor structure 15 using the defined openings 13A in the first patterned photoresist mask 13 so as to be in direct contact with the underlying graphene-coated nickel layer 11. In yet other embodiments, the photo-irradiation source 14 may be replaced by a suitable laser source whose laser scanning operation may be controlled to apply a set of laser pulses positioned with sufficient energy to convert the exposed first photosensitive polymer layer 12 into a via precursor structure 15. Although the sidewalls of the precursor structure 15 are substantially vertical, it should be understood that slight deviations in the sidewall profile may occur due to processing variations.

[0020] Instead of developing or removing the via precursor structure 15, another photosensitive polymer layer is deposited and processed to form a metal line precursor structure in direct contact with the via precursor structure 15. To this end, Figure 4 Shows the following Figure 3The processing of the semiconductor structure 4 after the second photosensitive polymer layer 16 is formed on the first photosensitive polymer layer 12 and the through-hole precursor structure 15. Before forming the second photosensitive polymer layer 16, the first patterned photoresist layer 13 can be stripped or removed. As disclosed herein, the second photosensitive polymer layer 16 can be formed with a photosensitive polyimide to a predetermined thickness over the semiconductor structure using any suitable deposition technique. For example, the second polymer dielectric layer 16 can be formed of any suitable photosensitive engineering plastic or polyimide material, which is given photosensitivity by chemically modifying the molecular structure of polyimide or poly(amic acid) as a polyimide precursor or by adding a low molecular weight additive (sensitizer, photoacid generator, photoradical generator, etc.) to the chemically modified polyimide or poly(amic acid). In other embodiments, the second polymer dielectric layer 16 can be formed of any suitable ultra-low-k photoimageable polymer that responds to light exposure with a chemical reaction that is then used for ion exchange to impregnate a suitable metal (e.g., Cu, Ni, Co, Pd, Pt) into the photosensitive polymer layer 16.

[0021] Figure 5 The following diagram shows a selected embodiment of the present disclosure. Figure 4 Processing of semiconductor structure 5 after forming a second patterned photoresist or hard mask layer 17 on the semiconductor structure. In selected embodiments, the second patterned photoresist or hard mask layer 17 may be formed by depositing, patterning, etching, or developing a photoresist layer formed of any material suitable for photolithography. As depicted, the second patterned photoresist or hard mask layer 17 includes defined openings 17A that expose the underlying second photosensitive polymer layer 16 at the intended etching locations for forming metal line etching openings. As indicated by the dashed lines, in embodiments where laser direct writing is subsequently used to transform selected portions of the second photosensitive polymer layer 16, the second patterned photoresist or hard mask layer 17 may not be required.

[0022] Figure 6 The following diagram shows a selected embodiment of the present disclosure. Figure 5The processing of the semiconductor structure 6 is followed by applying a photo-irradiation source 18 to the exposed polyimide regions 16, thereby producing a metal line precursor structure 19 from the exposed polyimide layer 16. Although any suitable photo-irradiation source 18 may be used, an ultraviolet (UV) light source may be used to define the location of the metal line precursor structure 19 using the defined openings 17A in the second patterned photoresist mask 17 so as to be in direct contact with the underlying via precursor structure 15. In yet other embodiments, the photo-irradiation source 18 may be replaced by a suitable laser source whose laser scanning operation may be controlled to apply a set of laser pulses positioned with sufficient energy to convert the exposed second photosensitive polymer layer 16 into the metal line precursor structure 19. Although the sidewalls of the metal line structure 19 are substantially vertical, it should be understood that slight deviations in the sidewall profile may occur due to processing variations.

[0023] As disclosed above, precursor structures 15, 19 may be formed using separate resist masks 13, 17 together with separate photosensitive polyimide layers 12, 16. However, other embodiments of the present disclosure may apply a photoirradiation source to a single photosensitive polyimide layer by sequentially forming separate resist masks on the single photosensitive polyimide layer.

[0024] Instead of developing or removing the metal line precursor structure 22, the polyimide stack and the via / metal line precursor structure are treated with a metal solution immersion to form a graphene interconnect structure from the via / metal line precursor structure. To this end, Figure 7 The following diagram shows a selected embodiment of the present disclosure. Figure 6 The processing of the semiconductor structure 7 after forming the metal-polyimide structures 21, 22 by exposing the polyimide stack 12, 16 and the precursor structure 15, 19 to a metal solution soak 20. Before performing the metal solution soak 20, the second patterned photoresist layer 17 can be stripped or removed. In selected embodiments, the metal solution soak 20 can be a nickel (Ni) solution soak, wherein the acid formed by the previous light exposure step 19 causes ion exchange, which causes the Ni metal in the solution to plate through the precursor structure 15, 19. After the nickel ion displacement in the soak, the nickel adheres to the exposed polyimide area, thereby forming the nickel-polyimide structure 21, 22. Specifically, the nickel solution soak can be used to form the nickel-polyimide structure by nucleophilic substitution of a nucleophilic nickel acylate complex (or similar nucleophilic agent) with the light-exposed polyimide material in the precursor structure 15, 19. In other embodiments, the soaking solution may be used with other nucleophilic complexes using other metals (eg, Cu, Co, Pd, Pt, etc.).

[0025] Figure 8The following diagram shows a selected embodiment of the present disclosure. Figure 7 The subsequent processing of the semiconductor structure 8 after performing a heat treatment 22 to convert the metal-polyimide structures 21, 22 into graphene structures 23, 24. In selected embodiments, the heat treatment 22 may follow a multi-stage heating schedule, wherein the semiconductor structure may be heated to a first temperature (T1) less than TMAX for a first period of time, followed by a gradual increase or step-up of the temperature process to TMAX, followed by maintaining TMAX for a second period of time, followed by a cooling period of time. In one embodiment, and by way of non-limiting example only, T1 may range between approximately 100°C and 200°C, while TMAX is greater than T1 and ranges between approximately 170°C and 280°C. The process parameters employed may be controlled to completely convert the mixed Ni metal and polyimide in the metal-polyimide structures 21, 22 into highly conductive graphene vias 23 and graphene wirings 24.

[0026] In order to improve the understanding of selected embodiments of the present disclosure, reference is now made to Figure 9-14 , Figure 9-14 A cross-sectional view of different fabrication stages of a semiconductor structure having a graphene interconnect structure formed using a non-photosensitive polymer interlayer dielectric layer in a selective polyimide to graphene conversion process is shown. Specifically, Fig. 9 A portion of a semiconductor structure 9 is shown in cross-section having a first polymer dielectric layer 32 and a graphene-coated nickel layer 31 formed over a substrate 30 in which one or more integrated circuit elements (not shown), such as transistors, resistors, capacitors, diodes, or other semiconductor components, are formed. To protect the integrated circuit elements, the substrate 30 also includes an initial insulating layer (not shown) that may be formed of any suitable insulating material. For example, a planarized tetraethyl borophosphosilicate (BPTEOS) layer may form all or part of an initial interlayer dielectric (ILD0) layer that provides a gettering function to help protect the integrated circuit elements and control field leakage between semiconductor transistors.

[0027] After forming the initial ILD0 layer in the substrate 30, a graphene-coated nickel layer 31 may be formed as a first metal line (M1) conductor layer using any suitable graphene coating technique. Alternatively, the graphene-coated nickel layer 31 may be formed as a solid graphene layer by directly converting the polyimide layer into a graphene foam structure without the need for a patterned metal layer using a laser-induced graphene technique described more fully below. Alternatively, the graphene-coated nickel layer 31 may be replaced with a patterned metal line layer selectively deposited, plated, or otherwise formed on the substrate 30.

[0028] After forming the graphene-coated nickel layer 11, a first polymer dielectric layer 32 may be formed over the semiconductor structure to a predetermined thickness using any suitable deposition technique, such as spin coating, CVD, PECVD, PVD, ALD, AP-CVD, CBD, or any combination thereof. For example, the first polymer dielectric layer 32 may be formed of a non-photosensitive carbon-containing polymer dielectric material or other suitable engineering plastic or polyimide material, including but not limited to a fluorinated polyimide (PI-FP, PI-FO, and PI-FH) film, which may be prepared by polycondensation by doping p-phenylenediamine (PDA), 4-40-diaminodiphenyl ether (ODA), and 4,40-(hexafluoroisopropylidene)bis(p-phenyloxy)diphenylamine (HFPBDA) into 4,40-(hexafluoroisopropylidene)diphthalic anhydride (6FDA). More generally, the first polyimide dielectric layer 32 is formed of a material having a chemical property that interacts with laser irradiation to directly form graphene.

[0029] Fig.10 The following diagram shows a selected embodiment of the present disclosure. Fig. 9 Processing of the semiconductor structure 10 after forming a first patterned photoresist or hard mask layer 33 on the semiconductor structure. In selected embodiments, the first patterned photoresist mask 33 can be formed on the first polymer dielectric layer 32 by depositing, patterning, etching, or developing a photoresist layer formed of any material suitable for photolithography. As formed, the first patterned photoresist or hard mask layer 33 includes defined openings 33A that expose the first polymer dielectric layer 32 at intended exposure locations for forming graphene through-hole structures in the first polymer dielectric layer 32 that contact the underlying graphene-coated nickel layer 31.

[0030] Fig.11 The following diagram shows a selected embodiment of the present disclosure. Fig.10 The processing of the semiconductor structure 11 after applying a laser irradiation source 34 to directly convert the portion of the first polyimide dielectric layer 32 exposed by the first patterned photoresist mask 33 into a graphene through-hole structure 35. Although any suitable laser irradiation source 34 can be used, lasers in the infrared, ultraviolet and visible ranges can be used to provide a laser-induced graphene process that synthesizes the graphene through-hole structure 35. For example, a femtosecond UV laser can be used to directly laser irradiate a polyimide (PI) plastic film into a 3D porous graphene material, which is a one-step process that does not require high temperature reaction conditions, solvents or subsequent processing. As disclosed herein, the application of the laser irradiation source 34 should be controlled to selectively apply the energy dose required to convert the exposed portion of the first polyimide dielectric layer 32 into the graphene through-hole structure 35.

[0031] Fig.12 Shows the following Fig.11 The semiconductor structure 12 is then processed after forming the second polymer dielectric layer 36 on the first polymer dielectric layer 32 and the graphene through-hole structure 35. After stripping or removing the first patterned photoresist layer 33, the second polymer dielectric layer 36 can be formed on the semiconductor structure to a predetermined thickness using any suitable deposition technique. For example, the second polymer dielectric layer 36 can be formed of a non-photosensitive carbon-containing polymer dielectric material or other suitable engineering plastic or polyimide material, including but not limited to fluorinated polyimide (PI-FP, PI-FO and PI-FH) film, which can be prepared by polycondensation by doping p-phenylenediamine (PDA), 4-40-diaminodiphenyl ether (ODA) and 4,40-(hexafluoroisopropylidene)bis(p-phenyloxy)diphenylamine (HFPBDA) into 4,40-(hexafluoroisopropylidene)diphthalic anhydride (6FDA). More generally, the second polymer dielectric layer 36 may be formed of a material having a chemical property that interacts with laser irradiation to directly form graphene.

[0032] Fig.13 The following diagram shows a selected embodiment of the present disclosure. Fig.12 Processing of the semiconductor structure 13 after forming a second patterned photoresist or hard mask layer 37 on the semiconductor structure. In selected embodiments, the second patterned photoresist or hard mask layer 37 can be formed by depositing, patterning, etching, or developing a photoresist layer formed of any material suitable for photolithography. As formed, the second patterned photoresist or hard mask layer 37 includes a defined opening 37A that exposes the underlying second polymer dielectric layer 36 at the intended exposure location for forming a graphene wiring structure in at least the second polymer dielectric layer 36 that contacts the underlying graphene via structure 35.

[0033] Fig.14 The following diagram shows a selected embodiment of the present disclosure. Fig.13The processing of the semiconductor structure 14 after applying a laser irradiation source 38 to directly convert the portion of the second polyimide dielectric layer 36 exposed by the second patterned photoresist mask 37 into a graphene wiring structure 39. Although any suitable laser irradiation source 38 can be used, a femtosecond UV laser can be used to directly laser irradiate a polyimide (PI) plastic film into a 3D porous graphene material, which is a one-step method that does not require high temperature reaction conditions, solvents, or subsequent processing. As disclosed herein, the application of the laser irradiation source 38 should be controlled to selectively apply the desired energy dose for converting at least the exposed portion of the second polyimide dielectric layer 36 into a graphene wiring structure 39.

[0034] As disclosed above, graphene via structures 35 and graphene wiring structures 39 may be formed from separate non-photosensitive polyimide layers 32, 36 using separate resist masks 33, 37. However, other embodiments of the present disclosure may apply a laser irradiation source to a single polyimide dielectric layer (e.g., 32) by sequentially forming separate resist masks on the single polyimide dielectric layer. In such embodiments where the intended graphene via structures 35 and metal wire structures 39 have different depth profiles, the application of the laser irradiation source should be controlled to selectively apply the energy dose required to convert the single polyimide dielectric layer into the graphene interconnect structures 35, 39. For example, the laser scanning operation may be controlled to apply a first set of laser pulses positioned with sufficient energy to convert the entirety of a single polyimide dielectric layer at a first exposure location into a graphene via structure 35, and to apply a second set of laser pulses positioned with sufficient energy to convert an upper portion of the single polyimide dielectric layer at a second exposure location into a graphene wiring structure 39. By appropriately constructing the polyimide dielectric layers 32, 36 with a material that is non-photosensitive but reactive to one or more laser radiation sources, graphene interconnect structures 35, 39 may be selectively formed in semiconductor structures to provide reduced resistivity and processing complexity compared to prior art techniques that use metal conductors (e.g., copper or nickel) to form conductive interconnect structures.

[0035] As will be appreciated, the graphene interconnect fabrication sequence described above may be repeated one or more times to form multiple graphene interconnect layers or levels above the substrate. For example, a second graphene interconnect structure may be formed in one or more additional polyimide dielectric layers by selectively applying a laser irradiation source to convert exposed portions of the additional polyimide dielectric layers into a second graphene wiring interconnect structure, thereby forming a second interlayer dielectric (ILD2) layer formed on the first ILD1 layer.

[0036] The last or topmost metal layer in the semiconductor structure can be formed of any conductive material, such as laser-induced graphene, aluminum, copper, tantalum, tungsten, tantalum nitride, tungsten nitride, titanium, titanium nitride, etc., and combinations thereof. As formed, each of the last metal layers is coupled to one or more integrated circuit elements (not shown) in the substrate via an intermediate graphene interconnect structure (e.g., 35, 39) formed within an ILD layer of an interconnect stack, which can be formed of any suitable polyimide dielectric layer. Although the specific arrangement, construction, and connection of the different conductive interconnect layers are not important, each conductive interconnect layer can be constructed within a constituent polyimide dielectric layer in the interconnect stack by directly converting the polyimide dielectric layer into a graphene interconnect structure using a masked laser irradiation source, as disclosed herein.

[0037] In order to enhance the contextual understanding of the present disclosure, reference is now made to Fig.15 , Fig.15 Example plan view showing conductive interconnect stacking Fig.15 , wherein the metal wire layers M2 and M3 are connected together by a through-hole structure VIA2 made according to a conventional manufacturing process. Specifically, the bottom metal wire layer M2 extends through a first defined path, which is positioned below the upper metal wire layer M3 extending through a second defined path. At selected overlapping points between the metal wire layers M2 and M3, one or more through-hole structures VIA2 are formed. Disadvantageously, conventional manufacturing tools limit each of the through-hole structures VIA2 to have a predetermined or defined shape, such as a circle or a rectangle. In addition, there are placement constraints that prevent two or more through-hole structures VIA2 from being placed adjacent to each other. For example, there are lateral spacing constraints generated by existing patterned masks and etching tools, which prevent the through-hole gaps 41-43 from being filled with additional through-hole structures VIA2 because the additional through-hole structures VIA2 will be adjacent to or overlap with the through-hole structures VIA2 44-46.

[0038] In order to improve the understanding of selected embodiments of the present disclosure, reference is now made to Fig.16 , Fig.16 Example plan view showing conductive interconnect stacking Fig.16, wherein the metal wire layers M2, M3 are connected together by a maximized via structure VIA2. Likewise, the bottom metal wire layer M2 extends through a first defined path, which is positioned below the upper metal wire layer M3 extending through a second defined path. However, by selectively applying laser irradiation using one or more photoresist masks to convert one or more polyimide layers directly into graphene via structures located at the overlap region between the bottom metal wire layer M2 and the upper metal wire layer M3, the resulting laser defined via structures VIA2 51, 52 provide maximized via connections between the metal wire layers M2, M3, thereby improving the conductivity of the conductive interconnect stack.

[0039] Now turn to reference Fig.17 , showing a simplified process flow for manufacturing a graphene interconnect structure according to selected embodiments of the present disclosure 17. Although described herein with reference to an example back-end process manufacturing process, it should be understood by those skilled in the art that the sequence of steps shown can be used at any suitable stage of the device manufacturing process and can be modified, streamlined or amplified according to the disclosure of the present invention. Therefore, it should be understood that the method of the present disclosure can be viewed as following Fig.17 The identified sequence of steps is performed in the order described in the specification, but the steps may also be performed in parallel, in a different order, or as combined independent operations.

[0040] After starting at step 101, the disclosed manufacturing method begins with one or more front-end-of-line (FEOL) processing steps 102 for fabricating one or more integrated circuit elements (e.g., transistors, capacitors, resistors, diodes, etc.) in a wafer substrate. Generally speaking, FEOL processing is the first part of IC manufacturing where individual components (transistors, capacitors, resistors, etc.) are patterned in the semiconductor and typically covers everything up to (but not including) the deposition of conductive interconnect layers.

[0041] At step 103, one or more first ILD interconnects with attached first metal (M1) lines are formed over the wafer substrate. Example first ILD interconnects may include an initial interlayer dielectric (ILD0) layer formed over the integrated circuit element by depositing, spin coating, or otherwise forming a silicon dioxide layer. In the initial ILD0 layer, a contact may be formed extending through the initial ILD0 layer to one end of the integrated circuit element (e.g., a source / drain region of a transistor device), for example by selectively etching a contact opening and then filling the opening with one or more conductive via layers. In contact with the contact, a first metal (M1) layer may be selectively formed over the initial ILD0 layer, for example by depositing a conductive metal layer over the wafer substrate, which is then patterned and etched to leave an M1 layer. In other embodiments, the M1 layer may be formed by selectively etching metal line etch openings in the initial ILD0 layer, filling the metal line etch openings with one or more polyimide layers, and then selectively applying a laser beam of appropriate energy dose and intensity to convert the one or more polyimide layers directly into a graphene M1 metal line layer. In other embodiments, the M1 layer may be formed as a graphene-coated nickel layer using any suitable graphene coating technology.

[0042] At step 104, a first polyimide layer is deposited and planarized over the wafer substrate. An example polyimide layer may be formed of a photosensitive polymer dielectric material having a dielectric constant k value less than about 2.5, formed to a predetermined thickness using any suitable deposition technique, such as CVD, PECVD, PVD, ALD, AP-CVD, CBD, or any combination thereof. Example photosensitive polymer dielectric materials include, but are not limited to, photosensitive engineering plastics or polyimide materials that are rendered photosensitive by chemically modifying the molecular structure of polyimide or poly(amic acid) as a polyimide precursor or by adding low molecular weight additives (sensitizers, photoacid generators, photoradical generators, etc.) to the chemically modified polyimide or poly(amic acid). In other embodiments, the first polyimide layer may be formed of a non-photosensitive carbon-containing polymer dielectric that responds to laser irradiation to directly form graphene. Examples of non-photosensitive carbon-containing polymer dielectric materials include, but are not limited to, fluorinated polyimide (PI-FP, PI-FO, and PI-FH) films, which can be prepared by polycondensation by doping p-phenylenediamine (PDA), 4-40-diaminodiphenyl ether (ODA), and 4,40-(hexafluoroisopropylidene)bis(p-phenyloxy)diphenylamine (HFPBDA) into 4,40-(hexafluoroisopropylidene)diphthalic anhydride (6FDA), respectively.

[0043] At step 105, a first photoresist and / or mask layer having a patterned through-hole etch opening is formed over the first polyimide layer, the patterned through-hole etch opening exposing a portion of the first polyimide layer. In selected embodiments, the first photoresist mask is formed by: coating the first polyimide layer with a photosensitive organic material; applying a light source having a patterned mask over the surface of the wafer substrate, the patterned mask blocking the light so that only unmasked areas of the material will be exposed to the light; and applying a solvent to develop the material so that the photosensitive material will dissolve away the areas exposed to the light due to degradation by the light and the developer, thereby leaving the coating where the mask was placed and leaving through-hole etch openings over the first polyimide layer from which the coating was removed.

[0044] In selected embodiments where the first polymer layer is a first photoimageable polyimide layer, the sequence of graphene interconnect fabrication steps continues with step 106 by selectively applying light to a portion of the first photoimageable polyimide layer exposed by the first photoresist mask, thereby forming a via precursor structure in the first photoimageable polyimide layer. In selected embodiments, the via precursor structure extends through the entirety of the first photoimageable polyimide layer to contact the M1 layer.

[0045] At step 107, after removing the first photoresist mask, a second photoimageable polyimide layer is formed over the semiconductor structure. The example second photoimageable polyimide layer can be formed of any suitable high performance polymer material having optical and dielectric properties such that the polymer material responds to light exposure with a chemical reaction that allows for an ion exchange reaction with nickel (or other suitable metal catalyst for graphene production). In selected embodiments, the second photoimageable polyimide layer can be deposited to a predetermined thickness using any suitable deposition technique (e.g., CVD, PECVD, PVD, ALD, AP-CVD, CBD, or any combination of the foregoing), and can then be planarized by applying CMP or other planarization steps to the second photoimageable polyimide layer.

[0046] At step 108, a second photoresist and / or mask layer having patterned metal line etch openings is formed over the second photoimageable polyimide layer, the patterned metal line etch openings exposing a portion of the second photoimageable polyimide layer. In selected embodiments, the second photoresist mask is formed using any suitable photoresist / mask formation sequence.

[0047] At step 109, light is selectively applied to a portion of the second photoimageable polyimide layer exposed by the second photoresist mask, thereby forming a metal line precursor structure in the second photoimageable polyimide layer. In selected embodiments, the metal line precursor structure extends downward through at least the second photoimageable polyimide layer to contact the via precursor structure.

[0048] At step 110, a metal soak solution is applied to the polyimide layer stack, which includes a first photoimageable polyimide layer and a second photoimageable polyimide layer and a via precursor structure and a metal line precursor structure. In selected embodiments, the metal soak solution is a nickel (Ni) solution soak, wherein the acid formed by the previous light exposure step (steps 106, 109) causes the Ni metal in the solution to plate through the via / metal line precursor structure to form a nickel-polyimide structure by enabling nucleophilic acylated nickel complex (or similar nucleophilic agent) to undergo nucleophilic substitution with the light-exposed polyimide material in the precursor structure.

[0049] At step 111, a thermal treatment step is applied to convert the via and metal line precursor structures into highly conductive graphene vias and wirings. In selected embodiments, the thermal treatment step may apply a specified heat budget so that the mixed nickel metal and polyimide materials in the via / metal line precursor structures are converted into graphene via and wiring conductors.

[0050] In selected embodiments where the first polymer layer is a first non-photoimageable polyimide layer, the sequence of graphene interconnect fabrication steps continues to step 112 by selectively applying a laser radiation source to a portion of the first non-photoimageable polyimide layer exposed by the first photoresist mask, thereby directly forming a graphene via structure in the first non-photoimageable polyimide layer. In selected embodiments, the graphene via structure extends through the entirety of the first non-photoimageable polyimide layer to contact the M1 layer.

[0051] At step 113, after removing the first photoresist mask, a second non-photoimageable polyimide layer is formed over the semiconductor structure. Example The second non-photoimageable polyimide layer can be formed of any suitable high performance polymer material, including but not limited to fluorinated polyimide (PI-FP, PI-FO, and PI-FH) films having optical and dielectric properties such that the polymer material responds to laser irradiation to directly form graphene. In selected embodiments, the second non-photoimageable polyimide layer can be deposited to a predetermined thickness using any suitable deposition technique (e.g., CVD, PECVD, PVD, ALD, AP-CVD, CBD, or any combination of the foregoing), and can then be planarized by applying CMP or other planarization steps to the second non-photoimageable polyimide layer.

[0052] At step 114, after removing the first photoresist mask, a second photoresist and / or mask layer is formed over the second non-photoimageable polyimide layer, wherein the second photoresist mask includes patterned metal line etch openings that expose a portion of the second non-photoimageable polyimide layer. In selected embodiments, the second photoresist mask is formed using any suitable photoresist / mask formation sequence.

[0053] At step 115, a laser radiation source is selectively applied to a portion of the second non-photoimageable polyimide layer exposed by the second photoresist mask, thereby forming a graphene wiring structure directly in the second non-photoimageable polyimide layer. In selected embodiments, the graphene wiring structure extends downward through at least the second non-photoimageable polyimide layer to contact the graphene via structure.

[0054] At step 116 , the manufacturing process flow ends, but it should be understood that additional back-end processing may be performed to complete the manufacturing of the integrated circuit structure, such as packaging, scribing, die separation, testing, etc.

[0055] As described above, the present disclosure provides a mechanism for manufacturing graphene interconnects by selectively exposing a polyimide dielectric layer as part of an unusually planar BEOL flow, which selective exposure does not require special metal, barrier or liner layers for graphene contact and avoids the most complex and expensive BEOL operations while providing the highest known conductivity. In addition to reducing manufacturing cost and complexity, the disclosed mechanism for integrating graphene interconnects provides advantages in reliability and yield by reducing or eliminating stress migration, electromigration or plasma-induced damage.

[0056] Although the described exemplary embodiments disclosed herein relate to various semiconductor and integrated circuit device structures and methods for manufacturing the same, the present invention is not necessarily limited to exemplary embodiments illustrating inventive aspects of the present invention applicable to a wide variety of semiconductor processes and / or devices. Therefore, the specific embodiments disclosed above are merely illustrative and should not be regarded as limitations on the present invention, as the present invention may be modified and practiced in different but equivalent ways, which are obvious to those skilled in the art who benefit from the teachings herein. Therefore, the foregoing description is not intended to limit the present invention to the specific form set forth, but on the contrary, is intended to cover such alternatives, modifications and equivalents as may be included in the spirit and scope of the present invention as defined by the appended claims, so that those skilled in the art should understand that they may make various changes, substitutions and variations in its broadest form without departing from the spirit and scope of the present invention.

[0057] Benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, these benefits, advantages, solutions to problems, and any elements that may make any benefit, advantage, or solution occur or become more obvious should not be construed as important, necessary, or essential features of the elements of any or all claims. As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover non-exclusive inclusions such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but may also include other elements that are not explicitly listed or inherent to such processes, methods, articles, or apparatus.

Claims

1. A method for manufacturing an integrated circuit, characterized in that include: providing an integrated circuit structure comprising one or more polymer interlayer dielectric (ILD) layers formed over a first conductive wiring layer; as well as Exposed portions of the one or more polymer ILD layers are selectively processed by applying radiation from a laser or light source to form a graphene interconnect structure in the one or more polymer ILD layers that is directly electrically connected to the first conductive wiring layer.

2. The method according to claim 1, characterized in that The one or more polymer ILD layers include one or more ultra low k photosensitive polymer layers that respond to irradiation from a light source with a chemical reaction that can be used for ion exchange to impregnate a suitable metal into the exposed portions of the one or more polymer ILD layers.

3. The method according to claim 1, characterized in that Selectively processing the exposed portions of the one or more polymer ILD layers includes: patterning a first resist material on one of the one or more polymer ILD layers to form a first resist mask having a via opening; selectively applying radiation from a light source using the via openings of the first resist mask to selectively expose first portions of the one or more polymer ILD layers in which graphene vias are to be formed from the graphene interconnect structure; patterning a second resist material on one of the one or more polymer ILD layers to form a second resist mask having metal line openings; selectively applying radiation from the light source using the metal line openings of the second resist mask to selectively expose second portions of the one or more polymer ILD layers in which graphene wiring is to be formed from the graphene interconnect structure; soak applying a metal solution to the first portion and the second portion of the one or more polymer ILD layers to form a metal-polyimide structure; and A thermal treatment is performed to convert the metal-polyimide structure into the graphene interconnect structure.

4. The method according to claim 1, characterized in that Selectively processing the exposed portions of the one or more polymer ILD layers includes: patterning a first resist material on one of the one or more polymer ILD layers to form a first resist mask having a via opening; selectively applying radiation from a laser source to defined first portions of the one or more polymer ILD layers using the via openings of the first resist mask to directly form a graphene via structure directly electrically connected to the first conductive wiring layer; patterning a second resist material on one of the one or more polymer ILD layers to form a second resist mask having metal line openings; and Irradiation from a laser source is selectively applied to defined second portions of the one or more polymer ILD layers using the metal line openings of the second resist mask to directly form graphene wiring lines that are directly electrically connected to the graphene via structures.

5. A method for forming a graphene interconnect structure, characterized in that: include: forming a first conductive layer over the first dielectric layer; forming one or more polyimide dielectric layers over the first conductive layer; Irradiation is selectively applied to convert the one or more polyimide dielectric layers into the graphene interconnect structure including graphene wiring formed in an upper portion of a first polyimide dielectric layer and a graphene via structure formed in the first polyimide dielectric layer to electrically connect the graphene wiring directly to the first conductive layer.

6. The method according to claim 5, characterized in that Forming one or more polyimide dielectric layers includes depositing and planarizing an ultra low k photosensitive polymer dielectric layer that responds to irradiation from a light source with a chemical reaction that can be used for ion exchange to impregnate a suitable metal into exposed portions of the ultra low k photosensitive polymer dielectric layer.

7. The method according to claim 6, characterized in that Selective applications of radiation include: patterning a first resist material over the ultra low k photosensitive polymer dielectric layer to form a first resist mask having via openings; selectively applying radiation from a light source using the via openings of the first resist mask to selectively expose a first portion of the ultra-low-k photosensitive polymer dielectric layer in which a graphene via is to be formed from the graphene interconnect structure; patterning a second resist material over the ultra low k photosensitive polymer dielectric layer to form a second resist mask having wiring openings; selectively applying radiation from the light source using the wiring openings of the second resist mask to selectively expose a second portion of the ultra-low-k photosensitive polymer dielectric layer in which graphene wirings are to be formed from the graphene interconnect structure; applying a metal solution by immersion to the first portion and the second portion of the ultra low k photosensitive polymer dielectric layer to form a metal-polyimide structure; and A thermal treatment is performed to convert the metal-polyimide structure into the graphene interconnect structure.

8. The method according to claim 5, characterized in that Forming one or more polyimide dielectric layers includes depositing and planarizing a non-photosensitive carbon-containing polymer dielectric layer that responds to irradiation from a laser source to form the graphene interconnect structure directly from exposed portions of the non-photosensitive carbon-containing polymer layer.

9. The method according to claim 8, characterized in that Selective applications of radiation include: patterning a first resist material over the non-photosensitive carbon-containing polymer dielectric layer to form a first resist mask having via openings; selectively applying irradiation from a laser source to a defined first portion of the non-photosensitive carbon-containing polymer dielectric layer using the via openings of the first resist mask to directly form a graphene via structure directly electrically connected to the first conductive layer; patterning a second resist material over the non-photosensitive carbon-containing polymer dielectric layer to form a second resist mask having wiring openings; and Irradiation from the laser source is selectively applied to a defined second portion of the non-photosensitive carbon-containing polymer dielectric layer using the wiring openings of the second resist mask to directly form graphene wirings that are directly electrically connected to the graphene via structures.

10. An integrated circuit, characterized in that: include: a substrate including one or more semiconductor devices formed therein; as well as A multi-layer graphene interconnect stack, the multi-layer graphene interconnect stack formed above the substrate, including a plurality of stacked graphene wirings, the plurality of stacked graphene wirings being vertically separated from each other by corresponding plurality of polyimide interlayer dielectric (ILD) layers, the multi-layer graphene interconnect stack comprising: a first graphene wiring in a first conductor layer, a second graphene wiring in a second conductor layer, the second graphene wiring being separated from the first graphene wiring by a first polyimide ILD layer, and a first graphene through-hole structure formed in the first polyimide ILD layer, the first graphene through-hole structure being used to electrically connect the first graphene wiring to the second graphene wiring; The first graphene wiring, the second graphene wiring, and the first graphene via structure each include a graphene foam structure that does not include an underlying metal layer.

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