Contact hole forming method, semiconductor device and chip

Abstract

The invention provides a contact hole forming method, a semiconductor device and a chip, and relates to the technical field of semiconductors. The contact hole forming method comprises the following steps: etching a semiconductor device from a contact hole delimiting position on the surface of the semiconductor device, and removing an interlayer dielectric layer and a part of an etching stop layer at the contact hole delimiting position; a metal silicide layer, an etching stop layer and an interlayer dielectric layer are sequentially formed at the delimited position of the contact hole from bottom to top; removing the residual etching stop layer at the delimited position of the contact hole by using a silicon-cobalt-nickel etching process; forming a side wall barrier layer on the side wall of the delimited contact hole, and forming a bottom barrier layer at the bottom of the delimited contact hole; removing a part of the bottom barrier layer by using an etching process; and filling a metal contact material in the delimited contact hole to form the contact hole. According to the invention, the excessive consumption of the metal silicide can be reduced, the lateral growth abnormity of the silicide is prevented, the thickness of the bottom barrier layer and the resistance of the contact hole are reduced, and the performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a contact hole forming method, a semiconductor device and a chip. Background Art

[0002] The manufacturing process of semiconductor integrated circuits is extremely complicated. It is necessary to first produce various electronic components required for a specific circuit on a silicon wafer, and then form an electrical connection between the various electronic components through internal connecting wires to form a specific circuit and realize the function of the specific circuit. Among them, in order to realize the electrical connection between the multi-layer circuits on the silicon wafer, a large number of contact holes need to be made. The performance of these contact holes has an important impact on the overall performance of the circuit.

[0003] In the prior art, after a semiconductor device is formed on a substrate, an etching stop layer and an interlayer dielectric layer are sequentially formed on the surface of the substrate, and then the interlayer dielectric layer and the etching stop layer are etched to expose the metal silicide underneath. Then, a sidewall barrier layer and a bottom barrier layer are formed on the sidewall and bottom of the contact hole, and then metal is filled to form the final contact hole. Traditional contact hole processes will perform excessive etching on the etching stop layer to ensure that the contact holes in different areas can be etched with complete patterns. Excessive etching will cause a certain degree of consumption of the metal silicide, and there is an argon cleaning step in the subsequent contact hole sidewall filling process, which will also consume the metal silicide. After two steps of consuming the metal silicide, the final metal silicide is excessively consumed. Due to the reaction of the deposited Ti with Si, the silicide grows abnormally laterally, and the barrier layer at the bottom of the contact hole is too thick, resulting in excessive resistance of the contact hole, which in turn affects the device performance. Summary of the invention

[0004] In view of the technical problems in the prior art such as excessive consumption of metal silicide, excessive thickness of the bottom barrier layer, and excessive resistance of the contact hole, which in turn affect the performance of the device, the present invention provides a contact hole forming method, a semiconductor device and a chip. The contact hole forming method can reduce the excessive consumption of metal silicide, prevent abnormal lateral growth of silicide caused by excessive loss of metal silicide, reduce the thickness of the bottom barrier layer, reduce the resistance of the contact hole, and improve the device performance.

[0005] To achieve the above-mentioned purpose, the first aspect of the present invention provides a contact hole forming method, which comprises: etching a semiconductor device from a contact hole demarcated position on the surface of the semiconductor device, and removing an interlayer dielectric layer and a portion of an etch stop layer at the contact hole demarcated position; wherein a metal silicide layer, an etch stop layer and an interlayer dielectric layer are sequentially formed from bottom to top at the contact hole demarcated position on the surface of the semiconductor device; removing the remaining etch stop layer at the contact hole demarcated position by a silicon-cobalt-nickel etching process to expose the metal silicide layer in the demarcated contact hole; forming a sidewall barrier layer on the sidewall of the demarcated contact hole, and forming a bottom barrier layer at the bottom of the demarcated contact hole; removing a portion of the bottom barrier layer by an etching process; and filling the demarcated contact hole with a metal contact material to form a contact hole.

[0006] Furthermore, the etching gas used for etching the semiconductor device from the designated position of the contact hole on the surface of the semiconductor device includes one or more of C4F8, CH2F2, CHF3, CF4, CO2, O2 and Ar, the etching gas flow rate is between 10sccm-200sccm, the pressure of the etching chamber is between 20mTorr-100mTorr, the etching source power is between 300W-2800W, the etching bias power is between 300W-2800W, and the etching time is between 8s-100s.

[0007] Further, after removing part of the etch stop layer in the defined contact hole, the thickness of the remaining etch stop layer in the defined contact hole is between

[0008] Furthermore, the etching gas used in the silicon-cobalt-nickel etching process includes one or more of NF3, NH3, H2 and He, the etching gas flow rate is between 10sccm-100sccm, the pressure of the etching chamber is between 3mTorr-10mTorr, the etching source power is between 20W-40W, and the etching time is between 5s-10s.

[0009] Further, after a portion of the bottom barrier layer is removed by an etching process, the thickness of the remaining bottom barrier layer is between

[0010] Furthermore, removing part of the bottom barrier layer by using an etching process includes: removing part of the bottom barrier layer by using a dry etching process.

[0011] Furthermore, the etching gas used in the dry etching process includes one or more of CHF3, CL2 and CF4, the etching gas flow rate is between 10sccm-60sccm, the pressure of the etching chamber is between 5mTorr-20mTorr, the etching bias power is between 30W-100W, and the etching time is between 5s-60s.

[0012] Furthermore, the side wall barrier layer and the bottom barrier layer are made of TiN material.

[0013] A second aspect of the present invention provides a semiconductor device, comprising a copper metal layer formed by the contact hole forming method described above.

[0014] A third aspect of the present invention provides a chip, which includes the semiconductor device described above.

[0015] Through the technical solution provided by the present invention, the present invention has at least the following technical effects:

[0016] The contact hole forming method of the present invention first etches the semiconductor device from the contact hole demarcation position on the surface of the semiconductor device, and removes the interlayer dielectric layer and part of the etching stop layer at the contact hole demarcation position; wherein, the contact hole demarcation position on the surface of the semiconductor device is sequentially formed with a metal silicide layer, an etching stop layer and an interlayer dielectric layer from bottom to top. Then, a silicon-cobalt-nickel etching process is used to remove the remaining etching stop layer at the contact hole demarcation position to expose the metal silicide layer in the demarcated contact hole, and then a sidewall barrier layer is formed on the sidewall of the demarcated contact hole, and a bottom barrier layer is formed at the bottom of the demarcated contact hole, and a part of the bottom barrier layer is removed by an etching process, and finally a metal contact material is filled in the demarcated contact hole to form a contact hole. Through the present invention, it is possible to reduce excessive consumption of metal silicide, prevent abnormal lateral growth of silicide caused by excessive loss of metal silicide, reduce the thickness of the bottom barrier layer, reduce the resistance of the contact hole, and improve device performance.

[0017] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0019] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0020] Figure 1 A flow chart of a contact hole forming method provided by an embodiment of the present invention;

[0021] Figure 2 A schematic structural diagram of a metal silicide layer, an etch stop layer and an interlayer dielectric layer formed in an embodiment of a contact hole forming method provided in an embodiment of the present invention;

[0022] Figure 3 A schematic structural diagram of removing an interlayer dielectric layer and a portion of an etch stop layer in a defined contact hole in an embodiment of a contact hole forming method provided in an embodiment of the present invention;

[0023] Figure 4 A schematic structural diagram of removing the remaining etch stop layer in an embodiment of the contact hole forming method provided in an embodiment of the present invention;

[0024] Figure 5 A schematic structural diagram of a bottom barrier layer and a sidewall barrier layer formed in an embodiment of a contact hole forming method provided in an embodiment of the present invention;

[0025] Figure 6 A schematic structural diagram of removing part of the bottom barrier layer and the filled metal contact material in an embodiment of the contact hole forming method provided in an embodiment of the present invention.

[0026] Description of Reference Numerals

[0027] 1-metal silicide layer; 2-etching stop layer; 3-interlayer dielectric layer; 4-bottom barrier layer; 5-sidewall barrier layer; 6-metal contact material. DETAILED DESCRIPTION

[0028] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.

[0029] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0030] In the present invention, unless otherwise specified, directional words such as "up, down, top, bottom" are usually used to describe the relative positional relationship of components in the direction shown in the drawings or in the vertical, perpendicular or gravity direction.

[0031] As the background technology, the performance of existing semiconductor devices is relatively poor.

[0032] Please refer to Figure 1According to a first aspect of an embodiment of the present invention, a contact hole forming method is provided, the method comprising: S101: etching a semiconductor device from a contact hole demarcated position on the surface of the semiconductor device, and removing an interlayer dielectric layer 3 and a portion of an etching stop layer 2 at the contact hole demarcated position; wherein, a metal silicide layer 1, an etching stop layer 2 and an interlayer dielectric layer 3 are sequentially formed from bottom to top at the contact hole demarcated position on the surface of the semiconductor device; S102: removing the remaining etching stop layer 2 at the contact hole demarcated position by a silicon-cobalt-nickel etching process to expose the metal silicide layer 1 in the demarcated contact hole; S103: forming a sidewall barrier layer 5 on the sidewall of the demarcated contact hole, and forming a bottom barrier layer 4 at the bottom of the demarcated contact hole; S104: removing a portion of the bottom barrier layer 4 by an etching process; S105: filling a metal contact material 6 in the demarcated contact hole to form a contact hole.

[0033] Specifically, step S101 is first performed: the semiconductor device is etched from the contact hole demarcated position on the surface of the semiconductor device to remove the interlayer dielectric layer 3 and part of the etching stop layer 2 at the contact hole demarcated position; wherein the contact hole demarcated position on the surface of the semiconductor device is sequentially formed with a metal silicide layer 1, an etching stop layer 2 and an interlayer dielectric layer 3 from bottom to top.

[0034] Furthermore, the etching gas used for etching the semiconductor device from the designated position of the contact hole on the surface of the semiconductor device includes one or more of C4F8, CH2F2, CHF3, CF4, CO2, O2 and Ar, the etching gas flow rate is between 10sccm-200sccm, the pressure of the etching chamber is between 20mTorr-100mTorr, the etching source power is between 300W-2800W, the etching bias power is between 300W-2800W, and the etching time is between 8s-100s.

[0035] Further, after removing part of the etch stop layer 2 in the defined contact hole, the thickness of the remaining etch stop layer 2 in the defined contact hole is between

[0036] Specifically, in the embodiment of the present invention, NMOS and PMOS formed on a substrate are used as examples of semiconductor devices. After the semiconductor device is formed on the substrate, a metal silicide layer 1 is formed at a contact hole defined position on the surface of the semiconductor device, and then an etching stop layer 2 and an interlayer dielectric layer 3 are formed on the surface of the substrate. Figure 2 The photoresist shown in the figure is exposed and developed according to the contact hole demarcation position to form an etching window on the photoresist, and the interlayer dielectric layer 3 and the etching stop layer 2 are etched in sequence through the etching window to remove the interlayer dielectric layer 3 and part of the etching stop layer 2 at the contact hole demarcation position, thereby obtaining Figure 3 The structure shown.

[0037] The etching gas used in the etching process includes one or more of C4F8, CH2F2, CHF3, CF4, CO2, O2 and Ar, the etching gas flow rate is between 10sccm-200sccm, the pressure of the etching chamber is between 20mTorr-100mTorr, the etching source power is between 300W-2800W, the etching bias power is between 300W-2800W, and the etching time is between 8s-100s. After removing part of the etching stop layer 2 in the designated contact hole, the thickness of the remaining etching stop layer 2 in the designated contact hole is between

[0038] Then, step S102 is performed: the remaining etching stop layer 2 at the defined position of the contact hole is removed by using a silicon-cobalt-nickel etching process to expose the metal silicide layer 1 in the defined contact hole.

[0039] Furthermore, the etching gas used in the silicon-cobalt-nickel etching process includes one or more of NF3, NH3, H2 and He, the etching gas flow rate is between 10sccm-100sccm, the pressure of the etching chamber is between 3mTorr-10mTorr, the etching source power is between 20W-40W, and the etching time is between 5s-10s.

[0040] Specifically, in the embodiment of the present invention, after removing part of the etch stop layer 2, the remaining etch stop layer 2 is further etched using a silicon-cobalt-nickel (SiCoNi) etching process to obtain Figure 4 The structure shown. The silicon-cobalt-nickel etching process has a high selectivity for the etching stop layer 2, can effectively remove the remaining etching stop layer 2, will not cause excessive damage to the metal silicide layer 1 below, and prevents excessive loss of metal silicide, which causes the subsequent deposition of Ti and Si to react and cause abnormal lateral growth of silicide. The etching gas used in the silicon-cobalt-nickel etching process includes one or more of NF3, NH3, H2 and He, the etching gas flow rate is between 10sccm-100sccm, the pressure of the etching chamber is between 3mTorr-10mTorr, the etching source power is between 20W-40W, and the etching time is between 5s-10s.

[0041] Then, step S103 is performed: forming a sidewall barrier layer 5 on the sidewall of the defined contact hole, and forming a bottom barrier layer 4 on the bottom of the defined contact hole.

[0042] Furthermore, the side wall barrier layer 5 and the bottom barrier layer 4 are made of TiN material.

[0043] Specifically, in the embodiment of the present invention, Figure 5As shown, after etching the etch stop layer 2, an adhesion layer is formed on the side wall and the bottom of the contact hole, and a bottom barrier layer 4 is formed at the bottom of the contact hole defined on the surface of the adhesion layer, and a side wall barrier layer 5 is formed on the side wall. The material of the side wall barrier layer 5 and the bottom barrier layer 4 is TiN material.

[0044] Then, step S104 is performed: a portion of the bottom barrier layer 4 is removed by an etching process.

[0045] Further, after a portion of the bottom barrier layer 4 is removed by etching, the thickness of the remaining bottom barrier layer 4 is between

[0046] Furthermore, removing part of the bottom barrier layer by using an etching process includes: removing part of the bottom barrier layer by using a dry etching process.

[0047] Furthermore, the etching gas used in the dry etching process includes one or more of CHF3, CL2 and CF4, the etching gas flow rate is between 10sccm-60sccm, the pressure of the etching chamber is between 5mTorr-20mTorr, the etching bias power is between 30W-100W, and the etching time is between 5s-60s.

[0048] Specifically, in the embodiment of the present invention, Figure 6 As shown, after forming the sidewall barrier layer 5 and the bottom barrier layer 4, an etching process is used to remove part of the bottom barrier layer 4, and the thickness of the bottom barrier layer 4 at the bottom of the contact hole is adjusted. Without affecting the thickness of the sidewall barrier layer 5 at the sidewall of the contact hole, the thickness of the bottom barrier layer 4 of the contact hole is reduced, thereby reducing the contact resistance of the contact hole. In this embodiment, a dry etching process is used to remove part of the bottom barrier layer 4. The etching gas used in the dry etching process includes one or more of CHF3, CL2 and CF4, the etching gas flow rate is between 10sccm-60sccm, the pressure of the etching chamber is between 5mTorr-20mTorr, the etching bias power is between 30W-100W, and the etching time is between 5s-60s. After dry etching, the thickness of the remaining bottom barrier layer 4 is between

[0049] Finally, step S105 is performed: filling the designated contact hole with metal contact material 6 to form the contact hole.

[0050] Specifically, in the embodiment of the present invention, after removing part of the bottom barrier layer 4, the metal contact material 6 is filled in the defined contact hole to form a final contact hole.

[0051] A second aspect of the present invention provides a semiconductor device, comprising a copper metal layer formed by the contact hole forming method described above.

[0052] A third aspect of the present invention provides a chip, which includes the semiconductor device described above.

[0053] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0054] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0055] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A contact hole forming method, characterized in that: The contact hole forming method comprises: Etching the semiconductor device from the contact hole demarcation position on the surface of the semiconductor device to remove the interlayer dielectric layer and part of the etching stop layer at the contact hole demarcation position; wherein the contact hole demarcation position on the surface of the semiconductor device is sequentially formed with a metal silicide layer, an etching stop layer and an interlayer dielectric layer from bottom to top; Removing the remaining etch stop layer at the contact hole defined position by using a silicon-cobalt-nickel etching process to expose the metal silicide layer in the defined contact hole; forming a sidewall barrier layer on the sidewalls of the defined contact hole, and forming a bottom barrier layer on the bottom of the defined contact hole; removing a portion of the bottom barrier layer by an etching process; The metal contact material is filled in the designated contact hole to form the contact hole.

2. The contact hole forming method according to claim 1, wherein: The etching gas used for etching the semiconductor device from the contact hole marked position on the surface of the semiconductor device includes one or more of C4F8, CH2F2, CHF3, CF4, CO2, O2 and Ar, the etching gas flow rate is between 10sccm-200sccm, the pressure of the etching chamber is between 20mTorr-100mTorr, the etching source power is between 300W-2800W, the etching bias power is between 300W-2800W, and the etching time is between 8s-100s.

3. The contact hole forming method according to claim 1, wherein: After removing part of the etch stop layer in the defined contact hole, the thickness of the remaining etch stop layer in the defined contact hole is between 4. The contact hole forming method according to claim 1, wherein: The etching gas used in the silicon-cobalt-nickel etching process includes one or more of NF3, NH3, H2 and He, the etching gas flow rate is between 10sccm-100sccm, the pressure of the etching chamber is between 3mTorr-10mTorr, the etching source power is between 20W-40W, and the etching time is between 5s-10s.

5. The contact hole forming method according to claim 1, wherein: After removing part of the bottom barrier layer by etching process, the thickness of the remaining bottom barrier layer is between 6. The contact hole forming method according to claim 1, wherein: The method of removing part of the bottom barrier layer by etching process comprises: A portion of the bottom barrier layer is removed using a dry etching process.

7. The contact hole forming method according to claim 6, characterized in that: The etching gas used in the dry etching process includes one or more of CHF3, CL2 and CF4, the etching gas flow rate is between 10sccm-60sccm, the pressure of the etching chamber is between 5mTorr-20mTorr, the etching bias power is between 30W-100W, and the etching time is between 5s-60s.

8. The contact hole forming method according to claim 6, wherein: The side wall barrier layer and the bottom barrier layer are made of TiN material.

9. A semiconductor device, characterized in that: The semiconductor device includes a contact hole formed by the contact hole forming method according to any one of claims 1 to 8.

10. A chip, characterized in that: The chip includes the semiconductor device according to claim 9.

Images