Method for improving 3D wafer stacking efficiency and semiconductor structure

Abstract

The invention belongs to the technical field of semiconductor processing, and particularly relates to a method for improving 3D wafer stacking efficiency and a semiconductor structure. A metal interconnection structure is arranged in a wafer oxide layer, a through hole is formed in the oxide layer from a bonding surface side, and the through hole is communicated with the metal interconnection structure and is filled with a conductor layer; the bonding surfaces of one wafer and the other wafer are opposite, and the conductor layers of the two wafers are communicated; a TSV through hole is formed in the bottom face of any wafer in the direction of the metal interconnection structure, and the TSV through hole is communicated with the metal interconnection structure; depositing an oxidation deposition layer in the TSV through hole, wherein the oxidation deposition layer covers the side wall of the TSV through hole and the bottom of the TSV through hole; injecting ions into the oxidation deposition layer on the side wall of the TSV; a photoetching step is executed, the oxidation deposition layer at the bottom of the TSV is removed, and the metal interconnection structure at the bottom of the TSV is exposed; and depositing a TSV through hole conductor layer in the TSV through hole, wherein the TSV through hole conductor layer is communicated with the metal interconnection structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor processing technology, and in particular to a method for improving 3D wafer stacking performance. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher integration in order to achieve faster computing speeds, larger data storage capacity and more functions. The higher the integration of semiconductor chips, the smaller the critical dimension of semiconductor devices.

[0003] 3D wafer stacking technology is an advanced semiconductor manufacturing process that achieves higher integration and performance by stacking multiple wafers vertically. 3D wafer stacking technology stacks multiple wafers vertically and uses technologies such as through silicon vias (TSV) to achieve inter-layer interconnection.

[0004] The through silicon via (TSV) process can connect the circuit made on the upper surface of the silicon wafer to the back of the silicon wafer through the metal filled in the through silicon via. Combined with the three-dimensional packaging process, the IC layout has evolved from the traditional two-dimensional side-by-side arrangement to the more advanced three-dimensional stacking, so that the component packaging is more compact and the chip lead distance is shorter, which can greatly improve the frequency and power characteristics of the circuit. The existing through silicon via process includes: etching through holes on the surface of the wafer using plasma etching; forming an insulating layer on the surface of the through hole using chemical vapor deposition; metallizing the through silicon via, filling the through hole with copper electroplating, and removing the excess copper electroplating layer using CMP; grinding the back of the wafer to expose the copper conductor layer to complete the through silicon via structure.

[0005] As a connection structure between multi-layer circuit structures, TSV plays the role of electrically connecting circuit devices between multiple layers. In the known prior art, there are many reasons that may cause leakage at TSV, such as: the interface between TSV and silicon substrate may be defective or contaminated, the thermal expansion coefficients of TSV and silicon substrate are different, the thermal stress generated during manufacturing and use may cause microcracks or defects, the insulating dielectric layer around TSV may have pinholes, cracks or uneven thickness, and the etching, deposition and other steps in the manufacturing process are not properly controlled.

[0006] If leakage occurs at the through silicon via, it will affect the connection performance of the circuit device and the stability of the electronic device structure. Summary of the invention

[0007] The purpose of the present invention is to solve one of the above technical problems and to provide a method for solving the leakage problem at the through silicon via in a 3D wafer stacking structure, thereby improving the stacking efficiency of the 3D wafer.

[0008] In order to achieve the above object, in some embodiments of the present invention, the following technical solutions are provided: A first aspect of the present invention provides a method for improving leakage of 3D wafer stacking, comprising: A method for improving 3D wafer stacking performance, comprising: A wafer is provided, wherein the wafer comprises a base layer and an oxide layer, wherein one side of the oxide layer is a bonding surface, and one side of the base layer is a bottom surface; a metal interconnection structure is arranged in the oxide layer, and a through hole is opened in the oxide layer from the bonding surface side, wherein the through hole is connected to the metal interconnection structure and filled with a conductor layer; The bonding surfaces of one wafer and another wafer are opposite, and the conductor layers of the two wafers are connected; Opening a TSV through hole on the bottom surface of any wafer in the direction of the metal interconnection structure, wherein the TSV through hole is connected to the metal interconnection structure; Depositing an oxide deposition layer in the TSV through hole, wherein the oxide deposition layer covers the sidewalls and the bottom of the TSV through hole; Implanting ions into the oxide deposition layer on the sidewall of the TSV through hole; Performing a photolithography step to remove the oxide deposition layer at the bottom of the TSV through hole and expose the metal interconnection structure at the bottom of the TSV through hole; A TSV through hole conductor layer is deposited into the TSV through hole, wherein the TSV through hole conductor layer is connected to the metal interconnection structure.

[0009] In combination with the first aspect of the present invention, in some embodiments of the present invention, the step of injecting ions includes: depositing a photoresist layer, wherein the photoresist layer covers the oxide deposition layer at the bottom of the TSV through hole, and the oxide deposition layer on the side wall of the TSV through hole is still in an exposed state; and injecting ions into the oxide deposition layer on the side wall of the TSV through hole.

[0010] In combination with the first aspect of the present invention, in some embodiments of the present invention, the types of implanted ions include but are not limited to: B, BF2, Si, Al, Phosp, AS.

[0011] In combination with the first aspect of the present invention, in some embodiments of the present invention, the energy of the implanted ions is controlled to be between 2KeV and 50KeV.

[0012] In combination with the first aspect of the present invention, in some embodiments of the present invention, the dose of implanted ions is controlled at 1e 12 / cm 2 -1e 15 / cm 2 .

[0013] In combination with the first aspect of the present invention, in some embodiments of the present invention, the thickness of the oxide deposition layer is .

[0014] In combination with the first aspect of the present invention, in some embodiments of the present invention, before the step of opening a TSV through hole on the bottom surface of any wafer, the method further includes: A passivation layer is deposited on the bottom surface of the wafer where TSV through holes are required to be opened, and TSV through holes are opened along the passivation layer toward the metal interconnection structure; the passivation layer includes a combination of an oxide layer and a silicon layer.

[0015] In combination with the first aspect of the present invention, in some embodiments of the present invention, the oxide deposition layer covers the surface of the passivation layer, and in the ion implantation step, ions are implanted into the oxide deposition layer on the surface of the passivation layer.

[0016] A second aspect of the present invention provides a semiconductor structure, which is constructed using the method provided in the first aspect of the present invention, comprising: The first wafer comprises a base layer and an oxide layer, wherein one side of the oxide layer is a bonding surface, and one side of the base layer is a bottom surface; a metal interconnection structure is arranged in the oxide layer, and a through hole is opened in the oxide layer from the bonding surface side, wherein the through hole is connected to the metal interconnection structure and filled with a conductor layer; The second wafer comprises a base layer and an oxide layer, wherein one side of the oxide layer is a bonding surface, and one side of the base layer is a bottom surface; a metal interconnection structure is arranged in the oxide layer, and a through hole is opened in the oxide layer from the bonding surface side, and the through hole is connected to the metal interconnection structure and filled with a conductor layer; The bonding surfaces of the first wafer and the second wafer are opposite to each other, and the conductor layer of the first wafer is connected to the conductor layer of the second wafer; A TSV through hole is opened on the bottom surface of the first wafer in the direction of the metal interconnection structure, wherein the TSV through hole is connected to the metal interconnection structure of the first wafer; Depositing an oxide deposition layer on the side wall of the TSV through hole, and implanting ions into the oxide deposition layer on the side of the TSV through hole; The TSV through hole fills a TSV through hole conductor layer, and the TSV through hole conductor layer is connected to the metal interconnection structure of the first wafer.

[0017] In some embodiments of the present invention, a passivation layer is disposed on the bottom surface of the first wafer, and the oxide deposition layer covers the passivation layer.

[0018] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: An oxide deposition layer is deposited inside the TSV through hole, and the oxide deposition layer at the bottom of the TSV through hole is removed by ion implantation and etching. Due to the difference in etching rate, the oxide deposition layer on the side wall of the TSV through hole can be prevented from being excessively damaged. A TSV through hole conductor layer is deposited outside the oxide deposition layer to form a 3D stacked interconnection structure. The oxide deposition layer on the side wall of the TSV through hole plays the role of insulation and preventing leakage. The present invention solves the problem of TSV through hole leakage through a simple process, and can improve the reliability of the interconnection structure of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0020] Figure 1 This is a schematic diagram of the wafer structure provided by the present invention.

[0021] Figure 2 It is a schematic diagram of the bonding structure of the first wafer and the second wafer of the present invention.

[0022] Figure 3a It is a schematic diagram of the bonding structure of the present invention without a passivation layer.

[0023] Figure 3b It is a schematic diagram of the bonding structure containing a passivation layer of the present invention.

[0024] Figure 4 This is a schematic structural diagram of the steps of opening a TSV through hole and depositing an oxide deposition layer in the present invention.

[0025] Figure 5 It is a schematic structural diagram of the ion implantation step of the present invention.

[0026] Figure 6 Schematic diagram of the structure of the etching oxide deposition layer step.

[0027] Figure 7 Schematic diagram of the structure of the conductor layer filling the TSV through hole.

[0028] In the above figures: 1-basal layer; 2- oxide layer; 3-Metal interconnect structure; 4-Through hole; 5- conductor layer; 601-bonding surface, 602-bottom surface; 7-TSV through hole; 8- Oxidation deposition layer; 9-TSV through hole conductor layer; 10-photoresist layer; 11- Passivation layer. DETAILED DESCRIPTION

[0029] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0030] Obviously, the drawings described below are only some examples or embodiments of the present application. For ordinary technicians in this field, the present application can also be applied to other similar scenarios based on these drawings without creative work. In addition, it can also be understood that although the efforts made in this development process may be complicated and lengthy, for ordinary technicians in this field related to the content disclosed in this application, some changes in design, manufacturing or production based on the technical content disclosed in this application are just conventional technical means, and should not be understood as insufficient content disclosed in this application.

[0031] 3D wafer stacking technology stacks multiple wafers in a vertical direction and uses technologies such as through silicon vias (TSV) to achieve inter-layer interconnection. The connection form of through silicon vias (TSV) can shorten the interconnection length, reduce delay and power consumption. However, TSV leakage is a major reliability issue that may affect chip performance and yield.

[0032] Through silicon via (TSV) requires etching processing, and the etching process and semiconductor structure defects can easily cause leakage in the through silicon via (TSV).

[0033] In the known prior art, TSV leakage is usually caused by the following factors: Insulation layer defects: The insulation layer of TSV (such as SiO2) may have cracks, holes or uneven thickness; Thermal stress: The high temperature process in the TSV manufacturing process or the thermal stress generated when the chip is working may cause the insulation layer to crack or interface delamination; Electromigration: Under high current density, metal filling materials (such as copper) may undergo electromigration, causing damage to the insulation layer; Process defects: Defects in process steps such as etching, deposition or chemical mechanical polishing (CMP) may cause incomplete TSV structure; Interface problems: There may be defects in the interface between TSV and the surrounding silicon substrate or metal interconnection, causing leakage paths.

[0034] TSV leakage will increase device power consumption, leading to an increase in static power consumption and affecting energy efficiency; it will cause signal attenuation or noise, affecting circuit performance and causing a decrease in signal integrity; long-term leakage may cause local overheating, accelerate device aging or even failure, and reduce device reliability; at the same time, TSV leakage is one of the main reasons for the yield loss of 3D stacked chips.

[0035] In the known prior art, the leakage problem is solved by improving and optimizing the insulating layer structure, for example, using uniform insulating materials (such as high-k dielectrics) and increasing the thickness of the insulating layer; the leakage problem can also be solved by improving the TSV process, for example, optimizing the etching and deposition processes, reducing the defects of the insulating layer, using low-temperature processes, reducing the impact of thermal stress on the insulating layer, etc. With the development of technology, leakage repair technologies have also emerged, such as laser repair or local re-deposition to repair defects.

[0036] The leakage structure processing method in the prior art has the defects of complex process technology and high technical requirements. To solve this problem, the present invention proposes a method for improving 3D wafer stack leakage, and based on this method, proposes a new semiconductor structure.

[0037] A first aspect of the present invention provides a method for improving leakage of 3D wafer stacking, which comprises the following steps.

[0038] S1: Prepare wafer.

[0039] A wafer is provided, comprising a base layer 1 and an oxide layer 2, wherein one side of the oxide layer is a bonding surface 601, and one side of the base layer is a bottom surface 602; a metal interconnection structure 3 is arranged in the oxide layer, a through hole is opened in the oxide layer from the bonding surface side, and the through hole 4 is connected to the metal interconnection structure 3 and filled with a conductor layer 5.

[0040] refer to Figure 1 , providing a schematic diagram of a wafer structure for the present invention.

[0041] The wafer base layer 1 can be a silicon base, a silicon carbide base, a silicon nitride base, etc. In this embodiment, a silicon nitride base is used. A multilayer semiconductor structure is deposited on the base layer 1, and the multilayer semiconductor structure includes an oxide layer 2. The oxide layer is mainly used for insulation, protection and device structure construction. The oxide layer can be made of silicon dioxide and a high dielectric constant material. During the deposition process of the oxide layer 2, a metal interconnection structure 3 is designed inside the oxide layer. The metal interconnection structure 3 is usually a copper block arranged inside the oxide layer 2. The copper block is mainly used for the interconnection layer in the wafer to achieve electrical connection of the device.

[0042] A through hole 4 is etched from the surface of the oxide layer 2 to the substrate layer 1. The through hole 4 needs to have a certain depth so that the metal interconnection structure 3 can be exposed after etching. A conductor layer 5 is filled in the through hole 4. The conductor layer 5 has conductivity and can be connected to the metal interconnection structure 3.

[0043] The same method is used to process multiple wafer structures.

[0044] S2: Wafer bonding.

[0045] refer to Figure 2 , provide wafers processed by step S1, defined as a first wafer and a second wafer, the bonding surfaces 601 of the first wafer and the second wafer are opposite, the conductor layers 5 of the two wafers are located at opposite positions, the conductor layers 5 are connected, and the circuit structure between the two wafers is connected. In this embodiment, the first wafer is defined as the one located above the illustrated position, and the second wafer is defined as the one located below.

[0046] S3: TSV through-hole processing step.

[0047] refer to Figure 3a and Figure 3b A TSV through hole 7 is opened on one side of the bottom surface 602 of any wafer in the direction of the metal interconnection structure 3, and the TSV through hole 7 is connected to the metal interconnection structure 3. The line width of the TSV through hole 7 is , can be selected according to actual processing needs.

[0048] Depositing an oxide deposition layer 8 in the TSV through hole 7, wherein the oxide deposition layer 8 covers the sidewall of the TSV through hole 7 and the bottom of the TSV through hole 7; Ions are injected into the oxide deposition layer on the side wall of the TSV through hole 7; the types of injected ions include but are not limited to: B, BF2, Si, Al, Phosp, AS, and any other ions that can be used for ion implantation lithography. During the ion implantation process, the energy of the injected ions is controlled at 2KeV-50KeV, and the dose of the injected ions is controlled at 1e 12 / cm 2 -1e 15 / cm 2 The control of ion implantation energy and the selection of dosage can be designed according to actual needs.

[0049] After the ion implantation is completed, a photolithography step is performed to remove the oxide deposition layer 8 at the bottom of the TSV through hole 7, exposing the metal interconnection structure 3 at the bottom of the TSV through hole 7. In this step, it is necessary to remove at least part of the oxide deposition layer 8 at the bottom of the TSV through hole 7, or remove it completely, so that the metal interconnection structure 3 can be exposed. In some embodiments, the oxide deposition layer 8 in the middle of the bottom of the TSV through hole 7 can also be removed, and the oxide deposition layer 8 adjacent to the side wall of the TSV through hole 7 can be retained.

[0050] Subsequently, a TSV through-hole conductor layer 9 is deposited in the TSV through-hole 7 . The TSV through-hole conductor layer 9 may also be made of copper. The TSV through-hole conductor layer 9 is connected to the metal interconnection structure 3 .

[0051] In this embodiment, step S2 and step S3 are performed on the first wafer. It should be understood that, with respect to the circuit structure layout of the semiconductor device, in some embodiments, step S2 and step S3 may also be performed on both the first wafer and the second wafer, that is, TSV through-hole 7 structures are processed on the bottom surfaces 602 of the two wafers.

[0052] The oxide deposition layer 8 on the side wall of the TSV through hole 7 is used to protect the TSV through hole 7, reduce the damage to the side wall oxide layer, and prevent leakage from occurring in the TSV through hole 7. In the present invention, an etching step is performed after ion implantation, and the ion implantation improves the damage to the side wall oxide deposition layer 8 caused during the etching process of the oxide deposition layer 8 at the bottom of the TSV through hole 7, thereby preventing leakage between the TSV through holes 7, and leakage between the TSV through hole 7 and other device connection structures.

[0053] In combination with the first aspect of the present invention, in some embodiments of the present invention, the thickness of the oxide deposition layer 8 is The design can be selected according to actual processing requirements. In some implementation structures, the thickness of the oxide deposition layer 8 at the bottom of the TSV through hole 7 is greater than the thickness of the oxide deposition layer 8 at the sidewall of the TSV through hole 7 .

[0054] refer to Figures 5 to 7 In combination with the first aspect of the present invention, in some embodiments of the present invention, an ion implantation etching technique is used to remove the oxide deposition layer 8 at the bottom of the TSV through hole 7. The step of removing the oxide deposition layer 8 at the bottom of the TSV through hole 7 includes: depositing a photoresist layer 10, the photoresist layer 10 covers the oxide deposition layer 8 at the bottom of the TSV through hole 7, and the oxide deposition layer on the side wall of the TSV through hole 7 is still exposed; and injecting ions into the oxide deposition layer 8 on the side wall of the TSV through hole 7. The photoresist layer 10 serves as a protective layer, covering the area that does not need to be implanted, to ensure that the ions are only implanted into the oxide deposition layer 8 on the side wall of the TSV through hole 7.

[0055] After the ion implantation is completed, an etching step is performed. The oxide deposition layer 8 on the side wall of the TSV through hole 7 is not etched away due to the implanted ions, thereby being able to insulate from other electrical connection structures and prevent leakage.

[0056] The use of TSV through hole 7 sidewall oxide layer photolithography technology to protect the oxide deposition layer 8 on the sidewall of the TSV through hole 7 can solve the problem of leakage between TSVs caused by damage caused by etching of the bottom oxide layer of the TSV, thereby affecting performance.

[0057] The present invention is also applicable to passivation layer technology.

[0058] In combination with the first aspect of the present invention, in some embodiments of the present invention, before the step of opening a TSV through hole 7 on the bottom surface of any wafer, the method further includes: A passivation layer 11 is deposited on the bottom surface 602 of the wafer where the TSV through hole 7 needs to be opened, and the TSV through hole 7 is opened along the passivation layer 11 in the direction of the metal interconnect structure 3. The semiconductor passivation layer 11 is a key step in the manufacture of semiconductor devices, and is mainly used to protect the device surface from the influence of the external environment (such as moisture, pollutants, mechanical damage, etc.), while improving the reliability and stability of the device.

[0059] In combination with the first aspect of the present invention, in some embodiments of the present invention, a passivation layer 11 is deposited on the bottom surface 602 of the first wafer, and the passivation layer 11 includes a combination of an oxide layer and a silicon layer, and may include multiple oxide layers and multiple silicon layers arranged at intervals.

[0060] In combination with the first aspect of the present invention, in some embodiments of the present invention, the oxide deposition layer 8 covers the surface of the passivation layer 11 .

[0061] In the step of ion implantation, ions are also implanted into the oxide deposition layer 8 on the surface of the passivation layer 11 .

[0062] Except for the structure of the passivation layer 11, other implementation steps are the same as the above-mentioned implementation method and will not be described in detail.

[0063] By adopting the 3D stacking method provided by the first aspect of the present invention, the oxide deposition layer 8 on the side wall of the TSV through hole 7 plays an insulating role, which can improve the leakage problem of the TSV through hole 7.

[0064] A second aspect of the present invention provides a semiconductor structure, which is constructed using the method provided by the first aspect of the present invention. The semiconductor structure is specifically a semiconductor bonding structure based on 3D stacking.

[0065] The semiconductor structure includes a first wafer and a second wafer that are bonded.

[0066] The first wafer includes a base layer 1 and an oxide layer 2, wherein one side of the oxide layer 2 is a bonding surface 601, and one side of the base layer is a bottom surface 602; a metal interconnection structure 3 is arranged in the oxide layer 2, a through hole is opened in the oxide layer 2 from the bonding surface 601 side, and the through hole 4 is connected to the metal interconnection structure 3 and filled with a conductor layer 5.

[0067] The second wafer includes a base layer 1 and an oxide layer 2, wherein one side of the oxide layer 2 is a bonding surface 601, and one side of the base layer is a bottom surface 602; a metal interconnection structure 3 is arranged in the oxide layer 2, a through hole is opened in the oxide layer 2 from the bonding surface 601 side, and the through hole 4 is connected to the metal interconnection structure 3 and filled with a conductor layer 5.

[0068] The bonding surfaces of the first wafer and the second wafer face each other, and the conductor layer 5 of the first wafer is connected to the conductor layer 5 of the second wafer.

[0069] A TSV through hole 7 is formed on the bottom surface of the first wafer in the direction of the metal interconnection structure 3, and the TSV through hole 7 is connected to the metal interconnection structure 3 of the first wafer; An oxide deposition layer 8 is deposited on the side of the TSV through hole 7; the oxide deposition layer 8 covers the side of the TSV through hole 7 and exposes the metal interconnect structure 3 at the bottom of the TSV through hole 7; ions are implanted inside the oxide deposition layer on the side of the TSV through hole 7, and the types of implanted ions include but are not limited to: B, BF2, Si, Al, Phosp, AS; The TSV via hole 7 is filled with a TSV via conductor layer 9 , and the TSV via conductor layer 9 is connected to the metal interconnection structure 3 of the first wafer.

[0070] In some embodiments of the present invention, a passivation layer 11 is disposed on the bottom surface of the first wafer, and the oxide deposition layer 8 covers the passivation layer 11 .

[0071] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. It should be pointed out that for those skilled in the art, any modification, equivalent replacement and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the patent application shall be based on the protection scope of the attached claims.

Claims

1. A method for improving 3D wafer stacking performance, characterized in that: include: Providing a wafer, the wafer comprising a base layer and an oxide layer, one side of the oxide layer being a bonding surface, and one side of the base layer being a bottom surface; A metal interconnection structure is arranged in the oxide layer, and a through hole is opened in the oxide layer from the bonding surface side, wherein the through hole is connected to the metal interconnection structure and filled with the conductor layer; The bonding surfaces of one wafer and another wafer are opposite, and the conductor layers of the two wafers are connected; Opening a TSV through hole on the bottom surface of any wafer in the direction of the metal interconnection structure, wherein the TSV through hole is connected to the metal interconnection structure; Depositing an oxide deposition layer in the TSV through hole, wherein the oxide deposition layer covers the sidewalls and the bottom of the TSV through hole; Implanting ions into the oxide deposition layer on the sidewall of the TSV through hole; Performing a photolithography step to remove the oxide deposition layer at the bottom of the TSV through hole and expose the metal interconnection structure at the bottom of the TSV through hole; A TSV through hole conductor layer is deposited into the TSV through hole, wherein the TSV through hole conductor layer is connected to the metal interconnection structure.

2. The method for improving 3D wafer stacking performance as claimed in claim 1, wherein: The step of injecting ions includes: depositing a photoresist layer, the photoresist layer covers the oxide deposition layer at the bottom of the TSV through hole, and the oxide deposition layer on the side wall of the TSV through hole is still exposed; and injecting ions into the oxide deposition layer on the side wall of the TSV through hole.

3. The method for improving 3D wafer stacking performance as claimed in claim 1, wherein: The types of implanted ions include but are not limited to: B, BF2, Si, Al, Phosp, AS.

4. The method for improving 3D wafer stacking performance as claimed in claim 1, wherein: The energy of the implanted ions is controlled at 2KeV-50KeV.

5. The method for improving 3D wafer stacking performance as claimed in claim 1, wherein: The dose of implanted ions is controlled at 1e 12 / cm 2 -1e 15 / cm 2 .

6. The method for improving 3D wafer stacking performance as claimed in claim 1, wherein: The thickness of the oxide deposition layer is .

7. The method for improving 3D wafer stacking performance as claimed in claim 1, wherein: Before any TSV through-hole step is performed on the bottom surface of the wafer, the method further includes: A passivation layer is deposited on the bottom surface of the wafer where TSV through holes are required to be opened, and TSV through holes are opened along the passivation layer toward the metal interconnection structure; the passivation layer includes a combination of an oxide layer and a silicon layer.

8. The method for improving 3D wafer stacking performance as claimed in claim 7, wherein: The oxide deposition layer covers the surface of the passivation layer, and in the ion implantation step, ions are implanted into the oxide deposition layer on the surface of the passivation layer.

9. A semiconductor structure, characterized in that: The method according to any one of claims 1 to 8 is used to construct the device, comprising: The first wafer comprises a base layer and an oxide layer, wherein one side of the oxide layer is a bonding surface, and one side of the base layer is a bottom surface; a metal interconnection structure is arranged in the oxide layer, and a through hole is opened in the oxide layer from the bonding surface side, wherein the through hole is connected to the metal interconnection structure and filled with a conductor layer; The second wafer comprises a base layer and an oxide layer, wherein one side of the oxide layer is a bonding surface, and one side of the base layer is a bottom surface; a metal interconnection structure is arranged in the oxide layer, and a through hole is opened in the oxide layer from the bonding surface side, and the through hole is connected to the metal interconnection structure and filled with a conductor layer; The bonding surfaces of the first wafer and the second wafer are opposite to each other, and the conductor layer of the first wafer is connected to the conductor layer of the second wafer; A TSV through hole is opened on the bottom surface of the first wafer in the direction of the metal interconnection structure, wherein the TSV through hole is connected to the metal interconnection structure of the first wafer; Depositing an oxide deposition layer on the side wall of the TSV through hole, and implanting ions inside the oxide deposition layer on the side of the TSV through hole; The TSV through hole fills a TSV through hole conductor layer, and the TSV through hole conductor layer is connected to the metal interconnection structure of the first wafer.

10. The semiconductor structure according to claim 9, wherein: A passivation layer is disposed on the bottom surface of the first wafer, and the oxide deposition layer covers the passivation layer.

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