Capacitor charging and discharging circuit, circuit board and equipment

Abstract

The invention provides a capacitor charging and discharging circuit, a circuit board and equipment, and relates to the technical field of capacitor charging and discharging, according to the scheme, charging current is output to a super capacitor through a charging current limiting module, when the equipment is powered down, a controlled discharging module conducts a discharging loop to start discharging after receiving a corresponding control signal, and the charging current limiting module outputs charging current to the super capacitor; and after the equipment finishes data storage, the controlled discharge module also turns off the discharge loop according to the corresponding control signal to stop discharging. According to the scheme, better charging current control can be provided, the problems that the charging current is too small, the charging time is long or the charging current is too large, an over-current point of an adapter is impacted, and the stability of a mainboard is influenced can be avoided, the discharging requirement can be quickly responded through the controlled discharging module, a discharging path is closed in time after a system completes necessary actions, and the system safety is improved. And the possibility of quick re-electrification without starting up due to slow discharge is solved. And the application requirements in a high-reliability scene are effectively met.

Description

Technical Field

[0001] The present application relates to the technical field of capacitor charging and discharging, and in particular to a capacitor charging and discharging circuit, a circuit board and a device. Background Art

[0002] As a new type of energy storage device, supercapacitor has a large capacity, and it also has the characteristics of short charging time, long service life, and good temperature characteristics, and can be used as a battery.

[0003] In scenarios where industrial control equipment requires high reliability, the reliability of data is required to be high. Therefore, in the event of an unexpected power outage, the equipment must be able to maintain power for a period of time to save data. In this regard, supercapacitors are usually used as backup power sources to store energy to provide power after an unexpected power outage of the industrial control equipment.

[0004] However, the inventors have found in actual applications that the charging and discharging circuits of supercapacitors used in related technologies have limitations and are not conducive to applications in scenarios that require high reliability. For example, the use of a diode plus a current-limiting resistor will make the charging current too small and the charging time long, and another discharge circuit is required during discharge. If a capacitor management chip is used, the circuit design is more complex, the charging voltage requirement is high, and the circuit cost is higher. Summary of the invention

[0005] The present application provides a capacitor charging and discharging circuit, circuit board and device, which solves the problem that the circuit design for charging and discharging supercapacitors is complex and difficult to apply in high-reliability scenarios. This solution can provide more accurate charging current limitation and discharge control, so that the power supply can be maintained for a period of time after the device loses power, meeting the application requirements of high-reliability scenarios.

[0006] In a first aspect, the present application provides a capacitor charging and discharging circuit, which includes an anti-backflow module, a charging current limiting module, a voltage equalization protection module and a controlled discharge module.

[0007] Among them, the input end of the anti-backflow module is connected to the power supply voltage, and the anti-backflow module is used to isolate the backflow voltage after the equipment is powered off; the input end of the charging current limiting module is connected to the output end of the anti-backflow module, and the output end of the charging current limiting module is connected to the grounded supercapacitor, and the charging current limiting module is used to provide charging current to the supercapacitor, and suspend the output charging current when the charging current is greater than the preset current limiting value; the voltage equalization protection module is connected in parallel with the supercapacitor; the input end of the controlled discharge module is connected to the output end of the charging current limiting module, and the output end of the controlled discharge module is connected to the output load, and the control end of the controlled discharge module is connected to the discharge control signal, and the controlled discharge module is used to control the discharge circuit according to the discharge control signal to start or stop discharge.

[0008] In a second aspect, the present application also provides a circuit board, which includes the capacitor charging and discharging circuit as described above.

[0009] In a third aspect, the present application also provides an industrial control device, which includes the circuit board as described above.

[0010] This application outputs charging current to the supercapacitor through a charging current limiting module, and can control the charging current by setting the reference voltage provided on the charging current limiting module, and after the supercapacitor is charged, when the device is powered off, the controlled discharge module turns on the discharge circuit to start discharging after receiving the corresponding control signal, and after the device completes data storage, the controlled discharge module also turns off the discharge circuit to stop discharging according to the corresponding control signal. This solution can provide better charging current control, can avoid the problem of too small charging current, long charging time or too large charging current, impacting the adapter overcurrent point and affecting the stability of the motherboard, and can quickly respond to the discharge demand through the controlled discharge module, and close the discharge path in time after the system completes the necessary actions, so as to solve the possibility of not starting up after rapid power-on due to slow discharge. Effectively meet the application requirements in high reliability scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A block diagram of a capacitor charging and discharging circuit according to an embodiment of the present application;

[0012] Figure 2 A principle block diagram of a charging current limiting module provided in an embodiment of the present application;

[0013] Figure 3 A circuit diagram of a current output unit provided in an embodiment of the present application;

[0014] Figure 4 A circuit diagram of an output control unit provided in one embodiment of the present application;

[0015] Figure 5 A circuit diagram of a voltage providing unit provided in an embodiment of the present application;

[0016] Figure 6 A circuit diagram of a current limiting detection unit provided in an embodiment of the present application;

[0017] Figure 7 A circuit diagram of a controlled discharge module provided in one embodiment of the present application;

[0018] Figure 8 A circuit diagram of a full-power reminder module provided in an embodiment of the present application;

[0019] Fig. 9 A principle block diagram of a capacitor charging and discharging circuit provided in another embodiment of the present application. DETAILED DESCRIPTION

[0020] The embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are only used to explain the embodiments of the present application, rather than to limit the embodiments of the present application. It should also be noted that, for ease of description, only the parts related to the embodiments of the present application rather than all structures are shown in the accompanying drawings, and those skilled in the art should be able to think of it after reading the specification of this application that as long as the technical features do not contradict each other, any combination of the technical features can constitute an optional implementation method.

[0021] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally a class, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally represents that the objects associated with each other are in an "or" relationship. In the description of the present application, "multiple" means two or more, and "several" means one or more.

[0022] In the high reliability scenario of industrial control equipment, industrial control equipment needs to be able to save data after power failure. For this reason, industrial control equipment needs to use supercapacitors as backup power supplies. If the charging current of the supercapacitor is too small and the charging time is long, it is easy for the backup power supply to fail to meet the voltage requirements for data preservation after the industrial control equipment loses power. In addition, if the discharge time is too long, the backup power supply will affect the restart of the industrial control equipment. Therefore, industrial control equipment needs better supercapacitor charging and discharging control to facilitate its application in high reliability scenarios.

[0023] To this end, the present application provides a capacitor charging and discharging circuit to power a supercapacitor, and uses the supercapacitor as a backup power source, so that the circuit can power the device through the supercapacitor after the device loses power. Figure 1 As shown, Figure 1 This is a principle block diagram of a capacitor charging and discharging circuit provided in an embodiment of the present application. The capacitor charging and discharging circuit includes an anti-backflow module 110, a charging current limiting module 120, a super capacitor, a voltage equalization protection module 130 and a controlled discharge module 140.

[0024] Specifically, the input end of the anti-backflow module 110 is connected to the power supply voltage, and the output end of the anti-backflow module 110 is connected to the input end of the charging current limiting module 120, and the output end of the charging current limiting module 120 is connected to the super capacitor, the super capacitor is grounded, and the voltage equalization protection module 130 is connected in parallel with the super capacitor. The input end of the controlled discharge module 140 is connected to the charging current limiting module 120, that is, the input end of the controlled discharge module 140 is connected to the super capacitor, and the output end of the controlled discharge module 140 is connected to the output load, and the control end of the controlled discharge module 140 is connected to the discharge control signal, which is provided by the device CPU (Central Processing Unit) or MCU (Microcontroller Unit) and other devices or modules, such as power-off detection of the device, so as to output a discharge control signal with a corresponding voltage state after the device is powered off to trigger the conduction and shutdown of the discharge circuit, that is, whether a path is formed between the super capacitor and the output load through the discharge control signal.

[0025] It should be noted that the number of supercapacitors is set according to the application requirements of the corresponding working voltage, by connecting the set supercapacitors in series in sequence. Of course, the corresponding voltage equalization protection module 130 is also set according to the number of supercapacitors to perform voltage equalization protection on each supercapacitor.

[0026] It is understandable that the circuit is connected to the power supply through the anti-backflow module 110 to access the power supply voltage. At the same time, the anti-backflow module 110 is also used to isolate the backflow voltage after the device loses power, that is, to prevent the supercapacitor from outputting the backflow voltage to the outside through the input terminal of the circuit, thereby isolating the voltage and reducing the power consumption on the supercapacitor. It is conceivable that the anti-backflow module 110 can be a module including a plurality of rectifier diodes connected in parallel, that is, the input terminal is connected through the anode end of the rectifier diode and the charging current limiting module 120 is connected through the cathode end of the rectifier diode to prevent backflow. Of course, the anti-backflow module can also be a charging anti-backflow circuit in the related art.

[0027] The charging current limiting module 120 can charge the supercapacitor by outputting a charging current, and the charging current can be set to a corresponding upper limit value (i.e., a preset current limit value) through the charging current limiting module 120, thereby controlling and adjusting the size of the charging current supplied to the supercapacitor, and thus controlling the charging time. Moreover, the charging current output by the charging current limiting module 120 corresponds to a corresponding preset current limit value, so that the output of the charging current is suspended when the charging current is greater than the preset current limit value, which can avoid the situation where the supercapacitor is damaged due to excessive charging current.

[0028] After receiving the corresponding discharge control signal, the on / off state of the controlled discharge module 140 changes, thereby turning on or off the discharge circuit. It can be imagined that a fully charged supercapacitor can store more electrical energy and thus has a longer discharge time. In this regard, the controlled discharge module 140 can turn on the discharge circuit in time after the device loses power, and the controlled discharge module 140 can turn off the discharge circuit in time after the device completes data storage, effectively avoiding the discharge time being too long and affecting the next startup of the industrial control equipment.

[0029] It can be seen from the above scheme that the capacitor charging and discharging circuit outputs charging current to the supercapacitor through the charging current limiting module 120 to store energy on the supercapacitor, and also limits the charging current during the charging process to avoid the charging current being too small, thereby prolonging the charging time, and to avoid the charging current exceeding the preset current limiting value and damaging the supercapacitor. In addition, the charging and discharging circuit controls whether the supercapacitor can discharge to the load through the controlled discharge module 140, discharges in time after the device loses power, and shuts off the discharge in time after the device completes data storage, thereby achieving effective capacitor charging and discharging control, which helps to power the industrial control equipment after power failure for data storage.

[0030] Figure 2 This is a principle block diagram of a charging current limiting module provided in an embodiment of the present application, such as Figure 2 As shown, the charging current limiting module includes a voltage providing unit 121 , a current limiting detection unit 122 , an output control unit 123 and a current output unit 124 .

[0031] Among them, the input end and output end of the current output unit 124 respectively serve as the input end and output end of the charging current limiting module, that is, the current output unit 124 outputs charging current to the supercapacitor, and the control end of the current output unit 124 is connected to the output end of the output control unit 123. Therefore, the output of the current output unit 124 is controlled by the output control unit 123.

[0032] The input end of the voltage providing unit 121 is connected to the supply voltage, the output end of the voltage providing unit 121 is connected to the comparison input end of the current limiting detection unit 122, and the sampling input end of the current limiting detection unit 122 is connected to the output end of the current output unit 124, and the output end of the current limiting detection unit 122 is connected to the input end of the output control unit 123.

[0033] It can be understood that the current limiting detection unit 122 samples the voltage of the current output unit 124 through the sampling input terminal thereon, that is, it can be imagined that a sampling resistor is provided in the current output unit 124, and the current limiting detection unit 122 samples the sampling resistor to obtain a corresponding sampling voltage; and the voltage providing unit 121 is used to output a reference voltage; it should be conceivable that, when the sampling resistor is determined, the sampling voltage is associated with the charging current, and the reference voltage is associated with a preset current limiting value corresponding to the charging current.

[0034] The current limiting detection unit 122 compares the sampling voltage with the reference voltage, thereby outputting a conduction control signal when the charging current is greater than a preset current limiting value, that is, outputting a conduction control signal when the sampling voltage is greater than the reference voltage. After receiving the conduction control signal, the output control unit 123 can control the current output unit 124 to suspend outputting the charging current.

[0035] Therefore, the charging current limiting module can use the voltage providing unit 121 to set the upper limit of the charging current, and sample the charging current through the current limiting detection unit 122, so that when the charging current is greater than the preset current limiting value, the current limiting detection unit outputs a conduction control signal so that the output control unit 123 controls the current output unit 124 to pause outputting the charging current, thereby realizing current limiting control of the charging current, and the circuit can flexibly adjust the capacitor charging current to optimize the overall performance of the circuit.

[0036] Figure 3 A circuit diagram of a current output unit provided in an embodiment of the present application. In one embodiment, the current output unit includes a first PMOS tube Q1, a first voltage-dividing resistor R1, a first filter capacitor C1, a sampling circuit R2 and a plurality of first voltage-stabilizing diodes. In the figure, the power Schottky diode ZD1, the power Schottky diode ZD2 and the power Schottky diode ZD3 are all used as the first voltage-stabilizing power Schottky diodes in the current output unit.

[0037] Among them, a plurality of first power Schottky diodes are connected in parallel, the anode end of each first power Schottky diode serves as the input end of the current output unit, and the cathode end of each first power Schottky diode is connected to the source end of the first PMOS tube Q1. Moreover, a first voltage-dividing resistor R1 and a first filter capacitor C1 are connected between the source end and the gate end of the first PMOS tube Q1, that is, the first voltage-dividing resistor R1 and the first filter capacitor C1 are connected in parallel. In addition, the drain end of the first PMOS tube Q1 is connected to the sampling resistor R2.

[0038] The two ends of the sampling resistor R2 serve as the first sampling pin and the second sampling pin of the voltage sampling end of the current output unit. The two ends of the sampling resistor R2 are respectively connected to the sampling input end of the current limiting detection unit, that is, the sampling input end of the current limiting detection unit is also provided with two pins to respectively connect the two ends of the sampling resistor R2.

[0039] It is understandable that after setting a plurality of power Schottky diodes, the current output unit can withstand a larger charging current and can also reduce the output internal resistance of the power supply. In the current output unit, the gate terminal of the first PMOS tube Q1 serves as the control terminal of the current output unit, which is connected to the output terminal of the output control unit, that is, the conduction state of the first PMOS tube Q1 corresponds to the on-off state of the current output unit. When the first PMOS tube Q1 is turned off, the current output unit stops outputting the charging current to the supercapacitor. Therefore, by controlling the gate terminal voltage of the first PMOS tube Q1, the charging current limiting module can realize the output control of the charging current, so as to stop charging when the charging current is greater than the preset current limiting value.

[0040] Figure 4 A circuit diagram of an output control unit provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, in one embodiment, the output control unit includes a first NMOS transistor Q2, a second voltage-dividing resistor R3, a second NMOS transistor Q3 and a third voltage-dividing resistor R4.

[0041] Among them, the drain end of the first NMOS tube Q2 is connected to the power supply voltage through the second voltage-dividing resistor R3; the gate end of the first NMOS tube Q2 serves as the control end of the output control unit, which is connected to the output end of the current limiting detection unit; and the source end of the first NMOS tube Q2 is grounded.

[0042] The gate terminal of the second NMOS transistor Q3 is connected to the drain terminal of the first NMOS transistor Q2, the source terminal of the second NMOS transistor Q3 is grounded, and the drain terminal of the second NMOS transistor Q3 is connected to the control terminal of the current output unit through the third voltage dividing resistor R4.

[0043] It can be understood that the conduction state of the first NMOS tube Q2 is controlled by the conduction control signal output by the current limiting detection unit, and the conduction state of the second NMOS tube Q3 is controlled by the conduction state of the first NMOS tube Q2. For example, when the conduction control signal is at a high level and the first NMOS tube Q2 meets the conduction condition, the first NMOS tube Q2 is turned on, and correspondingly, the gate terminal voltage of the second NMOS tube does not meet the conduction condition, and the second NMOS tube Q3 is turned off. On the contrary, when the conduction control signal is at a low level, the first NMOS tube Q2 is turned off, and the gate terminal of the second NMOS tube Q3 is equivalent to accessing the power supply voltage through the second voltage-dividing resistor R3, and the second NMOS tube Q3 meets the conduction condition and is turned on. Therefore, by switching the conduction state of the first NMOS tube and the second NMOS tube in the output control unit, the charging current limiting module can easily realize the control of whether to output the charging current.

[0044] Exemplary, combined Figure 3 and Figure 4 , the conduction state of the second NMOS tube Q3 will affect the conduction state of the first PMOS tube Q1, thereby realizing the output control of the charging current. For example, when the second NMOS tube Q3 is turned on, the gate terminal voltage of the first PMOS tube Q1 can meet the conduction condition, the first PMOS tube Q1 is turned on, and the charging current limiting module outputs the charging current to the super capacitor; when the second NMOS tube Q3 is turned off, the gate terminal voltage of the first PMOS tube Q1 cannot meet the conduction condition, the first PMOS tube Q1 is turned off, and the charging current limiting module stops outputting the charging current to the super capacitor.

[0045] It should be noted that, in some embodiments, the NMOS tube in the output control unit can also be replaced by a PMOS tube, and the source terminal of the PMOS tube is connected to the power supply voltage or the current output unit through a resistor, and the drain terminal of the PMOS tube is grounded through a resistor.

[0046] Figure 5 A circuit diagram of a voltage supply unit provided in an embodiment of the present application, the voltage supply unit is used to provide a reference voltage for the current limiting detection unit, and the voltage supply unit provides the reference voltage through a voltage stabilizing element and a corresponding voltage-dividing resistor. As shown in the figure, in one embodiment, the cathode end of the voltage stabilizing element U1 (represented by the Cat end in the figure) is connected to the supply voltage through the fourth voltage-dividing resistor R5, the cathode end of the voltage stabilizing element U1 is also connected to the reference end of the voltage stabilizing element U1 (represented by the Ref end in the figure) through the fifth voltage-dividing resistor R6, and the reference end of the voltage stabilizing element U1 is also grounded through the sixth voltage-dividing resistor R7, the sixth voltage-dividing resistor R7 is also connected in parallel with the second filter capacitor C2, and the anode end of the voltage stabilizing element U1 (represented by the Anode end in the figure) is grounded.

[0047] The first end of the first current limiting resistor R8 is connected to the cathode end of the voltage stabilizing element U1, and the second end of the first current limiting resistor R8 is also connected to a grounded seventh voltage-dividing resistor R9 and a grounded third filter capacitor C3, that is, the cathode end of the voltage stabilizing element U1 is also connected to the comparison input end of the current limiting detection unit through the first current limiting resistor R8.

[0048] Therefore, by changing the resistance values ​​of the fourth voltage-dividing resistor R5, the fifth voltage-dividing resistor R6, and the sixth voltage-dividing resistor R7, the reference voltage can be changed accordingly, thereby realizing the adjustment of the preset current limiting value. That is, according to the application requirements, after determining the required preset current limiting value, selecting the fourth voltage-dividing resistor R5, the fifth voltage-dividing resistor R6, and the sixth voltage-dividing resistor R7 with corresponding resistance values ​​can make the voltage providing unit output a reference voltage corresponding to the preset current limiting value, thereby realizing the current limiting control of the charging current.

[0049] Figure 6 A circuit diagram of a current limiting detection unit provided in an embodiment of the present application, corresponding to the first sampling pin and the second sampling pin included in the voltage sampling terminal, the current limiting detection unit is provided with two input terminals connected to the above pins. As shown in the figure, the current limiting detection unit is connected to the current output unit through the current amplifier chip U2 and the corresponding input resistor.

[0050] Specifically, the in-phase input terminal of the current amplifier chip U2 is connected to the first sampling pin through the first input resistor R10, and the inverting input terminal of the current amplifier chip U2 is connected to the second sampling pin through the second input resistor R11. The in-phase input terminal and the inverting input terminal of the current amplifier chip U2 are also connected through an anti-interference capacitor Cx to absorb interference signals and stabilize the voltage at the input terminal.

[0051] The output end of the current amplifier chip U2 is connected to the non-inverting input end of the first voltage comparator chip U3 through the first output resistor R12, and the inverting input end of the first voltage comparator chip U3 is connected to the output end of the voltage providing unit, and the output end of the first voltage comparator chip U3 is connected to the input end of the output control unit.

[0052] In addition, the output end of the first voltage comparator chip U3 is also connected to the non-inverting input end of the first voltage comparator chip U3 through the first feedback resistor R13, and the output end of the first voltage comparator chip U3 is also connected to the grounded eighth voltage-dividing resistor R14.

[0053] It can be understood that the charging current flows through the sampling resistor. The non-inverting input terminal and the inverting input terminal of the current amplifier chip U2 can be connected to the two ends of the sampling resistor to amplify the sampling signal, and then convert it into a voltage signal and input it into the first voltage comparator chip U3. The first voltage comparator chip U3 will compare it with the reference voltage. When the voltage signal is greater than the reference voltage, it means that the charging current is greater than the preset current limit value, and the first voltage comparator chip U3 outputs a high level.

[0054] For example, refer to Figure 3-6 The current amplifier chip U2 samples the sampling resistor. After comparing the sampled voltage with the reference voltage, if the first voltage comparator chip U3 outputs a high level, that is, the conduction control signal is a high level, the gate terminal voltage of the first NMOS tube Q2 meets the conduction condition, and correspondingly, the second NMOS tube Q3 is turned off. Accordingly, the first PMOS tube Q1 is turned off, and the charging current limiting module stops outputting the charging current to the supercapacitor.

[0055] The controlled discharge module controls the on-off of the discharge circuit according to the discharge control signal, that is, the control of forming a path between the supercapacitor and the load is affected by the discharge control signal. Figure 7 A circuit diagram of a controlled discharge module provided in an embodiment of the present application is shown in the figure. As shown in the figure, the controlled discharge module is connected to a supercapacitor through the anode end of a plurality of second power Schottky diodes connected in parallel to access the voltage released by the supercapacitor, wherein power Schottky diode ZD4, power Schottky diode ZD5 and power Schottky diode ZD6 serve as the second power Schottky diodes in the controlled discharge module.

[0056] The source terminal of the second PMOS tube Q4 is connected to the cathode terminal of each second power Schottky diode, and the source terminal of the second PMOS tube Q4 is connected to the gate terminal of the second PMOS tube Q4 through the second current limiting resistor R15 and the diode D1. The second current limiting resistor R15 can also be connected to the gate terminal of the second PMOS tube Q4 through two diodes connected in parallel. In addition, a fourth filter capacitor C4 is also provided between the source terminal of the second PMOS tube and the gate terminal of the second PMOS tube, and the drain terminal of the second PMOS tube is also connected to the anode terminal of the diode through a fifth filter capacitor C5.

[0057] The drain terminal of the third NMOS transistor Q5 is connected to the gate terminal of the second PMOS transistor Q4 through the ninth voltage-dividing resistor R16, the gate terminal of the third NMOS transistor Q5 is connected to the discharge control signal through the third input resistor R17, and the source terminal of the third NMOS transistor Q5 is connected to the grounded pull-down resistor R18. It should be noted that in some embodiments, a PMOS transistor can also be used to replace the third NMOS transistor.

[0058] It can be understood that the on-off state of the discharge circuit is determined by the on-state of the second PMOS tube Q4, and the on-state of the second PMOS tube Q4 is controlled by the on-state of the third NMOS tube Q5. For example, when the discharge control signal is at a high level and the gate terminal of the third NMOS tube Q5 meets the on-condition, the third NMOS tube Q5 is turned on, and the second current limiting resistor R15 and the ninth voltage dividing resistor R16 are connected in series to divide the voltage, so that the voltage drop between the source terminal and the gate terminal of the second PMOS tube Q4 is greater than the on-voltage, that is, the second PMOS tube Q4 meets the on-condition, the second PMOS tube Q4 is turned on, and therefore, the discharge circuit is turned on.

[0059] For example, in a specific application, when the voltage provided by the supercapacitor is less than or equal to the power supply voltage, the discharge control signal can be maintained at a high level, that is, the discharge circuit is always turned on, and a low-level discharge control signal is output after the data is saved, thereby disconnecting the discharge circuit. It can be understood that since the voltage provided by the supercapacitor is less than or equal to the power supply voltage, before the device is powered off, even if the discharge circuit is always turned on, the supercapacitor will not discharge to the outside, but continue to maintain a charged state; and when the device is powered off, the power supply voltage is equivalent to 0V, at which time the voltage provided by the supercapacitor is greater than the power supply voltage, and the supercapacitor discharges to the outside to provide power for the device to save data.

[0060] Of course, it is conceivable that for the control of the discharge control signal to maintain a high level continuously or switch to a high level or other voltage state when the power is off, a corresponding control strategy can be executed according to application requirements.

[0061] Therefore, this solution can simply and effectively realize the on-off control of the discharge circuit. After the device loses power, the discharge circuit is turned on through the discharge control signal in the circuit, thereby providing power for the device to save data; and after the device completes data saving, it can disconnect the discharge circuit by outputting a low-level discharge control signal, thereby stopping power supply.

[0062] In some embodiments, the source terminal of the third NMOS tube Q5 of the controlled discharge module is connected to the undervoltage indication signal without connecting the pull-down resistor, and the undervoltage indication signal can be provided by a processing module such as a CPU or an MCU. It should be noted that, in some embodiments, the undervoltage indication signal can also be provided by an anti-backflow module, that is, the anti-backflow module outputs the undervoltage indication signal when the main power input port needs to have an undervoltage.

[0063] Therefore, whether the controlled discharge module turns on the discharge circuit is also controlled by the undervoltage indication signal. For example, if the supercapacitor is charged with a boosted voltage, before the device is powered off, the voltage provided by the supercapacitor is greater than the power supply voltage. Therefore, if the discharge control signal is continuously at a high level, the undervoltage indication signal needs to be at a high level or left floating to avoid the discharge circuit being turned on and discharging in advance; and after the device is powered off, the undervoltage indication signal can be pulled low to turn on the discharge circuit, thereby discharging.

[0064] In some embodiments, the capacitor charging and discharging circuit further includes a full-charge prompt module, the input end of which is connected to a supercapacitor to output an indication signal when the voltage of the supercapacitor is greater than a preset voltage value. For example, a light-emitting diode is provided in the full-charge prompt module, and a full-charge indication is provided to the user by lighting up the light-emitting diode, thereby using a light signal as an indication signal; or a buzzer is provided in the full-charge prompt module, and a full-charge indication is provided to the user by sounding the buzzer, thereby using a sound signal as an indication signal; of course, it can also be a combination of the two, thereby outputting an acoustic and optical signal as an indication signal.

[0065] In one embodiment, if Figure 8 As shown, Figure 8 A circuit diagram of a full-charge prompt module provided in an embodiment of the present application. In the full-charge prompt module, the inverting input terminal of the second voltage comparator chip U4 is connected to a preset voltage, which can be provided by the charging limit module or obtained by dividing the supply voltage by a voltage divider resistor. The inverting input terminal of the second voltage comparator chip U4 is connected to a supercapacitor through a fourth input resistor R19, and the fourth input resistor R19 is also connected to a grounded tenth-voltage resistor R20.

[0066] Furthermore, the output end of the second voltage comparator chip U4 is connected to the gate end of the fourth NMOS transistor Q6 through the second output resistor R21. In addition, the output end of the second voltage comparator chip U4 is also connected to the non-inverting input end of the second voltage comparator chip U4 through the second feedback resistor R22. The gate end of the fourth NMOS transistor Q6 is also connected to a grounded bias voltage-dividing resistor R23, the source end of the fourth NMOS transistor Q6 is grounded, the drain end of the fourth NMOS transistor Q6 is connected to the cathode end of the light-emitting diode LED1, and the anode end of the light-emitting diode LED1 is connected to the power supply voltage through the eleventh voltage-dividing resistor R24.

[0067] It can be understood that the second voltage comparator chip U4 compares the voltage of the supercapacitor with the preset voltage. When the voltage of the supercapacitor is greater than the preset voltage, the second voltage comparator chip U4 outputs a high level, so that the fourth NMOS tube Q6 meets the conduction condition. When the fourth NMOS tube Q6 is turned on, the branch where the light-emitting diode LED1 is located is turned on, and then the light-emitting diode LED1 lights up, which serves as an indication.

[0068] Fig. 9 A principle block diagram of a capacitor charging and discharging circuit is provided for another embodiment of the present application. As shown in the figure, the capacitor charging and discharging circuit includes an anti-backflow module 110, a voltage regulation module 210, a charging current limiting module 120, a super capacitor, a voltage equalization protection module 130 and a controlled discharge module 140.

[0069] The input end of the anti-backflow module 110 is connected to the power supply voltage, and the output end of the anti-backflow module 110 is connected to the input end of the voltage regulation module 210, and the output end of the voltage regulation module 210 is connected to the input end of the charging current limiting module 120, and the output end of the charging current limiting module 120 is connected to the super capacitor, the super capacitor is grounded, and the voltage equalization protection module 130 is connected in parallel with the super capacitor. The input end of the controlled discharge module 140 is connected to the charging current limiting module 120, that is, the input end of the controlled discharge module 140 is connected to the super capacitor, and the output end of the controlled discharge module 140 is connected to the output load, and the control end of the controlled discharge module 140 is connected to the discharge control signal.

[0070] It is understandable that the voltage regulating module 210 is arranged before the charging current limiting module 120, and the capacitor charging and discharging circuit can adjust the voltage connected to the charging current limiting module 120 through the voltage regulating module 210, such as performing boost and / or buck regulation, so that the supercapacitor can meet the voltage requirements of the load. For example, in some embodiments, when the load requires a voltage of at least 5V and the power supply voltage is a fixed voltage of 5V, it is necessary to use the voltage regulating module 120 as a boost module to increase the voltage and charge the supercapacitor, so that the voltage supplied by the supercapacitor after the device is powered off has a corresponding voltage drop range relative to the 5V voltage required by the load, so that the device can complete data storage.

[0071] In some embodiments, when the power supply voltage is in a wide voltage range, the voltage regulating module is a buck-boost module to provide a corresponding voltage for the charging current limiting module, so that the voltage of the supercapacitor after charging will be greater than the power supply voltage. In this case, the controlled discharge module can be controlled by a discharge control signal and an undervoltage indication signal, that is, the source terminal of the third NMOS tube of the controlled discharge module is connected to the undervoltage indication signal, and the gate terminal of the third NMOS tube is connected to the discharge control signal. Exemplarily, the corresponding control strategy can be that the discharge control signal maintains a high level, and when the device is not powered off, the undervoltage indication signal is a high level, and the discharge circuit is disconnected; after the device is powered off, the undervoltage indication signal is a low level, and the discharge circuit is turned on.

[0072] Of course, corresponding to the above situation, the controlled discharge module can also be controlled by a discharge control signal, that is, the source terminal of the third NMOS tube of the controlled discharge module is connected to the pull-down resistor, and the gate terminal of the third NMOS tube is connected to the discharge control signal. The corresponding control strategy can be: after the device is powered off, a high-level discharge control signal is provided to turn on the discharge circuit.

[0073] It should be noted that the above-mentioned buck-boost module can be a module including a BUCK-BOOST buck-boost circuit, or a module including a buck-boost converter; the above-mentioned boost module can be a module including a BOOST boost circuit, or a module including an intermittent oscillation boost circuit.

[0074] The embodiment of the present application also provides a circuit board, which is like the capacitor charging and discharging circuit of the above embodiment, and has corresponding functions and beneficial effects. The circuit board can be applied to industrial control equipment, and the circuit on the circuit board can provide more effective charging and discharging control, and can still maintain power supply for a period of time after the device loses power so that the device can save data, which is helpful for the application of industrial control equipment in high reliability scenarios.

[0075] The embodiment of the present application also provides an industrial control device, which includes the circuit board provided in the above embodiment and has corresponding functions and beneficial effects. The industrial control device can achieve better charge and discharge control by using the above circuit board, achieve a larger charging current while shortening the charging time and limit the charging current to protect the supercapacitor, and can also quickly respond to the discharge demand and promptly turn on the discharge circuit to save data, which helps to meet the application requirements in high reliability scenarios.

[0076] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0077] Note that the above are only preferred embodiments of the present application and the technical principles used. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present application. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A capacitor charging and discharging circuit, characterized in that: include: An anti-backflow module, the input end of which is connected to the power supply voltage, and the anti-backflow module is used to isolate the backflow voltage after the device loses power; A charging current limiting module, wherein the input end of the charging current limiting module is connected to the output end of the anti-backflow module, the output end of the charging current limiting module is connected to a grounded supercapacitor, and the charging current limiting module is used to provide a charging current for the supercapacitor, and to suspend outputting the charging current when the charging current is greater than a preset current limiting value; A voltage balancing protection module, wherein the voltage balancing protection module is connected in parallel with the super capacitor; A controlled discharge module, wherein the input end of the controlled discharge module is connected to the output end of the charging current limiting module, the output end of the controlled discharge module is connected to the output load, the control end of the controlled discharge module is connected to a discharge control signal, and the controlled discharge module is used to control the discharge circuit according to the discharge control signal to start or stop discharge.

2. The capacitor charging and discharging circuit according to claim 1, characterized in that: The charging current limiting module comprises: A current output unit, wherein the input end of the current output unit serves as the input end of the charging current limiting module, and the output end of the current output unit serves as the output end of the charging current limiting module and is connected to the super capacitor; A voltage providing unit, wherein an input terminal of the voltage providing unit is connected to a supply voltage, and the voltage providing unit is used to provide a reference voltage corresponding to the preset current limiting value; a current limiting detection unit, wherein a sampling input terminal of the current limiting detection unit is connected to a voltage sampling terminal of the current output unit, a comparison input terminal of the current limiting detection unit is connected to an output terminal of the voltage providing unit, and the current limiting detection unit is used to compare a sampling voltage with the reference voltage to output a conduction control signal when the charging current is greater than a preset current limiting value; An output control unit, wherein the input end of the output control unit is connected to the power supply voltage, the control end of the output control unit is connected to the output end of the current limiting detection unit, the output end of the output control unit is connected to the control end of the current output unit, and the output control unit is used to control the current output unit to suspend outputting the charging current according to the received conduction control signal.

3. The capacitor charging and discharging circuit according to claim 2, characterized in that: The current output unit comprises: A plurality of first power Schottky diodes, wherein the plurality of first power Schottky diodes are connected in parallel, and anode terminals of the plurality of first power Schottky diodes are all used as input terminals of the current output unit; A first PMOS tube, wherein a source terminal of the first PMOS tube is connected to cathode terminals of the plurality of power Schottky diodes, and a source terminal of the first PMOS tube is also connected to a gate terminal of the first PMOS tube via a first voltage-dividing resistor, and the first voltage-dividing resistor is also connected in parallel to a first filter capacitor; The drain terminal of the first PMOS tube is connected to the super capacitor through a sampling resistor, and the two ends of the sampling resistor serve as the first sampling pin and the second sampling pin of the voltage sampling terminal respectively, and are connected to the sampling input terminal of the current limiting detection unit; The gate terminal of the first PMOS tube serves as the control terminal of the current output unit and is connected to the output terminal of the output control unit.

4. The capacitor charging and discharging circuit according to claim 2, characterized in that: The output control unit comprises: a first NMOS transistor, wherein a drain terminal of the first NMOS transistor is connected to a power supply voltage through a second voltage-dividing resistor, a gate terminal of the first NMOS transistor serves as a control terminal of the output control unit and is connected to an output terminal of the current limiting detection unit, and a source terminal of the first NMOS transistor is grounded; A second NMOS tube, wherein the gate terminal of the second NMOS tube is connected to the drain terminal of the first NMOS tube, the source terminal of the second NMOS tube is grounded, and the drain terminal of the second NMOS tube is connected to the control terminal of the current output unit through a third voltage-dividing resistor.

5. The capacitor charging and discharging circuit according to claim 2, characterized in that: The voltage providing unit comprises: A voltage stabilizing element, wherein the cathode end of the voltage stabilizing element is connected to the supply voltage through a fourth voltage-dividing resistor, and the cathode end of the voltage stabilizing element is also connected to the reference end of the voltage stabilizing element through a fifth voltage-dividing resistor, the reference end of the voltage stabilizing element is also grounded through a sixth voltage-dividing resistor, and the sixth voltage-dividing resistor is connected in parallel with the second filter capacitor, the fourth voltage-dividing resistor, the fifth voltage-dividing resistor and the sixth voltage-dividing resistor are used to determine a pre-selected reference voltage value, and the reference voltage value is used to determine the maximum value of the charging current value; A first current limiting resistor, wherein the first end of the first current limiting resistor is connected to the cathode end of the voltage stabilizing element, the second end of the first current limiting resistor serves as the output end of the voltage providing unit and is connected to the comparison input end of the current limiting detection unit, and the second end of the first current limiting resistor is also respectively connected to a grounded seventh voltage-dividing resistor and a grounded third filter capacitor.

6. The capacitor charging and discharging circuit according to claim 2, characterized in that: The voltage sampling terminal of the current output unit includes a first sampling pin and a second sampling pin, and the current limiting detection unit includes: A current amplifier chip, wherein the in-phase input terminal of the current amplifier chip is connected to the first sampling pin via a first input resistor, the inverting input terminal of the current amplifier chip is connected to the second sampling pin via a second input resistor, and the in-phase input terminal and the inverting input terminal of the current amplifier chip are connected to an anti-interference capacitor; A first voltage comparator chip, wherein the non-inverting input terminal of the first voltage comparator chip is connected to the output terminal of the current amplifier chip through a first output resistor, the inverting input terminal of the first voltage comparator chip is connected to the output terminal of the voltage providing unit, the output terminal of the first voltage comparator chip serves as the output terminal of the current limiting detection unit and is connected to the control terminal of the output control unit, the output terminal of the first voltage comparator chip is also connected to the non-inverting input terminal of the first voltage comparator chip through a first feedback, and the output terminal of the first voltage comparator chip is also connected to a grounded eighth voltage dividing resistor.

7. The capacitor charging and discharging circuit according to claim 1, characterized in that: The controlled discharge module comprises: A plurality of second power Schottky diodes, wherein the plurality of second power Schottky diodes are connected in parallel, and an anode end of the second power Schottky diode is connected to the super capacitor; a second PMOS tube, wherein the source terminal of the second PMOS tube is connected to the cathode terminal of the second voltage-stabilizing diode, the source terminal of the second PMOS tube is connected to the gate terminal of the second PMOS tube through a second current-limiting resistor and a diode, a third filter capacitor is further provided between the source terminal of the second PMOS tube and the gate terminal of the second PMOS tube, the drain terminal of the second PMOS tube is connected to the output load, and the drain terminal of the second PMOS tube is further connected to the anode terminal of the diode through a fourth filter capacitor; A third NMOS tube, the drain terminal of the third NMOS tube is connected to the gate terminal of the second PMOS tube through a ninth voltage-dividing resistor, the gate terminal of the third NMOS tube is connected to the discharge control signal through a third input resistor, the source terminal of the third NMOS tube is connected to a grounded pull-down resistor or is connected to an undervoltage indication signal, and the undervoltage indication signal is provided by the anti-backflow module or the processing module for discharge control of the controlled discharge module.

8. The capacitor charging and discharging circuit according to claim 1, characterized in that: It also includes a full-power indication module, the input end of which is connected to the supercapacitor, and the full-power indication module is used to output an indication signal when the voltage of the supercapacitor is greater than a preset voltage value.

9. The capacitor charging and discharging circuit according to claim 8, characterized in that: The full power indication module comprises: A second voltage comparator chip, wherein the non-inverting input terminal of the second voltage comparator chip is connected to the super capacitor through a fourth input resistor, the fourth input resistor is also connected to a grounded 10th voltage resistor, the inverting input terminal of the second voltage comparator chip is connected to a preset voltage, and the output terminal of the second voltage comparator chip is connected to the non-inverting input terminal of the second voltage comparator chip through a second feedback resistor; a fourth NMOS tube, wherein a gate terminal of the fourth NMOS tube is connected to the output terminal of the second voltage comparator chip through a second output resistor, a gate terminal of the fourth NMOS tube is further connected to a grounded bias voltage-dividing resistor, and a source terminal of the fourth NMOS tube is grounded; A light emitting diode, wherein the cathode terminal of the light emitting diode is connected to the drain terminal of the fourth NMOS tube, the anode terminal of the light emitting diode is connected to the first terminal of the eleventh voltage-dividing resistor, and the second terminal of the eleventh voltage-dividing resistor is connected to the power supply voltage.

10. The capacitor charging and discharging circuit according to any one of claims 1 to 9, characterized in that: It also includes a voltage regulating module, the input end of the voltage regulating module is connected to the output end of the anti-backflow module, the output end of the voltage regulating module is connected to the input end of the charging current limiting module, and the voltage regulating module is used to adjust the voltage connected to the charging current limiting module.

11. The capacitor charging and discharging circuit according to claim 10, characterized in that: The voltage regulating module is a buck-boost module or a boost module.

12. A circuit board, characterized in that: It comprises a capacitor charging and discharging circuit as described in any one of claims 1 to 11.

13. An industrial control device, characterized in that: Comprising the circuit board as claimed in claim 12.

Images